2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2005
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #ifdef CONFIG_VIDEO_SM501
38 #if defined(CONFIG_MPC5200_DDR)
39 #include "mt46v16m16-75.h"
41 #include "mt48lc16m16a2-75.h"
45 void ps2mult_early_init(void);
49 static void sdram_start (int hi_addr)
51 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
53 /* unlock mode register */
54 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
56 __asm__ volatile ("sync");
58 /* precharge all banks */
59 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
61 __asm__ volatile ("sync");
64 /* set mode register: extended mode */
65 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
66 __asm__ volatile ("sync");
68 /* set mode register: reset DLL */
69 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
70 __asm__ volatile ("sync");
73 /* precharge all banks */
74 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
76 __asm__ volatile ("sync");
79 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
81 __asm__ volatile ("sync");
83 /* set mode register */
84 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
85 __asm__ volatile ("sync");
87 /* normal operation */
88 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
89 __asm__ volatile ("sync");
94 * ATTENTION: Although partially referenced initdram does NOT make real use
95 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
96 * is something else than 0x00000000.
99 #if defined(CONFIG_MPC5200)
100 long int initdram (int board_type)
107 /* setup SDRAM chip selects */
108 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
109 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
110 __asm__ volatile ("sync");
112 /* setup config registers */
113 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
114 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
115 __asm__ volatile ("sync");
119 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
120 __asm__ volatile ("sync");
123 /* find RAM size using SDRAM CS0 only */
125 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
127 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
135 /* memory smaller than 1MB is impossible */
136 if (dramsize < (1 << 20)) {
140 /* set SDRAM CS0 size according to the amount of RAM found */
142 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
143 __builtin_ffs(dramsize >> 20) - 1;
145 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
148 /* let SDRAM CS1 start right after CS0 */
149 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
151 /* find RAM size using SDRAM CS1 only */
153 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
155 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
163 /* memory smaller than 1MB is impossible */
164 if (dramsize2 < (1 << 20)) {
168 /* set SDRAM CS1 size according to the amount of RAM found */
170 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
171 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
173 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
176 #else /* CFG_RAMBOOT */
178 /* retrieve size of memory connected to SDRAM CS0 */
179 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
180 if (dramsize >= 0x13) {
181 dramsize = (1 << (dramsize - 0x13)) << 20;
186 /* retrieve size of memory connected to SDRAM CS1 */
187 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
188 if (dramsize2 >= 0x13) {
189 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
194 #endif /* CFG_RAMBOOT */
196 /* return dramsize + dramsize2; */
200 #elif defined(CONFIG_MGT5100)
202 long int initdram (int board_type)
208 /* setup and enable SDRAM chip selects */
209 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
210 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
211 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
212 __asm__ volatile ("sync");
214 /* setup config registers */
215 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
216 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
218 /* address select register */
219 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
220 __asm__ volatile ("sync");
224 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
226 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
234 /* set SDRAM end address according to size */
235 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
237 #else /* CFG_RAMBOOT */
239 /* Retrieve amount of SDRAM available */
240 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
242 #endif /* CFG_RAMBOOT */
248 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
251 int checkboard (void)
253 #if defined (CONFIG_AEVFIFO)
254 puts ("Board: AEVFIFO\n");
257 #if defined (CONFIG_TQM5200)
258 puts ("Board: TQM5200 (TQ-Components GmbH)\n");
260 #if defined (CONFIG_STK52XX)
261 puts (" on a STK52XX baseboard\n");
267 void flash_preinit(void)
270 * Now, when we are in RAM, enable flash write
271 * access for detection process.
272 * Note that CS_BOOT cannot be cleared when
273 * executing in flash.
275 #if defined(CONFIG_MGT5100)
276 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
277 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
279 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
284 static struct pci_controller hose;
286 extern void pci_mpc5xxx_init(struct pci_controller *);
288 void pci_init_board(void)
290 pci_mpc5xxx_init(&hose);
294 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
296 #if defined (CONFIG_MINIFAP)
297 #define SM501_POWER_MODE0_GATE 0x00000040UL
298 #define SM501_POWER_MODE1_GATE 0x00000048UL
299 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
300 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
301 #define SM501_GPIO_DATA_HIGH 0x00010004UL
302 #define SM501_GPIO_51 0x00080000UL
304 #define GPIO_PSC1_4 0x01000000UL
307 void init_ide_reset (void)
309 debug ("init_ide_reset\n");
311 #if defined (CONFIG_MINIFAP)
312 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
314 /* enable GPIO control (in both power modes) */
315 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
316 POWER_MODE_GATE_GPIO_PWM_I2C;
317 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
318 POWER_MODE_GATE_GPIO_PWM_I2C;
319 /* configure GPIO51 as output */
320 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
323 /* Configure PSC1_4 as GPIO output for ATA reset */
324 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
325 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
329 void ide_set_reset (int idereset)
331 debug ("ide_reset(%d)\n", idereset);
333 #if defined (CONFIG_MINIFAP)
335 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
338 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
343 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
345 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
349 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
353 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
354 * is left open, no keypress is detected.
356 int post_hotkeys_pressed(void)
358 struct mpc5xxx_gpio *gpio;
360 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
363 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
364 * CODEC or UART mode. Consumer IrDA should still be possible.
366 gpio->port_config &= ~(0x07000000);
367 gpio->port_config |= 0x03000000;
369 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
370 gpio->simple_gpioe |= 0x20000000;
372 /* Configure GPIO_IRDA_1 as input */
373 gpio->simple_ddr &= ~(0x20000000);
375 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
379 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
381 void post_word_store (ulong a)
383 volatile ulong *save_addr =
384 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
389 ulong post_word_load (void)
391 volatile ulong *save_addr =
392 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
396 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
398 #ifdef CONFIG_PS2MULT
399 #ifdef CONFIG_BOARD_EARLY_INIT_R
400 int board_early_init_r (void)
402 ps2mult_early_init();
406 #endif /* CONFIG_PS2MULT */
408 #if defined(CONFIG_CS_AUTOCONF)
409 int last_stage_init (void)
412 * auto scan for really existing devices and re-set chip select
419 * Check for SRAM and SRAM size
422 /* save original SRAM content */
423 save = *(volatile u16 *)CFG_CS2_START;
426 /* write test pattern to SRAM */
427 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
428 __asm__ volatile ("sync");
430 * Put a different pattern on the data lines: otherwise they may float
431 * long enough to read back what we wrote.
433 tmp = *(volatile u16 *)CFG_FLASH_BASE;
435 puts ("!! possible error in SRAM detection\n");
437 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
438 /* no SRAM at all, disable cs */
439 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
440 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
441 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
443 __asm__ volatile ("sync");
444 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
445 /* make sure that we access a mirrored address */
446 *(volatile u16 *)CFG_CS2_START = 0x1111;
447 __asm__ volatile ("sync");
448 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
449 /* SRAM size = 512 kByte */
450 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
452 __asm__ volatile ("sync");
453 puts ("SRAM: 512 kB\n");
456 puts ("!! possible error in SRAM detection\n");
458 puts ("SRAM: 1 MB\n");
460 /* restore origianl SRAM content */
462 *(volatile u16 *)CFG_CS2_START = save;
463 __asm__ volatile ("sync");
467 * Check for Grafic Controller
470 /* save origianl FB content */
471 save = *(volatile u16 *)CFG_CS1_START;
474 /* write test pattern to FB memory */
475 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
476 __asm__ volatile ("sync");
478 * Put a different pattern on the data lines: otherwise they may float
479 * long enough to read back what we wrote.
481 tmp = *(volatile u16 *)CFG_FLASH_BASE;
483 puts ("!! possible error in grafic controller detection\n");
485 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
486 /* no grafic controller at all, disable cs */
487 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
488 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
489 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
491 __asm__ volatile ("sync");
493 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
495 /* restore origianl FB content */
497 *(volatile u16 *)CFG_CS1_START = save;
498 __asm__ volatile ("sync");
503 #endif /* CONFIG_CS_AUTOCONF */
505 #ifdef CONFIG_VIDEO_SM501
507 #define DISPLAY_WIDTH 640
508 #define DISPLAY_HEIGHT 480
510 #ifdef CONFIG_VIDEO_SM501_8BPP
511 #error CONFIG_VIDEO_SM501_8BPP not supported.
512 #endif /* CONFIG_VIDEO_SM501_8BPP */
514 #ifdef CONFIG_VIDEO_SM501_16BPP
515 #error CONFIG_VIDEO_SM501_16BPP not supported.
516 #endif /* CONFIG_VIDEO_SM501_16BPP */
517 #ifdef CONFIG_VIDEO_SM501_32BPP
518 static const SMI_REGS init_regs [] =
522 {0x00048, 0x00021807},
523 {0x0004C, 0x10090a01},
525 {0x00040, 0x00021807},
526 {0x00044, 0x10090a01},
528 {0x80200, 0x00010000},
530 {0x80208, 0x0A000A00},
531 {0x8020C, 0x02fa027f},
532 {0x80210, 0x004a028b},
533 {0x80214, 0x020c01df},
534 {0x80218, 0x000201e9},
535 {0x80200, 0x00013306},
536 #else /* panel + CRT */
538 {0x00048, 0x00021807},
539 {0x0004C, 0x091a0a01},
541 {0x00040, 0x00021807},
542 {0x00044, 0x091a0a01},
544 {0x80000, 0x0f013106},
545 {0x80004, 0xc428bb17},
546 {0x8000C, 0x00000000},
547 {0x80010, 0x0a000a00},
548 {0x80014, 0x02800000},
549 {0x80018, 0x01e00000},
550 {0x8001C, 0x00000000},
551 {0x80020, 0x01e00280},
552 {0x80024, 0x02fa027f},
553 {0x80028, 0x004a028b},
554 {0x8002C, 0x020c01df},
555 {0x80030, 0x000201e9},
556 {0x80200, 0x00010000},
560 #endif /* CONFIG_VIDEO_SM501_32BPP */
562 #ifdef CONFIG_CONSOLE_EXTRA_INFO
564 * Return text to be printed besides the logo.
566 void video_get_info_str (int line_number, char *info)
568 if (line_number == 1) {
569 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
570 #if defined (CONFIG_STK52XX)
571 } else if (line_number == 2) {
572 strcpy (info, " on a STK52XX baseboard");
582 * Returns SM501 register base address. First thing called in the
583 * driver. Checks if SM501 is physically present.
585 unsigned int board_video_init (void)
591 * Check for Grafic Controller
594 /* save origianl FB content */
595 save = *(volatile u16 *)CFG_CS1_START;
598 /* write test pattern to FB memory */
599 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
600 __asm__ volatile ("sync");
602 * Put a different pattern on the data lines: otherwise they may float
603 * long enough to read back what we wrote.
605 tmp = *(volatile u16 *)CFG_FLASH_BASE;
607 puts ("!! possible error in grafic controller detection\n");
609 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
610 /* no grafic controller found */
614 ret = SM501_MMIO_BASE;
618 *(volatile u16 *)CFG_CS1_START = save;
619 __asm__ volatile ("sync");
625 * Returns SM501 framebuffer address
627 unsigned int board_video_get_fb (void)
629 return SM501_FB_BASE;
633 * Called after initializing the SM501 and before clearing the screen.
635 void board_validate_screen (unsigned int base)
640 * Return a pointer to the initialization sequence.
642 const SMI_REGS *board_get_regs (void)
647 int board_get_width (void)
649 return DISPLAY_WIDTH;
652 int board_get_height (void)
654 return DISPLAY_HEIGHT;
657 #endif /* CONFIG_VIDEO_SM501 */