3 * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
5 * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
6 * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <asm/arch/s3c24x0_cpu.h>
28 static void rs485_setbrg (void);
29 static void rs485_cfgio (void);
30 static void set_rs485re(unsigned char rs485re_state);
31 static void set_rs485de(unsigned char rs485de_state);
32 static void rs485_setbrg (void);
34 static void trab_rs485_disable_tx(void);
35 static void trab_rs485_disable_rx(void);
38 #define UART_NR S3C24X0_UART1
40 /* CPLD-Register for controlling TRAB hardware functions */
41 #define CPLD_RS485_RE ((volatile unsigned long *)0x04028000)
43 static void rs485_setbrg (void)
45 struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
49 /* value is calculated so : (int)(PCLK/16./baudrate) -1 */
50 /* reg = (33000000 / (16 * gd->baudrate)) - 1; */
51 reg = (33000000 / (16 * 38400)) - 1;
53 /* FIFO enable, Tx/Rx FIFO clear */
56 /* Normal,No parity,1 stop,8 bit */
59 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
60 * normal,interrupt or polling
65 for (i = 0; i < 100; i++);
68 static void rs485_cfgio (void)
70 struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
72 gpio->pfcon &= ~(0x3 << 2);
73 gpio->pfcon |= (0x2 << 2); /* configure GPF1 as RXD1 */
75 gpio->pfcon &= ~(0x3 << 6);
76 gpio->pfcon |= (0x2 << 6); /* configure GPF3 as TXD1 */
78 gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */
79 gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */
81 gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
85 * Initialise the rs485 port with the given baudrate. The settings
86 * are always 8 data bits, no parity, 1 stop bit, no start bits.
98 * Read a single byte from the rs485 port. Returns 1 on success, 0
99 * otherwise. When the function is succesfull, the character read is
100 * written into its argument c.
102 int rs485_getc (void)
104 struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
106 /* wait for character to arrive */
107 while (!(uart->utrstat & 0x1))
110 return uart->urxh & 0xff;
114 * Output a single byte to the rs485 port.
116 void rs485_putc (const char c)
118 struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
120 /* wait for room in the tx FIFO */
121 while (!(uart->utrstat & 0x2))
126 /* If \n, also do \r */
132 * Test whether a character is in the RX buffer
134 int rs485_tstc (void)
136 struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
138 return uart->utrstat & 0x1;
141 void rs485_puts (const char *s)
157 /* function that controls the receiver enable for the rs485 */
158 /* rs485re_state reflects the level (0/1) of the RE pin */
160 static void set_rs485re(unsigned char rs485re_state)
163 *CPLD_RS485_RE = 0x010000;
165 *CPLD_RS485_RE = 0x0;
168 /* function that controls the sender enable for the rs485 */
169 /* rs485de_state reflects the level (0/1) of the DE pin */
171 static void set_rs485de(unsigned char rs485de_state)
173 struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
175 /* This is on PORT A bit 11 */
177 gpio->padat |= (1 << 11);
179 gpio->padat &= ~(1 << 11);
183 void trab_rs485_enable_tx(void)
189 void trab_rs485_enable_rx(void)
196 static void trab_rs485_disable_tx(void)
201 static void trab_rs485_disable_rx(void)