3 * Stefano Babic, DENX Gmbh, sbabic@denx.de
6 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/pxa-regs.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #define RH_A_PSM (1 << 8) /* power switching mode */
42 #define RH_A_NPS (1 << 9) /* no power switching */
44 extern struct serial_device serial_ffuart_device;
45 extern struct serial_device serial_btuart_device;
46 extern struct serial_device serial_stuart_device;
49 #define BOOT_CONSOLE "serial_stuart"
51 #define BOOT_CONSOLE "serial_ffuart"
53 /* ------------------------------------------------------------------------- */
56 * Miscelaneous platform dependent initialisations
59 int usb_board_init(void)
61 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
62 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
65 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
67 while (readl(UHCHR) & UHCHR_FSBIR)
70 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
71 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
73 /* Clear any OTG Pin Hold */
74 if (readl(PSSR) & PSSR_OTGPH)
75 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
77 writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
78 writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
80 /* Set port power control mask bits, only 3 ports. */
81 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
86 void usb_board_init_fail(void)
91 void usb_board_stop(void)
93 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
95 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
97 writel(readl(UHCCOMS) | 1, UHCCOMS);
100 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
105 int board_init (void)
107 /* memory and cpu-speed are setup before relocation */
108 /* so we do _nothing_ here */
110 /* arch number of ConXS Board */
111 gd->bd->bi_arch_number = 776;
113 /* adress of boot parameters */
114 gd->bd->bi_boot_params = 0xa000003c;
119 int board_late_init(void)
121 #if defined(CONFIG_SERIAL_MULTI)
122 char *console=getenv("boot_console");
124 if ((console == NULL) || (strcmp(console,"serial_btuart") &&
125 strcmp(console,"serial_stuart") &&
126 strcmp(console,"serial_ffuart"))) {
127 console = BOOT_CONSOLE;
129 setenv("stdout",console);
130 setenv("stdin", console);
131 setenv("stderr",console);
136 struct serial_device *default_serial_console (void)
138 return &serial_ffuart_device;
143 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
144 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
145 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
146 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
147 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
148 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
149 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
150 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
155 #ifdef CONFIG_DRIVER_DM9000
156 int board_eth_init(bd_t *bis)
158 return dm9000_initialize(bis);