3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/mx5x_pins.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/iomux.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/errno.h>
37 #include <fsl_esdhc.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 static u32 system_rev;
46 extern int mx51_fb_init(struct fb_videomode *mode);
48 #ifdef CONFIG_HW_WATCHDOG
51 static struct fb_videomode nec_nl6448bc26_09c = {
56 37650, /* pixclock = 26.56Mhz */
58 16, /* right margin */
59 31, /* upper margin */
60 12, /* lower margin */
64 FB_VMODE_NONINTERLACED, /* vmode */
68 void hw_watchdog_reset(void)
72 /* toggle watchdog trigger pin */
73 val = mxc_gpio_get(66);
75 mxc_gpio_set(66, val);
79 static void init_drive_strength(void)
81 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
82 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
83 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
84 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
85 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
86 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
87 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
88 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
89 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
90 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
91 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
92 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
93 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
94 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
95 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
96 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
97 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
98 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
99 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
100 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
101 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
102 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
103 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
104 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
105 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
106 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
107 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
109 /* Setting pad options */
110 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
111 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
112 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
113 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
114 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
115 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
116 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
117 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
118 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
119 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
120 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
121 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
122 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
123 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
124 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
125 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
126 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
127 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
128 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
129 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
130 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
131 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
132 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
133 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
134 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
135 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
136 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
137 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
138 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
139 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
140 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
141 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
142 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
143 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
144 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
145 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
146 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
147 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
148 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
149 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
150 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
151 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
154 u32 get_board_rev(void)
156 system_rev = get_cpu_rev();
163 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
169 static void setup_weim(void)
171 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
173 pweim->csgcr1 = 0x004100b9;
174 pweim->csgcr2 = 0x00000001;
175 pweim->csrcr1 = 0x0a018000;
177 pweim->cswcr1 = 0x0704a240;
180 static void setup_uart(void)
182 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
183 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
184 /* console RX on Pin EIM_D25 */
185 mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
186 mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
187 /* console TX on Pin EIM_D26 */
188 mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
189 mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
192 #ifdef CONFIG_MXC_SPI
193 void spi_io_init(void)
195 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
196 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
197 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
198 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
200 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
201 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
202 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
203 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
205 /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
206 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
207 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
208 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
209 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
212 * SS1 will be used as GPIO because of uninterrupted
213 * long SPI transmissions (GPIO4_25)
215 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
216 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
217 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
218 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
220 /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
221 mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
222 mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
223 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
224 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
226 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
227 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
228 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
229 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
232 static void reset_peripherals(int reset)
236 /* reset_n is on NANDF_D15 */
238 mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT);
240 #ifdef CONFIG_VISION2_HW_1_0
242 * set FEC Configuration lines
243 * set levels of FEC config lines
248 mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT);
249 mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT);
250 mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT);
252 /* set direction of FEC config lines */
257 mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT);
258 mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT);
259 mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT);
260 mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT);
262 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
263 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
264 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
265 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
266 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
267 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
268 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
269 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
270 /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
271 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
272 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
273 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
274 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
275 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
279 * activate reset_n pin
280 * Select mux mode: ALT3 mux port: NAND D15
282 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
283 mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
284 PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
286 /* set FEC Control lines */
287 mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN);
290 #ifdef CONFIG_VISION2_HW_1_0
292 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
293 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
296 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
297 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
300 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
301 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
304 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
305 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
308 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
309 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
312 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
313 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
316 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
317 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
322 static void power_init_mx51(void)
326 /* Write needed to Power Gate 2 register */
327 val = pmic_reg_read(REG_POWER_MISC);
329 /* enable VCAM with 2.775V to enable read from PMIC */
330 val = VCAMCONFIG | VCAMEN;
331 pmic_reg_write(REG_MODE_1, val);
334 * Set switchers in Auto in NORMAL mode & STANDBY mode
335 * Setup the switcher mode for SW1 & SW2
337 val = pmic_reg_read(REG_SW_4);
338 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
339 (SWMODE_MASK << SWMODE2_SHIFT)));
340 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
341 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
342 pmic_reg_write(REG_SW_4, val);
344 /* Setup the switcher mode for SW3 & SW4 */
345 val = pmic_reg_read(REG_SW_5);
346 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
347 (SWMODE_MASK << SWMODE3_SHIFT));
348 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
349 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
350 pmic_reg_write(REG_SW_5, val);
353 /* Set VGEN3 to 1.8V, VCAM to 3.0V */
354 val = pmic_reg_read(REG_SETTING_0);
355 val &= ~(VCAM_MASK | VGEN3_MASK);
357 pmic_reg_write(REG_SETTING_0, val);
359 /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
360 val = pmic_reg_read(REG_SETTING_1);
361 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
362 val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
363 pmic_reg_write(REG_SETTING_1, val);
365 /* Configure VGEN3 and VCAM regulators to use external PNP */
366 val = VGEN3CONFIG | VCAMCONFIG;
367 pmic_reg_write(REG_MODE_1, val);
370 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
371 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
372 VVIDEOEN | VAUDIOEN | VSDEN;
373 pmic_reg_write(REG_MODE_1, val);
375 val = pmic_reg_read(REG_POWER_CTL2);
377 pmic_reg_write(REG_POWER_CTL2, val);
384 static void setup_gpios(void)
388 /* CAM_SUP_DISn, GPIO1_7 */
389 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
390 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
392 /* DAB Display EN, GPIO3_1 */
393 mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
394 mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
396 /* WDOG_TRIGGER, GPIO3_2 */
397 mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
398 mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
400 /* Now we need to trigger the watchdog */
403 /* Display2 TxEN, GPIO3_3 */
404 mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
405 mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
407 /* DAB Light EN, GPIO3_4 */
408 mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
409 mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
411 /* AUDIO_MUTE, GPIO3_5 */
412 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
413 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
415 /* SPARE_OUT, GPIO3_6 */
416 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
417 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
419 /* BEEPER_EN, GPIO3_26 */
420 mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
421 mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
423 /* POWER_OFF, GPIO3_27 */
424 mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
425 mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
427 /* FRAM_WE, GPIO3_30 */
428 mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
429 mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
431 /* EXPANSION_EN, GPIO4_26 */
432 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
433 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
435 /* PWM Output GPIO1_2 */
436 mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
439 * Set GPIO1_4 to high and output; it is used to reset
440 * the system on reboot
443 mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT);
446 mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT);
447 for (i = 65; i < 71; i++) {
449 mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT);
453 mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT);
455 /* Set POWER_OFF high */
457 mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT);
460 mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT);
462 mxc_gpio_set(122, 0);
463 mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT);
465 mxc_gpio_set(121, 1);
466 mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT);
471 static void setup_fec(void)
474 mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
475 mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
478 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
479 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
482 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
483 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
486 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
487 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
490 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
491 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
494 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
495 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
498 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
499 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
502 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
503 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
506 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
507 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
510 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
511 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
514 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
515 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
518 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
519 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
522 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
523 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
526 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
527 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
530 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
531 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
534 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
535 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
538 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
539 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
542 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
543 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
546 struct fsl_esdhc_cfg esdhc_cfg[1] = {
547 {MMC_SDHC1_BASE_ADDR, 1},
550 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
552 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
554 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
555 *cd = mxc_gpio_get(0);
562 #ifdef CONFIG_FSL_ESDHC
563 int board_mmc_init(bd_t *bis)
565 mxc_request_iomux(MX51_PIN_SD1_CMD,
566 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
567 mxc_request_iomux(MX51_PIN_SD1_CLK,
568 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
569 mxc_request_iomux(MX51_PIN_SD1_DATA0,
570 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
571 mxc_request_iomux(MX51_PIN_SD1_DATA1,
572 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
573 mxc_request_iomux(MX51_PIN_SD1_DATA2,
574 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
575 mxc_request_iomux(MX51_PIN_SD1_DATA3,
576 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
577 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
578 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
579 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
581 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
582 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
583 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
584 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
586 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
587 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
588 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
589 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
591 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
592 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
593 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
594 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
596 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
597 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
598 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
599 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
601 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
602 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
603 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
604 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
606 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
607 mxc_request_iomux(MX51_PIN_GPIO1_0,
608 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
609 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
611 mxc_request_iomux(MX51_PIN_GPIO1_1,
612 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
613 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
616 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
620 int board_early_init_f(void)
624 init_drive_strength();
626 /* Setup debug led */
628 mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT);
629 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
630 mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
632 /* wait a little while to give the pll time to settle */
645 static void backlight(int on)
657 void lcd_enable(void)
661 mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
662 mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
665 mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
667 ret = mx51_fb_init(&nec_nl6448bc26_09c);
669 puts("LCD cannot be configured\n");
674 gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */
675 /* address of boot parameters */
676 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
681 int board_late_init(void)
685 reset_peripherals(1);
687 reset_peripherals(0);
690 /* Early revisions require a second reset */
691 #ifdef CONFIG_VISION2_HW_1_0
692 reset_peripherals(1);
694 reset_peripherals(0);
703 u32 system_rev = get_cpu_rev();
705 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
707 puts("Board: TTControl Vision II CPU V");
709 switch (system_rev & 0xff) {
728 cause = src_regs->srsr;
741 printf("unknown 0x%x", cause);
748 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
753 return cmd_usage(cmdtp);
755 on = (strcmp(argv[1], "on") == 0);
762 lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,