2 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
3 * Copyright (C) Jasbir Matharu
4 * Copyright (C) UDOO Team
6 * Author: Breno Lima <breno.lima@nxp.com>
7 * Author: Francesco Montefoschi <francesco.monte@gmail.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
17 #include <asm/imx-common/iomux-v3.h>
19 #include <fsl_esdhc.h>
20 #include <asm/arch/crm_regs.h>
22 #include <asm/arch/sys_proto.h>
24 #include <linux/sizes.h>
27 DECLARE_GLOBAL_DATA_PTR;
31 UDOO_NEO_TYPE_BASIC_KS,
33 UDOO_NEO_TYPE_EXTENDED,
36 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
38 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
41 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
42 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
47 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
48 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
50 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
55 gd->ram_size = imx_ddr_size();
59 static iomux_v3_cfg_t const uart1_pads[] = {
60 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
61 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
64 static iomux_v3_cfg_t const usdhc2_pads[] = {
65 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
66 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
67 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
74 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
77 static iomux_v3_cfg_t const board_recognition_pads[] = {
79 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
81 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
84 static iomux_v3_cfg_t const usdhc3_pads[] = {
85 /* Configured for WLAN */
86 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 static iomux_v3_cfg_t const wdog_b_pad = {
95 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
98 static iomux_v3_cfg_t const peri_3v3_pads[] = {
99 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
102 static void setup_iomux_uart(void)
104 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
109 /* Address of boot parameters */
110 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
113 * Because kernel set WDOG_B mux before pad with the commone pinctrl
114 * framwork now and wdog reset will be triggered once set WDOG_B mux
115 * with default pad setting, we set pad setting here to workaround this.
116 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
117 * as GPIO mux firstly here to workaround it.
119 imx_iomux_v3_setup_pad(wdog_b_pad);
121 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
122 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
123 ARRAY_SIZE(peri_3v3_pads));
125 /* Active high for ncp692 */
126 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
131 static int get_board_value(void)
135 imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
136 ARRAY_SIZE(board_recognition_pads));
138 gpio_direction_input(IMX_GPIO_NR(4, 13));
139 gpio_direction_input(IMX_GPIO_NR(4, 0));
141 r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
142 r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
145 * Machine selection -
147 * ---------------------------------
154 return (r184 << 1) + r185;
157 int board_early_init_f(void)
164 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
165 {USDHC2_BASE_ADDR, 0, 4},
166 {USDHC3_BASE_ADDR, 0, 4},
169 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
170 #define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
172 int board_mmc_getcd(struct mmc *mmc)
174 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
177 switch (cfg->esdhc_base) {
178 case USDHC2_BASE_ADDR:
179 ret = !gpio_get_value(USDHC2_CD_GPIO);
186 int board_mmc_init(bd_t *bis)
188 #ifndef CONFIG_SPL_BUILD
192 * According to the board_mmc_init() the following map is done:
193 * (U-boot device node) (Physical Port)
196 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
199 imx_iomux_v3_setup_multiple_pads(
200 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
201 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
202 gpio_direction_input(USDHC2_CD_GPIO);
203 gpio_direction_output(USDHC2_PWR_GPIO, 1);
206 imx_iomux_v3_setup_multiple_pads(
207 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
208 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
211 printf("Warning: you configured more USDHC controllers\
212 (%d) than supported by the board\n", i + 1);
216 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
219 failed to initialize mmc dev %d\n", i);
226 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
230 val = readl(&src_regs->sbmr1);
232 if ((val & 0xc0) != 0x40) {
233 printf("Not boot from USDHC!\n");
237 port = (val >> 11) & 0x3;
238 printf("port %d\n", port);
241 imx_iomux_v3_setup_multiple_pads(
242 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
243 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
244 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
245 gpio_direction_input(USDHC2_CD_GPIO);
246 gpio_direction_output(USDHC2_PWR_GPIO, 1);
249 imx_iomux_v3_setup_multiple_pads(
250 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
251 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
252 usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
256 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
257 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
261 char *board_string(void)
263 switch (get_board_value()) {
264 case UDOO_NEO_TYPE_BASIC:
266 case UDOO_NEO_TYPE_BASIC_KS:
268 case UDOO_NEO_TYPE_FULL:
270 case UDOO_NEO_TYPE_EXTENDED:
278 printf("Board: UDOO Neo %s\n", board_string());
282 int board_late_init(void)
284 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
285 setenv("board_name", board_string());
291 #ifdef CONFIG_SPL_BUILD
294 #include <asm/arch/mx6-ddr.h>
296 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
297 .dram_dqm0 = 0x00000028,
298 .dram_dqm1 = 0x00000028,
299 .dram_dqm2 = 0x00000028,
300 .dram_dqm3 = 0x00000028,
301 .dram_ras = 0x00000020,
302 .dram_cas = 0x00000020,
303 .dram_odt0 = 0x00000020,
304 .dram_odt1 = 0x00000020,
305 .dram_sdba2 = 0x00000000,
306 .dram_sdcke0 = 0x00003000,
307 .dram_sdcke1 = 0x00003000,
308 .dram_sdclk_0 = 0x00000030,
309 .dram_sdqs0 = 0x00000028,
310 .dram_sdqs1 = 0x00000028,
311 .dram_sdqs2 = 0x00000028,
312 .dram_sdqs3 = 0x00000028,
313 .dram_reset = 0x00000020,
316 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
317 .grp_addds = 0x00000020,
318 .grp_ddrmode_ctl = 0x00020000,
319 .grp_ddrpke = 0x00000000,
320 .grp_ddrmode = 0x00020000,
321 .grp_b0ds = 0x00000028,
322 .grp_b1ds = 0x00000028,
323 .grp_ctlds = 0x00000020,
324 .grp_ddr_type = 0x000c0000,
325 .grp_b2ds = 0x00000028,
326 .grp_b3ds = 0x00000028,
329 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
330 .p0_mpwldectrl0 = 0x000E000B,
331 .p0_mpwldectrl1 = 0x000E0010,
332 .p0_mpdgctrl0 = 0x41600158,
333 .p0_mpdgctrl1 = 0x01500140,
334 .p0_mprddlctl = 0x3A383E3E,
335 .p0_mpwrdlctl = 0x3A383C38,
338 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
339 .p0_mpwldectrl0 = 0x001E0022,
340 .p0_mpwldectrl1 = 0x001C0019,
341 .p0_mpdgctrl0 = 0x41540150,
342 .p0_mpdgctrl1 = 0x01440138,
343 .p0_mprddlctl = 0x403E4644,
344 .p0_mpwrdlctl = 0x3C3A4038,
348 static struct mx6_ddr3_cfg neo_mem_ddr = {
362 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
375 static void ccgr_init(void)
377 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
379 writel(0xFFFFFFFF, &ccm->CCGR0);
380 writel(0xFFFFFFFF, &ccm->CCGR1);
381 writel(0xFFFFFFFF, &ccm->CCGR2);
382 writel(0xFFFFFFFF, &ccm->CCGR3);
383 writel(0xFFFFFFFF, &ccm->CCGR4);
384 writel(0xFFFFFFFF, &ccm->CCGR5);
385 writel(0xFFFFFFFF, &ccm->CCGR6);
386 writel(0xFFFFFFFF, &ccm->CCGR7);
389 static void spl_dram_init(void)
391 int board = get_board_value();
393 struct mx6_ddr_sysinfo sysinfo = {
394 .dsize = 1, /* width of data bus: 1 = 32 bits */
399 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
400 .walat = 1, /* Write additional latency */
401 .ralat = 5, /* Read additional latency */
402 .mif3_mode = 3, /* Command prediction working mode */
403 .bi_on = 1, /* Bank interleaving enabled */
404 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
405 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
408 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
409 if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
410 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
413 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
416 void board_init_f(ulong dummy)
420 /* setup AIPS and disable watchdog */
423 board_early_init_f();
428 /* UART clocks enabled and gd valid - init serial console */
429 preloader_console_init();
431 /* DDR initialization */
435 memset(__bss_start, 0, __bss_end - __bss_start);
437 /* load/boot image from boot device */
438 board_init_r(NULL, 0);