git.sur5r.net Git - u-boot/blob - board/varisys/cyrus/tlb.c

   1 /*
   2  * Author: Adrian Cox
   3  * Based on corenet_ds tlb code
   4  *
   5  * SPDX-License-Identifier:    GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/mmu.h>
  10
  11 struct fsl_e_tlb_entry tlb_table[] = {
  12         /* TLB 0 - for temp stack in cache */
  13         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  14                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  15                       MAS3_SW|MAS3_SR, 0,
  16                       0, 0, BOOKE_PAGESZ_4K, 0),
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  19                       MAS3_SW|MAS3_SR, 0,
  20                       0, 0, BOOKE_PAGESZ_4K, 0),
  21         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  22                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  23                       MAS3_SW|MAS3_SR, 0,
  24                       0, 0, BOOKE_PAGESZ_4K, 0),
  25         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  26                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  27                       MAS3_SW|MAS3_SR, 0,
  28                       0, 0, BOOKE_PAGESZ_4K, 0),
  29
  30         /* TLB 1 */
  31         /* *I*** - Covers boot page */
  32 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  33         /*
  34          * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  35          * SRAM is at 0xfff00000, it covered the 0xfffff000.
  36          */
  37         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  38                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  39                         0, 0, BOOKE_PAGESZ_1M, 1),
  40 #else
  41         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  42                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  43                       0, 0, BOOKE_PAGESZ_4K, 1),
  44 #endif
  45
  46         /* *I*G* - CCSRBAR */
  47         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  48                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49                       0, 1, BOOKE_PAGESZ_16M, 1),
  50
  51         /* Local Bus */
  52         SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS,
  53                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                       0, 2, BOOKE_PAGESZ_64K, 1),
  55         SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS,
  56                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57                       0, 3, BOOKE_PAGESZ_4K, 1),
  58
  59         /* *I*G* - PCI */
  60         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  61                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  62                       0, 4, BOOKE_PAGESZ_1G, 1),
  63
  64         /* *I*G* - PCI */
  65         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  66                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  67                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68                       0, 5, BOOKE_PAGESZ_256M, 1),
  69
  70         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  71                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  72                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73                       0, 6, BOOKE_PAGESZ_256M, 1),
  74
  75         /* *I*G* - PCI I/O */
  76         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  77                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  78                       0, 7, BOOKE_PAGESZ_256K, 1),
  79
  80         /* Bman/Qman */
  81 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  82         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  83                       MAS3_SW|MAS3_SR, 0,
  84                       0, 9, BOOKE_PAGESZ_1M, 1),
  85         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
  86                       CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
  87                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88                       0, 10, BOOKE_PAGESZ_1M, 1),
  89 #endif
  90 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  91         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  92                       MAS3_SW|MAS3_SR, 0,
  93                       0, 11, BOOKE_PAGESZ_1M, 1),
  94         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
  95                       CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
  96                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  97                       0, 12, BOOKE_PAGESZ_1M, 1),
  98 #endif
  99 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 100         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 101                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 102                       0, 13, BOOKE_PAGESZ_4M, 1),
 103 #endif
 104 };
 105
 106 int num_tlb_entries = ARRAY_SIZE(tlb_table);