2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
4 * Author: Scott Wood <scottwood@freescale.com>
7 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/bitops.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 extern void disable_addr_trans (void);
41 extern void enable_addr_trans (void);
45 puts("Board: ve8313\n");
49 static long fixed_sdram(void)
51 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
53 #ifndef CONFIG_SYS_RAMBOOT
54 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
55 u32 msize_log2 = __ilog2(msize);
57 out_be32(&im->sysconf.ddrlaw[0].bar,
58 (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
59 out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
60 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
63 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
64 * or the DDR2 controller may fail to initialize correctly.
68 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
69 #warning Chip select bounds is only configurable in 16MB increments
71 out_be32(&im->ddr.csbnds[0].csbnds,
72 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
73 (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
75 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
77 /* Currently we use only one CS, so disable the other bank. */
78 out_be32(&im->ddr.cs_config[1], 0);
80 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
81 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
82 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
83 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
84 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
86 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
88 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
89 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
90 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
92 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
95 /* enable DDR controller */
96 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
98 /* now check the real size */
99 disable_addr_trans ();
100 msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
101 enable_addr_trans ();
107 phys_size_t initdram(int board_type)
109 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
110 volatile fsl_lbc_t *lbc = &im->im_lbc;
113 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
116 /* DDR SDRAM - Main SODIMM */
117 msize = fixed_sdram();
119 /* Local Bus setup lbcr and mrtpr */
120 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
121 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
124 /* return total bus SDRAM size(bytes) -- DDR */
128 #define VE8313_WDT_EN 0x00020000
129 #define VE8313_WDT_TRIG 0x00040000
131 int board_early_init_f (void)
133 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
134 volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
136 #if defined(CONFIG_HW_WATCHDOG)
138 clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
141 setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
143 /* set WDT pins as output */
144 setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
149 #if defined(CONFIG_HW_WATCHDOG)
150 void hw_watchdog_reset(void)
152 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
153 volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
156 reg = in_be32(&gpio->dat);
157 if (reg & VE8313_WDT_TRIG)
158 clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
160 setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
165 #if defined(CONFIG_PCI)
166 static struct pci_region pci_regions[] = {
168 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
169 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
170 size: CONFIG_SYS_PCI1_MEM_SIZE,
171 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
174 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
175 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
176 size: CONFIG_SYS_PCI1_MMIO_SIZE,
177 flags: PCI_REGION_MEM
180 bus_start: CONFIG_SYS_PCI1_IO_BASE,
181 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
182 size: CONFIG_SYS_PCI1_IO_SIZE,
187 void pci_init_board(void)
189 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
190 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
191 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
192 struct pci_region *reg[] = { pci_regions };
194 /* Enable all 3 PCI_CLK_OUTPUTs. */
195 setbits_be32(&clk->occr, 0xe0000000);
198 * Configure PCI Local Access Windows
200 out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
201 out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
203 out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
204 out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
206 mpc83xx_pci_init(1, reg);
210 #if defined(CONFIG_OF_BOARD_SETUP)
211 void ft_board_setup(void *blob, bd_t *bd)
213 ft_cpu_setup(blob, bd);
215 ft_pci_setup(blob, bd);