2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
5 #include <asm/ppc4xx.h>
7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
9 #include <ppc_asm.tmpl>
12 #include <asm/cache.h>
15 /******************************************************************************
16 * Function: ext_bus_cntlr_init
18 * Description: Configures EBC Controller and a few basic chip selects.
20 * CS0 is setup to get the Boot Flash out of the addresss range
21 * so that we may setup a stack. CS7 is setup so that we can
22 * access and reset the hardware watchdog.
24 * IMPORTANT: For pass1 this code must run from
25 * cache since you can not reliably change a peripheral banks
26 * timing register (pbxap) while running code from that bank.
27 * For ex., since we are running from ROM on bank 0, we can NOT
28 * execute the code that modifies bank 0 timings from ROM, so
29 * we run it from cache.
31 * Notes: Does NOT use the stack.
32 *****************************************************************************/
35 .globl ext_bus_cntlr_init
36 .type ext_bus_cntlr_init, @function
39 /********************************************************************
40 * Prefetch entire ext_bus_cntrl_init function into the icache.
41 * This is necessary because we are going to change the same CS we
42 * are executing from. Otherwise a CPU lockup may occur.
43 *******************************************************************/
46 mflr r3 /* get address of ..getAddr */
48 /* Calculate number of cache lines for this function */
49 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
52 icbt r0, r3 /* prefetch cache line for addr in r3*/
53 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
54 bdnz ..ebcloop /* continue for $CTR cache lines */
56 /********************************************************************
57 * Delay to ensure all accesses to ROM are complete before changing
58 * bank 0 timings. 200usec should be enough.
59 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
60 *******************************************************************/
62 ori r3, r3, 0xA000 /* wait 200us from reset */
65 bdnz ..spinlp /* spin loop */
67 /********************************************************************
68 * Setup External Bus Controller (EBC).
69 *******************************************************************/
71 mtdcr EBC0_CFGADDR, r3
72 addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
73 ori r4, r4, 0x0 /* Drive CS with external master */
74 mtdcr EBC0_CFGDATA, r4
76 /********************************************************************
77 * Change PCIINT signal to PerWE
78 *******************************************************************/
83 /********************************************************************
84 * Memory Bank 0 (Flash Bank 0) initialization
85 *******************************************************************/
87 mtdcr EBC0_CFGADDR, r3
88 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
89 ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
90 mtdcr EBC0_CFGDATA, r4
93 mtdcr EBC0_CFGADDR, r3
94 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
95 ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
96 mtdcr EBC0_CFGDATA, r4
98 /********************************************************************
99 * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
100 *******************************************************************/
102 mtdcr EBC0_CFGADDR, r3
103 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
104 ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
105 mtdcr EBC0_CFGDATA, r4
108 mtdcr EBC0_CFGADDR, r3
109 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
110 ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
111 mtdcr EBC0_CFGDATA, r4
113 /* We are all done */
114 mtlr r0 /* Restore link register */
115 blr /* Return to calling function */
116 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
117 /* end ext_bus_cntlr_init() */
119 /******************************************************************************
120 * Function: sdram_init
122 * Description: Configures SDRAM memory banks.
124 * Serial Presence Detect, "SPD," reads the SDRAM EEPROM
125 * via the IIC bus and then configures the SDRAM memory
126 * banks appropriately. If Auto Memory Configuration is
127 * is not used, it is assumed that a 4MB 11x8x2, non-ECC,
128 * SDRAM is soldered down.
130 * Notes: Expects that the stack is already setup.
131 *****************************************************************************/
135 .type sdram_init, @function
137 /* save the return info on stack */
138 mflr r0 /* Get link register */
139 stwu r1, -8(r1) /* Save back chain and move SP */
140 stw r0, +12(r1) /* Save link register */
143 * First call spd_sdram to try to init SDRAM according to the
144 * contents of the SPD EEPROM. If the SPD EEPROM is blank or
145 * erronious, spd_sdram returns 0 in R3.
149 addic. r3, r3, 0 /* Check for error, save dram size */
150 bne ..sdri_done /* If it worked, we're done... */
152 /********************************************************************
153 * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
154 * is the SMALLEST SDRAM size the 405 supports. We can do this
155 * because W7O boards have soldered on RAM, and there will always
156 * be some amount present. If we were using DIMMs, we should hang
157 * the board instead, since it doesn't have any RAM to continue
159 *******************************************************************/
162 * Disable memory controller to allow
163 * values to be changed.
165 addi r3, 0, SDRAM0_CFG
166 mtdcr SDRAM0_CFGADDR, r3
169 mtdcr SDRAM0_CFGDATA, r4
172 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
173 * All other banks are disabled.
175 addi r3, 0, SDRAM0_B0CR
176 mtdcr SDRAM0_CFGADDR, r3
177 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
178 ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
179 mtdcr SDRAM0_CFGDATA, r4
181 /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
182 addi r4, 0, 0 /* Zero the data reg */
184 addi r3, r3, 4 /* Point to MB1CF reg */
185 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
186 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
188 addi r3, r3, 4 /* Point to MB2CF reg */
189 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
190 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
192 addi r3, r3, 4 /* Point to MB3CF reg */
193 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
194 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
196 /********************************************************************
197 * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
198 * To set the appropriate timings, we assume sdram is
199 * 100MHz (pc100 compliant).
200 *******************************************************************/
205 addi r3, 0, SDRAM0_TR
206 mtdcr SDRAM0_CFGADDR, r3
207 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
209 mtdcr SDRAM0_CFGDATA, r4
214 addi r3, 0, SDRAM0_RTR
215 mtdcr SDRAM0_CFGADDR, r3
216 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
217 mtdcr SDRAM0_CFGDATA, r4
219 /********************************************************************
220 * Delay to ensure 200usec have elapsed since reset. Assume worst
221 * case that the core is running 200Mhz:
222 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
223 *******************************************************************/
225 ori r3, r3, 0xA000 /* Wait 200us from reset */
228 bdnz ..spinlp2 /* spin loop */
230 /********************************************************************
231 * Set memory controller options reg, MCOPT1.
232 *******************************************************************/
233 addi r3, 0, SDRAM0_CFG
234 mtdcr SDRAM0_CFGADDR, r3
235 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
236 ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
237 mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
240 /* restore and return */
241 lwz r0, +12(r1) /* Get saved link register */
242 addi r1, r1, +8 /* Remove frame from stack */
243 mtlr r0 /* Restore link register */
244 blr /* Return to calling function */
245 .Lfe1: .size sdram_init,.Lfe1-sdram_init
246 /* end sdram_init() */