git.sur5r.net Git - u-boot/blob - board/wandboard/wandboard.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2014 O.S. Systems Software LTDA.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <asm/mach-imx/sata.h>
  23 #include <asm/io.h>
  24 #include <linux/sizes.h>
  25 #include <common.h>
  26 #include <fsl_esdhc.h>
  27 #include <mmc.h>
  28 #include <miiphy.h>
  29 #include <netdev.h>
  30 #include <phy.h>
  31 #include <i2c.h>
  32 #include <power/pmic.h>
  33 #include <power/pfuze100_pmic.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  42         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  50         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  51
  52 #define USDHC1_CD_GPIO          IMX_GPIO_NR(1, 2)
  53 #define USDHC3_CD_GPIO          IMX_GPIO_NR(3, 9)
  54 #define ETH_PHY_RESET           IMX_GPIO_NR(3, 29)
  55 #define ETH_PHY_AR8035_POWER    IMX_GPIO_NR(7, 13)
  56 #define REV_DETECTION           IMX_GPIO_NR(2, 28)
  57
  58 static bool with_pmic;
  59
  60 int dram_init(void)
  61 {
  62         gd->ram_size = imx_ddr_size();
  63
  64         return 0;
  65 }
  66
  67 static iomux_v3_cfg_t const uart1_pads[] = {
  68         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  69         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  70 };
  71
  72 static iomux_v3_cfg_t const usdhc1_pads[] = {
  73         IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74         IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75         IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76         IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77         IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78         IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  79         /* Carrier MicroSD Card Detect */
  80         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81 };
  82
  83 static iomux_v3_cfg_t const usdhc3_pads[] = {
  84         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  86         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  87         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  88         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  89         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  90         /* SOM MicroSD Card Detect */
  91         IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92 };
  93
  94 static iomux_v3_cfg_t const enet_pads[] = {
  95         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  97         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  99         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 100         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 101         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 102         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 103         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 104         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 105         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 106         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 107         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 108         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 109         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 110         /* AR8031 PHY Reset */
 111         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 112 };
 113
 114 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
 115         /* AR8035 POWER */
 116         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 117 };
 118
 119 static iomux_v3_cfg_t const rev_detection_pad[] = {
 120         IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 121 };
 122
 123 static void setup_iomux_uart(void)
 124 {
 125         SETUP_IOMUX_PADS(uart1_pads);
 126 }
 127
 128 static void setup_iomux_enet(void)
 129 {
 130         SETUP_IOMUX_PADS(enet_pads);
 131
 132         if (with_pmic) {
 133                 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
 134                 /* enable AR8035 POWER */
 135                 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
 136         }
 137         /* wait until 3.3V of PHY and clock become stable */
 138         mdelay(10);
 139
 140         /* Reset AR8031 PHY */
 141         gpio_direction_output(ETH_PHY_RESET, 0);
 142         mdelay(10);
 143         gpio_set_value(ETH_PHY_RESET, 1);
 144         udelay(100);
 145 }
 146
 147 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 148         {USDHC3_BASE_ADDR},
 149         {USDHC1_BASE_ADDR},
 150 };
 151
 152 int board_mmc_getcd(struct mmc *mmc)
 153 {
 154         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 155         int ret = 0;
 156
 157         switch (cfg->esdhc_base) {
 158         case USDHC1_BASE_ADDR:
 159                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 160                 break;
 161         case USDHC3_BASE_ADDR:
 162                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 163                 break;
 164         }
 165
 166         return ret;
 167 }
 168
 169 int board_mmc_init(bd_t *bis)
 170 {
 171         int ret;
 172         u32 index = 0;
 173
 174         /*
 175          * Following map is done:
 176          * (U-Boot device node)    (Physical Port)
 177          * mmc0                    SOM MicroSD
 178          * mmc1                    Carrier board MicroSD
 179          */
 180         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 181                 switch (index) {
 182                 case 0:
 183                         SETUP_IOMUX_PADS(usdhc3_pads);
 184                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 185                         usdhc_cfg[0].max_bus_width = 4;
 186                         gpio_direction_input(USDHC3_CD_GPIO);
 187                         break;
 188                 case 1:
 189                         SETUP_IOMUX_PADS(usdhc1_pads);
 190                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 191                         usdhc_cfg[1].max_bus_width = 4;
 192                         gpio_direction_input(USDHC1_CD_GPIO);
 193                         break;
 194                 default:
 195                         printf("Warning: you configured more USDHC controllers"
 196                                "(%d) then supported by the board (%d)\n",
 197                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 198                         return -EINVAL;
 199                 }
 200
 201                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 202                 if (ret)
 203                         return ret;
 204         }
 205
 206         return 0;
 207 }
 208
 209 static int ar8031_phy_fixup(struct phy_device *phydev)
 210 {
 211         unsigned short val;
 212         int mask;
 213
 214         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 215         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 216         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 217         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 218
 219         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 220         if (with_pmic)
 221                 mask = 0xffe7;  /* AR8035 */
 222         else
 223                 mask = 0xffe3;  /* AR8031 */
 224
 225         val &= mask;
 226         val |= 0x18;
 227         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 228
 229         /* introduce tx clock delay */
 230         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 231         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 232         val |= 0x0100;
 233         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 234
 235         return 0;
 236 }
 237
 238 int board_phy_config(struct phy_device *phydev)
 239 {
 240         ar8031_phy_fixup(phydev);
 241
 242         if (phydev->drv->config)
 243                 phydev->drv->config(phydev);
 244
 245         return 0;
 246 }
 247
 248 #if defined(CONFIG_VIDEO_IPUV3)
 249 struct i2c_pads_info mx6q_i2c2_pad_info = {
 250         .scl = {
 251                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
 252                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 253                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
 254                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 255                 .gp = IMX_GPIO_NR(4, 12)
 256         },
 257         .sda = {
 258                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
 259                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 260                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
 261                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 262                 .gp = IMX_GPIO_NR(4, 13)
 263         }
 264 };
 265
 266 struct i2c_pads_info mx6dl_i2c2_pad_info = {
 267         .scl = {
 268                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
 269                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 270                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
 271                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 272                 .gp = IMX_GPIO_NR(4, 12)
 273         },
 274         .sda = {
 275                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
 276                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 277                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
 278                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 279                 .gp = IMX_GPIO_NR(4, 13)
 280         }
 281 };
 282
 283 struct i2c_pads_info mx6q_i2c3_pad_info = {
 284         .scl = {
 285                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
 286                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 287                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
 288                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 289                 .gp = IMX_GPIO_NR(1, 5)
 290         },
 291         .sda = {
 292                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
 293                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 294                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
 295                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 296                 .gp = IMX_GPIO_NR(7, 11)
 297         }
 298 };
 299
 300 struct i2c_pads_info mx6dl_i2c3_pad_info = {
 301         .scl = {
 302                 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
 303                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 304                 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
 305                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 306                 .gp = IMX_GPIO_NR(1, 5)
 307         },
 308         .sda = {
 309                 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
 310                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 311                 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
 312                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 313                 .gp = IMX_GPIO_NR(7, 11)
 314         }
 315 };
 316
 317 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
 318         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 319         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
 320         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
 321         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
 322         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
 323         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
 324         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
 325         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
 326         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
 327         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
 328         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
 329         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
 330         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
 331         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
 332         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
 333         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
 334         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
 335         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
 336         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
 337         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
 338         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
 339         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
 340         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
 341         IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
 342         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
 343 };
 344
 345 static void do_enable_hdmi(struct display_info_t const *dev)
 346 {
 347         imx_enable_hdmi_phy();
 348 }
 349
 350 static int detect_i2c(struct display_info_t const *dev)
 351 {
 352         return (0 == i2c_set_bus_num(dev->bus)) &&
 353                         (0 == i2c_probe(dev->addr));
 354 }
 355
 356 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 357 {
 358         SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 359
 360         gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 361         gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 362 }
 363
 364 struct display_info_t const displays[] = {{
 365         .bus    = -1,
 366         .addr   = 0,
 367         .pixfmt = IPU_PIX_FMT_RGB24,
 368         .detect = detect_hdmi,
 369         .enable = do_enable_hdmi,
 370         .mode   = {
 371                 .name           = "HDMI",
 372                 .refresh        = 60,
 373                 .xres           = 1024,
 374                 .yres           = 768,
 375                 .pixclock       = 15385,
 376                 .left_margin    = 220,
 377                 .right_margin   = 40,
 378                 .upper_margin   = 21,
 379                 .lower_margin   = 7,
 380                 .hsync_len      = 60,
 381                 .vsync_len      = 10,
 382                 .sync           = FB_SYNC_EXT,
 383                 .vmode          = FB_VMODE_NONINTERLACED
 384 } }, {
 385         .bus    = 1,
 386         .addr   = 0x10,
 387         .pixfmt = IPU_PIX_FMT_RGB666,
 388         .detect = detect_i2c,
 389         .enable = enable_fwadapt_7wvga,
 390         .mode   = {
 391                 .name           = "FWBADAPT-LCD-F07A-0102",
 392                 .refresh        = 60,
 393                 .xres           = 800,
 394                 .yres           = 480,
 395                 .pixclock       = 33260,
 396                 .left_margin    = 128,
 397                 .right_margin   = 128,
 398                 .upper_margin   = 22,
 399                 .lower_margin   = 22,
 400                 .hsync_len      = 1,
 401                 .vsync_len      = 1,
 402                 .sync           = 0,
 403                 .vmode          = FB_VMODE_NONINTERLACED
 404 } } };
 405 size_t display_count = ARRAY_SIZE(displays);
 406
 407 static void setup_display(void)
 408 {
 409         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 410         int reg;
 411
 412         enable_ipu_clock();
 413         imx_setup_hdmi();
 414
 415         reg = readl(&mxc_ccm->chsccdr);
 416         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 417                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 418         writel(reg, &mxc_ccm->chsccdr);
 419
 420         /* Disable LCD backlight */
 421         SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
 422         gpio_direction_input(IMX_GPIO_NR(4, 20));
 423 }
 424 #endif /* CONFIG_VIDEO_IPUV3 */
 425
 426 int board_eth_init(bd_t *bis)
 427 {
 428         setup_iomux_enet();
 429
 430         return cpu_eth_init(bis);
 431 }
 432
 433 int board_early_init_f(void)
 434 {
 435         setup_iomux_uart();
 436 #ifdef CONFIG_SATA
 437         setup_sata();
 438 #endif
 439
 440         return 0;
 441 }
 442
 443 #define PMIC_I2C_BUS            2
 444
 445 int power_init_board(void)
 446 {
 447         struct pmic *p;
 448         u32 reg;
 449
 450         /* configure PFUZE100 PMIC */
 451         power_pfuze100_init(PMIC_I2C_BUS);
 452         p = pmic_get("PFUZE100");
 453         if (p && !pmic_probe(p)) {
 454                 pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 455                 printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 456                 with_pmic = true;
 457
 458                 /* Set VGEN2 to 1.5V and enable */
 459                 pmic_reg_read(p, PFUZE100_VGEN2VOL, &reg);
 460                 reg &= ~(LDO_VOL_MASK);
 461                 reg |= (LDOA_1_50V | (1 << (LDO_EN)));
 462                 pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
 463         }
 464
 465         return 0;
 466 }
 467
 468 /*
 469  * Do not overwrite the console
 470  * Use always serial for U-Boot console
 471  */
 472 int overwrite_console(void)
 473 {
 474         return 1;
 475 }
 476
 477 #ifdef CONFIG_CMD_BMODE
 478 static const struct boot_mode board_boot_modes[] = {
 479         /* 4 bit bus width */
 480         {"mmc0",          MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 481         {"mmc1",          MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 482         {NULL,   0},
 483 };
 484 #endif
 485
 486 static bool is_revc1(void)
 487 {
 488         SETUP_IOMUX_PADS(rev_detection_pad);
 489         gpio_direction_input(REV_DETECTION);
 490
 491         if (gpio_get_value(REV_DETECTION))
 492                 return true;
 493         else
 494                 return false;
 495 }
 496
 497 static bool is_revd1(void)
 498 {
 499         if (with_pmic)
 500                 return true;
 501         else
 502                 return false;
 503 }
 504
 505 int board_late_init(void)
 506 {
 507 #ifdef CONFIG_CMD_BMODE
 508         add_board_boot_modes(board_boot_modes);
 509 #endif
 510
 511 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 512         if (is_mx6dqp())
 513                 env_set("board_rev", "MX6QP");
 514         else if (is_mx6dq())
 515                 env_set("board_rev", "MX6Q");
 516         else
 517                 env_set("board_rev", "MX6DL");
 518
 519         if (is_revd1())
 520                 env_set("board_name", "D1");
 521         else if (is_revc1())
 522                 env_set("board_name", "C1");
 523         else
 524                 env_set("board_name", "B1");
 525 #endif
 526         return 0;
 527 }
 528
 529 int board_init(void)
 530 {
 531         /* address of boot parameters */
 532         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 533
 534 #if defined(CONFIG_VIDEO_IPUV3)
 535         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 536         if (is_mx6dq() || is_mx6dqp()) {
 537                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 538                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
 539         } else {
 540                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 541                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
 542         }
 543
 544         setup_display();
 545 #endif
 546
 547         return 0;
 548 }
 549
 550 int checkboard(void)
 551 {
 552         if (is_revd1())
 553                 puts("Board: Wandboard rev D1\n");
 554         else if (is_revc1())
 555                 puts("Board: Wandboard rev C1\n");
 556         else
 557                 puts("Board: Wandboard rev B1\n");
 558
 559         return 0;
 560 }