git.sur5r.net Git - u-boot/blob - board/warp7/warp7.c

   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors
   3  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx7-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/mach-imx/hab.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/mxc_i2c.h>
  16 #include <asm/io.h>
  17 #include <common.h>
  18 #include <fsl_esdhc.h>
  19 #include <i2c.h>
  20 #include <mmc.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <usb.h>
  23 #include <netdev.h>
  24 #include <power/pmic.h>
  25 #include <power/pfuze3000_pmic.h>
  26 #include "../freescale/common/pfuze.h"
  27 #include <asm/setup.h>
  28 #include <asm/bootm.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
  33                         PAD_CTL_HYS)
  34 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW |     \
  35                         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  36
  37 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  38         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  39
  40 #ifdef CONFIG_SYS_I2C_MXC
  41 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  42 /* I2C1 for PMIC */
  43 static struct i2c_pads_info i2c_pad_info1 = {
  44         .scl = {
  45                 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
  46                 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
  47                 .gp = IMX_GPIO_NR(4, 8),
  48         },
  49         .sda = {
  50                 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
  51                 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
  52                 .gp = IMX_GPIO_NR(4, 9),
  53         },
  54 };
  55 #endif
  56
  57 int dram_init(void)
  58 {
  59         gd->ram_size = PHYS_SDRAM_SIZE;
  60
  61         return 0;
  62 }
  63
  64 static iomux_v3_cfg_t const wdog_pads[] = {
  65         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  66 };
  67
  68 static iomux_v3_cfg_t const uart1_pads[] = {
  69         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  70         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  71 };
  72
  73 static iomux_v3_cfg_t const usdhc3_pads[] = {
  74         MX7D_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX7D_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85 };
  86
  87 static void setup_iomux_uart(void)
  88 {
  89         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  90 };
  91
  92 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  93         {USDHC3_BASE_ADDR},
  94 };
  95
  96 int board_mmc_getcd(struct mmc *mmc)
  97 {
  98                 /* Assume uSDHC3 emmc is always present */
  99                 return 1;
 100 }
 101
 102 int board_mmc_init(bd_t *bis)
 103 {
 104         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 105         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 106
 107         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 108 }
 109
 110 int board_early_init_f(void)
 111 {
 112         setup_iomux_uart();
 113
 114         return 0;
 115 }
 116
 117 #ifdef CONFIG_POWER
 118 #define I2C_PMIC       0
 119 static struct pmic *pfuze;
 120 int power_init_board(void)
 121 {
 122         int ret;
 123         unsigned int reg, rev_id;
 124
 125         ret = power_pfuze3000_init(I2C_PMIC);
 126         if (ret)
 127                 return ret;
 128
 129         pfuze = pmic_get("PFUZE3000");
 130         ret = pmic_probe(pfuze);
 131         if (ret)
 132                 return ret;
 133
 134         pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
 135         pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
 136         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 137
 138         /* disable Low Power Mode during standby mode */
 139         pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
 140
 141         return 0;
 142 }
 143 #endif
 144
 145 int board_eth_init(bd_t *bis)
 146 {
 147         int ret = 0;
 148
 149 #ifdef CONFIG_USB_ETHER
 150         ret = usb_eth_initialize(bis);
 151         if (ret < 0)
 152                 printf("Error %d registering USB ether.\n", ret);
 153 #endif
 154
 155         return ret;
 156 }
 157
 158 int board_init(void)
 159 {
 160         /* address of boot parameters */
 161         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 162
 163         #ifdef CONFIG_SYS_I2C_MXC
 164                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 165         #endif
 166
 167         return 0;
 168 }
 169
 170 int checkboard(void)
 171 {
 172         char *mode;
 173
 174         if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
 175                 mode = "secure";
 176         else
 177                 mode = "non-secure";
 178
 179         printf("Board: WARP7 in %s mode\n", mode);
 180
 181         return 0;
 182 }
 183
 184 int board_usb_phy_mode(int port)
 185 {
 186         return USB_INIT_DEVICE;
 187 }
 188
 189 int board_late_init(void)
 190 {
 191         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 192 #ifdef CONFIG_SERIAL_TAG
 193         struct tag_serialnr serialnr;
 194         char serial_string[0x20];
 195 #endif
 196
 197         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 198
 199         set_wdog_reset(wdog);
 200
 201         /*
 202          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 203          * since we use PMIC_PWRON to reset the board.
 204          */
 205         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 206
 207 #ifdef CONFIG_SECURE_BOOT
 208         /* Determine HAB state */
 209         env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
 210 #else
 211         env_set_ulong(HAB_ENABLED_ENVNAME, 0);
 212 #endif
 213
 214 #ifdef CONFIG_SERIAL_TAG
 215         /* Set serial# standard environment variable based on OTP settings */
 216         get_board_serial(&serialnr);
 217         snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
 218                  serialnr.low, serialnr.high);
 219         env_set("serial#", serial_string);
 220 #endif
 221
 222         return 0;
 223 }