git.sur5r.net Git - u-boot/blob - board/warp7/warp7.c

   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors
   3  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx7-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/imx-common/iomux-v3.h>
  14 #include <asm/io.h>
  15 #include <common.h>
  16 #include <fsl_esdhc.h>
  17 #include <mmc.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <usb.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
  24                         PAD_CTL_HYS)
  25 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW |     \
  26                         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  27
  28 int dram_init(void)
  29 {
  30         gd->ram_size = PHYS_SDRAM_SIZE;
  31
  32         return 0;
  33 }
  34
  35 static iomux_v3_cfg_t const wdog_pads[] = {
  36         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  37 };
  38
  39 static iomux_v3_cfg_t const uart1_pads[] = {
  40         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  41         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  42 };
  43
  44 static iomux_v3_cfg_t const usdhc3_pads[] = {
  45         MX7D_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  46         MX7D_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  47         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  48         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  49         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  50         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  51         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  52         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  53         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  54         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  55         MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56 };
  57
  58 static void setup_iomux_uart(void)
  59 {
  60         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  61 };
  62
  63 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  64         {USDHC3_BASE_ADDR},
  65 };
  66
  67 int board_mmc_getcd(struct mmc *mmc)
  68 {
  69                 /* Assume uSDHC3 emmc is always present */
  70                 return 1;
  71 }
  72
  73 int board_mmc_init(bd_t *bis)
  74 {
  75         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  76         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  77
  78         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  79 }
  80
  81 int board_early_init_f(void)
  82 {
  83         setup_iomux_uart();
  84
  85         return 0;
  86 }
  87
  88 int board_init(void)
  89 {
  90         /* address of boot parameters */
  91         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  92
  93         return 0;
  94 }
  95
  96 int checkboard(void)
  97 {
  98         puts("Board: WARP7\n");
  99
 100         return 0;
 101 }
 102
 103 int board_usb_phy_mode(int port)
 104 {
 105         return USB_INIT_DEVICE;
 106 }
 107
 108 int board_late_init(void)
 109 {
 110         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 111
 112         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 113
 114         set_wdog_reset(wdog);
 115
 116         /*
 117          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 118          * since we use PMIC_PWRON to reset the board.
 119          */
 120         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 121
 122         return 0;
 123 }