git.sur5r.net Git - u-boot/blob - board/warp7/warp7.c

   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors
   3  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx7-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/imx-common/iomux-v3.h>
  14 #include <asm/io.h>
  15 #include <common.h>
  16 #include <fsl_esdhc.h>
  17 #include <mmc.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <usb.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
  24                         PAD_CTL_HYS)
  25 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW |     \
  26                         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  27
  28 int dram_init(void)
  29 {
  30         gd->ram_size = PHYS_SDRAM_SIZE;
  31
  32         return 0;
  33 }
  34
  35 static iomux_v3_cfg_t const uart1_pads[] = {
  36         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  37         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  38 };
  39
  40 static iomux_v3_cfg_t const usdhc3_pads[] = {
  41         MX7D_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  42         MX7D_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  43         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  44         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  45         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  46         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  47         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  48         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  49         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  50         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  51         MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  52 };
  53
  54 static void setup_iomux_uart(void)
  55 {
  56         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  57 };
  58
  59 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  60         {USDHC3_BASE_ADDR},
  61 };
  62
  63 int board_mmc_getcd(struct mmc *mmc)
  64 {
  65                 /* Assume uSDHC3 emmc is always present */
  66                 return 1;
  67 }
  68
  69 int board_mmc_init(bd_t *bis)
  70 {
  71         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  72         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  73
  74         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  75 }
  76
  77 int board_early_init_f(void)
  78 {
  79         setup_iomux_uart();
  80
  81         return 0;
  82 }
  83
  84 int board_init(void)
  85 {
  86         /* address of boot parameters */
  87         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  88
  89         return 0;
  90 }
  91
  92 int checkboard(void)
  93 {
  94         puts("Board: WARP7\n");
  95
  96         return 0;
  97 }
  98
  99 int board_usb_phy_mode(int port)
 100 {
 101         return USB_INIT_DEVICE;
 102 }