2 * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
4 * Based on flea3.c and mx35pdk.c
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/errno.h>
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/iomux-mx35.h>
33 #include <power/pmic.h>
37 #include <fsl_esdhc.h>
38 #include <linux/types.h>
40 #include <asm/arch/sys_proto.h>
44 #define CCM_CCMR_CONFIG 0x003F4208
46 #define ESDCTL_DDR2_CONFIG 0x007FFC3F
52 DECLARE_GLOBAL_DATA_PTR;
56 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
62 static void board_setup_sdram(void)
64 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
66 /* Initialize with default values both CSD0/1 */
67 writel(0x2000, &esdc->esdctl0);
68 writel(0x2000, &esdc->esdctl1);
70 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
74 static void setup_iomux_fec(void)
76 static const iomux_v3_cfg_t fec_pads[] = {
77 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
78 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
79 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
80 MX35_PAD_FEC_COL__FEC_COL,
81 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
82 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
83 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
84 MX35_PAD_FEC_MDC__FEC_MDC,
85 MX35_PAD_FEC_MDIO__FEC_MDIO,
86 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
87 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
88 MX35_PAD_FEC_CRS__FEC_CRS,
89 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
90 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
91 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
92 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
93 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
94 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
97 /* setup pins for FEC */
98 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
101 int woodburn_init(void)
103 struct ccm_regs *ccm =
104 (struct ccm_regs *)IMX_CCM_BASE;
106 /* initialize PLL and clock configuration */
107 writel(CCM_CCMR_CONFIG, &ccm->ccmr);
113 writel(readl(&ccm->cgr0) |
114 MXC_CCM_CGR0_EMI_MASK |
115 MXC_CCM_CGR0_EDIO_MASK |
116 MXC_CCM_CGR0_EPIT1_MASK,
119 writel(readl(&ccm->cgr1) |
120 MXC_CCM_CGR1_FEC_MASK |
121 MXC_CCM_CGR1_GPIO1_MASK |
122 MXC_CCM_CGR1_GPIO2_MASK |
123 MXC_CCM_CGR1_GPIO3_MASK |
124 MXC_CCM_CGR1_I2C1_MASK |
125 MXC_CCM_CGR1_I2C2_MASK |
126 MXC_CCM_CGR1_I2C3_MASK,
130 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
132 /* Set pinmux for the required peripherals */
135 /* setup GPIO1_4 FEC_ENABLE signal */
136 imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
137 gpio_direction_output(4, 1);
138 imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
139 gpio_direction_output(9, 1);
144 #if defined(CONFIG_SPL_BUILD)
145 void board_init_f(ulong dummy)
147 /* Set the stack pointer. */
148 asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
150 /* Initialize MUX and SDRAM */
154 memset(__bss_start, 0, __bss_end - __bss_start);
156 /* Set global data pointer. */
159 preloader_console_init();
162 board_init_r(NULL, 0);
165 void spl_board_init(void)
172 /* Booting from NOR in external mode */
173 int board_early_init_f(void)
175 return woodburn_init();
185 /* address of boot parameters */
186 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
188 ret = pmic_init(I2C_PMIC);
192 p = pmic_get("FSL_PMIC");
195 * Set switchers in Auto in NORMAL mode & STANDBY mode
196 * Setup the switcher mode for SW1 & SW2
198 pmic_reg_read(p, REG_SW_4, &val);
199 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
200 (SWMODE_MASK << SWMODE2_SHIFT)));
201 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
202 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
205 pmic_reg_write(p, REG_SW_4, val);
207 /* Setup the switcher mode for SW3 & SW4 */
208 pmic_reg_read(p, REG_SW_5, &val);
209 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
210 (SWMODE_MASK << SWMODE3_SHIFT));
211 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
212 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
213 pmic_reg_write(p, REG_SW_5, val);
215 /* Set VGEN1 to 3.15V */
216 pmic_reg_read(p, REG_SETTING_0, &val);
217 val &= ~(VGEN1_MASK);
219 pmic_reg_write(p, REG_SETTING_0, val);
221 pmic_reg_read(p, REG_MODE_0, &val);
223 pmic_reg_write(p, REG_MODE_0, val);
229 #if defined(CONFIG_FSL_ESDHC)
230 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
232 int board_mmc_init(bd_t *bis)
234 static const iomux_v3_cfg_t sdhc1_pads[] = {
235 MX35_PAD_SD1_CMD__ESDHC1_CMD,
236 MX35_PAD_SD1_CLK__ESDHC1_CLK,
237 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
238 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
239 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
240 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
243 /* configure pins for SDHC1 only */
244 imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
246 /* MMC Card Detect on GPIO1_7 */
247 imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
248 gpio_direction_input(GPIO_MMC_CD);
250 /* MMC Write Protection on GPIO1_8 */
251 imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
252 gpio_direction_input(GPIO_MMC_WP);
254 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
256 return fsl_esdhc_initialize(bis, &esdhc_cfg);
259 int board_mmc_getcd(struct mmc *mmc)
261 return !gpio_get_value(GPIO_MMC_CD);
265 u32 get_board_rev(void)
269 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;