2 * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
4 * Based on flea3.c and mx35pdk.c
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/errno.h>
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/mx35_pins.h>
32 #include <asm/arch/iomux.h>
34 #include <power/pmic.h>
38 #include <fsl_esdhc.h>
39 #include <linux/types.h>
41 #include <asm/arch/sys_proto.h>
45 #define CCM_CCMR_CONFIG 0x003F4208
47 #define ESDCTL_DDR2_CONFIG 0x007FFC3F
53 DECLARE_GLOBAL_DATA_PTR;
57 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
63 static void board_setup_sdram(void)
65 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
67 /* Initialize with default values both CSD0/1 */
68 writel(0x2000, &esdc->esdctl0);
69 writel(0x2000, &esdc->esdctl1);
71 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
75 static void setup_iomux_fec(void)
77 /* setup pins for FEC */
78 mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
79 mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
80 mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
81 mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
82 mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
83 mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
84 mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
85 mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
86 mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
87 mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
88 mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
89 mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
90 mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
91 mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
92 mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
93 mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
94 mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
95 mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
98 int woodburn_init(void)
100 struct ccm_regs *ccm =
101 (struct ccm_regs *)IMX_CCM_BASE;
103 /* initialize PLL and clock configuration */
104 writel(CCM_CCMR_CONFIG, &ccm->ccmr);
110 writel(readl(&ccm->cgr0) |
111 MXC_CCM_CGR0_EMI_MASK |
112 MXC_CCM_CGR0_EDIO_MASK |
113 MXC_CCM_CGR0_EPIT1_MASK,
116 writel(readl(&ccm->cgr1) |
117 MXC_CCM_CGR1_FEC_MASK |
118 MXC_CCM_CGR1_GPIO1_MASK |
119 MXC_CCM_CGR1_GPIO2_MASK |
120 MXC_CCM_CGR1_GPIO3_MASK |
121 MXC_CCM_CGR1_I2C1_MASK |
122 MXC_CCM_CGR1_I2C2_MASK |
123 MXC_CCM_CGR1_I2C3_MASK,
127 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
129 /* Set pinmux for the required peripherals */
132 /* setup GPIO1_4 FEC_ENABLE signal */
133 mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
134 gpio_direction_output(4, 1);
135 mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
136 gpio_direction_output(9, 1);
141 #if defined(CONFIG_SPL_BUILD)
142 void board_init_f(ulong dummy)
144 /* Set the stack pointer. */
145 asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
147 /* Initialize MUX and SDRAM */
151 memset(__bss_start, 0, __bss_end__ - __bss_start);
153 /* Set global data pointer. */
156 preloader_console_init();
159 board_init_r(NULL, 0);
162 void spl_board_init(void)
169 /* Booting from NOR in external mode */
170 int board_early_init_f(void)
172 return woodburn_init();
182 /* address of boot parameters */
183 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
185 ret = pmic_init(I2C_PMIC);
189 p = pmic_get("FSL_PMIC");
192 * Set switchers in Auto in NORMAL mode & STANDBY mode
193 * Setup the switcher mode for SW1 & SW2
195 pmic_reg_read(p, REG_SW_4, &val);
196 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
197 (SWMODE_MASK << SWMODE2_SHIFT)));
198 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
199 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
202 pmic_reg_write(p, REG_SW_4, val);
204 /* Setup the switcher mode for SW3 & SW4 */
205 pmic_reg_read(p, REG_SW_5, &val);
206 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
207 (SWMODE_MASK << SWMODE3_SHIFT));
208 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
209 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
210 pmic_reg_write(p, REG_SW_5, val);
212 /* Set VGEN1 to 3.15V */
213 pmic_reg_read(p, REG_SETTING_0, &val);
214 val &= ~(VGEN1_MASK);
216 pmic_reg_write(p, REG_SETTING_0, val);
218 pmic_reg_read(p, REG_MODE_0, &val);
220 pmic_reg_write(p, REG_MODE_0, val);
226 #if defined(CONFIG_FSL_ESDHC)
227 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
229 int board_mmc_init(bd_t *bis)
231 /* configure pins for SDHC1 only */
232 mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
233 mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
234 mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
235 mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
236 mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
237 mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
239 /* MMC Card Detect on GPIO1_7 */
240 mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
241 mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
242 gpio_direction_input(GPIO_MMC_CD);
244 /* MMC Write Protection on GPIO1_8 */
245 mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
246 mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
247 gpio_direction_input(GPIO_MMC_WP);
249 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
251 return fsl_esdhc_initialize(bis, &esdhc_cfg);
254 int board_mmc_getcd(struct mmc *mmc)
256 return !gpio_get_value(GPIO_MMC_CD);
260 u32 get_board_rev(void)
264 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;