2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/immap_85xx.h>
27 #include <asm/fsl_pci.h>
29 #include <fdt_support.h>
31 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
32 extern void fsl_pci_config_unlock(struct pci_controller *hose);
33 extern void fsl_pci_init(struct pci_controller *hose);
35 int first_free_busno = 0;
38 static struct pci_controller pci1_hose;
41 static struct pci_controller pcie1_hose;
44 static struct pci_controller pcie2_hose;
47 static struct pci_controller pcie3_hose;
51 /* Correlate host/agent POR bits to usable info. Table 4-14 */
52 struct host_agent_cfg_t {
55 } host_agent_cfg[8] = {
66 /* Correlate port width POR bits to usable info. Table 4-15 */
67 struct io_port_cfg_t {
88 #elif defined CONFIG_MPC8548
89 /* Correlate host/agent POR bits to usable info. Table 4-12 */
90 struct host_agent_cfg_t {
94 } host_agent_cfg[8] = {
98 {{0, 0}, {0}, 0}, /* reserved */
105 /* Correlate port width POR bits to usable info. Table 4-13 */
106 struct io_port_cfg_t {
121 void pci_init_board(void)
123 struct pci_controller *hose;
124 volatile ccsr_fsl_pci_t *pci;
127 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
128 uint devdisr = gur->devdisr;
129 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
130 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
131 struct pci_region *r;
134 uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
135 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
136 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
137 uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
138 uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
140 width = 0; /* Silence compiler warning... */
141 io_sel &= 0xf; /* Silence compiler warning... */
142 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
144 host = host_agent_cfg[host_agent].pci_host[0];
148 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
149 printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
151 pcix ? "PCIX" : "PCI",
152 pci_spd_norm ? ">=" : "<=",
153 pcix ? freq * 2 : freq,
154 host ? "host" : "agent",
155 pci_arb ? "arbiter" : "external-arbiter");
158 r += fsl_pci_setup_inbound_windows(r);
160 /* outbound memory */
162 CONFIG_SYS_PCI1_MEM_BASE,
163 CONFIG_SYS_PCI1_MEM_PHYS,
164 CONFIG_SYS_PCI1_MEM_SIZE,
169 CONFIG_SYS_PCI1_IO_BASE,
170 CONFIG_SYS_PCI1_IO_PHYS,
171 CONFIG_SYS_PCI1_IO_SIZE,
174 hose->region_count = r - hose->regions;
176 hose->first_busno = first_free_busno;
177 pci_setup_indirect(hose, (int)&pci->cfg_addr,
178 (int)&pci->cfg_data);
182 /* Unlock inbound PCI configuration cycles */
184 fsl_pci_config_unlock(hose);
186 first_free_busno = hose->last_busno + 1;
187 printf(" PCI1 on bus %02x - %02x\n",
188 hose->first_busno, hose->last_busno);
190 printf(" PCI1: disabled\n");
192 #elif defined CONFIG_MPC8548
193 /* PCI1 not present on MPC8572 */
194 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
197 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
199 host = host_agent_cfg[host_agent].pcie_root[0];
200 width = io_port_cfg[io_sel].pcie_width[0];
203 if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
204 printf("\n PCIE1 connected as %s (x%d)",
205 host ? "Root Complex" : "End Point", width);
206 if (pci->pme_msg_det) {
207 pci->pme_msg_det = 0xffffffff;
208 debug(" with errors. Clearing. Now 0x%08x",
214 r += fsl_pci_setup_inbound_windows(r);
216 /* outbound memory */
218 CONFIG_SYS_PCIE1_MEM_BASE,
219 CONFIG_SYS_PCIE1_MEM_PHYS,
220 CONFIG_SYS_PCIE1_MEM_SIZE,
225 CONFIG_SYS_PCIE1_IO_BASE,
226 CONFIG_SYS_PCIE1_IO_PHYS,
227 CONFIG_SYS_PCIE1_IO_SIZE,
230 hose->region_count = r - hose->regions;
232 hose->first_busno = first_free_busno;
233 pci_setup_indirect(hose, (int)&pci->cfg_addr,
234 (int) &pci->cfg_data);
238 /* Unlock inbound PCI configuration cycles */
240 fsl_pci_config_unlock(hose);
242 first_free_busno = hose->last_busno + 1;
243 printf(" PCIE1 on bus %02x - %02x\n",
244 hose->first_busno, hose->last_busno);
247 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
248 #endif /* CONFIG_PCIE1 */
251 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
253 host = host_agent_cfg[host_agent].pcie_root[1];
254 width = io_port_cfg[io_sel].pcie_width[1];
257 if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
258 printf("\n PCIE2 connected as %s (x%d)",
259 host ? "Root Complex" : "End Point", width);
260 if (pci->pme_msg_det) {
261 pci->pme_msg_det = 0xffffffff;
262 debug(" with errors. Clearing. Now 0x%08x",
268 r += fsl_pci_setup_inbound_windows(r);
270 /* outbound memory */
272 CONFIG_SYS_PCIE2_MEM_BASE,
273 CONFIG_SYS_PCIE2_MEM_PHYS,
274 CONFIG_SYS_PCIE2_MEM_SIZE,
279 CONFIG_SYS_PCIE2_IO_BASE,
280 CONFIG_SYS_PCIE2_IO_PHYS,
281 CONFIG_SYS_PCIE2_IO_SIZE,
284 hose->region_count = r - hose->regions;
286 hose->first_busno = first_free_busno;
287 pci_setup_indirect(hose, (int)&pci->cfg_addr,
288 (int)&pci->cfg_data);
292 /* Unlock inbound PCI configuration cycles */
294 fsl_pci_config_unlock(hose);
296 first_free_busno = hose->last_busno + 1;
297 printf(" PCIE2 on bus %02x - %02x\n",
298 hose->first_busno, hose->last_busno);
301 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
302 #endif /* CONFIG_PCIE2 */
305 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
307 host = host_agent_cfg[host_agent].pcie_root[2];
308 width = io_port_cfg[io_sel].pcie_width[2];
311 if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
312 printf("\n PCIE3 connected as %s (x%d)",
313 host ? "Root Complex" : "End Point", width);
314 if (pci->pme_msg_det) {
315 pci->pme_msg_det = 0xffffffff;
316 debug(" with errors. Clearing. Now 0x%08x",
322 r += fsl_pci_setup_inbound_windows(r);
324 /* outbound memory */
326 CONFIG_SYS_PCIE3_MEM_BASE,
327 CONFIG_SYS_PCIE3_MEM_PHYS,
328 CONFIG_SYS_PCIE3_MEM_SIZE,
333 CONFIG_SYS_PCIE3_IO_BASE,
334 CONFIG_SYS_PCIE3_IO_PHYS,
335 CONFIG_SYS_PCIE3_IO_SIZE,
338 hose->region_count = r - hose->regions;
340 hose->first_busno = first_free_busno;
341 pci_setup_indirect(hose, (int)&pci->cfg_addr,
342 (int)&pci->cfg_data);
346 /* Unlock inbound PCI configuration cycles */
348 fsl_pci_config_unlock(hose);
350 first_free_busno = hose->last_busno + 1;
351 printf(" PCIE3 on bus %02x - %02x\n",
352 hose->first_busno, hose->last_busno);
355 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
356 #endif /* CONFIG_PCIE3 */
359 #if defined(CONFIG_OF_BOARD_SETUP)
360 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
361 struct pci_controller *hose);
363 void ft_board_pci_setup(void *blob, bd_t *bd)
365 /* TODO - make node name (eg pci0) dynamic */
367 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
370 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
373 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
376 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
379 #endif /* CONFIG_OF_BOARD_SETUP */