2 * Copyright 2008 Extreme Engineering Solutions, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
13 unsigned long get_board_sys_clk(ulong dummy)
15 #if defined(CONFIG_MPC85xx)
16 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
17 #elif defined(CONFIG_MPC86xx)
18 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
19 volatile ccsr_gur_t *gur = &immap->im_gur;
22 if (in_be32(&gur->gpporcr) & 0x10000)
34 * Return DDR input clock - synchronous with SYSCLK or 66 MHz
35 * Note: 86xx doesn't support asynchronous DDR clk
37 unsigned long get_board_ddr_clk(ulong dummy)
39 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
40 u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
43 return get_board_sys_clk(dummy);
46 if (in_be32(&gur->gpporcr) & 0x20000)