2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/fsl_ddr_sdram.h>
27 #include <asm/fsl_ddr_dimm_params.h>
29 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
31 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
32 sizeof(ddr2_spd_eeprom_t));
35 unsigned int fsl_ddr_get_mem_data_rate(void)
37 return get_bus_freq(0);
40 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
41 unsigned int ctrl_num)
44 unsigned int i2c_address = 0;
46 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
48 i2c_address = SPD_EEPROM_ADDRESS1;
49 #ifdef SPD_EEPROM_ADDRESS2
50 } else if (ctrl_num == 1) {
51 i2c_address = SPD_EEPROM_ADDRESS2;
54 /* An inalid ctrl number was give, use default SPD */
55 printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num);
56 i2c_address = SPD_EEPROM_ADDRESS1;
59 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
64 * There are four board-specific SDRAM timing parameters which must be
65 * calculated based on the particular PCB artwork. These are:
66 * 1.) CPO (Read Capture Delay)
67 * - TIMING_CFG_2 register
68 * Source: Calculation based on board trace lengths and
69 * chip-specific internal delays.
70 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
71 * - TIMING_CFG_2 register
72 * Source: Calculation based on board trace lengths.
73 * Unless clock and DQ lanes are very different
74 * lengths (>2"), this should be set to the nominal value
76 * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
77 * - DDR_SDRAM_CLK_CNTL register
78 * Source: Signal Integrity Simulations
79 * 4.) 2T Timing on Addr/Ctl
80 * - TIMING_CFG_2 register
81 * Source: Signal Integrity Simulations
82 * Usually only needed with heavy load/very high speed (>DDR2-800)
84 * PCB routing on the XPedite5170 is nearly identical to the XPedite5370
85 * so we use the XPedite5370 settings as a basis for the XPedite5170.
88 typedef struct board_memctl_options {
89 uint16_t datarate_mhz_low;
90 uint16_t datarate_mhz_high;
93 uint8_t write_data_delay;
94 } board_memctl_options_t;
96 static struct board_memctl_options bopts_ctrl[][2] = {
101 .datarate_mhz_low = 500,
102 .datarate_mhz_high = 750,
105 .write_data_delay = 2,
109 .datarate_mhz_low = 750,
110 .datarate_mhz_high = 850,
113 .write_data_delay = 2,
120 .datarate_mhz_low = 500,
121 .datarate_mhz_high = 750,
124 .write_data_delay = 2,
128 .datarate_mhz_low = 750,
129 .datarate_mhz_high = 850,
132 .write_data_delay = 2,
137 void fsl_ddr_board_options(memctl_options_t *popts,
138 dimm_params_t *pdimm,
139 unsigned int ctrl_num)
141 struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
144 unsigned int datarate;
146 get_sys_info(&sysinfo);
147 datarate = fsl_ddr_get_mem_data_rate() / 1000000;
149 for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
150 if ((bopts[i].datarate_mhz_low <= datarate) &&
151 (bopts[i].datarate_mhz_high >= datarate)) {
152 debug("controller %d:\n", ctrl_num);
153 debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
154 debug(" cpo = %d\n", bopts[i].cpo_override);
155 debug(" write_data_delay = %d\n",
156 bopts[i].write_data_delay);
157 popts->clk_adjust = bopts[i].clk_adjust;
158 popts->cpo_override = bopts[i].cpo_override;
159 popts->write_data_delay = bopts[i].write_data_delay;
164 * Factors to consider for half-strength driver enable:
165 * - number of DIMMs installed
167 popts->half_strength_driver_enable = 0;