2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/fsl_ddr_sdram.h>
27 #include <asm/fsl_ddr_dimm_params.h>
29 void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
31 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
32 sizeof(ddr2_spd_eeprom_t));
36 * There are four board-specific SDRAM timing parameters which must be
37 * calculated based on the particular PCB artwork. These are:
38 * 1.) CPO (Read Capture Delay)
39 * - TIMING_CFG_2 register
40 * Source: Calculation based on board trace lengths and
41 * chip-specific internal delays.
42 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
43 * - TIMING_CFG_2 register
44 * Source: Calculation based on board trace lengths.
45 * Unless clock and DQ lanes are very different
46 * lengths (>2"), this should be set to the nominal value
48 * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
49 * - DDR_SDRAM_CLK_CNTL register
50 * Source: Signal Integrity Simulations
51 * 4.) 2T Timing on Addr/Ctl
52 * - TIMING_CFG_2 register
53 * Source: Signal Integrity Simulations
54 * Usually only needed with heavy load/very high speed (>DDR2-800)
56 * PCB routing on the XPedite5170 is nearly identical to the XPedite5370
57 * so we use the XPedite5370 settings as a basis for the XPedite5170.
60 typedef struct board_memctl_options {
61 uint16_t datarate_mhz_low;
62 uint16_t datarate_mhz_high;
65 uint8_t write_data_delay;
66 } board_memctl_options_t;
68 static struct board_memctl_options bopts_ctrl[][2] = {
73 .datarate_mhz_low = 500,
74 .datarate_mhz_high = 750,
77 .write_data_delay = 2,
81 .datarate_mhz_low = 750,
82 .datarate_mhz_high = 850,
85 .write_data_delay = 2,
92 .datarate_mhz_low = 500,
93 .datarate_mhz_high = 750,
96 .write_data_delay = 2,
100 .datarate_mhz_low = 750,
101 .datarate_mhz_high = 850,
104 .write_data_delay = 2,
109 void fsl_ddr_board_options(memctl_options_t *popts,
110 dimm_params_t *pdimm,
111 unsigned int ctrl_num)
113 struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
116 unsigned int datarate;
118 get_sys_info(&sysinfo);
119 datarate = get_ddr_freq(0) / 1000000;
121 for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
122 if ((bopts[i].datarate_mhz_low <= datarate) &&
123 (bopts[i].datarate_mhz_high >= datarate)) {
124 debug("controller %d:\n", ctrl_num);
125 debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
126 debug(" cpo = %d\n", bopts[i].cpo_override);
127 debug(" write_data_delay = %d\n",
128 bopts[i].write_data_delay);
129 popts->clk_adjust = bopts[i].clk_adjust;
130 popts->cpo_override = bopts[i].cpo_override;
131 popts->write_data_delay = bopts[i].write_data_delay;
136 * Factors to consider for half-strength driver enable:
137 * - number of DIMMs installed
139 popts->half_strength_driver_enable = 0;