2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2008 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/fsl_ddr_sdram.h>
28 #include <asm/fsl_ddr_dimm_params.h>
30 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
32 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
33 sizeof(ddr2_spd_eeprom_t));
36 unsigned int fsl_ddr_get_mem_data_rate(void)
38 return get_ddr_freq(0);
41 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
42 unsigned int ctrl_num)
45 unsigned int i2c_address = 0;
47 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
49 i2c_address = SPD_EEPROM_ADDRESS1;
51 i2c_address = SPD_EEPROM_ADDRESS2;
52 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
57 * There are four board-specific SDRAM timing parameters which must be
58 * calculated based on the particular PCB artwork. These are:
59 * 1.) CPO (Read Capture Delay)
60 * - TIMING_CFG_2 register
61 * Source: Calculation based on board trace lengths and
62 * chip-specific internal delays.
63 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
64 * - TIMING_CFG_2 register
65 * Source: Calculation based on board trace lengths.
66 * Unless clock and DQ lanes are very different
67 * lengths (>2"), this should be set to the nominal value
69 * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
70 * - DDR_SDRAM_CLK_CNTL register
71 * Source: Signal Integrity Simulations
72 * 4.) 2T Timing on Addr/Ctl
73 * - TIMING_CFG_2 register
74 * Source: Signal Integrity Simulations
75 * Usually only needed with heavy load/very high speed (>DDR2-800)
77 * ====== XPedite5370 DDR2-600 read delay calculations ======
79 * See Freescale's App Note AN2583 as refrence. This document also
80 * contains the chip-specific delays for 8548E, 8572, etc.
83 * Minimum chip delay (Ch 0): 1.372ns
84 * Maximum chip delay (Ch 0): 2.914ns
85 * Minimum chip delay (Ch 1): 1.220ns
86 * Maximum chip delay (Ch 1): 2.595ns
88 * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
90 * Minimum delay calc (Ch 0):
91 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
92 * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
96 * Maximum delay calc (Ch 0):
97 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
98 * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
102 * Minimum delay calc (Ch 1):
103 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
104 * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
108 * Maximum delay calc (Ch 1):
109 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
110 * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
114 * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
115 * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
116 * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
117 * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
120 * ====== XPedite5370 DDR2-800 read delay calculations ======
122 * See Freescale's App Note AN2583 as refrence. This document also
123 * contains the chip-specific delays for 8548E, 8572, etc.
126 * Minimum chip delay (Ch 0): 1.372ns
127 * Maximum chip delay (Ch 0): 2.914ns
128 * Minimum chip delay (Ch 1): 1.220ns
129 * Maximum chip delay (Ch 1): 2.595ns
131 * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
133 * Minimum delay calc (Ch 0):
134 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
135 * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
139 * Maximum delay calc (Ch 0):
140 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
141 * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
145 * Minimum delay calc (Ch 1):
146 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
147 * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
151 * Maximum delay calc (Ch 1):
152 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
153 * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
157 * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
158 * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
159 * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
160 * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
162 * Write latency (WR_DATA_DELAY) is calculated by doing the following:
164 * The DDR SDRAM specification requires DQS be received no sooner than
165 * 75% of an SDRAM clock period—and no later than 125% of a clock
166 * period—from the capturing clock edge of the command/address at the
169 * Based on the above tracelengths, the following are calculated:
170 * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
171 * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
172 * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
173 * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
175 * Difference in arrival time CLK vs. DQS:
179 * Both of these values are much less than 25% of the clock
180 * period at DDR2-600 or DDR2-800, so no additional delay is needed over
181 * the 1/2 cycle which normally aligns the first DQS transition
182 * exactly WL (CAS latency minus one cycle) after the CAS strobe.
183 * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
184 * terminology corresponds to exactly one clock period delay after
185 * the CAS strobe. (due to the fact that the "delay" is referenced
186 * from the *falling* edge of the CLK, just after the rising edge
187 * which the CAS strobe is latched on.
190 typedef struct board_memctl_options {
191 uint16_t datarate_mhz_low;
192 uint16_t datarate_mhz_high;
194 uint8_t cpo_override;
195 uint8_t write_data_delay;
196 } board_memctl_options_t;
198 static struct board_memctl_options bopts_ctrl[][2] = {
203 .datarate_mhz_low = 500,
204 .datarate_mhz_high = 750,
207 .write_data_delay = 2,
211 .datarate_mhz_low = 750,
212 .datarate_mhz_high = 850,
215 .write_data_delay = 2,
222 .datarate_mhz_low = 500,
223 .datarate_mhz_high = 750,
226 .write_data_delay = 2,
230 .datarate_mhz_low = 750,
231 .datarate_mhz_high = 850,
234 .write_data_delay = 2,
239 void fsl_ddr_board_options(memctl_options_t *popts,
240 dimm_params_t *pdimm,
241 unsigned int ctrl_num)
243 struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
246 unsigned int datarate;
248 get_sys_info(&sysinfo);
249 datarate = sysinfo.freqDDRBus / 1000 / 1000;
251 for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
252 if ((bopts[i].datarate_mhz_low <= datarate) &&
253 (bopts[i].datarate_mhz_high >= datarate)) {
254 debug("controller %d:\n", ctrl_num);
255 debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
256 debug(" cpo = %d\n", bopts[i].cpo_override);
257 debug(" write_data_delay = %d\n",
258 bopts[i].write_data_delay);
259 popts->clk_adjust = bopts[i].clk_adjust;
260 popts->cpo_override = bopts[i].cpo_override;
261 popts->write_data_delay = bopts[i].write_data_delay;
266 * Factors to consider for half-strength driver enable:
267 * - number of DIMMs installed
269 popts->half_strength_driver_enable = 0;