1 /******************************************************************************
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
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9 * option) any later version.
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22 * FITNESS FOR A PARTICULAR PURPOSE.
25 * Xilinx hardware products are not intended for use in life support
26 * appliances, devices, or systems. Use in such applications is
27 * expressly prohibited.
30 * (c) Copyright 2002-2004 Xilinx Inc.
31 * All rights reserved.
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 * This file contains the DMA channel component. This component supports
45 * a distributed DMA design in which each device can have it's own dedicated
46 * DMA channel, as opposed to a centralized DMA design. This component
47 * performs processing for DMA on all devices.
49 * See xdma_channel.h for more information about this component.
55 ******************************************************************************/
57 /***************************** Include Files *********************************/
59 #include "xdma_channel.h"
60 #include "xbasic_types.h"
63 /************************** Constant Definitions *****************************/
65 /**************************** Type Definitions *******************************/
67 /***************** Macros (Inline Functions) Definitions *********************/
69 /************************** Function Prototypes ******************************/
71 /******************************************************************************
75 * XDmaChannel_Initialize
79 * This function initializes a DMA channel. This function must be called
80 * prior to using a DMA channel. Initialization of a channel includes setting
81 * up the registers base address, and resetting the channel such that it's in a
82 * known state. Interrupts for the channel are disabled when the channel is
87 * InstancePtr contains a pointer to the DMA channel to operate on.
89 * BaseAddress contains the base address of the registers for the DMA channel.
93 * XST_SUCCESS indicating initialization was successful.
99 ******************************************************************************/
101 XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress)
103 /* assert to verify input arguments, don't assert base address */
105 XASSERT_NONVOID(InstancePtr != NULL);
107 /* setup the base address of the registers for the DMA channel such
108 * that register accesses can be done
110 InstancePtr->RegBaseAddress = BaseAddress;
112 /* initialize the scatter gather list such that it indicates it has not
113 * been created yet and the DMA channel is ready to use (initialized)
115 InstancePtr->GetPtr = NULL;
116 InstancePtr->PutPtr = NULL;
117 InstancePtr->CommitPtr = NULL;
118 InstancePtr->LastPtr = NULL;
120 InstancePtr->TotalDescriptorCount = 0;
121 InstancePtr->ActiveDescriptorCount = 0;
122 InstancePtr->IsReady = XCOMPONENT_IS_READY;
124 /* initialize the version of the component
126 XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
128 /* reset the DMA channel such that it's in a known state and ready
129 * and indicate the initialization occured with no errors, note that
130 * the is ready variable must be set before this call or reset will assert
132 XDmaChannel_Reset(InstancePtr);
137 /******************************************************************************
141 * XDmaChannel_IsReady
145 * This function determines if a DMA channel component has been successfully
146 * initialized such that it's ready to use.
150 * InstancePtr contains a pointer to the DMA channel to operate on.
154 * TRUE if the DMA channel component is ready, FALSE otherwise.
160 ******************************************************************************/
162 XDmaChannel_IsReady(XDmaChannel * InstancePtr)
164 /* assert to verify input arguments used by the base component */
166 XASSERT_NONVOID(InstancePtr != NULL);
168 return InstancePtr->IsReady == XCOMPONENT_IS_READY;
171 /******************************************************************************
175 * XDmaChannel_GetVersion
179 * This function gets the software version for the specified DMA channel
184 * InstancePtr contains a pointer to the DMA channel to operate on.
188 * A pointer to the software version of the specified DMA channel.
194 ******************************************************************************/
196 XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
198 /* assert to verify input arguments */
200 XASSERT_NONVOID(InstancePtr != NULL);
201 XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
203 /* return a pointer to the version of the DMA channel */
205 return &InstancePtr->Version;
208 /******************************************************************************
212 * XDmaChannel_SelfTest
216 * This function performs a self test on the specified DMA channel. This self
217 * test is destructive as the DMA channel is reset and a register default is
222 * InstancePtr is a pointer to the DMA channel to be operated on.
226 * XST_SUCCESS is returned if the self test is successful, or one of the
229 * XST_DMA_RESET_REGISTER_ERROR Indicates the control register value
230 * after a reset was not correct
234 * This test does not performs a DMA transfer to test the channel because the
235 * DMA hardware will not currently allow a non-local memory transfer to non-local
236 * memory (memory copy), but only allows a non-local memory to or from the device
237 * memory (typically a FIFO).
239 ******************************************************************************/
241 #define XDC_CONTROL_REG_RESET_MASK 0x98000000UL /* control reg reset value */
244 XDmaChannel_SelfTest(XDmaChannel * InstancePtr)
248 /* assert to verify input arguments */
250 XASSERT_NONVOID(InstancePtr != NULL);
251 XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
253 /* reset the DMA channel such that it's in a known state before the test
254 * it resets to no interrupts enabled, the desired state for the test
256 XDmaChannel_Reset(InstancePtr);
258 /* this should be the first test to help prevent a lock up with the polling
259 * loop that occurs later in the test, check the reset value of the DMA
260 * control register to make sure it's correct, return with an error if not
262 ControlReg = XDmaChannel_GetControl(InstancePtr);
263 if (ControlReg != XDC_CONTROL_REG_RESET_MASK) {
264 return XST_DMA_RESET_REGISTER_ERROR;
270 /******************************************************************************
278 * This function resets the DMA channel. This is a destructive operation such
279 * that it should not be done while a channel is being used. If the DMA channel
280 * is transferring data into other blocks, such as a FIFO, it may be necessary
281 * to reset other blocks. This function does not modify the contents of a
282 * scatter gather list for a DMA channel such that the user is responsible for
283 * getting buffer descriptors from the list if necessary.
287 * InstancePtr contains a pointer to the DMA channel to operate on.
297 ******************************************************************************/
299 XDmaChannel_Reset(XDmaChannel * InstancePtr)
301 /* assert to verify input arguments */
303 XASSERT_VOID(InstancePtr != NULL);
304 XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
306 /* reset the DMA channel such that it's in a known state, the reset
307 * register is self clearing such that it only has to be set
309 XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET,
313 /******************************************************************************
317 * XDmaChannel_GetControl
321 * This function gets the control register contents of the DMA channel.
325 * InstancePtr contains a pointer to the DMA channel to operate on.
329 * The control register contents of the DMA channel. One or more of the
330 * following values may be contained the register. Each of the values are
333 * XDC_DMACR_SOURCE_INCR_MASK Increment the source address
334 * XDC_DMACR_DEST_INCR_MASK Increment the destination address
335 * XDC_DMACR_SOURCE_LOCAL_MASK Local source address
336 * XDC_DMACR_DEST_LOCAL_MASK Local destination address
337 * XDC_DMACR_SG_ENABLE_MASK Scatter gather enable
338 * XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt
339 * XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet
345 ******************************************************************************/
347 XDmaChannel_GetControl(XDmaChannel * InstancePtr)
349 /* assert to verify input arguments */
351 XASSERT_NONVOID(InstancePtr != NULL);
352 XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
354 /* return the contents of the DMA control register */
356 return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
359 /******************************************************************************
363 * XDmaChannel_SetControl
367 * This function sets the control register of the specified DMA channel.
371 * InstancePtr contains a pointer to the DMA channel to operate on.
373 * Control contains the value to be written to the control register of the DMA
374 * channel. One or more of the following values may be contained the register.
375 * Each of the values are unique bit masks such that they may be ORed together
376 * to enable multiple bits or inverted and ANDed to disable multiple bits.
378 * XDC_DMACR_SOURCE_INCR_MASK Increment the source address
379 * XDC_DMACR_DEST_INCR_MASK Increment the destination address
380 * XDC_DMACR_SOURCE_LOCAL_MASK Local source address
381 * XDC_DMACR_DEST_LOCAL_MASK Local destination address
382 * XDC_DMACR_SG_ENABLE_MASK Scatter gather enable
383 * XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt
384 * XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet
394 ******************************************************************************/
396 XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control)
398 /* assert to verify input arguments except the control which can't be
399 * asserted since all values are valid
401 XASSERT_VOID(InstancePtr != NULL);
402 XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
404 /* set the DMA control register to the specified value */
406 XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control);
409 /******************************************************************************
413 * XDmaChannel_GetStatus
417 * This function gets the status register contents of the DMA channel.
421 * InstancePtr contains a pointer to the DMA channel to operate on.
425 * The status register contents of the DMA channel. One or more of the
426 * following values may be contained the register. Each of the values are
429 * XDC_DMASR_BUSY_MASK The DMA channel is busy
430 * XDC_DMASR_BUS_ERROR_MASK A bus error occurred
431 * XDC_DMASR_BUS_TIMEOUT_MASK A bus timeout occurred
432 * XDC_DMASR_LAST_BD_MASK The last buffer descriptor of a packet
438 ******************************************************************************/
440 XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
442 /* assert to verify input arguments */
444 XASSERT_NONVOID(InstancePtr != NULL);
445 XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
447 /* return the contents of the DMA status register */
449 return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
452 /******************************************************************************
456 * XDmaChannel_SetIntrStatus
460 * This function sets the interrupt status register of the specified DMA channel.
461 * Setting any bit of the interrupt status register will clear the bit to
462 * indicate the interrupt processing has been completed. The definitions of each
463 * bit in the register match the definition of the bits in the interrupt enable
468 * InstancePtr contains a pointer to the DMA channel to operate on.
470 * Status contains the value to be written to the status register of the DMA
471 * channel. One or more of the following values may be contained the register.
472 * Each of the values are unique bit masks such that they may be ORed together
473 * to enable multiple bits or inverted and ANDed to disable multiple bits.
475 * XDC_IXR_DMA_DONE_MASK The dma operation is done
476 * XDC_IXR_DMA_ERROR_MASK The dma operation had an error
477 * XDC_IXR_PKT_DONE_MASK A packet is complete
478 * XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
479 * XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
480 * XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
481 * XDC_IXR_BD_MASK A buffer descriptor is done
491 ******************************************************************************/
493 XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
495 /* assert to verify input arguments except the status which can't be
496 * asserted since all values are valid
498 XASSERT_VOID(InstancePtr != NULL);
499 XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
501 /* set the interrupt status register with the specified value such that
502 * all bits which are set in the register are cleared effectively clearing
503 * any active interrupts
505 XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status);
508 /******************************************************************************
512 * XDmaChannel_GetIntrStatus
516 * This function gets the interrupt status register of the specified DMA channel.
517 * The interrupt status register indicates which interrupts are active
518 * for the DMA channel. If an interrupt is active, the status register must be
519 * set (written) with the bit set for each interrupt which has been processed
520 * in order to clear the interrupts. The definitions of each bit in the register
521 * match the definition of the bits in the interrupt enable register.
525 * InstancePtr contains a pointer to the DMA channel to operate on.
529 * The interrupt status register contents of the specified DMA channel.
530 * One or more of the following values may be contained the register.
531 * Each of the values are unique bit masks.
533 * XDC_IXR_DMA_DONE_MASK The dma operation is done
534 * XDC_IXR_DMA_ERROR_MASK The dma operation had an error
535 * XDC_IXR_PKT_DONE_MASK A packet is complete
536 * XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
537 * XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
538 * XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
539 * XDC_IXR_SG_END_MASK Current descriptor was the end of the list
540 * XDC_IXR_BD_MASK A buffer descriptor is done
546 ******************************************************************************/
548 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
550 /* assert to verify input arguments */
552 XASSERT_NONVOID(InstancePtr != NULL);
553 XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
555 /* return the contents of the interrupt status register */
557 return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
560 /******************************************************************************
564 * XDmaChannel_SetIntrEnable
568 * This function sets the interrupt enable register of the specified DMA
569 * channel. The interrupt enable register contains bits which enable
570 * individual interrupts for the DMA channel. The definitions of each bit
571 * in the register match the definition of the bits in the interrupt status
576 * InstancePtr contains a pointer to the DMA channel to operate on.
578 * Enable contains the interrupt enable register contents to be written
579 * in the DMA channel. One or more of the following values may be contained
580 * the register. Each of the values are unique bit masks such that they may be
581 * ORed together to enable multiple bits or inverted and ANDed to disable
584 * XDC_IXR_DMA_DONE_MASK The dma operation is done
585 * XDC_IXR_DMA_ERROR_MASK The dma operation had an error
586 * XDC_IXR_PKT_DONE_MASK A packet is complete
587 * XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
588 * XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
589 * XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
590 * XDC_IXR_SG_END_MASK Current descriptor was the end of the list
591 * XDC_IXR_BD_MASK A buffer descriptor is done
601 ******************************************************************************/
603 XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
605 /* assert to verify input arguments except the enable which can't be
606 * asserted since all values are valid
608 XASSERT_VOID(InstancePtr != NULL);
609 XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
611 /* set the interrupt enable register to the specified value */
613 XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable);
616 /******************************************************************************
620 * XDmaChannel_GetIntrEnable
624 * This function gets the interrupt enable of the DMA channel. The
625 * interrupt enable contains flags which enable individual interrupts for the
626 * DMA channel. The definitions of each bit in the register match the definition
627 * of the bits in the interrupt status register.
631 * InstancePtr contains a pointer to the DMA channel to operate on.
635 * The interrupt enable of the DMA channel. One or more of the following values
636 * may be contained the register. Each of the values are unique bit masks.
638 * XDC_IXR_DMA_DONE_MASK The dma operation is done
639 * XDC_IXR_DMA_ERROR_MASK The dma operation had an error
640 * XDC_IXR_PKT_DONE_MASK A packet is complete
641 * XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
642 * XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
643 * XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
644 * XDC_IXR_BD_MASK A buffer descriptor is done
650 ******************************************************************************/
652 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr)
654 /* assert to verify input arguments */
656 XASSERT_NONVOID(InstancePtr != NULL);
657 XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
659 /* return the contents of the interrupt enable register */
661 return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET);
664 /******************************************************************************
668 * XDmaChannel_Transfer
672 * This function starts the DMA channel transferring data from a memory source
673 * to a memory destination. This function only starts the operation and returns
674 * before the operation may be complete. If the interrupt is enabled, an
675 * interrupt will be generated when the operation is complete, otherwise it is
676 * necessary to poll the channel status to determine when it's complete. It is
677 * the responsibility of the caller to determine when the operation is complete
678 * by handling the generated interrupt or polling the status. It is also the
679 * responsibility of the caller to ensure that the DMA channel is not busy with
680 * another transfer before calling this function.
684 * InstancePtr contains a pointer to the DMA channel to operate on.
686 * SourcePtr contains a pointer to the source memory where the data is to
687 * be tranferred from and must be 32 bit aligned.
689 * DestinationPtr contains a pointer to the destination memory where the data
690 * is to be transferred and must be 32 bit aligned.
692 * ByteCount contains the number of bytes to transfer during the DMA operation.
700 * The DMA h/w will not currently allow a non-local memory transfer to non-local
701 * memory (memory copy), but only allows a non-local memory to or from the device
702 * memory (typically a FIFO).
704 * It is the responsibility of the caller to ensure that the cache is
705 * flushed and invalidated both before and after the DMA operation completes
706 * if the memory pointed to is cached. The caller must also ensure that the
707 * pointers contain a physical address rather than a virtual address
708 * if address translation is being used.
710 ******************************************************************************/
712 XDmaChannel_Transfer(XDmaChannel * InstancePtr,
713 u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount)
715 /* assert to verify input arguments and the alignment of any arguments
716 * which have expected alignments
718 XASSERT_VOID(InstancePtr != NULL);
719 XASSERT_VOID(SourcePtr != NULL);
720 XASSERT_VOID(((u32) SourcePtr & 3) == 0);
721 XASSERT_VOID(DestinationPtr != NULL);
722 XASSERT_VOID(((u32) DestinationPtr & 3) == 0);
723 XASSERT_VOID(ByteCount != 0);
724 XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
726 /* setup the source and destination address registers for the transfer */
728 XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET,
731 XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET,
732 (u32) DestinationPtr);
734 /* start the DMA transfer to copy from the source buffer to the
735 * destination buffer by writing the length to the length register
737 XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount);