3 * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
4 * This work has been supported by: QTechnology http://qtec.com/
5 * based on xparameters-ml507.h by Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
13 #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
14 #define XPAR_IIC_EEPROM_BASEADDR 0x81600000
15 #define XPAR_INTC_0_BASEADDR 0x87000000
16 #define XPAR_FLASH_MEM0_BASEADDR 0xF0000000
17 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000
18 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000
19 #define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
20 #define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
21 #define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
22 #define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
23 #define XPAR_LLTEMAC_0_BASEADDR 0x83000000
24 #define XPAR_LLTEMAC_1_BASEADDR 0x83000040