git.sur5r.net Git - u-boot/blob - board/xilinx/zynq/board.c

   1 /*
   2  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
   3  * (C) Copyright 2013 - 2018 Xilinx, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <fdtdec.h>
  10 #include <fpga.h>
  11 #include <mmc.h>
  12 #include <zynqpl.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/arch/ps7_init_gpl.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  20     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  21 static xilinx_desc fpga;
  22
  23 /* It can be done differently */
  24 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
  25 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  26 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
  27 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
  28 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
  29 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  30 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  31 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
  32 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  33 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  34 #endif
  35
  36 int board_init(void)
  37 {
  38 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  39     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  40         u32 idcode;
  41
  42         idcode = zynq_slcr_get_idcode();
  43
  44         switch (idcode) {
  45         case XILINX_ZYNQ_7007S:
  46                 fpga = fpga007s;
  47                 break;
  48         case XILINX_ZYNQ_7010:
  49                 fpga = fpga010;
  50                 break;
  51         case XILINX_ZYNQ_7012S:
  52                 fpga = fpga012s;
  53                 break;
  54         case XILINX_ZYNQ_7014S:
  55                 fpga = fpga014s;
  56                 break;
  57         case XILINX_ZYNQ_7015:
  58                 fpga = fpga015;
  59                 break;
  60         case XILINX_ZYNQ_7020:
  61                 fpga = fpga020;
  62                 break;
  63         case XILINX_ZYNQ_7030:
  64                 fpga = fpga030;
  65                 break;
  66         case XILINX_ZYNQ_7035:
  67                 fpga = fpga035;
  68                 break;
  69         case XILINX_ZYNQ_7045:
  70                 fpga = fpga045;
  71                 break;
  72         case XILINX_ZYNQ_7100:
  73                 fpga = fpga100;
  74                 break;
  75         }
  76 #endif
  77
  78 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  79     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  80         fpga_init();
  81         fpga_add(fpga_xilinx, &fpga);
  82 #endif
  83
  84         return 0;
  85 }
  86
  87 int board_late_init(void)
  88 {
  89         switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
  90         case ZYNQ_BM_QSPI:
  91                 env_set("modeboot", "qspiboot");
  92                 break;
  93         case ZYNQ_BM_NAND:
  94                 env_set("modeboot", "nandboot");
  95                 break;
  96         case ZYNQ_BM_NOR:
  97                 env_set("modeboot", "norboot");
  98                 break;
  99         case ZYNQ_BM_SD:
 100                 env_set("modeboot", "sdboot");
 101                 break;
 102         case ZYNQ_BM_JTAG:
 103                 env_set("modeboot", "jtagboot");
 104                 break;
 105         default:
 106                 env_set("modeboot", "");
 107                 break;
 108         }
 109
 110         return 0;
 111 }
 112
 113 #ifdef CONFIG_DISPLAY_BOARDINFO
 114 int checkboard(void)
 115 {
 116         u32 version = zynq_get_silicon_version();
 117
 118         version <<= 1;
 119         if (version > (PCW_SILICON_VERSION_3 << 1))
 120                 version += 1;
 121
 122         puts("Board: Xilinx Zynq\n");
 123         printf("Silicon: v%d.%d\n", version >> 1, version & 1);
 124
 125         return 0;
 126 }
 127 #endif
 128
 129 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 130 {
 131 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 132     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
 133         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 134                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 135                         ethaddr, 6))
 136                 printf("I2C EEPROM MAC address read failed\n");
 137 #endif
 138
 139         return 0;
 140 }
 141
 142 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 143 int dram_init_banksize(void)
 144 {
 145         return fdtdec_setup_memory_banksize();
 146 }
 147
 148 int dram_init(void)
 149 {
 150         if (fdtdec_setup_memory_size() != 0)
 151                 return -EINVAL;
 152
 153         zynq_ddrc_init();
 154
 155         return 0;
 156 }
 157 #else
 158 int dram_init(void)
 159 {
 160         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 161
 162         zynq_ddrc_init();
 163
 164         return 0;
 165 }
 166 #endif