git.sur5r.net Git - u-boot/blob - board/xilinx/zynq/board.c

   1 /*
   2  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <fpga.h>
  10 #include <mmc.h>
  11 #include <netdev.h>
  12 #include <zynqpl.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #ifdef CONFIG_FPGA
  19 static xilinx_desc fpga;
  20
  21 /* It can be done differently */
  22 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  23 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
  24 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  25 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  26 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  27 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  28 #endif
  29
  30 int board_init(void)
  31 {
  32 #ifdef CONFIG_FPGA
  33         u32 idcode;
  34
  35         idcode = zynq_slcr_get_idcode();
  36
  37         switch (idcode) {
  38         case XILINX_ZYNQ_7010:
  39                 fpga = fpga010;
  40                 break;
  41         case XILINX_ZYNQ_7015:
  42                 fpga = fpga015;
  43                 break;
  44         case XILINX_ZYNQ_7020:
  45                 fpga = fpga020;
  46                 break;
  47         case XILINX_ZYNQ_7030:
  48                 fpga = fpga030;
  49                 break;
  50         case XILINX_ZYNQ_7045:
  51                 fpga = fpga045;
  52                 break;
  53         case XILINX_ZYNQ_7100:
  54                 fpga = fpga100;
  55                 break;
  56         }
  57 #endif
  58
  59 #ifdef CONFIG_FPGA
  60         fpga_init();
  61         fpga_add(fpga_xilinx, &fpga);
  62 #endif
  63
  64         return 0;
  65 }
  66
  67 int board_late_init(void)
  68 {
  69         switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
  70         case ZYNQ_BM_NOR:
  71                 setenv("modeboot", "norboot");
  72                 break;
  73         case ZYNQ_BM_SD:
  74                 setenv("modeboot", "sdboot");
  75                 break;
  76         case ZYNQ_BM_JTAG:
  77                 setenv("modeboot", "jtagboot");
  78                 break;
  79         default:
  80                 setenv("modeboot", "");
  81                 break;
  82         }
  83
  84         return 0;
  85 }
  86
  87 int board_eth_init(bd_t *bis)
  88 {
  89         u32 ret = 0;
  90
  91 #ifdef CONFIG_XILINX_AXIEMAC
  92         ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
  93                                                 XILINX_AXIDMA_BASEADDR);
  94 #endif
  95 #ifdef CONFIG_XILINX_EMACLITE
  96         u32 txpp = 0;
  97         u32 rxpp = 0;
  98 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
  99         txpp = 1;
 100 # endif
 101 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
 102         rxpp = 1;
 103 # endif
 104         ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
 105                         txpp, rxpp);
 106 #endif
 107
 108 #if defined(CONFIG_ZYNQ_GEM)
 109 # if defined(CONFIG_ZYNQ_GEM0)
 110         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
 111                                                 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
 112 # endif
 113 # if defined(CONFIG_ZYNQ_GEM1)
 114         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
 115                                                 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
 116 # endif
 117 #endif
 118         return ret;
 119 }
 120
 121 #ifdef CONFIG_CMD_MMC
 122 int board_mmc_init(bd_t *bd)
 123 {
 124         int ret = 0;
 125
 126 #if defined(CONFIG_ZYNQ_SDHCI)
 127 # if defined(CONFIG_ZYNQ_SDHCI0)
 128         ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
 129 # endif
 130 # if defined(CONFIG_ZYNQ_SDHCI1)
 131         ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
 132 # endif
 133 #endif
 134         return ret;
 135 }
 136 #endif
 137
 138 int dram_init(void)
 139 {
 140 #ifdef CONFIG_OF_CONTROL
 141         int node;
 142         fdt_addr_t addr;
 143         fdt_size_t size;
 144         const void *blob = gd->fdt_blob;
 145
 146         node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
 147                                              "memory", 7);
 148         if (node == -FDT_ERR_NOTFOUND) {
 149                 debug("ZYNQ DRAM: Can't get memory node\n");
 150                 return -1;
 151         }
 152         addr = fdtdec_get_addr_size(blob, node, "reg", &size);
 153         if (addr == FDT_ADDR_T_NONE || size == 0) {
 154                 debug("ZYNQ DRAM: Can't get base address or size\n");
 155                 return -1;
 156         }
 157         gd->ram_size = size;
 158 #else
 159         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 160 #endif
 161         zynq_ddrc_init();
 162
 163         return 0;
 164 }