git.sur5r.net Git - u-boot/blob - board/xilinx/zynq/board.c

   1 /*
   2  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <fpga.h>
  10 #include <mmc.h>
  11 #include <netdev.h>
  12 #include <zynqpl.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  19     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  20 static xilinx_desc fpga;
  21
  22 /* It can be done differently */
  23 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  24 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
  25 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  26 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  27 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
  28 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  29 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  30 #endif
  31
  32 int board_init(void)
  33 {
  34 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  35     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  36         u32 idcode;
  37
  38         idcode = zynq_slcr_get_idcode();
  39
  40         switch (idcode) {
  41         case XILINX_ZYNQ_7010:
  42                 fpga = fpga010;
  43                 break;
  44         case XILINX_ZYNQ_7015:
  45                 fpga = fpga015;
  46                 break;
  47         case XILINX_ZYNQ_7020:
  48                 fpga = fpga020;
  49                 break;
  50         case XILINX_ZYNQ_7030:
  51                 fpga = fpga030;
  52                 break;
  53         case XILINX_ZYNQ_7035:
  54                 fpga = fpga035;
  55                 break;
  56         case XILINX_ZYNQ_7045:
  57                 fpga = fpga045;
  58                 break;
  59         case XILINX_ZYNQ_7100:
  60                 fpga = fpga100;
  61                 break;
  62         }
  63 #endif
  64
  65 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  66     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  67         fpga_init();
  68         fpga_add(fpga_xilinx, &fpga);
  69 #endif
  70
  71         return 0;
  72 }
  73
  74 int board_late_init(void)
  75 {
  76         switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
  77         case ZYNQ_BM_NOR:
  78                 setenv("modeboot", "norboot");
  79                 break;
  80         case ZYNQ_BM_SD:
  81                 setenv("modeboot", "sdboot");
  82                 break;
  83         case ZYNQ_BM_JTAG:
  84                 setenv("modeboot", "jtagboot");
  85                 break;
  86         default:
  87                 setenv("modeboot", "");
  88                 break;
  89         }
  90
  91         return 0;
  92 }
  93
  94 int board_eth_init(bd_t *bis)
  95 {
  96         u32 ret = 0;
  97
  98 #ifdef CONFIG_XILINX_AXIEMAC
  99         ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
 100                                                 XILINX_AXIDMA_BASEADDR);
 101 #endif
 102 #ifdef CONFIG_XILINX_EMACLITE
 103         u32 txpp = 0;
 104         u32 rxpp = 0;
 105 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
 106         txpp = 1;
 107 # endif
 108 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
 109         rxpp = 1;
 110 # endif
 111         ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
 112                         txpp, rxpp);
 113 #endif
 114
 115 #if defined(CONFIG_ZYNQ_GEM)
 116 # if defined(CONFIG_ZYNQ_GEM0)
 117         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
 118                                                 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
 119 # endif
 120 # if defined(CONFIG_ZYNQ_GEM1)
 121         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
 122                                                 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
 123 # endif
 124 #endif
 125         return ret;
 126 }
 127
 128 #ifdef CONFIG_CMD_MMC
 129 int board_mmc_init(bd_t *bd)
 130 {
 131         int ret = 0;
 132
 133 #if defined(CONFIG_ZYNQ_SDHCI)
 134 # if defined(CONFIG_ZYNQ_SDHCI0)
 135         ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
 136 # endif
 137 # if defined(CONFIG_ZYNQ_SDHCI1)
 138         ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
 139 # endif
 140 #endif
 141         return ret;
 142 }
 143 #endif
 144
 145 int dram_init(void)
 146 {
 147 #ifdef CONFIG_OF_CONTROL
 148         int node;
 149         fdt_addr_t addr;
 150         fdt_size_t size;
 151         const void *blob = gd->fdt_blob;
 152
 153         node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
 154                                              "memory", 7);
 155         if (node == -FDT_ERR_NOTFOUND) {
 156                 debug("ZYNQ DRAM: Can't get memory node\n");
 157                 return -1;
 158         }
 159         addr = fdtdec_get_addr_size(blob, node, "reg", &size);
 160         if (addr == FDT_ADDR_T_NONE || size == 0) {
 161                 debug("ZYNQ DRAM: Can't get base address or size\n");
 162                 return -1;
 163         }
 164         gd->ram_size = size;
 165 #else
 166         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 167 #endif
 168         zynq_ddrc_init();
 169
 170         return 0;
 171 }