git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 *  This program is free software; you can redistribute it and/or modify
   6 *  it under the terms of the GNU General Public License as published by
   7 *  the Free Software Foundation; either version 2 of the License, or
   8 *  (at your option) any later version.
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 *  You should have received a copy of the GNU General Public License along
  16 *  with this program; if not, see <http://www.gnu.org/licenses/>
  17 *
  18 *
  19 ******************************************************************************/
  20
  21 #include <xil_io.h>
  22 /* #include <sleep.h> */
  23 #include "psu_init_gpl.h"
  24
  25 int mask_pollOnValue(u32 add , u32 mask, u32 value );
  26
  27 int mask_poll(u32 add , u32 mask );
  28
  29 void mask_delay(u32 delay);
  30
  31 u32 mask_read(u32 add , u32 mask );
  32
  33 static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val)
  34 {
  35         unsigned long RegVal = 0x0;
  36         RegVal = Xil_In32 (offset);
  37         RegVal &= ~(mask);
  38         RegVal |= (val & mask);
  39         Xil_Out32 (offset, RegVal);
  40 }
  41
  42         void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
  43             int rdata =0;
  44             rdata  = Xil_In32(addr);
  45             rdata  = rdata & (~mask);
  46             rdata  = rdata | (value << shift);
  47             Xil_Out32(addr,rdata);
  48             }
  49
  50 unsigned long psu_pll_init_data() {
  51                 // : RPLL INIT
  52                 /*Register : RPLL_CFG @ 0XFF5E0034</p>
  53
  54                 PLL loop filter resistor control
  55                 PSU_CRL_APB_RPLL_CFG_RES                                                        0x2
  56
  57                 PLL charge pump control
  58                 PSU_CRL_APB_RPLL_CFG_CP                                                         0x3
  59
  60                 PLL loop filter high frequency capacitor control
  61                 PSU_CRL_APB_RPLL_CFG_LFHF                                                       0x3
  62
  63                 Lock circuit counter setting
  64                 PSU_CRL_APB_RPLL_CFG_LOCK_CNT                                                   0x258
  65
  66                 Lock circuit configuration settings for lock windowsize
  67                 PSU_CRL_APB_RPLL_CFG_LOCK_DLY                                                   0x3f
  68
  69                 Helper data. Values are to be looked up in a table from Data Sheet
  70                 (OFFSET, MASK, VALUE)      (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U)
  71                 RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK |  0 );
  72
  73                 RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT
  74                         | 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT
  75                         | 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT
  76                         | 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
  77                         | 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
  78                         |  0 ) & RegMask); */
  79                 PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
  80         /*############################################################################################################################ */
  81
  82                 // : UPDATE FB_DIV
  83                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
  84
  85                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
  86                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
  87                 PSU_CRL_APB_RPLL_CTRL_PRE_SRC                                                   0x0
  88
  89                 The integer portion of the feedback divider to the PLL
  90                 PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x48
  91
  92                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
  93                 PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1
  94
  95                 PLL Basic Control
  96                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00717F00U ,0x00014800U)
  97                 RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK |  0 );
  98
  99                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
 100                         | 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT
 101                         | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT
 102                         |  0 ) & RegMask); */
 103                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U);
 104         /*############################################################################################################################ */
 105
 106                 // : BY PASS PLL
 107                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 108
 109                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 110                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 111                 PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1
 112
 113                 PLL Basic Control
 114                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)
 115                 RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
 116
 117                 RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 118                         |  0 ) & RegMask); */
 119                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 120         /*############################################################################################################################ */
 121
 122                 // : ASSERT RESET
 123                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 124
 125                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 126                 PSU_CRL_APB_RPLL_CTRL_RESET                                                     1
 127
 128                 PLL Basic Control
 129                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)
 130                 RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
 131
 132                 RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT
 133                         |  0 ) & RegMask); */
 134                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 135         /*############################################################################################################################ */
 136
 137                 // : DEASSERT RESET
 138                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 139
 140                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 141                 PSU_CRL_APB_RPLL_CTRL_RESET                                                     0
 142
 143                 PLL Basic Control
 144                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)
 145                 RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
 146
 147                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT
 148                         |  0 ) & RegMask); */
 149                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 150         /*############################################################################################################################ */
 151
 152                 // : CHECK PLL STATUS
 153                 /*Register : PLL_STATUS @ 0XFF5E0040</p>
 154
 155                 RPLL is locked
 156                 PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1
 157                 (OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000002U ,0x00000002U)  */
 158                 mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U);
 159
 160         /*############################################################################################################################ */
 161
 162                 // : REMOVE PLL BY PASS
 163                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 164
 165                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 166                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 167                 PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0
 168
 169                 PLL Basic Control
 170                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)
 171                 RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
 172
 173                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 174                         |  0 ) & RegMask); */
 175                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 176         /*############################################################################################################################ */
 177
 178                 /*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048</p>
 179
 180                 Divisor value for this clock.
 181                 PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3
 182
 183                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
 184                 (OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)
 185                 RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
 186
 187                 RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 188                         |  0 ) & RegMask); */
 189                 PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 190         /*############################################################################################################################ */
 191
 192                 // : RPLL FRAC CFG
 193                 /*Register : RPLL_FRAC_CFG @ 0XFF5E0038</p>
 194
 195                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 196                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 197                 PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED                                               0x0
 198
 199                 Fractional value for the Feedback value.
 200                 PSU_CRL_APB_RPLL_FRAC_CFG_DATA                                                  0x0
 201
 202                 Fractional control for the PLL
 203                 (OFFSET, MASK, VALUE)      (0XFF5E0038, 0x8000FFFFU ,0x00000000U)
 204                 RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK |  0 );
 205
 206                 RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
 207                         | 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
 208                         |  0 ) & RegMask); */
 209                 PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 210         /*############################################################################################################################ */
 211
 212                 // : IOPLL INIT
 213                 /*Register : IOPLL_CFG @ 0XFF5E0024</p>
 214
 215                 PLL loop filter resistor control
 216                 PSU_CRL_APB_IOPLL_CFG_RES                                                       0xc
 217
 218                 PLL charge pump control
 219                 PSU_CRL_APB_IOPLL_CFG_CP                                                        0x3
 220
 221                 PLL loop filter high frequency capacitor control
 222                 PSU_CRL_APB_IOPLL_CFG_LFHF                                                      0x3
 223
 224                 Lock circuit counter setting
 225                 PSU_CRL_APB_IOPLL_CFG_LOCK_CNT                                                  0x339
 226
 227                 Lock circuit configuration settings for lock windowsize
 228                 PSU_CRL_APB_IOPLL_CFG_LOCK_DLY                                                  0x3f
 229
 230                 Helper data. Values are to be looked up in a table from Data Sheet
 231                 (OFFSET, MASK, VALUE)      (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU)
 232                 RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK |  0 );
 233
 234                 RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT
 235                         | 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT
 236                         | 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT
 237                         | 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
 238                         | 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
 239                         |  0 ) & RegMask); */
 240                 PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU);
 241         /*############################################################################################################################ */
 242
 243                 // : UPDATE FB_DIV
 244                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 245
 246                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 247                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 248                 PSU_CRL_APB_IOPLL_CTRL_PRE_SRC                                                  0x0
 249
 250                 The integer portion of the feedback divider to the PLL
 251                 PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x2d
 252
 253                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 254                 PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x0
 255
 256                 PLL Basic Control
 257                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00717F00U ,0x00002D00U)
 258                 RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK |  0 );
 259
 260                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
 261                         | 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
 262                         | 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT
 263                         |  0 ) & RegMask); */
 264                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U);
 265         /*############################################################################################################################ */
 266
 267                 // : BY PASS PLL
 268                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 269
 270                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 271                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 272                 PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1
 273
 274                 PLL Basic Control
 275                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)
 276                 RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
 277
 278                 RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 279                         |  0 ) & RegMask); */
 280                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 281         /*############################################################################################################################ */
 282
 283                 // : ASSERT RESET
 284                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 285
 286                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 287                 PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1
 288
 289                 PLL Basic Control
 290                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)
 291                 RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
 292
 293                 RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
 294                         |  0 ) & RegMask); */
 295                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 296         /*############################################################################################################################ */
 297
 298                 // : DEASSERT RESET
 299                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 300
 301                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 302                 PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0
 303
 304                 PLL Basic Control
 305                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)
 306                 RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
 307
 308                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
 309                         |  0 ) & RegMask); */
 310                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 311         /*############################################################################################################################ */
 312
 313                 // : CHECK PLL STATUS
 314                 /*Register : PLL_STATUS @ 0XFF5E0040</p>
 315
 316                 IOPLL is locked
 317                 PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1
 318                 (OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000001U ,0x00000001U)  */
 319                 mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U);
 320
 321         /*############################################################################################################################ */
 322
 323                 // : REMOVE PLL BY PASS
 324                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 325
 326                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 327                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 328                 PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0
 329
 330                 PLL Basic Control
 331                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)
 332                 RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
 333
 334                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 335                         |  0 ) & RegMask); */
 336                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 337         /*############################################################################################################################ */
 338
 339                 /*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044</p>
 340
 341                 Divisor value for this clock.
 342                 PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x3
 343
 344                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
 345                 (OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000300U)
 346                 RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
 347
 348                 RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 349                         |  0 ) & RegMask); */
 350                 PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 351         /*############################################################################################################################ */
 352
 353                 // : IOPLL FRAC CFG
 354                 /*Register : IOPLL_FRAC_CFG @ 0XFF5E0028</p>
 355
 356                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 357                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 358                 PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED                                              0x0
 359
 360                 Fractional value for the Feedback value.
 361                 PSU_CRL_APB_IOPLL_FRAC_CFG_DATA                                                 0x0
 362
 363                 Fractional control for the PLL
 364                 (OFFSET, MASK, VALUE)      (0XFF5E0028, 0x8000FFFFU ,0x00000000U)
 365                 RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK |  0 );
 366
 367                 RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
 368                         | 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
 369                         |  0 ) & RegMask); */
 370                 PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 371         /*############################################################################################################################ */
 372
 373                 // : APU_PLL INIT
 374                 /*Register : APLL_CFG @ 0XFD1A0024</p>
 375
 376                 PLL loop filter resistor control
 377                 PSU_CRF_APB_APLL_CFG_RES                                                        0x2
 378
 379                 PLL charge pump control
 380                 PSU_CRF_APB_APLL_CFG_CP                                                         0x3
 381
 382                 PLL loop filter high frequency capacitor control
 383                 PSU_CRF_APB_APLL_CFG_LFHF                                                       0x3
 384
 385                 Lock circuit counter setting
 386                 PSU_CRF_APB_APLL_CFG_LOCK_CNT                                                   0x258
 387
 388                 Lock circuit configuration settings for lock windowsize
 389                 PSU_CRF_APB_APLL_CFG_LOCK_DLY                                                   0x3f
 390
 391                 Helper data. Values are to be looked up in a table from Data Sheet
 392                 (OFFSET, MASK, VALUE)      (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)
 393                 RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK |  0 );
 394
 395                 RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT
 396                         | 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT
 397                         | 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT
 398                         | 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
 399                         | 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
 400                         |  0 ) & RegMask); */
 401                 PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
 402         /*############################################################################################################################ */
 403
 404                 // : UPDATE FB_DIV
 405                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 406
 407                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 408                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 409                 PSU_CRF_APB_APLL_CTRL_PRE_SRC                                                   0x0
 410
 411                 The integer portion of the feedback divider to the PLL
 412                 PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x48
 413
 414                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 415                 PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1
 416
 417                 PLL Basic Control
 418                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00717F00U ,0x00014800U)
 419                 RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK |  0 );
 420
 421                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
 422                         | 0x00000048U << CRF_APB_APLL_CTRL_FBDIV_SHIFT
 423                         | 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT
 424                         |  0 ) & RegMask); */
 425                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U);
 426         /*############################################################################################################################ */
 427
 428                 // : BY PASS PLL
 429                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 430
 431                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 432                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 433                 PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1
 434
 435                 PLL Basic Control
 436                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)
 437                 RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
 438
 439                 RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
 440                         |  0 ) & RegMask); */
 441                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 442         /*############################################################################################################################ */
 443
 444                 // : ASSERT RESET
 445                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 446
 447                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 448                 PSU_CRF_APB_APLL_CTRL_RESET                                                     1
 449
 450                 PLL Basic Control
 451                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)
 452                 RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
 453
 454                 RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT
 455                         |  0 ) & RegMask); */
 456                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 457         /*############################################################################################################################ */
 458
 459                 // : DEASSERT RESET
 460                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 461
 462                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 463                 PSU_CRF_APB_APLL_CTRL_RESET                                                     0
 464
 465                 PLL Basic Control
 466                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)
 467                 RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
 468
 469                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT
 470                         |  0 ) & RegMask); */
 471                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 472         /*############################################################################################################################ */
 473
 474                 // : CHECK PLL STATUS
 475                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 476
 477                 APLL is locked
 478                 PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1
 479                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000001U ,0x00000001U)  */
 480                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U);
 481
 482         /*############################################################################################################################ */
 483
 484                 // : REMOVE PLL BY PASS
 485                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 486
 487                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 488                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 489                 PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0
 490
 491                 PLL Basic Control
 492                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)
 493                 RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
 494
 495                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
 496                         |  0 ) & RegMask); */
 497                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 498         /*############################################################################################################################ */
 499
 500                 /*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048</p>
 501
 502                 Divisor value for this clock.
 503                 PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 504
 505                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 506                 (OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000300U)
 507                 RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 508
 509                 RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 510                         |  0 ) & RegMask); */
 511                 PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 512         /*############################################################################################################################ */
 513
 514                 // : APLL FRAC CFG
 515                 /*Register : APLL_FRAC_CFG @ 0XFD1A0028</p>
 516
 517                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 518                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 519                 PSU_CRF_APB_APLL_FRAC_CFG_ENABLED                                               0x0
 520
 521                 Fractional value for the Feedback value.
 522                 PSU_CRF_APB_APLL_FRAC_CFG_DATA                                                  0x0
 523
 524                 Fractional control for the PLL
 525                 (OFFSET, MASK, VALUE)      (0XFD1A0028, 0x8000FFFFU ,0x00000000U)
 526                 RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK |  0 );
 527
 528                 RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
 529                         | 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
 530                         |  0 ) & RegMask); */
 531                 PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 532         /*############################################################################################################################ */
 533
 534                 // : DDR_PLL INIT
 535                 /*Register : DPLL_CFG @ 0XFD1A0030</p>
 536
 537                 PLL loop filter resistor control
 538                 PSU_CRF_APB_DPLL_CFG_RES                                                        0x2
 539
 540                 PLL charge pump control
 541                 PSU_CRF_APB_DPLL_CFG_CP                                                         0x3
 542
 543                 PLL loop filter high frequency capacitor control
 544                 PSU_CRF_APB_DPLL_CFG_LFHF                                                       0x3
 545
 546                 Lock circuit counter setting
 547                 PSU_CRF_APB_DPLL_CFG_LOCK_CNT                                                   0x258
 548
 549                 Lock circuit configuration settings for lock windowsize
 550                 PSU_CRF_APB_DPLL_CFG_LOCK_DLY                                                   0x3f
 551
 552                 Helper data. Values are to be looked up in a table from Data Sheet
 553                 (OFFSET, MASK, VALUE)      (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)
 554                 RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK |  0 );
 555
 556                 RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT
 557                         | 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT
 558                         | 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT
 559                         | 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
 560                         | 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
 561                         |  0 ) & RegMask); */
 562                 PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
 563         /*############################################################################################################################ */
 564
 565                 // : UPDATE FB_DIV
 566                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 567
 568                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 569                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 570                 PSU_CRF_APB_DPLL_CTRL_PRE_SRC                                                   0x0
 571
 572                 The integer portion of the feedback divider to the PLL
 573                 PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x40
 574
 575                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 576                 PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1
 577
 578                 PLL Basic Control
 579                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00717F00U ,0x00014000U)
 580                 RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK |  0 );
 581
 582                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
 583                         | 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT
 584                         | 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT
 585                         |  0 ) & RegMask); */
 586                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U);
 587         /*############################################################################################################################ */
 588
 589                 // : BY PASS PLL
 590                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 591
 592                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 593                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 594                 PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1
 595
 596                 PLL Basic Control
 597                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)
 598                 RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
 599
 600                 RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 601                         |  0 ) & RegMask); */
 602                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 603         /*############################################################################################################################ */
 604
 605                 // : ASSERT RESET
 606                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 607
 608                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 609                 PSU_CRF_APB_DPLL_CTRL_RESET                                                     1
 610
 611                 PLL Basic Control
 612                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)
 613                 RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
 614
 615                 RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT
 616                         |  0 ) & RegMask); */
 617                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 618         /*############################################################################################################################ */
 619
 620                 // : DEASSERT RESET
 621                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 622
 623                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 624                 PSU_CRF_APB_DPLL_CTRL_RESET                                                     0
 625
 626                 PLL Basic Control
 627                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)
 628                 RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
 629
 630                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT
 631                         |  0 ) & RegMask); */
 632                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 633         /*############################################################################################################################ */
 634
 635                 // : CHECK PLL STATUS
 636                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 637
 638                 DPLL is locked
 639                 PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1
 640                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000002U ,0x00000002U)  */
 641                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U);
 642
 643         /*############################################################################################################################ */
 644
 645                 // : REMOVE PLL BY PASS
 646                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 647
 648                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 649                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 650                 PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0
 651
 652                 PLL Basic Control
 653                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)
 654                 RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
 655
 656                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 657                         |  0 ) & RegMask); */
 658                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 659         /*############################################################################################################################ */
 660
 661                 /*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C</p>
 662
 663                 Divisor value for this clock.
 664                 PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 665
 666                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 667                 (OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000300U)
 668                 RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 669
 670                 RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 671                         |  0 ) & RegMask); */
 672                 PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 673         /*############################################################################################################################ */
 674
 675                 // : DPLL FRAC CFG
 676                 /*Register : DPLL_FRAC_CFG @ 0XFD1A0034</p>
 677
 678                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 679                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 680                 PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED                                               0x0
 681
 682                 Fractional value for the Feedback value.
 683                 PSU_CRF_APB_DPLL_FRAC_CFG_DATA                                                  0x0
 684
 685                 Fractional control for the PLL
 686                 (OFFSET, MASK, VALUE)      (0XFD1A0034, 0x8000FFFFU ,0x00000000U)
 687                 RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK |  0 );
 688
 689                 RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
 690                         | 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
 691                         |  0 ) & RegMask); */
 692                 PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 693         /*############################################################################################################################ */
 694
 695                 // : VIDEO_PLL INIT
 696                 /*Register : VPLL_CFG @ 0XFD1A003C</p>
 697
 698                 PLL loop filter resistor control
 699                 PSU_CRF_APB_VPLL_CFG_RES                                                        0x2
 700
 701                 PLL charge pump control
 702                 PSU_CRF_APB_VPLL_CFG_CP                                                         0x3
 703
 704                 PLL loop filter high frequency capacitor control
 705                 PSU_CRF_APB_VPLL_CFG_LFHF                                                       0x3
 706
 707                 Lock circuit counter setting
 708                 PSU_CRF_APB_VPLL_CFG_LOCK_CNT                                                   0x28a
 709
 710                 Lock circuit configuration settings for lock windowsize
 711                 PSU_CRF_APB_VPLL_CFG_LOCK_DLY                                                   0x3f
 712
 713                 Helper data. Values are to be looked up in a table from Data Sheet
 714                 (OFFSET, MASK, VALUE)      (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U)
 715                 RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK |  0 );
 716
 717                 RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT
 718                         | 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT
 719                         | 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT
 720                         | 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
 721                         | 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
 722                         |  0 ) & RegMask); */
 723                 PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U);
 724         /*############################################################################################################################ */
 725
 726                 // : UPDATE FB_DIV
 727                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 728
 729                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 730                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 731                 PSU_CRF_APB_VPLL_CTRL_PRE_SRC                                                   0x0
 732
 733                 The integer portion of the feedback divider to the PLL
 734                 PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x39
 735
 736                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 737                 PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1
 738
 739                 PLL Basic Control
 740                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00717F00U ,0x00013900U)
 741                 RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK |  0 );
 742
 743                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
 744                         | 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT
 745                         | 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT
 746                         |  0 ) & RegMask); */
 747                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U);
 748         /*############################################################################################################################ */
 749
 750                 // : BY PASS PLL
 751                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 752
 753                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 754                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 755                 PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1
 756
 757                 PLL Basic Control
 758                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)
 759                 RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
 760
 761                 RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 762                         |  0 ) & RegMask); */
 763                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 764         /*############################################################################################################################ */
 765
 766                 // : ASSERT RESET
 767                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 768
 769                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 770                 PSU_CRF_APB_VPLL_CTRL_RESET                                                     1
 771
 772                 PLL Basic Control
 773                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)
 774                 RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
 775
 776                 RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT
 777                         |  0 ) & RegMask); */
 778                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 779         /*############################################################################################################################ */
 780
 781                 // : DEASSERT RESET
 782                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 783
 784                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 785                 PSU_CRF_APB_VPLL_CTRL_RESET                                                     0
 786
 787                 PLL Basic Control
 788                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)
 789                 RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
 790
 791                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT
 792                         |  0 ) & RegMask); */
 793                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 794         /*############################################################################################################################ */
 795
 796                 // : CHECK PLL STATUS
 797                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 798
 799                 VPLL is locked
 800                 PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1
 801                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000004U ,0x00000004U)  */
 802                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U);
 803
 804         /*############################################################################################################################ */
 805
 806                 // : REMOVE PLL BY PASS
 807                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 808
 809                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 810                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 811                 PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0
 812
 813                 PLL Basic Control
 814                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)
 815                 RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
 816
 817                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 818                         |  0 ) & RegMask); */
 819                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 820         /*############################################################################################################################ */
 821
 822                 /*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050</p>
 823
 824                 Divisor value for this clock.
 825                 PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 826
 827                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 828                 (OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000300U)
 829                 RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 830
 831                 RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 832                         |  0 ) & RegMask); */
 833                 PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 834         /*############################################################################################################################ */
 835
 836                 // : VIDEO FRAC CFG
 837                 /*Register : VPLL_FRAC_CFG @ 0XFD1A0040</p>
 838
 839                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 840                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 841                 PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED                                               0x1
 842
 843                 Fractional value for the Feedback value.
 844                 PSU_CRF_APB_VPLL_FRAC_CFG_DATA                                                  0x820c
 845
 846                 Fractional control for the PLL
 847                 (OFFSET, MASK, VALUE)      (0XFD1A0040, 0x8000FFFFU ,0x8000820CU)
 848                 RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK |  0 );
 849
 850                 RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
 851                         | 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
 852                         |  0 ) & RegMask); */
 853                 PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU);
 854         /*############################################################################################################################ */
 855
 856
 857   return 1;
 858 }
 859 unsigned long psu_clock_init_data() {
 860                 // : CLOCK CONTROL SLCR REGISTER
 861                 /*Register : GEM3_REF_CTRL @ 0XFF5E005C</p>
 862
 863                 Clock active for the RX channel
 864                 PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1
 865
 866                 Clock active signal. Switch to 0 to disable the clock
 867                 PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1
 868
 869                 6 bit divider
 870                 PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x1
 871
 872                 6 bit divider
 873                 PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0xc
 874
 875                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 876                 clock. This is not usually an issue, but designers must be aware.)
 877                 PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0
 878
 879                 This register controls this reference clock
 880                 (OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06010C00U)
 881                 RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK |  0 );
 882
 883                 RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
 884                         | 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
 885                         | 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
 886                         | 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
 887                         | 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
 888                         |  0 ) & RegMask); */
 889                 PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U);
 890         /*############################################################################################################################ */
 891
 892                 /*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060</p>
 893
 894                 Clock active signal. Switch to 0 to disable the clock
 895                 PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1
 896
 897                 6 bit divider
 898                 PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1
 899
 900                 6 bit divider
 901                 PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x6
 902
 903                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 904                 clock. This is not usually an issue, but designers must be aware.)
 905                 PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0
 906
 907                 This register controls this reference clock
 908                 (OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02010600U)
 909                 RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK |  0 );
 910
 911                 RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
 912                         | 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
 913                         | 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
 914                         | 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
 915                         |  0 ) & RegMask); */
 916                 PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U);
 917         /*############################################################################################################################ */
 918
 919                 /*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C</p>
 920
 921                 Clock active signal. Switch to 0 to disable the clock
 922                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1
 923
 924                 6 bit divider
 925                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0xf
 926
 927                 6 bit divider
 928                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x5
 929
 930                 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 931                 clock. This is not usually an issue, but designers must be aware.)
 932                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0
 933
 934                 This register controls this reference clock
 935                 (OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x020F0500U)
 936                 RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK |  0 );
 937
 938                 RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
 939                         | 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
 940                         | 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
 941                         | 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
 942                         |  0 ) & RegMask); */
 943                 PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U);
 944         /*############################################################################################################################ */
 945
 946                 /*Register : QSPI_REF_CTRL @ 0XFF5E0068</p>
 947
 948                 Clock active signal. Switch to 0 to disable the clock
 949                 PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1
 950
 951                 6 bit divider
 952                 PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x1
 953
 954                 6 bit divider
 955                 PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0xc
 956
 957                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 958                 clock. This is not usually an issue, but designers must be aware.)
 959                 PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0
 960
 961                 This register controls this reference clock
 962                 (OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
 963                 RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK |  0 );
 964
 965                 RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
 966                         | 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
 967                         | 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
 968                         | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
 969                         |  0 ) & RegMask); */
 970                 PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U);
 971         /*############################################################################################################################ */
 972
 973                 /*Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>
 974
 975                 Clock active signal. Switch to 0 to disable the clock
 976                 PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1
 977
 978                 6 bit divider
 979                 PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x1
 980
 981                 6 bit divider
 982                 PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x6
 983
 984                 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 985                 clock. This is not usually an issue, but designers must be aware.)
 986                 PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x2
 987
 988                 This register controls this reference clock
 989                 (OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01010602U)
 990                 RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK |  0 );
 991
 992                 RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
 993                         | 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
 994                         | 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
 995                         | 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
 996                         |  0 ) & RegMask); */
 997                 PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
 998         /*############################################################################################################################ */
 999
1000                 /*Register : SDIO_CLK_CTRL @ 0XFF18030C</p>
1001
1002                 MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]
1003                 PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL                                     0
1004
1005                 SoC Debug Clock Control
1006                 (OFFSET, MASK, VALUE)      (0XFF18030C, 0x00020000U ,0x00000000U)
1007                 RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK |  0 );
1008
1009                 RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
1010                         |  0 ) & RegMask); */
1011                 PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U);
1012         /*############################################################################################################################ */
1013
1014                 /*Register : UART0_REF_CTRL @ 0XFF5E0074</p>
1015
1016                 Clock active signal. Switch to 0 to disable the clock
1017                 PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1
1018
1019                 6 bit divider
1020                 PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x1
1021
1022                 6 bit divider
1023                 PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0xf
1024
1025                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1026                 clock. This is not usually an issue, but designers must be aware.)
1027                 PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0
1028
1029                 This register controls this reference clock
1030                 (OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01010F00U)
1031                 RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK |  0 );
1032
1033                 RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
1034                         | 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
1035                         | 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
1036                         | 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
1037                         |  0 ) & RegMask); */
1038                 PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1039         /*############################################################################################################################ */
1040
1041                 /*Register : UART1_REF_CTRL @ 0XFF5E0078</p>
1042
1043                 Clock active signal. Switch to 0 to disable the clock
1044                 PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1
1045
1046                 6 bit divider
1047                 PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x1
1048
1049                 6 bit divider
1050                 PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0xf
1051
1052                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1053                 clock. This is not usually an issue, but designers must be aware.)
1054                 PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0
1055
1056                 This register controls this reference clock
1057                 (OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01010F00U)
1058                 RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK |  0 );
1059
1060                 RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
1061                         | 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
1062                         | 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
1063                         | 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
1064                         |  0 ) & RegMask); */
1065                 PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1066         /*############################################################################################################################ */
1067
1068                 /*Register : I2C0_REF_CTRL @ 0XFF5E0120</p>
1069
1070                 Clock active signal. Switch to 0 to disable the clock
1071                 PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1
1072
1073                 6 bit divider
1074                 PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x1
1075
1076                 6 bit divider
1077                 PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0xf
1078
1079                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1080                 clock. This is not usually an issue, but designers must be aware.)
1081                 PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0
1082
1083                 This register controls this reference clock
1084                 (OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01010F00U)
1085                 RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK |  0 );
1086
1087                 RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
1088                         | 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
1089                         | 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
1090                         | 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
1091                         |  0 ) & RegMask); */
1092                 PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1093         /*############################################################################################################################ */
1094
1095                 /*Register : I2C1_REF_CTRL @ 0XFF5E0124</p>
1096
1097                 Clock active signal. Switch to 0 to disable the clock
1098                 PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1
1099
1100                 6 bit divider
1101                 PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0x1
1102
1103                 6 bit divider
1104                 PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0xf
1105
1106                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1107                 clock. This is not usually an issue, but designers must be aware.)
1108                 PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0
1109
1110                 This register controls this reference clock
1111                 (OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x01010F00U)
1112                 RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK |  0 );
1113
1114                 RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
1115                         | 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
1116                         | 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
1117                         | 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
1118                         |  0 ) & RegMask); */
1119                 PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1120         /*############################################################################################################################ */
1121
1122                 /*Register : CAN1_REF_CTRL @ 0XFF5E0088</p>
1123
1124                 Clock active signal. Switch to 0 to disable the clock
1125                 PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1
1126
1127                 6 bit divider
1128                 PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x1
1129
1130                 6 bit divider
1131                 PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0xf
1132
1133                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1134                 clock. This is not usually an issue, but designers must be aware.)
1135                 PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0
1136
1137                 This register controls this reference clock
1138                 (OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01010F00U)
1139                 RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK |  0 );
1140
1141                 RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
1142                         | 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
1143                         | 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
1144                         | 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
1145                         |  0 ) & RegMask); */
1146                 PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1147         /*############################################################################################################################ */
1148
1149                 /*Register : CPU_R5_CTRL @ 0XFF5E0090</p>
1150
1151                 Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
1152                 d lead to system hang
1153                 PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1
1154
1155                 6 bit divider
1156                 PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x3
1157
1158                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1159                 clock. This is not usually an issue, but designers must be aware.)
1160                 PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2
1161
1162                 This register controls this reference clock
1163                 (OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01000302U)
1164                 RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK |  0 );
1165
1166                 RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
1167                         | 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
1168                         | 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
1169                         |  0 ) & RegMask); */
1170                 PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1171         /*############################################################################################################################ */
1172
1173                 /*Register : IOU_SWITCH_CTRL @ 0XFF5E009C</p>
1174
1175                 Clock active signal. Switch to 0 to disable the clock
1176                 PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1
1177
1178                 6 bit divider
1179                 PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6
1180
1181                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1182                 clock. This is not usually an issue, but designers must be aware.)
1183                 PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x2
1184
1185                 This register controls this reference clock
1186                 (OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000602U)
1187                 RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK |  0 );
1188
1189                 RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
1190                         | 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
1191                         | 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
1192                         |  0 ) & RegMask); */
1193                 PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1194         /*############################################################################################################################ */
1195
1196                 /*Register : PCAP_CTRL @ 0XFF5E00A4</p>
1197
1198                 Clock active signal. Switch to 0 to disable the clock
1199                 PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1
1200
1201                 6 bit divider
1202                 PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x6
1203
1204                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1205                 clock. This is not usually an issue, but designers must be aware.)
1206                 PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x2
1207
1208                 This register controls this reference clock
1209                 (OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000602U)
1210                 RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK |  0 );
1211
1212                 RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT
1213                         | 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
1214                         | 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
1215                         |  0 ) & RegMask); */
1216                 PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1217         /*############################################################################################################################ */
1218
1219                 /*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8</p>
1220
1221                 Clock active signal. Switch to 0 to disable the clock
1222                 PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1
1223
1224                 6 bit divider
1225                 PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x3
1226
1227                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1228                 clock. This is not usually an issue, but designers must be aware.)
1229                 PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2
1230
1231                 This register controls this reference clock
1232                 (OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000302U)
1233                 RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK |  0 );
1234
1235                 RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
1236                         | 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
1237                         | 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
1238                         |  0 ) & RegMask); */
1239                 PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1240         /*############################################################################################################################ */
1241
1242                 /*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC</p>
1243
1244                 Clock active signal. Switch to 0 to disable the clock
1245                 PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1
1246
1247                 6 bit divider
1248                 PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0xf
1249
1250                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1251                 clock. This is not usually an issue, but designers must be aware.)
1252                 PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2
1253
1254                 This register controls this reference clock
1255                 (OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01000F02U)
1256                 RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK |  0 );
1257
1258                 RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
1259                         | 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
1260                         | 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
1261                         |  0 ) & RegMask); */
1262                 PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U);
1263         /*############################################################################################################################ */
1264
1265                 /*Register : DBG_LPD_CTRL @ 0XFF5E00B0</p>
1266
1267                 Clock active signal. Switch to 0 to disable the clock
1268                 PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1
1269
1270                 6 bit divider
1271                 PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x6
1272
1273                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1274                 clock. This is not usually an issue, but designers must be aware.)
1275                 PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x2
1276
1277                 This register controls this reference clock
1278                 (OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01000602U)
1279                 RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK |  0 );
1280
1281                 RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
1282                         | 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
1283                         | 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
1284                         |  0 ) & RegMask); */
1285                 PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1286         /*############################################################################################################################ */
1287
1288                 /*Register : ADMA_REF_CTRL @ 0XFF5E00B8</p>
1289
1290                 Clock active signal. Switch to 0 to disable the clock
1291                 PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1
1292
1293                 6 bit divider
1294                 PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x3
1295
1296                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1297                 clock. This is not usually an issue, but designers must be aware.)
1298                 PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2
1299
1300                 This register controls this reference clock
1301                 (OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000302U)
1302                 RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK |  0 );
1303
1304                 RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
1305                         | 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
1306                         | 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
1307                         |  0 ) & RegMask); */
1308                 PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1309         /*############################################################################################################################ */
1310
1311                 /*Register : PL0_REF_CTRL @ 0XFF5E00C0</p>
1312
1313                 Clock active signal. Switch to 0 to disable the clock
1314                 PSU_CRL_APB_PL0_REF_CTRL_CLKACT                                                 0x1
1315
1316                 6 bit divider
1317                 PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1                                               0x1
1318
1319                 6 bit divider
1320                 PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0                                               0xf
1321
1322                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1323                 clock. This is not usually an issue, but designers must be aware.)
1324                 PSU_CRL_APB_PL0_REF_CTRL_SRCSEL                                                 0x0
1325
1326                 This register controls this reference clock
1327                 (OFFSET, MASK, VALUE)      (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)
1328                 RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK |  0 );
1329
1330                 RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
1331                         | 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
1332                         | 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
1333                         | 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
1334                         |  0 ) & RegMask); */
1335                 PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1336         /*############################################################################################################################ */
1337
1338                 /*Register : PL1_REF_CTRL @ 0XFF5E00C4</p>
1339
1340                 Clock active signal. Switch to 0 to disable the clock
1341                 PSU_CRL_APB_PL1_REF_CTRL_CLKACT                                                 0x1
1342
1343                 6 bit divider
1344                 PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1                                               0x4
1345
1346                 6 bit divider
1347                 PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0                                               0xf
1348
1349                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1350                 clock. This is not usually an issue, but designers must be aware.)
1351                 PSU_CRL_APB_PL1_REF_CTRL_SRCSEL                                                 0x0
1352
1353                 This register controls this reference clock
1354                 (OFFSET, MASK, VALUE)      (0XFF5E00C4, 0x013F3F07U ,0x01040F00U)
1355                 RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK |  0 );
1356
1357                 RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
1358                         | 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
1359                         | 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
1360                         | 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
1361                         |  0 ) & RegMask); */
1362                 PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U);
1363         /*############################################################################################################################ */
1364
1365                 /*Register : PL2_REF_CTRL @ 0XFF5E00C8</p>
1366
1367                 Clock active signal. Switch to 0 to disable the clock
1368                 PSU_CRL_APB_PL2_REF_CTRL_CLKACT                                                 0x1
1369
1370                 6 bit divider
1371                 PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1                                               0x1
1372
1373                 6 bit divider
1374                 PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0                                               0x4
1375
1376                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1377                 clock. This is not usually an issue, but designers must be aware.)
1378                 PSU_CRL_APB_PL2_REF_CTRL_SRCSEL                                                 0x2
1379
1380                 This register controls this reference clock
1381                 (OFFSET, MASK, VALUE)      (0XFF5E00C8, 0x013F3F07U ,0x01010402U)
1382                 RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK |  0 );
1383
1384                 RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
1385                         | 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
1386                         | 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
1387                         | 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
1388                         |  0 ) & RegMask); */
1389                 PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U);
1390         /*############################################################################################################################ */
1391
1392                 /*Register : PL3_REF_CTRL @ 0XFF5E00CC</p>
1393
1394                 Clock active signal. Switch to 0 to disable the clock
1395                 PSU_CRL_APB_PL3_REF_CTRL_CLKACT                                                 0x1
1396
1397                 6 bit divider
1398                 PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1                                               0x1
1399
1400                 6 bit divider
1401                 PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0                                               0x3
1402
1403                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1404                 clock. This is not usually an issue, but designers must be aware.)
1405                 PSU_CRL_APB_PL3_REF_CTRL_SRCSEL                                                 0x2
1406
1407                 This register controls this reference clock
1408                 (OFFSET, MASK, VALUE)      (0XFF5E00CC, 0x013F3F07U ,0x01010302U)
1409                 RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK |  0 );
1410
1411                 RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
1412                         | 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
1413                         | 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
1414                         | 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
1415                         |  0 ) & RegMask); */
1416                 PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U);
1417         /*############################################################################################################################ */
1418
1419                 /*Register : AMS_REF_CTRL @ 0XFF5E0108</p>
1420
1421                 6 bit divider
1422                 PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1
1423
1424                 6 bit divider
1425                 PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x1d
1426
1427                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1428                 clock. This is not usually an issue, but designers must be aware.)
1429                 PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x2
1430
1431                 Clock active signal. Switch to 0 to disable the clock
1432                 PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1
1433
1434                 This register controls this reference clock
1435                 (OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01011D02U)
1436                 RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK |  0 );
1437
1438                 RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
1439                         | 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
1440                         | 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
1441                         | 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
1442                         |  0 ) & RegMask); */
1443                 PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U);
1444         /*############################################################################################################################ */
1445
1446                 /*Register : DLL_REF_CTRL @ 0XFF5E0104</p>
1447
1448                 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1449                 is not usually an issue, but designers must be aware.)
1450                 PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0
1451
1452                 This register controls this reference clock
1453                 (OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)
1454                 RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK |  0 );
1455
1456                 RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
1457                         |  0 ) & RegMask); */
1458                 PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U);
1459         /*############################################################################################################################ */
1460
1461                 /*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128</p>
1462
1463                 6 bit divider
1464                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0xf
1465
1466                 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and
1467                  cycles of the new clock. This is not usually an issue, but designers must be aware.)
1468                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x0
1469
1470                 Clock active signal. Switch to 0 to disable the clock
1471                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1
1472
1473                 This register controls this reference clock
1474                 (OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01000F00U)
1475                 RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK |  0 );
1476
1477                 RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
1478                         | 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
1479                         | 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
1480                         |  0 ) & RegMask); */
1481                 PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U);
1482         /*############################################################################################################################ */
1483
1484                 /*Register : SATA_REF_CTRL @ 0XFD1A00A0</p>
1485
1486                 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1487                 he new clock. This is not usually an issue, but designers must be aware.)
1488                 PSU_CRF_APB_SATA_REF_CTRL_SRCSEL                                                0x0
1489
1490                 Clock active signal. Switch to 0 to disable the clock
1491                 PSU_CRF_APB_SATA_REF_CTRL_CLKACT                                                0x1
1492
1493                 6 bit divider
1494                 PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0                                              0x2
1495
1496                 This register controls this reference clock
1497                 (OFFSET, MASK, VALUE)      (0XFD1A00A0, 0x01003F07U ,0x01000200U)
1498                 RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK |  0 );
1499
1500                 RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
1501                         | 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
1502                         | 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
1503                         |  0 ) & RegMask); */
1504                 PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1505         /*############################################################################################################################ */
1506
1507                 /*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070</p>
1508
1509                 6 bit divider
1510                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x1
1511
1512                 6 bit divider
1513                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x3
1514
1515                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1516                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
1517                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x3
1518
1519                 Clock active signal. Switch to 0 to disable the clock
1520                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1
1521
1522                 This register controls this reference clock
1523                 (OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01010303U)
1524                 RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK |  0 );
1525
1526                 RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
1527                         | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
1528                         | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
1529                         | 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
1530                         |  0 ) & RegMask); */
1531                 PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U);
1532         /*############################################################################################################################ */
1533
1534                 /*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074</p>
1535
1536                 6 bit divider
1537                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x1
1538
1539                 6 bit divider
1540                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x27
1541
1542                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1543                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
1544                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0
1545
1546                 Clock active signal. Switch to 0 to disable the clock
1547                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1
1548
1549                 This register controls this reference clock
1550                 (OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01012700U)
1551                 RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK |  0 );
1552
1553                 RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
1554                         | 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
1555                         | 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
1556                         | 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
1557                         |  0 ) & RegMask); */
1558                 PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U);
1559         /*############################################################################################################################ */
1560
1561                 /*Register : DP_STC_REF_CTRL @ 0XFD1A007C</p>
1562
1563                 6 bit divider
1564                 PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x1
1565
1566                 6 bit divider
1567                 PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x11
1568
1569                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
1570                 e new clock. This is not usually an issue, but designers must be aware.)
1571                 PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x3
1572
1573                 Clock active signal. Switch to 0 to disable the clock
1574                 PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1
1575
1576                 This register controls this reference clock
1577                 (OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01011103U)
1578                 RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK |  0 );
1579
1580                 RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
1581                         | 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
1582                         | 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
1583                         | 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
1584                         |  0 ) & RegMask); */
1585                 PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U);
1586         /*############################################################################################################################ */
1587
1588                 /*Register : ACPU_CTRL @ 0XFD1A0060</p>
1589
1590                 6 bit divider
1591                 PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0x1
1592
1593                 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1594                 lock. This is not usually an issue, but designers must be aware.)
1595                 PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0
1596
1597                 Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
1598                 PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1
1599
1600                 Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
1601                  to the entire APU
1602                 PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1
1603
1604                 This register controls this reference clock
1605                 (OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03000100U)
1606                 RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |  0 );
1607
1608                 RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
1609                         | 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
1610                         | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
1611                         | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
1612                         |  0 ) & RegMask); */
1613                 PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U);
1614         /*############################################################################################################################ */
1615
1616                 /*Register : DBG_TRACE_CTRL @ 0XFD1A0064</p>
1617
1618                 6 bit divider
1619                 PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x2
1620
1621                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1622                 he new clock. This is not usually an issue, but designers must be aware.)
1623                 PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x0
1624
1625                 Clock active signal. Switch to 0 to disable the clock
1626                 PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1
1627
1628                 This register controls this reference clock
1629                 (OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01000200U)
1630                 RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK |  0 );
1631
1632                 RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
1633                         | 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
1634                         | 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
1635                         |  0 ) & RegMask); */
1636                 PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1637         /*############################################################################################################################ */
1638
1639                 /*Register : DBG_FPD_CTRL @ 0XFD1A0068</p>
1640
1641                 6 bit divider
1642                 PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x2
1643
1644                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1645                 he new clock. This is not usually an issue, but designers must be aware.)
1646                 PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x0
1647
1648                 Clock active signal. Switch to 0 to disable the clock
1649                 PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1
1650
1651                 This register controls this reference clock
1652                 (OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01000200U)
1653                 RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK |  0 );
1654
1655                 RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
1656                         | 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
1657                         | 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
1658                         |  0 ) & RegMask); */
1659                 PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1660         /*############################################################################################################################ */
1661
1662                 /*Register : DDR_CTRL @ 0XFD1A0080</p>
1663
1664                 6 bit divider
1665                 PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0x2
1666
1667                 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1668                 s not usually an issue, but designers must be aware.)
1669                 PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0
1670
1671                 This register controls this reference clock
1672                 (OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000200U)
1673                 RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK |  0 );
1674
1675                 RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
1676                         | 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT
1677                         |  0 ) & RegMask); */
1678                 PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
1679         /*############################################################################################################################ */
1680
1681                 /*Register : GPU_REF_CTRL @ 0XFD1A0084</p>
1682
1683                 6 bit divider
1684                 PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x1
1685
1686                 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1687                 he new clock. This is not usually an issue, but designers must be aware.)
1688                 PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x0
1689
1690                 Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).
1691                 PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1
1692
1693                 Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
1694                 PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1
1695
1696                 Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
1697                 PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1
1698
1699                 This register controls this reference clock
1700                 (OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07000100U)
1701                 RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK |  0 );
1702
1703                 RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
1704                         | 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
1705                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
1706                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
1707                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
1708                         |  0 ) & RegMask); */
1709                 PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U);
1710         /*############################################################################################################################ */
1711
1712                 /*Register : GDMA_REF_CTRL @ 0XFD1A00B8</p>
1713
1714                 6 bit divider
1715                 PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x2
1716
1717                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1718                 lock. This is not usually an issue, but designers must be aware.)
1719                 PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x0
1720
1721                 Clock active signal. Switch to 0 to disable the clock
1722                 PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1
1723
1724                 This register controls this reference clock
1725                 (OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000200U)
1726                 RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK |  0 );
1727
1728                 RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
1729                         | 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
1730                         | 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
1731                         |  0 ) & RegMask); */
1732                 PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1733         /*############################################################################################################################ */
1734
1735                 /*Register : DPDMA_REF_CTRL @ 0XFD1A00BC</p>
1736
1737                 6 bit divider
1738                 PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x2
1739
1740                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1741                 lock. This is not usually an issue, but designers must be aware.)
1742                 PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x0
1743
1744                 Clock active signal. Switch to 0 to disable the clock
1745                 PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1
1746
1747                 This register controls this reference clock
1748                 (OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000200U)
1749                 RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK |  0 );
1750
1751                 RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
1752                         | 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
1753                         | 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
1754                         |  0 ) & RegMask); */
1755                 PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1756         /*############################################################################################################################ */
1757
1758                 /*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0</p>
1759
1760                 6 bit divider
1761                 PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x2
1762
1763                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1764                 lock. This is not usually an issue, but designers must be aware.)
1765                 PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x2
1766
1767                 Clock active signal. Switch to 0 to disable the clock
1768                 PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1
1769
1770                 This register controls this reference clock
1771                 (OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000202U)
1772                 RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK |  0 );
1773
1774                 RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
1775                         | 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
1776                         | 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
1777                         |  0 ) & RegMask); */
1778                 PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U);
1779         /*############################################################################################################################ */
1780
1781                 /*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4</p>
1782
1783                 6 bit divider
1784                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x5
1785
1786                 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1787                 he new clock. This is not usually an issue, but designers must be aware.)
1788                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x2
1789
1790                 Clock active signal. Switch to 0 to disable the clock
1791                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1
1792
1793                 This register controls this reference clock
1794                 (OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01000502U)
1795                 RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK |  0 );
1796
1797                 RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
1798                         | 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
1799                         | 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
1800                         |  0 ) & RegMask); */
1801                 PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U);
1802         /*############################################################################################################################ */
1803
1804                 /*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8</p>
1805
1806                 6 bit divider
1807                 PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x2
1808
1809                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1810                 he new clock. This is not usually an issue, but designers must be aware.)
1811                 PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x0
1812
1813                 This register controls this reference clock
1814                 (OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000200U)
1815                 RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK |  0 );
1816
1817                 RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
1818                         | 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
1819                         |  0 ) & RegMask); */
1820                 PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
1821         /*############################################################################################################################ */
1822
1823                 /*Register : IOU_TTC_APB_CLK @ 0XFF180380</p>
1824
1825                 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
1826                 0" = Select the R5 clock for the APB interface of TTC0
1827                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL                                           0
1828
1829                 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
1830                 0" = Select the R5 clock for the APB interface of TTC1
1831                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL                                           0
1832
1833                 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
1834                 0" = Select the R5 clock for the APB interface of TTC2
1835                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL                                           0
1836
1837                 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
1838                 0" = Select the R5 clock for the APB interface of TTC3
1839                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL                                           0
1840
1841                 TTC APB clock select
1842                 (OFFSET, MASK, VALUE)      (0XFF180380, 0x000000FFU ,0x00000000U)
1843                 RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK |  0 );
1844
1845                 RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
1846                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
1847                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
1848                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
1849                         |  0 ) & RegMask); */
1850                 PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U);
1851         /*############################################################################################################################ */
1852
1853                 /*Register : WDT_CLK_SEL @ 0XFD610100</p>
1854
1855                 System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)
1856                 PSU_FPD_SLCR_WDT_CLK_SEL_SELECT                                                 0
1857
1858                 SWDT clock source select
1859                 (OFFSET, MASK, VALUE)      (0XFD610100, 0x00000001U ,0x00000000U)
1860                 RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
1861
1862                 RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
1863                         |  0 ) & RegMask); */
1864                 PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
1865         /*############################################################################################################################ */
1866
1867                 /*Register : WDT_CLK_SEL @ 0XFF180300</p>
1868
1869                 System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout
1870                 ia MIO
1871                 PSU_IOU_SLCR_WDT_CLK_SEL_SELECT                                                 0
1872
1873                 SWDT clock source select
1874                 (OFFSET, MASK, VALUE)      (0XFF180300, 0x00000001U ,0x00000000U)
1875                 RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
1876
1877                 RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
1878                         |  0 ) & RegMask); */
1879                 PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
1880         /*############################################################################################################################ */
1881
1882                 /*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050</p>
1883
1884                 System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk
1885                 PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT                                          0
1886
1887                 SWDT clock source select
1888                 (OFFSET, MASK, VALUE)      (0XFF410050, 0x00000001U ,0x00000000U)
1889                 RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK |  0 );
1890
1891                 RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
1892                         |  0 ) & RegMask); */
1893                 PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
1894         /*############################################################################################################################ */
1895
1896
1897   return 1;
1898 }
1899 unsigned long psu_ddr_init_data() {
1900                 // : DDR INITIALIZATION
1901                 // : DDR CONTROLLER RESET
1902                 /*Register : RST_DDR_SS @ 0XFD1A0108</p>
1903
1904                 DDR block level reset inside of the DDR Sub System
1905                 PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X1
1906
1907                 DDR sub system block level reset
1908                 (OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000008U)
1909                 RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
1910
1911                 RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
1912                         |  0 ) & RegMask); */
1913                 PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U);
1914         /*############################################################################################################################ */
1915
1916                 /*Register : MSTR @ 0XFD070000</p>
1917
1918                 Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32
1919                 evice
1920                 PSU_DDRC_MSTR_DEVICE_CONFIG                                                     0x1
1921
1922                 Choose which registers are used. - 0 - Original registers - 1 - Shadow registers
1923                 PSU_DDRC_MSTR_FREQUENCY_MODE                                                    0x0
1924
1925                 Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
1926                 esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 -
1927                 ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
1928                 ks - 1111 - Four ranks
1929                 PSU_DDRC_MSTR_ACTIVE_RANKS                                                      0x1
1930
1931                 SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
1932                  of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls
1933                 he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
1934                 -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
1935                  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
1936                 PSU_DDRC_MSTR_BURST_RDWR                                                        0x4
1937
1938                 Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM
1939                 n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
1940                 l_off_mode is not supported, and this bit must be set to '0'.
1941                 PSU_DDRC_MSTR_DLL_OFF_MODE                                                      0x0
1942
1943                 Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
1944                 AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
1945                 dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
1946                 figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).
1947                 PSU_DDRC_MSTR_DATA_BUS_WIDTH                                                    0x0
1948
1949                 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
1950                  only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode
1951                 s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set
1952                 PSU_DDRC_MSTR_GEARDOWN_MODE                                                     0x0
1953
1954                 If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held
1955                 or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in
1956                 PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
1957                 ing is not supported in DDR4 geardown mode.
1958                 PSU_DDRC_MSTR_EN_2T_TIMING_MODE                                                 0x0
1959
1960                 When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
1961                 t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
1962                  (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
1963                 _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'
1964                 PSU_DDRC_MSTR_BURSTCHOP                                                         0x0
1965
1966                 Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
1967                 port LPDDR4.
1968                 PSU_DDRC_MSTR_LPDDR4                                                            0x0
1969
1970                 Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support
1971                 DR4.
1972                 PSU_DDRC_MSTR_DDR4                                                              0x1
1973
1974                 Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
1975                 port LPDDR3.
1976                 PSU_DDRC_MSTR_LPDDR3                                                            0x0
1977
1978                 Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
1979                 port LPDDR2.
1980                 PSU_DDRC_MSTR_LPDDR2                                                            0x0
1981
1982                 Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
1983
1984                 PSU_DDRC_MSTR_DDR3                                                              0x0
1985
1986                 Master Register
1987                 (OFFSET, MASK, VALUE)      (0XFD070000, 0xE30FBE3DU ,0x41040010U)
1988                 RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK |  0 );
1989
1990                 RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT
1991                         | 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT
1992                         | 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT
1993                         | 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT
1994                         | 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT
1995                         | 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
1996                         | 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT
1997                         | 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
1998                         | 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT
1999                         | 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT
2000                         | 0x00000001U << DDRC_MSTR_DDR4_SHIFT
2001                         | 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT
2002                         | 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT
2003                         | 0x00000000U << DDRC_MSTR_DDR3_SHIFT
2004                         |  0 ) & RegMask); */
2005                 PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U);
2006         /*############################################################################################################################ */
2007
2008                 /*Register : MRCTRL0 @ 0XFD070010</p>
2009
2010                 Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
2011                  automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
2012                 re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
2013                 PSU_DDRC_MRCTRL0_MR_WR                                                          0x0
2014
2015                 Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
2016                  - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
2017                 R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
2018                 dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well
2019                 s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
2020                 put Inversion of RDIMMs.
2021                 PSU_DDRC_MRCTRL0_MR_ADDR                                                        0x0
2022
2023                 Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
2024                  However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
2025                 amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks
2026                  and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3
2027                 PSU_DDRC_MRCTRL0_MR_RANK                                                        0x3
2028
2029                 Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not.
2030                 or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
2031                  be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared
2032                 o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
2033                 n is not allowed - 1 - Software intervention is allowed
2034                 PSU_DDRC_MRCTRL0_SW_INIT_INT                                                    0x0
2035
2036                 Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
2037                 PSU_DDRC_MRCTRL0_PDA_EN                                                         0x0
2038
2039                 Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
2040                 PSU_DDRC_MRCTRL0_MPR_EN                                                         0x0
2041
2042                 Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
2043                 d
2044                 PSU_DDRC_MRCTRL0_MR_TYPE                                                        0x0
2045
2046                 Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i
2047                 it_int - pda_en - mpr_en
2048                 (OFFSET, MASK, VALUE)      (0XFD070010, 0x8000F03FU ,0x00000030U)
2049                 RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK |  0 );
2050
2051                 RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT
2052                         | 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT
2053                         | 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT
2054                         | 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT
2055                         | 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT
2056                         | 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT
2057                         | 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT
2058                         |  0 ) & RegMask); */
2059                 PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U);
2060         /*############################################################################################################################ */
2061
2062                 /*Register : DERATEEN @ 0XFD070020</p>
2063
2064                 Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
2065                  Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
2066                 g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
2067                 PSU_DDRC_DERATEEN_RC_DERATE_VALUE                                               0x3
2068
2069                 Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
2070                 r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
2071                 PSU_DDRC_DERATEEN_DERATE_BYTE                                                   0x0
2072
2073                 Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
2074                 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
2075                 for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.
2076                 PSU_DDRC_DERATEEN_DERATE_VALUE                                                  0x0
2077
2078                 Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
2079                 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
2080                 mode.
2081                 PSU_DDRC_DERATEEN_DERATE_ENABLE                                                 0x0
2082
2083                 Temperature Derate Enable Register
2084                 (OFFSET, MASK, VALUE)      (0XFD070020, 0x000003F3U ,0x00000300U)
2085                 RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK |  0 );
2086
2087                 RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
2088                         | 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT
2089                         | 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT
2090                         | 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT
2091                         |  0 ) & RegMask); */
2092                 PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U);
2093         /*############################################################################################################################ */
2094
2095                 /*Register : DERATEINT @ 0XFD070024</p>
2096
2097                 Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
2098                 DR3/LPDDR4. This register must not be set to zero
2099                 PSU_DDRC_DERATEINT_MR4_READ_INTERVAL                                            0x800000
2100
2101                 Temperature Derate Interval Register
2102                 (OFFSET, MASK, VALUE)      (0XFD070024, 0xFFFFFFFFU ,0x00800000U)
2103                 RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK |  0 );
2104
2105                 RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
2106                         |  0 ) & RegMask); */
2107                 PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U);
2108         /*############################################################################################################################ */
2109
2110                 /*Register : PWRCTL @ 0XFD070030</p>
2111
2112                 Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
2113                 r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state -
2114                  - Allow transition from Self refresh state
2115                 PSU_DDRC_PWRCTL_STAY_IN_SELFREF                                                 0x0
2116
2117                 A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
2118                 M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
2119                 are Exit from Self Refresh
2120                 PSU_DDRC_PWRCTL_SELFREF_SW                                                      0x0
2121
2122                 When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
2123                 st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For
2124                 on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
2125                 DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
2126                 PSU_DDRC_PWRCTL_MPSM_EN                                                         0x0
2127
2128                 Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
2129                 is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
2130                 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in
2131                 ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
2132                 rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)
2133                 PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE                                         0x0
2134
2135                 When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
2136                 et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down
2137                 xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
2138                  should not be set to 1. FOR PERFORMANCE ONLY.
2139                 PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN                                                0x0
2140
2141                 If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
2142                 RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.
2143                 PSU_DDRC_PWRCTL_POWERDOWN_EN                                                    0x0
2144
2145                 If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
2146                 f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.
2147                 PSU_DDRC_PWRCTL_SELFREF_EN                                                      0x0
2148
2149                 Low Power Control Register
2150                 (OFFSET, MASK, VALUE)      (0XFD070030, 0x0000007FU ,0x00000000U)
2151                 RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK |  0 );
2152
2153                 RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
2154                         | 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT
2155                         | 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT
2156                         | 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
2157                         | 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
2158                         | 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT
2159                         | 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT
2160                         |  0 ) & RegMask); */
2161                 PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U);
2162         /*############################################################################################################################ */
2163
2164                 /*Register : PWRTMG @ 0XFD070034</p>
2165
2166                 After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in
2167                 he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2168                 PSU_DDRC_PWRTMG_SELFREF_TO_X32                                                  0x40
2169
2170                 Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
2171                 ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
2172                 iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.
2173                 PSU_DDRC_PWRTMG_T_DPD_X4096                                                     0x84
2174
2175                 After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
2176                  PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
2177                 PSU_DDRC_PWRTMG_POWERDOWN_TO_X32                                                0x10
2178
2179                 Low Power Timing Register
2180                 (OFFSET, MASK, VALUE)      (0XFD070034, 0x00FFFF1FU ,0x00408410U)
2181                 RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK |  0 );
2182
2183                 RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
2184                         | 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT
2185                         | 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
2186                         |  0 ) & RegMask); */
2187                 PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U);
2188         /*############################################################################################################################ */
2189
2190                 /*Register : RFSHCTL0 @ 0XFD070050</p>
2191
2192                 Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
2193                 d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
2194                  It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
2195                 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
2196                 om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.
2197                 PSU_DDRC_RFSHCTL0_REFRESH_MARGIN                                                0x2
2198
2199                 If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
2200                 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
2201                  would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
2202                 HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
2203                 formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
2204                 ued to the uMCTL2. FOR PERFORMANCE ONLY.
2205                 PSU_DDRC_RFSHCTL0_REFRESH_TO_X32                                                0x10
2206
2207                 The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
2208                 reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
2209                 reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
2210                 RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
2211                 . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
2212                 tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
2213                 fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
2214                 ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
2215                 tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
2216                 d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
2217                 initiated update is complete.
2218                 PSU_DDRC_RFSHCTL0_REFRESH_BURST                                                 0x0
2219
2220                 - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
2221                 t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
2222                 support LPDDR2/LPDDR3/LPDDR4
2223                 PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH                                              0x0
2224
2225                 Refresh Control Register 0
2226                 (OFFSET, MASK, VALUE)      (0XFD070050, 0x00F1F1F4U ,0x00210000U)
2227                 RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK |  0 );
2228
2229                 RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
2230                         | 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
2231                         | 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
2232                         | 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
2233                         |  0 ) & RegMask); */
2234                 PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U);
2235         /*############################################################################################################################ */
2236
2237                 /*Register : RFSHCTL3 @ 0XFD070060</p>
2238
2239                 Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
2240                 ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
2241                 orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
2242                 self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in
2243                 uture version of the uMCTL2.
2244                 PSU_DDRC_RFSHCTL3_REFRESH_MODE                                                  0x0
2245
2246                 Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value
2247                 s automatically updated when exiting reset, so it does not need to be toggled initially.
2248                 PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL                                          0x0
2249
2250                 When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
2251                 ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
2252                 auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
2253                 is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'.
2254                 his register field is changeable on the fly.
2255                 PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH                                              0x1
2256
2257                 Refresh Control Register 3
2258                 (OFFSET, MASK, VALUE)      (0XFD070060, 0x00000073U ,0x00000001U)
2259                 RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK |  0 );
2260
2261                 RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
2262                         | 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
2263                         | 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
2264                         |  0 ) & RegMask); */
2265                 PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U);
2266         /*############################################################################################################################ */
2267
2268                 /*Register : RFSHTMG @ 0XFD070064</p>
2269
2270                 tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
2271                  for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
2272                 , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should
2273                 e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
2274                 ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
2275                 programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
2276                 TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.
2277                 PSU_DDRC_RFSHTMG_T_RFC_NOM_X32                                                  0x82
2278
2279                 Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the
2280                 REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
2281                  - 0 - tREFBW parameter not used - 1 - tREFBW parameter used
2282                 PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN                                               0x1
2283
2284                 tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
2285                  RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
2286                 DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
2287                  per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
2288                 equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
2289                 opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.
2290                 PSU_DDRC_RFSHTMG_T_RFC_MIN                                                      0x8b
2291
2292                 Refresh Timing Register
2293                 (OFFSET, MASK, VALUE)      (0XFD070064, 0x0FFF83FFU ,0x0082808BU)
2294                 RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK |  0 );
2295
2296                 RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
2297                         | 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
2298                         | 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT
2299                         |  0 ) & RegMask); */
2300                 PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU);
2301         /*############################################################################################################################ */
2302
2303                 /*Register : ECCCFG0 @ 0XFD070070</p>
2304
2305                 Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined
2306                 PSU_DDRC_ECCCFG0_DIS_SCRUB                                                      0x1
2307
2308                 ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
2309                  use
2310                 PSU_DDRC_ECCCFG0_ECC_MODE                                                       0x0
2311
2312                 ECC Configuration Register 0
2313                 (OFFSET, MASK, VALUE)      (0XFD070070, 0x00000017U ,0x00000010U)
2314                 RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK |  0 );
2315
2316                 RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT
2317                         | 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT
2318                         |  0 ) & RegMask); */
2319                 PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U);
2320         /*############################################################################################################################ */
2321
2322                 /*Register : ECCCFG1 @ 0XFD070074</p>
2323
2324                 Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
2325                 ng, if ECCCFG1.data_poison_en=1
2326                 PSU_DDRC_ECCCFG1_DATA_POISON_BIT                                                0x0
2327
2328                 Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers
2329                 PSU_DDRC_ECCCFG1_DATA_POISON_EN                                                 0x0
2330
2331                 ECC Configuration Register 1
2332                 (OFFSET, MASK, VALUE)      (0XFD070074, 0x00000003U ,0x00000000U)
2333                 RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK |  0 );
2334
2335                 RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
2336                         | 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
2337                         |  0 ) & RegMask); */
2338                 PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U);
2339         /*############################################################################################################################ */
2340
2341                 /*Register : CRCPARCTL1 @ 0XFD0700C4</p>
2342
2343                 The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
2344                 the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY
2345                 pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
2346                 L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
2347                 dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
2348                 e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks
2349                 PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT                                             0x10
2350
2351                 After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
2352                 M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
2353                 the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
2354                 the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
2355                 RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
2356                  handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
2357                 rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
2358                 ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in
2359                 he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is
2360                 one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in
2361                 PR Page 1 should be treated as 'Don't care'.
2362                 PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW                                           0x1
2363
2364                 - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
2365                  CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
2366                  disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)
2367                 PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE                                     0x0
2368
2369                 CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
2370                 d to support DDR4.
2371                 PSU_DDRC_CRCPARCTL1_CRC_INC_DM                                                  0x0
2372
2373                 CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
2374                  CRC mode register setting in the DRAM.
2375                 PSU_DDRC_CRCPARCTL1_CRC_ENABLE                                                  0x0
2376
2377                 C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of
2378                 /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
2379                 is register should be 1.
2380                 PSU_DDRC_CRCPARCTL1_PARITY_ENABLE                                               0x0
2381
2382                 CRC Parity Control Register1
2383                 (OFFSET, MASK, VALUE)      (0XFD0700C4, 0x3F000391U ,0x10000200U)
2384                 RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK |  0 );
2385
2386                 RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
2387                         | 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
2388                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
2389                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
2390                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
2391                         | 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
2392                         |  0 ) & RegMask); */
2393                 PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U);
2394         /*############################################################################################################################ */
2395
2396                 /*Register : CRCPARCTL2 @ 0XFD0700C8</p>
2397
2398                 Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
2399                  - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
2400                 er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
2401                 PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX                                          0x40
2402
2403                 Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
2404                 tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
2405                 value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
2406                 PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX                                          0x5
2407
2408                 Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
2409                 ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
2410                 er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
2411                 les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
2412                 or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
2413                 ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
2414                 max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
2415                 bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
2416                 + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
2417                 ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The
2418                 ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
2419                 to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
2420                  Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
2421                 PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
2422                 _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
2423                 C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
2424                 e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
2425                  bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
2426                 H-6 Values of 0, 1 and 2 are illegal.
2427                 PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4                                0x1f
2428
2429                 CRC Parity Control Register2
2430                 (OFFSET, MASK, VALUE)      (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)
2431                 RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK |  0 );
2432
2433                 RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
2434                         | 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
2435                         | 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
2436                         |  0 ) & RegMask); */
2437                 PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU);
2438         /*############################################################################################################################ */
2439
2440                 /*Register : INIT0 @ 0XFD0700D0</p>
2441
2442                 If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
2443                  in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
2444                 ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
2445                 r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported
2446                 or LPDDR4 in this version of the uMCTL2.
2447                 PSU_DDRC_INIT0_SKIP_DRAM_INIT                                                   0x0
2448
2449                 Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires
2450                  400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
2451                 grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
2452                 MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.
2453                 PSU_DDRC_INIT0_POST_CKE_X1024                                                   0x2
2454
2455                 Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2
2456                 pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
2457                 tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
2458                  to next integer value.
2459                 PSU_DDRC_INIT0_PRE_CKE_X1024                                                    0x106
2460
2461                 SDRAM Initialization Register 0
2462                 (OFFSET, MASK, VALUE)      (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)
2463                 RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK |  0 );
2464
2465                 RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
2466                         | 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT
2467                         | 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT
2468                         |  0 ) & RegMask); */
2469                 PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U);
2470         /*############################################################################################################################ */
2471
2472                 /*Register : INIT1 @ 0XFD0700D4</p>
2473
2474                 Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
2475                 LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1
2476                 PSU_DDRC_INIT1_DRAM_RSTN_X1024                                                  0x2
2477
2478                 Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
2479                 bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.
2480                 PSU_DDRC_INIT1_FINAL_WAIT_X32                                                   0x0
2481
2482                 Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
2483                 . There is no known specific requirement for this; it may be set to zero.
2484                 PSU_DDRC_INIT1_PRE_OCD_X32                                                      0x0
2485
2486                 SDRAM Initialization Register 1
2487                 (OFFSET, MASK, VALUE)      (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)
2488                 RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK |  0 );
2489
2490                 RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
2491                         | 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT
2492                         | 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT
2493                         |  0 ) & RegMask); */
2494                 PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U);
2495         /*############################################################################################################################ */
2496
2497                 /*Register : INIT2 @ 0XFD0700D8</p>
2498
2499                 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.
2500                 PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32                                             0x23
2501
2502                 Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
2503                 e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.
2504                 PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1                                              0x5
2505
2506                 SDRAM Initialization Register 2
2507                 (OFFSET, MASK, VALUE)      (0XFD0700D8, 0x0000FF0FU ,0x00002305U)
2508                 RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK |  0 );
2509
2510                 RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
2511                         | 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
2512                         |  0 ) & RegMask); */
2513                 PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U);
2514         /*############################################################################################################################ */
2515
2516                 /*Register : INIT3 @ 0XFD0700DC</p>
2517
2518                 DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
2519                  DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
2520                 register
2521                 PSU_DDRC_INIT3_MR                                                               0x930
2522
2523                 DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
2524                 bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
2525                  bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
2526                 lue to write to MR2 register
2527                 PSU_DDRC_INIT3_EMR                                                              0x301
2528
2529                 SDRAM Initialization Register 3
2530                 (OFFSET, MASK, VALUE)      (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U)
2531                 RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK |  0 );
2532
2533                 RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT
2534                         | 0x00000301U << DDRC_INIT3_EMR_SHIFT
2535                         |  0 ) & RegMask); */
2536                 PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U);
2537         /*############################################################################################################################ */
2538
2539                 /*Register : INIT4 @ 0XFD0700E0</p>
2540
2541                 DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3
2542                 egister mDDR: Unused
2543                 PSU_DDRC_INIT4_EMR2                                                             0x20
2544
2545                 DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to
2546                 rite to MR13 register
2547                 PSU_DDRC_INIT4_EMR3                                                             0x200
2548
2549                 SDRAM Initialization Register 4
2550                 (OFFSET, MASK, VALUE)      (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)
2551                 RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK |  0 );
2552
2553                 RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT
2554                         | 0x00000200U << DDRC_INIT4_EMR3_SHIFT
2555                         |  0 ) & RegMask); */
2556                 PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U);
2557         /*############################################################################################################################ */
2558
2559                 /*Register : INIT5 @ 0XFD0700E4</p>
2560
2561                 ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock
2562                 ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.
2563                 PSU_DDRC_INIT5_DEV_ZQINIT_X32                                                   0x21
2564
2565                 Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
2566                 3 typically requires 10 us.
2567                 PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024                                              0x4
2568
2569                 SDRAM Initialization Register 5
2570                 (OFFSET, MASK, VALUE)      (0XFD0700E4, 0x00FF03FFU ,0x00210004U)
2571                 RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK |  0 );
2572
2573                 RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
2574                         | 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
2575                         |  0 ) & RegMask); */
2576                 PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U);
2577         /*############################################################################################################################ */
2578
2579                 /*Register : INIT6 @ 0XFD0700E8</p>
2580
2581                 DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
2582                 PSU_DDRC_INIT6_MR4                                                              0x0
2583
2584                 DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
2585                 PSU_DDRC_INIT6_MR5                                                              0x6c0
2586
2587                 SDRAM Initialization Register 6
2588                 (OFFSET, MASK, VALUE)      (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)
2589                 RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK |  0 );
2590
2591                 RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT
2592                         | 0x000006C0U << DDRC_INIT6_MR5_SHIFT
2593                         |  0 ) & RegMask); */
2594                 PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
2595         /*############################################################################################################################ */
2596
2597                 /*Register : INIT7 @ 0XFD0700EC</p>
2598
2599                 DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
2600                 PSU_DDRC_INIT7_MR6                                                              0x819
2601
2602                 SDRAM Initialization Register 7
2603                 (OFFSET, MASK, VALUE)      (0XFD0700EC, 0xFFFF0000U ,0x08190000U)
2604                 RegMask = (DDRC_INIT7_MR6_MASK |  0 );
2605
2606                 RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT
2607                         |  0 ) & RegMask); */
2608                 PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U);
2609         /*############################################################################################################################ */
2610
2611                 /*Register : DIMMCTL @ 0XFD0700F0</p>
2612
2613                 Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
2614                 ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
2615                  address mirroring is enabled.
2616                 PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING                                          0x0
2617
2618                 Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
2619                  be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output
2620                 nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
2621                 effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
2622                 led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled
2623                 PSU_DDRC_DIMMCTL_MRS_BG1_EN                                                     0x1
2624
2625                 Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
2626                  be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled,
2627                 his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address
2628                 f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled
2629                 PSU_DDRC_DIMMCTL_MRS_A17_EN                                                     0x0
2630
2631                 Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
2632                 which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17,
2633                 A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
2634                 lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated.
2635                 or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
2636                  has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
2637                 ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.
2638                 PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN                                             0x0
2639
2640                 Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
2641                 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits
2642                 re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
2643                 at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
2644                 sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
2645                  swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
2646                 ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
2647                 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
2648                 hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
2649                 ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
2650                 not implement address mirroring
2651                 PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN                                              0x0
2652
2653                 Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
2654                 R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
2655                 CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
2656                  each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses
2657                 PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN                                             0x0
2658
2659                 DIMM Control Register
2660                 (OFFSET, MASK, VALUE)      (0XFD0700F0, 0x0000003FU ,0x00000010U)
2661                 RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK |  0 );
2662
2663                 RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
2664                         | 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
2665                         | 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT
2666                         | 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
2667                         | 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
2668                         | 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
2669                         |  0 ) & RegMask); */
2670                 PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U);
2671         /*############################################################################################################################ */
2672
2673                 /*Register : RANKCTL @ 0XFD0700F4</p>
2674
2675                 Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
2676                 e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
2677                 nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
2678                 ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
2679                 ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed
2680                 n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
2681                 ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
2682                 or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
2683                  to the next integer.
2684                 PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP                                               0x6
2685
2686                 Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
2687                 e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
2688                 sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
2689                 p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
2690                 ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
2691                 requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
2692                 quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and
2693                 ound it up to the next integer.
2694                 PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP                                               0x6
2695
2696                 Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
2697                 nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
2698                 on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
2699                 -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
2700                 _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
2701                 om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
2702                 ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to
2703                 llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
2704                 ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as
2705                 ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
2706                 . FOR PERFORMANCE ONLY.
2707                 PSU_DDRC_RANKCTL_MAX_RANK_RD                                                    0xf
2708
2709                 Rank Control Register
2710                 (OFFSET, MASK, VALUE)      (0XFD0700F4, 0x00000FFFU ,0x0000066FU)
2711                 RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK |  0 );
2712
2713                 RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
2714                         | 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
2715                         | 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT
2716                         |  0 ) & RegMask); */
2717                 PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU);
2718         /*############################################################################################################################ */
2719
2720                 /*Register : DRAMTMG0 @ 0XFD070100</p>
2721
2722                 Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles
2723                  15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
2724                  value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
2725                 Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this
2726                 arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
2727                 with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
2728                 PSU_DDRC_DRAMTMG0_WR2PRE                                                        0x11
2729
2730                 tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
2731                 in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next
2732                 nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks
2733                 PSU_DDRC_DRAMTMG0_T_FAW                                                         0x11
2734
2735                 tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
2736                 imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
2737                  No rounding up. Unit: Multiples of 1024 clocks.
2738                 PSU_DDRC_DRAMTMG0_T_RAS_MAX                                                     0x24
2739
2740                 tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode,
2741                 rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
2742                  (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
2743                 PSU_DDRC_DRAMTMG0_T_RAS_MIN                                                     0x12
2744
2745                 SDRAM Timing Register 0
2746                 (OFFSET, MASK, VALUE)      (0XFD070100, 0x7F3F7F3FU ,0x11112412U)
2747                 RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK |  0 );
2748
2749                 RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT
2750                         | 0x00000011U << DDRC_DRAMTMG0_T_FAW_SHIFT
2751                         | 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
2752                         | 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
2753                         |  0 ) & RegMask); */
2754                 PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x11112412U);
2755         /*############################################################################################################################ */
2756
2757                 /*Register : DRAMTMG1 @ 0XFD070104</p>
2758
2759                 tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
2760                  is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2,
2761                 rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks
2762                 PSU_DDRC_DRAMTMG1_T_XP                                                          0x4
2763
2764                 tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
2765                 R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
2766                 S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
2767                 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
2768                 gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
2769                 e. Unit: Clocks.
2770                 PSU_DDRC_DRAMTMG1_RD2PRE                                                        0x4
2771
2772                 tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
2773                  up to next integer value. Unit: Clocks.
2774                 PSU_DDRC_DRAMTMG1_T_RC                                                          0x1a
2775
2776                 SDRAM Timing Register 1
2777                 (OFFSET, MASK, VALUE)      (0XFD070104, 0x001F1F7FU ,0x0004041AU)
2778                 RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK |  0 );
2779
2780                 RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT
2781                         | 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT
2782                         | 0x0000001AU << DDRC_DRAMTMG1_T_RC_SHIFT
2783                         |  0 ) & RegMask); */
2784                 PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x0004041AU);
2785         /*############################################################################################################################ */
2786
2787                 /*Register : DRAMTMG2 @ 0XFD070108</p>
2788
2789                 Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
2790                 t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
2791                 tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
2792                 equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
2793                  is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
2794                 PSU_DDRC_DRAMTMG2_WRITE_LATENCY                                                 0x7
2795
2796                 Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
2797                 using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For
2798                 onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
2799                 er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
2800                 s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
2801                 PSU_DDRC_DRAMTMG2_READ_LATENCY                                                  0x8
2802
2803                 DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
2804                 PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
2805                 /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
2806                 time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL =
2807                 urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
2808                 tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
2809                 DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
2810                 gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
2811                 PSU_DDRC_DRAMTMG2_RD2WR                                                         0x6
2812
2813                 DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
2814                 k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
2815                  per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
2816                  length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
2817                 d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
2818                  delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
2819                 ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
2820                 PSU_DDRC_DRAMTMG2_WR2RD                                                         0xe
2821
2822                 SDRAM Timing Register 2
2823                 (OFFSET, MASK, VALUE)      (0XFD070108, 0x3F3F3F3FU ,0x0708060EU)
2824                 RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK |  0 );
2825
2826                 RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
2827                         | 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT
2828                         | 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT
2829                         | 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT
2830                         |  0 ) & RegMask); */
2831                 PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU);
2832         /*############################################################################################################################ */
2833
2834                 /*Register : DRAMTMG3 @ 0XFD07010C</p>
2835
2836                 Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
2837                  LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW
2838                 nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
2839                  used for the time from a MRW/MRR to a MRW/MRR.
2840                 PSU_DDRC_DRAMTMG3_T_MRW                                                         0x5
2841
2842                 tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time
2843                 rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
2844                 nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
2845                 4 is used, set to tMRD_PAR(tMOD+PL) instead.
2846                 PSU_DDRC_DRAMTMG3_T_MRD                                                         0x4
2847
2848                 tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
2849                 y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
2850                  if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
2851                  + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.
2852                 PSU_DDRC_DRAMTMG3_T_MOD                                                         0xc
2853
2854                 SDRAM Timing Register 3
2855                 (OFFSET, MASK, VALUE)      (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)
2856                 RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK |  0 );
2857
2858                 RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT
2859                         | 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT
2860                         | 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT
2861                         |  0 ) & RegMask); */
2862                 PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU);
2863         /*############################################################################################################################ */
2864
2865                 /*Register : DRAMTMG4 @ 0XFD070110</p>
2866
2867                 tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
2868                 am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
2869                 lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
2870                 PSU_DDRC_DRAMTMG4_T_RCD                                                         0x8
2871
2872                 DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
2873                 time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
2874                 d it up to the next integer value. Unit: clocks.
2875                 PSU_DDRC_DRAMTMG4_T_CCD                                                         0x3
2876
2877                 DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
2878                  activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
2879                 it up to the next integer value. Unit: Clocks.
2880                 PSU_DDRC_DRAMTMG4_T_RRD                                                         0x3
2881
2882                 tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
2883                 (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
2884                 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
2885                 PSU_DDRC_DRAMTMG4_T_RP                                                          0x9
2886
2887                 SDRAM Timing Register 4
2888                 (OFFSET, MASK, VALUE)      (0XFD070110, 0x1F0F0F1FU ,0x08030309U)
2889                 RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK |  0 );
2890
2891                 RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT
2892                         | 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT
2893                         | 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT
2894                         | 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT
2895                         |  0 ) & RegMask); */
2896                 PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U);
2897         /*############################################################################################################################ */
2898
2899                 /*Register : DRAMTMG5 @ 0XFD070114</p>
2900
2901                 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
2902                 e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
2903                 tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
2904                 eger.
2905                 PSU_DDRC_DRAMTMG5_T_CKSRX                                                       0x6
2906
2907                 This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
2908                  SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4:
2909                 ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
2910                 to next integer.
2911                 PSU_DDRC_DRAMTMG5_T_CKSRE                                                       0x6
2912
2913                 Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
2914                 tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE
2915                  1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
2916                 .
2917                 PSU_DDRC_DRAMTMG5_T_CKESR                                                       0x4
2918
2919                 Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of
2920                 CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set
2921                 his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
2922                  next integer value. Unit: Clocks.
2923                 PSU_DDRC_DRAMTMG5_T_CKE                                                         0x3
2924
2925                 SDRAM Timing Register 5
2926                 (OFFSET, MASK, VALUE)      (0XFD070114, 0x0F0F3F1FU ,0x06060403U)
2927                 RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK |  0 );
2928
2929                 RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT
2930                         | 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT
2931                         | 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT
2932                         | 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT
2933                         |  0 ) & RegMask); */
2934                 PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U);
2935         /*############################################################################################################################ */
2936
2937                 /*Register : DRAMTMG6 @ 0XFD070118</p>
2938
2939                 This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after
2940                 PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
2941                 ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
2942                 devices.
2943                 PSU_DDRC_DRAMTMG6_T_CKDPDE                                                      0x1
2944
2945                 This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock
2946                 table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
2947                 gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
2948                 R or LPDDR2 devices.
2949                 PSU_DDRC_DRAMTMG6_T_CKDPDX                                                      0x1
2950
2951                 This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the
2952                 lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
2953                 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it
2954                 p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2955                 PSU_DDRC_DRAMTMG6_T_CKCSX                                                       0x4
2956
2957                 SDRAM Timing Register 6
2958                 (OFFSET, MASK, VALUE)      (0XFD070118, 0x0F0F000FU ,0x01010004U)
2959                 RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK |  0 );
2960
2961                 RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT
2962                         | 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT
2963                         | 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT
2964                         |  0 ) & RegMask); */
2965                 PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U);
2966         /*############################################################################################################################ */
2967
2968                 /*Register : DRAMTMG7 @ 0XFD07011C</p>
2969
2970                 This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE.
2971                 ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
2972                 is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
2973                 DDR2/LPDDR3/LPDDR4 devices.
2974                 PSU_DDRC_DRAMTMG7_T_CKPDE                                                       0x6
2975
2976                 This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
2977                 time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
2978                 , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
2979                 g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2980                 PSU_DDRC_DRAMTMG7_T_CKPDX                                                       0x6
2981
2982                 SDRAM Timing Register 7
2983                 (OFFSET, MASK, VALUE)      (0XFD07011C, 0x00000F0FU ,0x00000606U)
2984                 RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK |  0 );
2985
2986                 RegVal = ((0x00000006U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
2987                         | 0x00000006U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
2988                         |  0 ) & RegMask); */
2989                 PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000606U);
2990         /*############################################################################################################################ */
2991
2992                 /*Register : DRAMTMG8 @ 0XFD070120</p>
2993
2994                 tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
2995                 O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
2996                  is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.
2997                 PSU_DDRC_DRAMTMG8_T_XS_FAST_X32                                                 0x4
2998
2999                 tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
3000                 ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
3001                 nsure this is less than or equal to t_xs_x32.
3002                 PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32                                                0x4
3003
3004                 tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3005                 bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3006                 DR4 SDRAMs.
3007                 PSU_DDRC_DRAMTMG8_T_XS_DLL_X32                                                  0xd
3008
3009                 tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3010                 above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3011                 DDR4 SDRAMs.
3012                 PSU_DDRC_DRAMTMG8_T_XS_X32                                                      0x6
3013
3014                 SDRAM Timing Register 8
3015                 (OFFSET, MASK, VALUE)      (0XFD070120, 0x7F7F7F7FU ,0x04040D06U)
3016                 RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK |  0 );
3017
3018                 RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
3019                         | 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
3020                         | 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
3021                         | 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT
3022                         |  0 ) & RegMask); */
3023                 PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U);
3024         /*############################################################################################################################ */
3025
3026                 /*Register : DRAMTMG9 @ 0XFD070124</p>
3027
3028                 DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
3029                 PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE                                              0x0
3030
3031                 tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a'
3032                 o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
3033                 nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.
3034                 PSU_DDRC_DRAMTMG9_T_CCD_S                                                       0x2
3035
3036                 tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
3037                 ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
3038                 R4. Unit: Clocks.
3039                 PSU_DDRC_DRAMTMG9_T_RRD_S                                                       0x2
3040
3041                 CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
3042                 round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
3043                  Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
3044                 d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
3045                 is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using
3046                 he above equation by 2, and round it up to next integer.
3047                 PSU_DDRC_DRAMTMG9_WR2RD_S                                                       0xb
3048
3049                 SDRAM Timing Register 9
3050                 (OFFSET, MASK, VALUE)      (0XFD070124, 0x40070F3FU ,0x0002020BU)
3051                 RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK |  0 );
3052
3053                 RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
3054                         | 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT
3055                         | 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT
3056                         | 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT
3057                         |  0 ) & RegMask); */
3058                 PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU);
3059         /*############################################################################################################################ */
3060
3061                 /*Register : DRAMTMG11 @ 0XFD07012C</p>
3062
3063                 tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
3064                 this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
3065                 ples of 32 clocks.
3066                 PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32                                            0x6f
3067
3068                 tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
3069                  RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.
3070                 PSU_DDRC_DRAMTMG11_T_MPX_LH                                                     0x7
3071
3072                 tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
3073                 up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
3074                 PSU_DDRC_DRAMTMG11_T_MPX_S                                                      0x1
3075
3076                 tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
3077                 r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
3078                 teger.
3079                 PSU_DDRC_DRAMTMG11_T_CKMPE                                                      0xe
3080
3081                 SDRAM Timing Register 11
3082                 (OFFSET, MASK, VALUE)      (0XFD07012C, 0x7F1F031FU ,0x6F07010EU)
3083                 RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK |  0 );
3084
3085                 RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
3086                         | 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT
3087                         | 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT
3088                         | 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT
3089                         |  0 ) & RegMask); */
3090                 PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU);
3091         /*############################################################################################################################ */
3092
3093                 /*Register : DRAMTMG12 @ 0XFD070130</p>
3094
3095                 tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
3096                 REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.
3097                 PSU_DDRC_DRAMTMG12_T_CMDCKE                                                     0x2
3098
3099                 tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
3100                 /2) and round it up to next integer value.
3101                 PSU_DDRC_DRAMTMG12_T_CKEHCMD                                                    0x6
3102
3103                 tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
3104                 s to (tMRD_PDA/2) and round it up to next integer value.
3105                 PSU_DDRC_DRAMTMG12_T_MRD_PDA                                                    0x8
3106
3107                 SDRAM Timing Register 12
3108                 (OFFSET, MASK, VALUE)      (0XFD070130, 0x00030F1FU ,0x00020608U)
3109                 RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK |  0 );
3110
3111                 RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT
3112                         | 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
3113                         | 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
3114                         |  0 ) & RegMask); */
3115                 PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U);
3116         /*############################################################################################################################ */
3117
3118                 /*Register : ZQCTL0 @ 0XFD070180</p>
3119
3120                 - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
3121                 ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
3122                 ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3123                 PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ                                                     0x1
3124
3125                 - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
3126                 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
3127                 own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
3128                 ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3129                 PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL                                                    0x0
3130
3131                 - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
3132                 nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
3133                 rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3134                 PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED                                              0x0
3135
3136                 - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable
3137                 ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
3138                 gns supporting DDR4 devices.
3139                 PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL                                                  0x0
3140
3141                 tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
3142                 on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
3143                 er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
3144                 ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for
3145                 esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3146                 PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP                                                   0x100
3147
3148                 tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
3149                 ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
3150                 e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
3151                 s.
3152                 PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP                                                  0x40
3153
3154                 ZQ Control Register 0
3155                 (OFFSET, MASK, VALUE)      (0XFD070180, 0xF7FF03FFU ,0x81000040U)
3156                 RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK |  0 );
3157
3158                 RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
3159                         | 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
3160                         | 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
3161                         | 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
3162                         | 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
3163                         | 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
3164                         |  0 ) & RegMask); */
3165                 PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U);
3166         /*############################################################################################################################ */
3167
3168                 /*Register : ZQCTL1 @ 0XFD070184</p>
3169
3170                 tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
3171                 ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is
3172                 nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
3173                 PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP                                                  0x20
3174
3175                 Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
3176                 PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs
3177                 upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3178                 PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024                                       0x19707
3179
3180                 ZQ Control Register 1
3181                 (OFFSET, MASK, VALUE)      (0XFD070184, 0x3FFFFFFFU ,0x02019707U)
3182                 RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK |  0 );
3183
3184                 RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
3185                         | 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
3186                         |  0 ) & RegMask); */
3187                 PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U);
3188         /*############################################################################################################################ */
3189
3190                 /*Register : DFITMG0 @ 0XFD070190</p>
3191
3192                 Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
3193                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
3194                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
3195                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
3196                 PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY                                               0x4
3197
3198                 Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
3199                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
3200                 fer to PHY specification for correct value.
3201                 PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR                                             0x1
3202
3203                 Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
3204                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
3205                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
3206                  latency through the RDIMM. Unit: Clocks
3207                 PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN                                                0xb
3208
3209                 Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
3210                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
3211                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
3212                 e.
3213                 PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR                                             0x1
3214
3215                 Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
3216                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
3217                 te, max supported value is 8. Unit: Clocks
3218                 PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA                                                0x2
3219
3220                 Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
3221                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
3222                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
3223                 rough the RDIMM.
3224                 PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT                                                 0xb
3225
3226                 DFI Timing Register 0
3227                 (OFFSET, MASK, VALUE)      (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)
3228                 RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK |  0 );
3229
3230                 RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
3231                         | 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
3232                         | 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
3233                         | 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
3234                         | 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
3235                         | 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
3236                         |  0 ) & RegMask); */
3237                 PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU);
3238         /*############################################################################################################################ */
3239
3240                 /*Register : DFITMG1 @ 0XFD070194</p>
3241
3242                 Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven.
3243                 his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
3244                 the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
3245                 PSU_DDRC_DFITMG1_DFI_T_CMD_LAT                                                  0x0
3246
3247                 Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
3248                  is driven.
3249                 PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT                                                0x0
3250
3251                 Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
3252                 nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
3253                  correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to
3254                 phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
3255                 RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
3256                 : Clocks
3257                 PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY                                             0x3
3258
3259                 Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to
3260                 he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase
3261                 ligned, this timing parameter should be rounded up to the next integer value.
3262                 PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE                                         0x3
3263
3264                 Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first
3265                 alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
3266                 not phase aligned, this timing parameter should be rounded up to the next integer value.
3267                 PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE                                          0x4
3268
3269                 DFI Timing Register 1
3270                 (OFFSET, MASK, VALUE)      (0XFD070194, 0xF31F0F0FU ,0x00030304U)
3271                 RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK |  0 );
3272
3273                 RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
3274                         | 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
3275                         | 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
3276                         | 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
3277                         | 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
3278                         |  0 ) & RegMask); */
3279                 PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U);
3280         /*############################################################################################################################ */
3281
3282                 /*Register : DFILPCFG0 @ 0XFD070198</p>
3283
3284                 Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
3285                 g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
3286                 PSU_DDRC_DFILPCFG0_DFI_TLP_RESP                                                 0x7
3287
3288                 Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
3289                 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
3290                 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD -
3291                 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
3292                 .
3293                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD                                            0x0
3294
3295                 Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
3296                 nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.
3297                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD                                                0x0
3298
3299                 Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
3300                 les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 -
3301                 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
3302                 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited
3303                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR                                             0x0
3304
3305                 Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
3306                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR                                                 0x1
3307
3308                 Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
3309                 s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
3310                 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
3311                  cycles - 0xE - 262144 cycles - 0xF - Unlimited
3312                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD                                             0x0
3313
3314                 Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
3315                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD                                                 0x1
3316
3317                 DFI Low Power Configuration Register 0
3318                 (OFFSET, MASK, VALUE)      (0XFD070198, 0x0FF1F1F1U ,0x07000101U)
3319                 RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK |  0 );
3320
3321                 RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
3322                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
3323                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
3324                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
3325                         | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
3326                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
3327                         | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
3328                         |  0 ) & RegMask); */
3329                 PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000101U);
3330         /*############################################################################################################################ */
3331
3332                 /*Register : DFILPCFG1 @ 0XFD07019C</p>
3333
3334                 Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
3335                 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles
3336                  0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
3337                 D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.
3338                 PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM                                           0x2
3339
3340                 Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
3341                 only present for designs supporting DDR4 devices.
3342                 PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM                                               0x1
3343
3344                 DFI Low Power Configuration Register 1
3345                 (OFFSET, MASK, VALUE)      (0XFD07019C, 0x000000F1U ,0x00000021U)
3346                 RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK |  0 );
3347
3348                 RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
3349                         | 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
3350                         |  0 ) & RegMask); */
3351                 PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U);
3352         /*############################################################################################################################ */
3353
3354                 /*Register : DFIUPD1 @ 0XFD0701A4</p>
3355
3356                 This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
3357                 ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
3358                 t read request when the uMCTL2 is idle. Unit: 1024 clocks
3359                 PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024                               0x41
3360
3361                 This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request;
3362                 hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
3363                 idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
3364                 e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
3365                 Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
3366                 024. Unit: 1024 clocks
3367                 PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024                               0xe2
3368
3369                 DFI Update Register 1
3370                 (OFFSET, MASK, VALUE)      (0XFD0701A4, 0x00FF00FFU ,0x004100E2U)
3371                 RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK |  0 );
3372
3373                 RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
3374                         | 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
3375                         |  0 ) & RegMask); */
3376                 PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U);
3377         /*############################################################################################################################ */
3378
3379                 /*Register : DFIMISC @ 0XFD0701B0</p>
3380
3381                 Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high
3382                 PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY                                           0x0
3383
3384                 DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
3385                 in designs configured to support DDR4 and LPDDR4.
3386                 PSU_DDRC_DFIMISC_PHY_DBI_MODE                                                   0x0
3387
3388                 PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
3389                 ion
3390                 PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN                                           0x0
3391
3392                 DFI Miscellaneous Control Register
3393                 (OFFSET, MASK, VALUE)      (0XFD0701B0, 0x00000007U ,0x00000000U)
3394                 RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK |  0 );
3395
3396                 RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
3397                         | 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
3398                         | 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
3399                         |  0 ) & RegMask); */
3400                 PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U);
3401         /*############################################################################################################################ */
3402
3403                 /*Register : DFITMG2 @ 0XFD0701B4</p>
3404
3405                 >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
3406                 l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
3407                 PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT                                               0x9
3408
3409                 Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
3410                 l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
3411                 PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT                                               0x6
3412
3413                 DFI Timing Register 2
3414                 (OFFSET, MASK, VALUE)      (0XFD0701B4, 0x00003F3FU ,0x00000906U)
3415                 RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK |  0 );
3416
3417                 RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
3418                         | 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
3419                         |  0 ) & RegMask); */
3420                 PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U);
3421         /*############################################################################################################################ */
3422
3423                 /*Register : DBICTL @ 0XFD0701C0</p>
3424
3425                 Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
3426                 as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
3427                 PSU_DDRC_DBICTL_RD_DBI_EN                                                       0x0
3428
3429                 Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
3430                 ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
3431                 PSU_DDRC_DBICTL_WR_DBI_EN                                                       0x0
3432
3433                 DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
3434                 mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
3435                 : Set this to inverted value of MR13[5] which is opposite polarity from this signal
3436                 PSU_DDRC_DBICTL_DM_EN                                                           0x1
3437
3438                 DM/DBI Control Register
3439                 (OFFSET, MASK, VALUE)      (0XFD0701C0, 0x00000007U ,0x00000001U)
3440                 RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK |  0 );
3441
3442                 RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT
3443                         | 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT
3444                         | 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT
3445                         |  0 ) & RegMask); */
3446                 PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U);
3447         /*############################################################################################################################ */
3448
3449                 /*Register : ADDRMAP0 @ 0XFD070200</p>
3450
3451                 Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
3452                  bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.
3453                 PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0                                               0x1f
3454
3455                 Address Map Register 0
3456                 (OFFSET, MASK, VALUE)      (0XFD070200, 0x0000001FU ,0x0000001FU)
3457                 RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK |  0 );
3458
3459                 RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
3460                         |  0 ) & RegMask); */
3461                 PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU);
3462         /*############################################################################################################################ */
3463
3464                 /*Register : ADDRMAP1 @ 0XFD070204</p>
3465
3466                 Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
3467                 bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.
3468                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2                                               0x1f
3469
3470                 Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
3471                 r each of the bank address bits is determined by adding the internal base to the value of this field.
3472                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1                                               0xa
3473
3474                 Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
3475                 r each of the bank address bits is determined by adding the internal base to the value of this field.
3476                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0                                               0xa
3477
3478                 Address Map Register 1
3479                 (OFFSET, MASK, VALUE)      (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)
3480                 RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK |  0 );
3481
3482                 RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
3483                         | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
3484                         | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
3485                         |  0 ) & RegMask); */
3486                 PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU);
3487         /*############################################################################################################################ */
3488
3489                 /*Register : ADDRMAP2 @ 0XFD070208</p>
3490
3491                 - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
3492                 s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
3493                  Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
3494                  this field. If set to 15, this column address bit is set to 0.
3495                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5                                                0x0
3496
3497                 - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
3498                 s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
3499                 Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
3500                 this field. If set to 15, this column address bit is set to 0.
3501                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4                                                0x0
3502
3503                 - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
3504                 s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
3505                 Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
3506                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
3507                  this case.
3508                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3                                                0x0
3509
3510                 - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
3511                 s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
3512                 Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
3513                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.
3514                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2                                                0x0
3515
3516                 Address Map Register 2
3517                 (OFFSET, MASK, VALUE)      (0XFD070208, 0x0F0F0F0FU ,0x00000000U)
3518                 RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK |  0 );
3519
3520                 RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
3521                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
3522                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
3523                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
3524                         |  0 ) & RegMask); */
3525                 PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U);
3526         /*############################################################################################################################ */
3527
3528                 /*Register : ADDRMAP3 @ 0XFD07020C</p>
3529
3530                 - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
3531                 s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
3532                 column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
3533                  determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note:
3534                 er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
3535                 ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
3536                  hence column bit 10 is used.
3537                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9                                                0x0
3538
3539                 - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
3540                 s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
3541                  LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
3542                 ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
3543                 cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
3544                 mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
3545                 .
3546                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8                                                0x0
3547
3548                 - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
3549                 s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
3550                 Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
3551                 this field. If set to 15, this column address bit is set to 0.
3552                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7                                                0x0
3553
3554                 - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
3555                 s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
3556                 Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
3557                 this field. If set to 15, this column address bit is set to 0.
3558                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6                                                0x0
3559
3560                 Address Map Register 3
3561                 (OFFSET, MASK, VALUE)      (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)
3562                 RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK |  0 );
3563
3564                 RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
3565                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
3566                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
3567                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
3568                         |  0 ) & RegMask); */
3569                 PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U);
3570         /*############################################################################################################################ */
3571
3572                 /*Register : ADDRMAP4 @ 0XFD070210</p>
3573
3574                 - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
3575                 mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must
3576                 e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
3577                 l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
3578                 n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
3579                 dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
3580                 PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11                                               0xf
3581
3582                 - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
3583                 mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
3584                 To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
3585                 termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
3586                 JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
3587                 bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
3588                 nce column bit 10 is used.
3589                 PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10                                               0xf
3590
3591                 Address Map Register 4
3592                 (OFFSET, MASK, VALUE)      (0XFD070210, 0x00000F0FU ,0x00000F0FU)
3593                 RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK |  0 );
3594
3595                 RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
3596                         | 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
3597                         |  0 ) & RegMask); */
3598                 PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU);
3599         /*############################################################################################################################ */
3600
3601                 /*Register : ADDRMAP5 @ 0XFD070214</p>
3602
3603                 Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
3604                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.
3605                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11                                               0x8
3606
3607                 Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
3608                 bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF
3609                 ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value
3610                 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
3611                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10                                             0xf
3612
3613                 Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
3614                  each of the row address bits is determined by adding the internal base to the value of this field.
3615                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1                                                0x8
3616
3617                 Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
3618                  each of the row address bits is determined by adding the internal base to the value of this field.
3619                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0                                                0x8
3620
3621                 Address Map Register 5
3622                 (OFFSET, MASK, VALUE)      (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)
3623                 RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK |  0 );
3624
3625                 RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
3626                         | 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
3627                         | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
3628                         | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
3629                         |  0 ) & RegMask); */
3630                 PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U);
3631         /*############################################################################################################################ */
3632
3633                 /*Register : ADDRMAP6 @ 0XFD070218</p>
3634
3635                 Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
3636                 having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
3637                 y in designs configured to support LPDDR3.
3638                 PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB                                               0x0
3639
3640                 Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
3641                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
3642                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15                                               0xf
3643
3644                 Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
3645                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.
3646                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14                                               0x8
3647
3648                 Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
3649                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.
3650                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13                                               0x8
3651
3652                 Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
3653                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.
3654                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12                                               0x8
3655
3656                 Address Map Register 6
3657                 (OFFSET, MASK, VALUE)      (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)
3658                 RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK |  0 );
3659
3660                 RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
3661                         | 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
3662                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
3663                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
3664                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
3665                         |  0 ) & RegMask); */
3666                 PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U);
3667         /*############################################################################################################################ */
3668
3669                 /*Register : ADDRMAP7 @ 0XFD07021C</p>
3670
3671                 Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
3672                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.
3673                 PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17                                               0xf
3674
3675                 Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
3676                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.
3677                 PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16                                               0xf
3678
3679                 Address Map Register 7
3680                 (OFFSET, MASK, VALUE)      (0XFD07021C, 0x00000F0FU ,0x00000F0FU)
3681                 RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK |  0 );
3682
3683                 RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
3684                         | 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
3685                         |  0 ) & RegMask); */
3686                 PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU);
3687         /*############################################################################################################################ */
3688
3689                 /*Register : ADDRMAP8 @ 0XFD070220</p>
3690
3691                 Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
3692                 address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If
3693                 et to 31, bank group address bit 1 is set to 0.
3694                 PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1                                                 0x8
3695
3696                 Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
3697                 bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
3698                 PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0                                                 0x8
3699
3700                 Address Map Register 8
3701                 (OFFSET, MASK, VALUE)      (0XFD070220, 0x00001F1FU ,0x00000808U)
3702                 RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK |  0 );
3703
3704                 RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
3705                         | 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
3706                         |  0 ) & RegMask); */
3707                 PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U);
3708         /*############################################################################################################################ */
3709
3710                 /*Register : ADDRMAP9 @ 0XFD070224</p>
3711
3712                 Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
3713                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3714                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3715                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5                                                0x8
3716
3717                 Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
3718                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3719                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3720                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4                                                0x8
3721
3722                 Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
3723                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
3724                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3725                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3                                                0x8
3726
3727                 Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
3728                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
3729                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3730                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2                                                0x8
3731
3732                 Address Map Register 9
3733                 (OFFSET, MASK, VALUE)      (0XFD070224, 0x0F0F0F0FU ,0x08080808U)
3734                 RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK |  0 );
3735
3736                 RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
3737                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
3738                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
3739                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
3740                         |  0 ) & RegMask); */
3741                 PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U);
3742         /*############################################################################################################################ */
3743
3744                 /*Register : ADDRMAP10 @ 0XFD070228</p>
3745
3746                 Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
3747                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3748                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3749                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9                                               0x8
3750
3751                 Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
3752                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3753                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3754                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8                                               0x8
3755
3756                 Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
3757                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3758                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3759                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7                                               0x8
3760
3761                 Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
3762                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3763                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3764                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6                                               0x8
3765
3766                 Address Map Register 10
3767                 (OFFSET, MASK, VALUE)      (0XFD070228, 0x0F0F0F0FU ,0x08080808U)
3768                 RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK |  0 );
3769
3770                 RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
3771                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
3772                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
3773                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
3774                         |  0 ) & RegMask); */
3775                 PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U);
3776         /*############################################################################################################################ */
3777
3778                 /*Register : ADDRMAP11 @ 0XFD07022C</p>
3779
3780                 Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit
3781                 or each of the row address bits is determined by adding the internal base to the value of this field. This register field is
3782                 sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3783                 PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10                                              0x8
3784
3785                 Address Map Register 11
3786                 (OFFSET, MASK, VALUE)      (0XFD07022C, 0x0000000FU ,0x00000008U)
3787                 RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK |  0 );
3788
3789                 RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
3790                         |  0 ) & RegMask); */
3791                 PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U);
3792         /*############################################################################################################################ */
3793
3794                 /*Register : ODTCFG @ 0XFD070240</p>
3795
3796                 Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
3797                 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: -
3798                 L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1
3799                 CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
3800                 PSU_DDRC_ODTCFG_WR_ODT_HOLD                                                     0x6
3801
3802                 The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
3803                 remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
3804                 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
3805                  DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
3806                 PSU_DDRC_ODTCFG_WR_ODT_DELAY                                                    0x0
3807
3808                 Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
3809                  0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
3810                 tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
3811                 )
3812                 PSU_DDRC_ODTCFG_RD_ODT_HOLD                                                     0x6
3813
3814                 The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must
3815                 emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
3816                 CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
3817                 L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
3818                 write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
3819                 uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
3820                 PSU_DDRC_ODTCFG_RD_ODT_DELAY                                                    0x0
3821
3822                 ODT Configuration Register
3823                 (OFFSET, MASK, VALUE)      (0XFD070240, 0x0F1F0F7CU ,0x06000600U)
3824                 RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK |  0 );
3825
3826                 RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
3827                         | 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
3828                         | 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
3829                         | 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
3830                         |  0 ) & RegMask); */
3831                 PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U);
3832         /*############################################################################################################################ */
3833
3834                 /*Register : ODTMAP @ 0XFD070244</p>
3835
3836                 Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can
3837                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
3838                  etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
3839                 PSU_DDRC_ODTMAP_RANK1_RD_ODT                                                    0x0
3840
3841                 Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
3842                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
3843                 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
3844                 PSU_DDRC_ODTMAP_RANK1_WR_ODT                                                    0x0
3845
3846                 Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can
3847                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
3848                  etc. For each rank, set its bit to 1 to enable its ODT.
3849                 PSU_DDRC_ODTMAP_RANK0_RD_ODT                                                    0x0
3850
3851                 Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
3852                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
3853                 etc. For each rank, set its bit to 1 to enable its ODT.
3854                 PSU_DDRC_ODTMAP_RANK0_WR_ODT                                                    0x1
3855
3856                 ODT/Rank Map Register
3857                 (OFFSET, MASK, VALUE)      (0XFD070244, 0x00003333U ,0x00000001U)
3858                 RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK |  0 );
3859
3860                 RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
3861                         | 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
3862                         | 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
3863                         | 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
3864                         |  0 ) & RegMask); */
3865                 PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U);
3866         /*############################################################################################################################ */
3867
3868                 /*Register : SCHED @ 0XFD070250</p>
3869
3870                 When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
3871                 non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
3872                 ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this
3873                 egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
3874                 OR PERFORMANCE ONLY
3875                 PSU_DDRC_SCHED_RDWR_IDLE_GAP                                                    0x1
3876
3877                 UNUSED
3878                 PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS                                           0x0
3879
3880                 Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
3881                  the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
3882                 to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
3883                 priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
3884                  than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
3885                 sing out of single bit error correction RMW operation.
3886                 PSU_DDRC_SCHED_LPR_NUM_ENTRIES                                                  0x20
3887
3888                 If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
3889                 e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this
3890                 egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
3891                 es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed
3892                 s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
3893                 ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open
3894                 age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
3895                 ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.
3896                 PSU_DDRC_SCHED_PAGECLOSE                                                        0x0
3897
3898                 If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
3899                 PSU_DDRC_SCHED_PREFER_WRITE                                                     0x0
3900
3901                 Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
3902                 ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
3903                 e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
3904                 ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.
3905                 PSU_DDRC_SCHED_FORCE_LOW_PRI_N                                                  0x1
3906
3907                 Scheduler Control Register
3908                 (OFFSET, MASK, VALUE)      (0XFD070250, 0x7FFF3F07U ,0x01002001U)
3909                 RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK |  0 );
3910
3911                 RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
3912                         | 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
3913                         | 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
3914                         | 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT
3915                         | 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT
3916                         | 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
3917                         |  0 ) & RegMask); */
3918                 PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U);
3919         /*############################################################################################################################ */
3920
3921                 /*Register : PERFLPR1 @ 0XFD070264</p>
3922
3923                 Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
3924                  transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
3925                 PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH                                           0x8
3926
3927                 Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
3928                 er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
3929                 be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
3930                 PSU_DDRC_PERFLPR1_LPR_MAX_STARVE                                                0x40
3931
3932                 Low Priority Read CAM Register 1
3933                 (OFFSET, MASK, VALUE)      (0XFD070264, 0xFF00FFFFU ,0x08000040U)
3934                 RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK |  0 );
3935
3936                 RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
3937                         | 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
3938                         |  0 ) & RegMask); */
3939                 PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
3940         /*############################################################################################################################ */
3941
3942                 /*Register : PERFWR1 @ 0XFD07026C</p>
3943
3944                 Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
3945                 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
3946                 PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH                                              0x8
3947
3948                 Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
3949                 r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
3950                 e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
3951                 PSU_DDRC_PERFWR1_W_MAX_STARVE                                                   0x40
3952
3953                 Write CAM Register 1
3954                 (OFFSET, MASK, VALUE)      (0XFD07026C, 0xFF00FFFFU ,0x08000040U)
3955                 RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK |  0 );
3956
3957                 RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
3958                         | 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT
3959                         |  0 ) & RegMask); */
3960                 PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
3961         /*############################################################################################################################ */
3962
3963                 /*Register : DQMAP5 @ 0XFD070294</p>
3964
3965                 All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
3966                 all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and
3967                 wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
3968                 port DDR4.
3969                 PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP                                                0x1
3970
3971                 DQ Map Register 5
3972                 (OFFSET, MASK, VALUE)      (0XFD070294, 0x00000001U ,0x00000001U)
3973                 RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK |  0 );
3974
3975                 RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
3976                         |  0 ) & RegMask); */
3977                 PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U);
3978         /*############################################################################################################################ */
3979
3980                 /*Register : DBG0 @ 0XFD070300</p>
3981
3982                 When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
3983                 lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
3984                 s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.
3985                 PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT                                            0x0
3986
3987                 When 1, disable write combine. FOR DEBUG ONLY
3988                 PSU_DDRC_DBG0_DIS_WC                                                            0x0
3989
3990                 Debug Register 0
3991                 (OFFSET, MASK, VALUE)      (0XFD070300, 0x00000011U ,0x00000000U)
3992                 RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK |  0 );
3993
3994                 RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
3995                         | 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT
3996                         |  0 ) & RegMask); */
3997                 PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U);
3998         /*############################################################################################################################ */
3999
4000                 /*Register : DBGCMD @ 0XFD07030C</p>
4001
4002                 Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
4003                 the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
4004                 register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
4005                 _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
4006                  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).
4007                 PSU_DDRC_DBGCMD_HW_REF_ZQ_EN                                                    0x0
4008
4009                 Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in
4010                 he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
4011                 PSU_DDRC_DBGCMD_CTRLUPD                                                         0x0
4012
4013                 Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to
4014                 he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
4015                 en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
4016                 d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
4017                 de.
4018                 PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT                                                  0x0
4019
4020                 Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
4021                 refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4022                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4023                 wn operating modes or Maximum Power Saving Mode.
4024                 PSU_DDRC_DBGCMD_RANK1_REFRESH                                                   0x0
4025
4026                 Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
4027                 refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4028                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4029                 wn operating modes or Maximum Power Saving Mode.
4030                 PSU_DDRC_DBGCMD_RANK0_REFRESH                                                   0x0
4031
4032                 Command Debug Register
4033                 (OFFSET, MASK, VALUE)      (0XFD07030C, 0x80000033U ,0x00000000U)
4034                 RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK |  0 );
4035
4036                 RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
4037                         | 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT
4038                         | 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
4039                         | 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT
4040                         | 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT
4041                         |  0 ) & RegMask); */
4042                 PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U);
4043         /*############################################################################################################################ */
4044
4045                 /*Register : SWCTL @ 0XFD070320</p>
4046
4047                 Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back
4048                 egister to 1 once programming is done.
4049                 PSU_DDRC_SWCTL_SW_DONE                                                          0x0
4050
4051                 Software register programming control enable
4052                 (OFFSET, MASK, VALUE)      (0XFD070320, 0x00000001U ,0x00000000U)
4053                 RegMask = (DDRC_SWCTL_SW_DONE_MASK |  0 );
4054
4055                 RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT
4056                         |  0 ) & RegMask); */
4057                 PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U);
4058         /*############################################################################################################################ */
4059
4060                 /*Register : PCCFG @ 0XFD070400</p>
4061
4062                 Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
4063                 e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
4064                 h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
4065                 ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
4066                 _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
4067                 ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
4068                 DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
4069                 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
4070                 -AC is enabled
4071                 PSU_DDRC_PCCFG_BL_EXP_MODE                                                      0x0
4072
4073                 Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
4074                 rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
4075                 ge DDRC transactions.
4076                 PSU_DDRC_PCCFG_PAGEMATCH_LIMIT                                                  0x0
4077
4078                 If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based
4079                 n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
4080                 _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
4081                 PSU_DDRC_PCCFG_GO2CRITICAL_EN                                                   0x1
4082
4083                 Port Common Configuration Register
4084                 (OFFSET, MASK, VALUE)      (0XFD070400, 0x00000111U ,0x00000001U)
4085                 RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK |  0 );
4086
4087                 RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT
4088                         | 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
4089                         | 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
4090                         |  0 ) & RegMask); */
4091                 PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U);
4092         /*############################################################################################################################ */
4093
4094                 /*Register : PCFGR_0 @ 0XFD070404</p>
4095
4096                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4097                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4098                 imit register.
4099                 PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN                                           0x0
4100
4101                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4102                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4103                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4104                 ess handshaking (it is not associated with any particular command).
4105                 PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN                                              0x1
4106
4107                 If set to 1, enables aging function for the read channel of the port.
4108                 PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN                                               0x0
4109
4110                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4111                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4112                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4113                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4114                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4115                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4116                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4117                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4118                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4119                 he two LSBs of this register field are tied internally to 2'b00.
4120                 PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY                                               0xf
4121
4122                 Port n Configuration Read Register
4123                 (OFFSET, MASK, VALUE)      (0XFD070404, 0x000073FFU ,0x0000200FU)
4124                 RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK |  0 );
4125
4126                 RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
4127                         | 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
4128                         | 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
4129                         | 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
4130                         |  0 ) & RegMask); */
4131                 PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU);
4132         /*############################################################################################################################ */
4133
4134                 /*Register : PCFGW_0 @ 0XFD070408</p>
4135
4136                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4137                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4138                 imit register.
4139                 PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN                                           0x1
4140
4141                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4142                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4143                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4144                 not associated with any particular command).
4145                 PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN                                              0x1
4146
4147                 If set to 1, enables aging function for the write channel of the port.
4148                 PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN                                               0x0
4149
4150                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4151                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4152                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4153                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4154                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4155                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4156                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4157                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4158                 PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY                                               0xf
4159
4160                 Port n Configuration Write Register
4161                 (OFFSET, MASK, VALUE)      (0XFD070408, 0x000073FFU ,0x0000600FU)
4162                 RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK |  0 );
4163
4164                 RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
4165                         | 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
4166                         | 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
4167                         | 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
4168                         |  0 ) & RegMask); */
4169                 PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU);
4170         /*############################################################################################################################ */
4171
4172                 /*Register : PCTRL_0 @ 0XFD070490</p>
4173
4174                 Enables port n.
4175                 PSU_DDRC_PCTRL_0_PORT_EN                                                        0x1
4176
4177                 Port n Control Register
4178                 (OFFSET, MASK, VALUE)      (0XFD070490, 0x00000001U ,0x00000001U)
4179                 RegMask = (DDRC_PCTRL_0_PORT_EN_MASK |  0 );
4180
4181                 RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT
4182                         |  0 ) & RegMask); */
4183                 PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U);
4184         /*############################################################################################################################ */
4185
4186                 /*Register : PCFGQOS0_0 @ 0XFD070494</p>
4187
4188                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4189                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4190                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4191                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1                                            0x2
4192
4193                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4194                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4195                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4196                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0                                            0x0
4197
4198                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4199                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4200                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4201                  values.
4202                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1                                             0xb
4203
4204                 Port n Read QoS Configuration Register 0
4205                 (OFFSET, MASK, VALUE)      (0XFD070494, 0x0033000FU ,0x0020000BU)
4206                 RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK |  0 );
4207
4208                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
4209                         | 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
4210                         | 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
4211                         |  0 ) & RegMask); */
4212                 PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU);
4213         /*############################################################################################################################ */
4214
4215                 /*Register : PCFGQOS1_0 @ 0XFD070498</p>
4216
4217                 Specifies the timeout value for transactions mapped to the red address queue.
4218                 PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR                                           0x0
4219
4220                 Specifies the timeout value for transactions mapped to the blue address queue.
4221                 PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB                                           0x0
4222
4223                 Port n Read QoS Configuration Register 1
4224                 (OFFSET, MASK, VALUE)      (0XFD070498, 0x07FF07FFU ,0x00000000U)
4225                 RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK |  0 );
4226
4227                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
4228                         | 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
4229                         |  0 ) & RegMask); */
4230                 PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U);
4231         /*############################################################################################################################ */
4232
4233                 /*Register : PCFGR_1 @ 0XFD0704B4</p>
4234
4235                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4236                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4237                 imit register.
4238                 PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN                                           0x0
4239
4240                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4241                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4242                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4243                 ess handshaking (it is not associated with any particular command).
4244                 PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN                                              0x1
4245
4246                 If set to 1, enables aging function for the read channel of the port.
4247                 PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN                                               0x0
4248
4249                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4250                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4251                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4252                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4253                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4254                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4255                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4256                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4257                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4258                 he two LSBs of this register field are tied internally to 2'b00.
4259                 PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY                                               0xf
4260
4261                 Port n Configuration Read Register
4262                 (OFFSET, MASK, VALUE)      (0XFD0704B4, 0x000073FFU ,0x0000200FU)
4263                 RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK |  0 );
4264
4265                 RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
4266                         | 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
4267                         | 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
4268                         | 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
4269                         |  0 ) & RegMask); */
4270                 PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU);
4271         /*############################################################################################################################ */
4272
4273                 /*Register : PCFGW_1 @ 0XFD0704B8</p>
4274
4275                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4276                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4277                 imit register.
4278                 PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN                                           0x1
4279
4280                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4281                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4282                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4283                 not associated with any particular command).
4284                 PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN                                              0x1
4285
4286                 If set to 1, enables aging function for the write channel of the port.
4287                 PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN                                               0x0
4288
4289                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4290                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4291                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4292                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4293                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4294                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4295                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4296                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4297                 PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY                                               0xf
4298
4299                 Port n Configuration Write Register
4300                 (OFFSET, MASK, VALUE)      (0XFD0704B8, 0x000073FFU ,0x0000600FU)
4301                 RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK |  0 );
4302
4303                 RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
4304                         | 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
4305                         | 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
4306                         | 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
4307                         |  0 ) & RegMask); */
4308                 PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU);
4309         /*############################################################################################################################ */
4310
4311                 /*Register : PCTRL_1 @ 0XFD070540</p>
4312
4313                 Enables port n.
4314                 PSU_DDRC_PCTRL_1_PORT_EN                                                        0x1
4315
4316                 Port n Control Register
4317                 (OFFSET, MASK, VALUE)      (0XFD070540, 0x00000001U ,0x00000001U)
4318                 RegMask = (DDRC_PCTRL_1_PORT_EN_MASK |  0 );
4319
4320                 RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT
4321                         |  0 ) & RegMask); */
4322                 PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U);
4323         /*############################################################################################################################ */
4324
4325                 /*Register : PCFGQOS0_1 @ 0XFD070544</p>
4326
4327                 This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
4328                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
4329                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4330                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2                                            0x2
4331
4332                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4333                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4334                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4335                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1                                            0x0
4336
4337                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4338                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4339                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4340                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0                                            0x0
4341
4342                 Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
4343                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
4344                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
4345                 ust be set to distinct values.
4346                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2                                             0xb
4347
4348                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4349                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4350                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4351                  values.
4352                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1                                             0x3
4353
4354                 Port n Read QoS Configuration Register 0
4355                 (OFFSET, MASK, VALUE)      (0XFD070544, 0x03330F0FU ,0x02000B03U)
4356                 RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK |  0 );
4357
4358                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
4359                         | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
4360                         | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
4361                         | 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
4362                         | 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
4363                         |  0 ) & RegMask); */
4364                 PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U);
4365         /*############################################################################################################################ */
4366
4367                 /*Register : PCFGQOS1_1 @ 0XFD070548</p>
4368
4369                 Specifies the timeout value for transactions mapped to the red address queue.
4370                 PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR                                           0x0
4371
4372                 Specifies the timeout value for transactions mapped to the blue address queue.
4373                 PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB                                           0x0
4374
4375                 Port n Read QoS Configuration Register 1
4376                 (OFFSET, MASK, VALUE)      (0XFD070548, 0x07FF07FFU ,0x00000000U)
4377                 RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK |  0 );
4378
4379                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
4380                         | 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
4381                         |  0 ) & RegMask); */
4382                 PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U);
4383         /*############################################################################################################################ */
4384
4385                 /*Register : PCFGR_2 @ 0XFD070564</p>
4386
4387                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4388                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4389                 imit register.
4390                 PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN                                           0x0
4391
4392                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4393                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4394                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4395                 ess handshaking (it is not associated with any particular command).
4396                 PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN                                              0x1
4397
4398                 If set to 1, enables aging function for the read channel of the port.
4399                 PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN                                               0x0
4400
4401                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4402                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4403                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4404                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4405                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4406                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4407                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4408                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4409                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4410                 he two LSBs of this register field are tied internally to 2'b00.
4411                 PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY                                               0xf
4412
4413                 Port n Configuration Read Register
4414                 (OFFSET, MASK, VALUE)      (0XFD070564, 0x000073FFU ,0x0000200FU)
4415                 RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK |  0 );
4416
4417                 RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
4418                         | 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
4419                         | 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
4420                         | 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
4421                         |  0 ) & RegMask); */
4422                 PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU);
4423         /*############################################################################################################################ */
4424
4425                 /*Register : PCFGW_2 @ 0XFD070568</p>
4426
4427                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4428                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4429                 imit register.
4430                 PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN                                           0x1
4431
4432                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4433                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4434                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4435                 not associated with any particular command).
4436                 PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN                                              0x1
4437
4438                 If set to 1, enables aging function for the write channel of the port.
4439                 PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN                                               0x0
4440
4441                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4442                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4443                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4444                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4445                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4446                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4447                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4448                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4449                 PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY                                               0xf
4450
4451                 Port n Configuration Write Register
4452                 (OFFSET, MASK, VALUE)      (0XFD070568, 0x000073FFU ,0x0000600FU)
4453                 RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK |  0 );
4454
4455                 RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
4456                         | 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
4457                         | 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
4458                         | 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
4459                         |  0 ) & RegMask); */
4460                 PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU);
4461         /*############################################################################################################################ */
4462
4463                 /*Register : PCTRL_2 @ 0XFD0705F0</p>
4464
4465                 Enables port n.
4466                 PSU_DDRC_PCTRL_2_PORT_EN                                                        0x1
4467
4468                 Port n Control Register
4469                 (OFFSET, MASK, VALUE)      (0XFD0705F0, 0x00000001U ,0x00000001U)
4470                 RegMask = (DDRC_PCTRL_2_PORT_EN_MASK |  0 );
4471
4472                 RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT
4473                         |  0 ) & RegMask); */
4474                 PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U);
4475         /*############################################################################################################################ */
4476
4477                 /*Register : PCFGQOS0_2 @ 0XFD0705F4</p>
4478
4479                 This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
4480                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
4481                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4482                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2                                            0x2
4483
4484                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4485                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4486                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4487                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1                                            0x0
4488
4489                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4490                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4491                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4492                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0                                            0x0
4493
4494                 Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
4495                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
4496                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
4497                 ust be set to distinct values.
4498                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2                                             0xb
4499
4500                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4501                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4502                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4503                  values.
4504                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1                                             0x3
4505
4506                 Port n Read QoS Configuration Register 0
4507                 (OFFSET, MASK, VALUE)      (0XFD0705F4, 0x03330F0FU ,0x02000B03U)
4508                 RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK |  0 );
4509
4510                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
4511                         | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
4512                         | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
4513                         | 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
4514                         | 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
4515                         |  0 ) & RegMask); */
4516                 PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U);
4517         /*############################################################################################################################ */
4518
4519                 /*Register : PCFGQOS1_2 @ 0XFD0705F8</p>
4520
4521                 Specifies the timeout value for transactions mapped to the red address queue.
4522                 PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR                                           0x0
4523
4524                 Specifies the timeout value for transactions mapped to the blue address queue.
4525                 PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB                                           0x0
4526
4527                 Port n Read QoS Configuration Register 1
4528                 (OFFSET, MASK, VALUE)      (0XFD0705F8, 0x07FF07FFU ,0x00000000U)
4529                 RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK |  0 );
4530
4531                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
4532                         | 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
4533                         |  0 ) & RegMask); */
4534                 PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U);
4535         /*############################################################################################################################ */
4536
4537                 /*Register : PCFGR_3 @ 0XFD070614</p>
4538
4539                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4540                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4541                 imit register.
4542                 PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN                                           0x0
4543
4544                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4545                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4546                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4547                 ess handshaking (it is not associated with any particular command).
4548                 PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN                                              0x1
4549
4550                 If set to 1, enables aging function for the read channel of the port.
4551                 PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN                                               0x0
4552
4553                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4554                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4555                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4556                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4557                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4558                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4559                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4560                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4561                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4562                 he two LSBs of this register field are tied internally to 2'b00.
4563                 PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY                                               0xf
4564
4565                 Port n Configuration Read Register
4566                 (OFFSET, MASK, VALUE)      (0XFD070614, 0x000073FFU ,0x0000200FU)
4567                 RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK |  0 );
4568
4569                 RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
4570                         | 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
4571                         | 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
4572                         | 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
4573                         |  0 ) & RegMask); */
4574                 PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU);
4575         /*############################################################################################################################ */
4576
4577                 /*Register : PCFGW_3 @ 0XFD070618</p>
4578
4579                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4580                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4581                 imit register.
4582                 PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN                                           0x1
4583
4584                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4585                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4586                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4587                 not associated with any particular command).
4588                 PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN                                              0x1
4589
4590                 If set to 1, enables aging function for the write channel of the port.
4591                 PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN                                               0x0
4592
4593                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4594                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4595                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4596                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4597                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4598                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4599                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4600                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4601                 PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY                                               0xf
4602
4603                 Port n Configuration Write Register
4604                 (OFFSET, MASK, VALUE)      (0XFD070618, 0x000073FFU ,0x0000600FU)
4605                 RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK |  0 );
4606
4607                 RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
4608                         | 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
4609                         | 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
4610                         | 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
4611                         |  0 ) & RegMask); */
4612                 PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU);
4613         /*############################################################################################################################ */
4614
4615                 /*Register : PCTRL_3 @ 0XFD0706A0</p>
4616
4617                 Enables port n.
4618                 PSU_DDRC_PCTRL_3_PORT_EN                                                        0x1
4619
4620                 Port n Control Register
4621                 (OFFSET, MASK, VALUE)      (0XFD0706A0, 0x00000001U ,0x00000001U)
4622                 RegMask = (DDRC_PCTRL_3_PORT_EN_MASK |  0 );
4623
4624                 RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT
4625                         |  0 ) & RegMask); */
4626                 PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U);
4627         /*############################################################################################################################ */
4628
4629                 /*Register : PCFGQOS0_3 @ 0XFD0706A4</p>
4630
4631                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4632                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4633                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4634                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1                                            0x1
4635
4636                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4637                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4638                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4639                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0                                            0x0
4640
4641                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4642                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4643                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4644                  values.
4645                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1                                             0x3
4646
4647                 Port n Read QoS Configuration Register 0
4648                 (OFFSET, MASK, VALUE)      (0XFD0706A4, 0x0033000FU ,0x00100003U)
4649                 RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK |  0 );
4650
4651                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
4652                         | 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
4653                         | 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
4654                         |  0 ) & RegMask); */
4655                 PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
4656         /*############################################################################################################################ */
4657
4658                 /*Register : PCFGQOS1_3 @ 0XFD0706A8</p>
4659
4660                 Specifies the timeout value for transactions mapped to the red address queue.
4661                 PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR                                           0x0
4662
4663                 Specifies the timeout value for transactions mapped to the blue address queue.
4664                 PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB                                           0x4f
4665
4666                 Port n Read QoS Configuration Register 1
4667                 (OFFSET, MASK, VALUE)      (0XFD0706A8, 0x07FF07FFU ,0x0000004FU)
4668                 RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK |  0 );
4669
4670                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
4671                         | 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
4672                         |  0 ) & RegMask); */
4673                 PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU);
4674         /*############################################################################################################################ */
4675
4676                 /*Register : PCFGWQOS0_3 @ 0XFD0706AC</p>
4677
4678                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
4679                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
4680                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1                                           0x1
4681
4682                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
4683                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
4684                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0                                           0x0
4685
4686                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
4687                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
4688                 s to higher port priority.
4689                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL                                             0x3
4690
4691                 Port n Write QoS Configuration Register 0
4692                 (OFFSET, MASK, VALUE)      (0XFD0706AC, 0x0033000FU ,0x00100003U)
4693                 RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK |  0 );
4694
4695                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
4696                         | 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
4697                         | 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
4698                         |  0 ) & RegMask); */
4699                 PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
4700         /*############################################################################################################################ */
4701
4702                 /*Register : PCFGWQOS1_3 @ 0XFD0706B0</p>
4703
4704                 Specifies the timeout value for write transactions.
4705                 PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT                                           0x4f
4706
4707                 Port n Write QoS Configuration Register 1
4708                 (OFFSET, MASK, VALUE)      (0XFD0706B0, 0x000007FFU ,0x0000004FU)
4709                 RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK |  0 );
4710
4711                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
4712                         |  0 ) & RegMask); */
4713                 PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU);
4714         /*############################################################################################################################ */
4715
4716                 /*Register : PCFGR_4 @ 0XFD0706C4</p>
4717
4718                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4719                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4720                 imit register.
4721                 PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN                                           0x1
4722
4723                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4724                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4725                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4726                 ess handshaking (it is not associated with any particular command).
4727                 PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN                                              0x1
4728
4729                 If set to 1, enables aging function for the read channel of the port.
4730                 PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN                                               0x0
4731
4732                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4733                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4734                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4735                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4736                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4737                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4738                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4739                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4740                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4741                 he two LSBs of this register field are tied internally to 2'b00.
4742                 PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY                                               0xf
4743
4744                 Port n Configuration Read Register
4745                 (OFFSET, MASK, VALUE)      (0XFD0706C4, 0x000073FFU ,0x0000600FU)
4746                 RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK |  0 );
4747
4748                 RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
4749                         | 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
4750                         | 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
4751                         | 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
4752                         |  0 ) & RegMask); */
4753                 PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU);
4754         /*############################################################################################################################ */
4755
4756                 /*Register : PCFGW_4 @ 0XFD0706C8</p>
4757
4758                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4759                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4760                 imit register.
4761                 PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN                                           0x1
4762
4763                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4764                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4765                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4766                 not associated with any particular command).
4767                 PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN                                              0x1
4768
4769                 If set to 1, enables aging function for the write channel of the port.
4770                 PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN                                               0x0
4771
4772                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4773                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4774                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4775                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4776                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4777                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4778                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4779                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4780                 PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY                                               0xf
4781
4782                 Port n Configuration Write Register
4783                 (OFFSET, MASK, VALUE)      (0XFD0706C8, 0x000073FFU ,0x0000600FU)
4784                 RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK |  0 );
4785
4786                 RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
4787                         | 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
4788                         | 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
4789                         | 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
4790                         |  0 ) & RegMask); */
4791                 PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU);
4792         /*############################################################################################################################ */
4793
4794                 /*Register : PCTRL_4 @ 0XFD070750</p>
4795
4796                 Enables port n.
4797                 PSU_DDRC_PCTRL_4_PORT_EN                                                        0x1
4798
4799                 Port n Control Register
4800                 (OFFSET, MASK, VALUE)      (0XFD070750, 0x00000001U ,0x00000001U)
4801                 RegMask = (DDRC_PCTRL_4_PORT_EN_MASK |  0 );
4802
4803                 RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT
4804                         |  0 ) & RegMask); */
4805                 PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U);
4806         /*############################################################################################################################ */
4807
4808                 /*Register : PCFGQOS0_4 @ 0XFD070754</p>
4809
4810                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4811                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4812                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4813                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1                                            0x1
4814
4815                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4816                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4817                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4818                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0                                            0x0
4819
4820                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4821                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4822                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4823                  values.
4824                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1                                             0x3
4825
4826                 Port n Read QoS Configuration Register 0
4827                 (OFFSET, MASK, VALUE)      (0XFD070754, 0x0033000FU ,0x00100003U)
4828                 RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK |  0 );
4829
4830                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
4831                         | 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
4832                         | 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
4833                         |  0 ) & RegMask); */
4834                 PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
4835         /*############################################################################################################################ */
4836
4837                 /*Register : PCFGQOS1_4 @ 0XFD070758</p>
4838
4839                 Specifies the timeout value for transactions mapped to the red address queue.
4840                 PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR                                           0x0
4841
4842                 Specifies the timeout value for transactions mapped to the blue address queue.
4843                 PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB                                           0x4f
4844
4845                 Port n Read QoS Configuration Register 1
4846                 (OFFSET, MASK, VALUE)      (0XFD070758, 0x07FF07FFU ,0x0000004FU)
4847                 RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK |  0 );
4848
4849                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
4850                         | 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
4851                         |  0 ) & RegMask); */
4852                 PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU);
4853         /*############################################################################################################################ */
4854
4855                 /*Register : PCFGWQOS0_4 @ 0XFD07075C</p>
4856
4857                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
4858                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
4859                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1                                           0x1
4860
4861                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
4862                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
4863                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0                                           0x0
4864
4865                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
4866                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
4867                 s to higher port priority.
4868                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL                                             0x3
4869
4870                 Port n Write QoS Configuration Register 0
4871                 (OFFSET, MASK, VALUE)      (0XFD07075C, 0x0033000FU ,0x00100003U)
4872                 RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK |  0 );
4873
4874                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
4875                         | 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
4876                         | 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
4877                         |  0 ) & RegMask); */
4878                 PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
4879         /*############################################################################################################################ */
4880
4881                 /*Register : PCFGWQOS1_4 @ 0XFD070760</p>
4882
4883                 Specifies the timeout value for write transactions.
4884                 PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT                                           0x4f
4885
4886                 Port n Write QoS Configuration Register 1
4887                 (OFFSET, MASK, VALUE)      (0XFD070760, 0x000007FFU ,0x0000004FU)
4888                 RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK |  0 );
4889
4890                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
4891                         |  0 ) & RegMask); */
4892                 PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU);
4893         /*############################################################################################################################ */
4894
4895                 /*Register : PCFGR_5 @ 0XFD070774</p>
4896
4897                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4898                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4899                 imit register.
4900                 PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN                                           0x0
4901
4902                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4903                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4904                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4905                 ess handshaking (it is not associated with any particular command).
4906                 PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN                                              0x1
4907
4908                 If set to 1, enables aging function for the read channel of the port.
4909                 PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN                                               0x0
4910
4911                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4912                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4913                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4914                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4915                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4916                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4917                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4918                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4919                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4920                 he two LSBs of this register field are tied internally to 2'b00.
4921                 PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY                                               0xf
4922
4923                 Port n Configuration Read Register
4924                 (OFFSET, MASK, VALUE)      (0XFD070774, 0x000073FFU ,0x0000200FU)
4925                 RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK |  0 );
4926
4927                 RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
4928                         | 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
4929                         | 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
4930                         | 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
4931                         |  0 ) & RegMask); */
4932                 PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU);
4933         /*############################################################################################################################ */
4934
4935                 /*Register : PCFGW_5 @ 0XFD070778</p>
4936
4937                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4938                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4939                 imit register.
4940                 PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN                                           0x1
4941
4942                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4943                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4944                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4945                 not associated with any particular command).
4946                 PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN                                              0x1
4947
4948                 If set to 1, enables aging function for the write channel of the port.
4949                 PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN                                               0x0
4950
4951                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4952                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4953                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4954                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4955                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4956                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4957                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4958                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4959                 PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY                                               0xf
4960
4961                 Port n Configuration Write Register
4962                 (OFFSET, MASK, VALUE)      (0XFD070778, 0x000073FFU ,0x0000600FU)
4963                 RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK |  0 );
4964
4965                 RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
4966                         | 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
4967                         | 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
4968                         | 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
4969                         |  0 ) & RegMask); */
4970                 PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU);
4971         /*############################################################################################################################ */
4972
4973                 /*Register : PCTRL_5 @ 0XFD070800</p>
4974
4975                 Enables port n.
4976                 PSU_DDRC_PCTRL_5_PORT_EN                                                        0x1
4977
4978                 Port n Control Register
4979                 (OFFSET, MASK, VALUE)      (0XFD070800, 0x00000001U ,0x00000001U)
4980                 RegMask = (DDRC_PCTRL_5_PORT_EN_MASK |  0 );
4981
4982                 RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT
4983                         |  0 ) & RegMask); */
4984                 PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U);
4985         /*############################################################################################################################ */
4986
4987                 /*Register : PCFGQOS0_5 @ 0XFD070804</p>
4988
4989                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4990                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4991                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4992                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1                                            0x1
4993
4994                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4995                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4996                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4997                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0                                            0x0
4998
4999                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5000                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5001                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5002                  values.
5003                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1                                             0x3
5004
5005                 Port n Read QoS Configuration Register 0
5006                 (OFFSET, MASK, VALUE)      (0XFD070804, 0x0033000FU ,0x00100003U)
5007                 RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK |  0 );
5008
5009                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
5010                         | 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
5011                         | 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
5012                         |  0 ) & RegMask); */
5013                 PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
5014         /*############################################################################################################################ */
5015
5016                 /*Register : PCFGQOS1_5 @ 0XFD070808</p>
5017
5018                 Specifies the timeout value for transactions mapped to the red address queue.
5019                 PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR                                           0x0
5020
5021                 Specifies the timeout value for transactions mapped to the blue address queue.
5022                 PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB                                           0x4f
5023
5024                 Port n Read QoS Configuration Register 1
5025                 (OFFSET, MASK, VALUE)      (0XFD070808, 0x07FF07FFU ,0x0000004FU)
5026                 RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK |  0 );
5027
5028                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
5029                         | 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
5030                         |  0 ) & RegMask); */
5031                 PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU);
5032         /*############################################################################################################################ */
5033
5034                 /*Register : PCFGWQOS0_5 @ 0XFD07080C</p>
5035
5036                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5037                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
5038                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1                                           0x1
5039
5040                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5041                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
5042                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0                                           0x0
5043
5044                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5045                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5046                 s to higher port priority.
5047                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL                                             0x3
5048
5049                 Port n Write QoS Configuration Register 0
5050                 (OFFSET, MASK, VALUE)      (0XFD07080C, 0x0033000FU ,0x00100003U)
5051                 RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK |  0 );
5052
5053                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
5054                         | 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
5055                         | 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
5056                         |  0 ) & RegMask); */
5057                 PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
5058         /*############################################################################################################################ */
5059
5060                 /*Register : PCFGWQOS1_5 @ 0XFD070810</p>
5061
5062                 Specifies the timeout value for write transactions.
5063                 PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT                                           0x4f
5064
5065                 Port n Write QoS Configuration Register 1
5066                 (OFFSET, MASK, VALUE)      (0XFD070810, 0x000007FFU ,0x0000004FU)
5067                 RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK |  0 );
5068
5069                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
5070                         |  0 ) & RegMask); */
5071                 PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU);
5072         /*############################################################################################################################ */
5073
5074                 /*Register : SARBASE0 @ 0XFD070F04</p>
5075
5076                 Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
5077                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5078                 PSU_DDRC_SARBASE0_BASE_ADDR                                                     0x0
5079
5080                 SAR Base Address Register n
5081                 (OFFSET, MASK, VALUE)      (0XFD070F04, 0x000001FFU ,0x00000000U)
5082                 RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK |  0 );
5083
5084                 RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT
5085                         |  0 ) & RegMask); */
5086                 PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U);
5087         /*############################################################################################################################ */
5088
5089                 /*Register : SARSIZE0 @ 0XFD070F08</p>
5090
5091                 Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
5092                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
5093                 or example, if register is programmed to 0, region will have 1 block.
5094                 PSU_DDRC_SARSIZE0_NBLOCKS                                                       0x0
5095
5096                 SAR Size Register n
5097                 (OFFSET, MASK, VALUE)      (0XFD070F08, 0x000000FFU ,0x00000000U)
5098                 RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK |  0 );
5099
5100                 RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT
5101                         |  0 ) & RegMask); */
5102                 PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U);
5103         /*############################################################################################################################ */
5104
5105                 /*Register : SARBASE1 @ 0XFD070F0C</p>
5106
5107                 Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
5108                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5109                 PSU_DDRC_SARBASE1_BASE_ADDR                                                     0x10
5110
5111                 SAR Base Address Register n
5112                 (OFFSET, MASK, VALUE)      (0XFD070F0C, 0x000001FFU ,0x00000010U)
5113                 RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK |  0 );
5114
5115                 RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT
5116                         |  0 ) & RegMask); */
5117                 PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U);
5118         /*############################################################################################################################ */
5119
5120                 /*Register : SARSIZE1 @ 0XFD070F10</p>
5121
5122                 Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
5123                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
5124                 or example, if register is programmed to 0, region will have 1 block.
5125                 PSU_DDRC_SARSIZE1_NBLOCKS                                                       0xf
5126
5127                 SAR Size Register n
5128                 (OFFSET, MASK, VALUE)      (0XFD070F10, 0x000000FFU ,0x0000000FU)
5129                 RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK |  0 );
5130
5131                 RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT
5132                         |  0 ) & RegMask); */
5133                 PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU);
5134         /*############################################################################################################################ */
5135
5136                 /*Register : DFITMG0_SHADOW @ 0XFD072190</p>
5137
5138                 Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
5139                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
5140                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
5141                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
5142                 PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY                                        0x7
5143
5144                 Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
5145                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
5146                 fer to PHY specification for correct value.
5147                 PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR                                      0x1
5148
5149                 Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
5150                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
5151                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
5152                  latency through the RDIMM. Unit: Clocks
5153                 PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN                                         0x2
5154
5155                 Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
5156                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
5157                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
5158                 e.
5159                 PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR                                      0x1
5160
5161                 Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
5162                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
5163                 te, max supported value is 8. Unit: Clocks
5164                 PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA                                         0x0
5165
5166                 Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
5167                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
5168                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
5169                 rough the RDIMM.
5170                 PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT                                          0x2
5171
5172                 DFI Timing Shadow Register 0
5173                 (OFFSET, MASK, VALUE)      (0XFD072190, 0x1FBFBF3FU ,0x07828002U)
5174                 RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK |  0 );
5175
5176                 RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
5177                         | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
5178                         | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
5179                         | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
5180                         | 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
5181                         | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
5182                         |  0 ) & RegMask); */
5183                 PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U);
5184         /*############################################################################################################################ */
5185
5186                 // : DDR CONTROLLER RESET
5187                 /*Register : RST_DDR_SS @ 0XFD1A0108</p>
5188
5189                 DDR block level reset inside of the DDR Sub System
5190                 PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X0
5191
5192                 DDR sub system block level reset
5193                 (OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000000U)
5194                 RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
5195
5196                 RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
5197                         |  0 ) & RegMask); */
5198                 PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U);
5199         /*############################################################################################################################ */
5200
5201                 // : DDR PHY
5202                 /*Register : PGCR0 @ 0XFD080010</p>
5203
5204                 Address Copy
5205                 PSU_DDR_PHY_PGCR0_ADCP                                                          0x0
5206
5207                 Reserved. Returns zeroes on reads.
5208                 PSU_DDR_PHY_PGCR0_RESERVED_30_27                                                0x0
5209
5210                 PHY FIFO Reset
5211                 PSU_DDR_PHY_PGCR0_PHYFRST                                                       0x1
5212
5213                 Oscillator Mode Address/Command Delay Line Select
5214                 PSU_DDR_PHY_PGCR0_OSCACDL                                                       0x3
5215
5216                 Reserved. Returns zeroes on reads.
5217                 PSU_DDR_PHY_PGCR0_RESERVED_23_19                                                0x0
5218
5219                 Digital Test Output Select
5220                 PSU_DDR_PHY_PGCR0_DTOSEL                                                        0x0
5221
5222                 Reserved. Returns zeroes on reads.
5223                 PSU_DDR_PHY_PGCR0_RESERVED_13                                                   0x0
5224
5225                 Oscillator Mode Division
5226                 PSU_DDR_PHY_PGCR0_OSCDIV                                                        0xf
5227
5228                 Oscillator Enable
5229                 PSU_DDR_PHY_PGCR0_OSCEN                                                         0x0
5230
5231                 Reserved. Returns zeroes on reads.
5232                 PSU_DDR_PHY_PGCR0_RESERVED_7_0                                                  0x0
5233
5234                 PHY General Configuration Register 0
5235                 (OFFSET, MASK, VALUE)      (0XFD080010, 0xFFFFFFFFU ,0x07001E00U)
5236                 RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK |  0 );
5237
5238                 RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT
5239                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
5240                         | 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT
5241                         | 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT
5242                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
5243                         | 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT
5244                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT
5245                         | 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT
5246                         | 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT
5247                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
5248                         |  0 ) & RegMask); */
5249                 PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U);
5250         /*############################################################################################################################ */
5251
5252                 /*Register : PGCR2 @ 0XFD080018</p>
5253
5254                 Clear Training Status Registers
5255                 PSU_DDR_PHY_PGCR2_CLRTSTAT                                                      0x0
5256
5257                 Clear Impedance Calibration
5258                 PSU_DDR_PHY_PGCR2_CLRZCAL                                                       0x0
5259
5260                 Clear Parity Error
5261                 PSU_DDR_PHY_PGCR2_CLRPERR                                                       0x0
5262
5263                 Initialization Complete Pin Configuration
5264                 PSU_DDR_PHY_PGCR2_ICPC                                                          0x0
5265
5266                 Data Training PUB Mode Exit Timer
5267                 PSU_DDR_PHY_PGCR2_DTPMXTMR                                                      0xf
5268
5269                 Initialization Bypass
5270                 PSU_DDR_PHY_PGCR2_INITFSMBYP                                                    0x0
5271
5272                 PLL FSM Bypass
5273                 PSU_DDR_PHY_PGCR2_PLLFSMBYP                                                     0x0
5274
5275                 Refresh Period
5276                 PSU_DDR_PHY_PGCR2_TREFPRD                                                       0x10028
5277
5278                 PHY General Configuration Register 2
5279                 (OFFSET, MASK, VALUE)      (0XFD080018, 0xFFFFFFFFU ,0x00F10028U)
5280                 RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK |  0 );
5281
5282                 RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT
5283                         | 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT
5284                         | 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT
5285                         | 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT
5286                         | 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT
5287                         | 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT
5288                         | 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
5289                         | 0x00010028U << DDR_PHY_PGCR2_TREFPRD_SHIFT
5290                         |  0 ) & RegMask); */
5291                 PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F10028U);
5292         /*############################################################################################################################ */
5293
5294                 /*Register : PGCR3 @ 0XFD08001C</p>
5295
5296                 CKN Enable
5297                 PSU_DDR_PHY_PGCR3_CKNEN                                                         0x55
5298
5299                 CK Enable
5300                 PSU_DDR_PHY_PGCR3_CKEN                                                          0xaa
5301
5302                 Reserved. Return zeroes on reads.
5303                 PSU_DDR_PHY_PGCR3_RESERVED_15                                                   0x0
5304
5305                 Enable Clock Gating for AC [0] ctl_rd_clk
5306                 PSU_DDR_PHY_PGCR3_GATEACRDCLK                                                   0x2
5307
5308                 Enable Clock Gating for AC [0] ddr_clk
5309                 PSU_DDR_PHY_PGCR3_GATEACDDRCLK                                                  0x2
5310
5311                 Enable Clock Gating for AC [0] ctl_clk
5312                 PSU_DDR_PHY_PGCR3_GATEACCTLCLK                                                  0x2
5313
5314                 Reserved. Return zeroes on reads.
5315                 PSU_DDR_PHY_PGCR3_RESERVED_8                                                    0x0
5316
5317                 Controls DDL Bypass Modes
5318                 PSU_DDR_PHY_PGCR3_DDLBYPMODE                                                    0x2
5319
5320                 IO Loop-Back Select
5321                 PSU_DDR_PHY_PGCR3_IOLB                                                          0x0
5322
5323                 AC Receive FIFO Read Mode
5324                 PSU_DDR_PHY_PGCR3_RDMODE                                                        0x0
5325
5326                 Read FIFO Reset Disable
5327                 PSU_DDR_PHY_PGCR3_DISRST                                                        0x0
5328
5329                 Clock Level when Clock Gating
5330                 PSU_DDR_PHY_PGCR3_CLKLEVEL                                                      0x0
5331
5332                 PHY General Configuration Register 3
5333                 (OFFSET, MASK, VALUE)      (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U)
5334                 RegMask = (DDR_PHY_PGCR3_CKNEN_MASK | DDR_PHY_PGCR3_CKEN_MASK | DDR_PHY_PGCR3_RESERVED_15_MASK | DDR_PHY_PGCR3_GATEACRDCLK_MASK | DDR_PHY_PGCR3_GATEACDDRCLK_MASK | DDR_PHY_PGCR3_GATEACCTLCLK_MASK | DDR_PHY_PGCR3_RESERVED_8_MASK | DDR_PHY_PGCR3_DDLBYPMODE_MASK | DDR_PHY_PGCR3_IOLB_MASK | DDR_PHY_PGCR3_RDMODE_MASK | DDR_PHY_PGCR3_DISRST_MASK | DDR_PHY_PGCR3_CLKLEVEL_MASK |  0 );
5335
5336                 RegVal = ((0x00000055U << DDR_PHY_PGCR3_CKNEN_SHIFT
5337                         | 0x000000AAU << DDR_PHY_PGCR3_CKEN_SHIFT
5338                         | 0x00000000U << DDR_PHY_PGCR3_RESERVED_15_SHIFT
5339                         | 0x00000002U << DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
5340                         | 0x00000002U << DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
5341                         | 0x00000002U << DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
5342                         | 0x00000000U << DDR_PHY_PGCR3_RESERVED_8_SHIFT
5343                         | 0x00000002U << DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
5344                         | 0x00000000U << DDR_PHY_PGCR3_IOLB_SHIFT
5345                         | 0x00000000U << DDR_PHY_PGCR3_RDMODE_SHIFT
5346                         | 0x00000000U << DDR_PHY_PGCR3_DISRST_SHIFT
5347                         | 0x00000000U << DDR_PHY_PGCR3_CLKLEVEL_SHIFT
5348                         |  0 ) & RegMask); */
5349                 PSU_Mask_Write (DDR_PHY_PGCR3_OFFSET ,0xFFFFFFFFU ,0x55AA5480U);
5350         /*############################################################################################################################ */
5351
5352                 /*Register : PGCR5 @ 0XFD080024</p>
5353
5354                 Frequency B Ratio Term
5355                 PSU_DDR_PHY_PGCR5_FRQBT                                                         0x1
5356
5357                 Frequency A Ratio Term
5358                 PSU_DDR_PHY_PGCR5_FRQAT                                                         0x1
5359
5360                 DFI Disconnect Time Period
5361                 PSU_DDR_PHY_PGCR5_DISCNPERIOD                                                   0x0
5362
5363                 Receiver bias core side control
5364                 PSU_DDR_PHY_PGCR5_VREF_RBCTRL                                                   0xf
5365
5366                 Reserved. Return zeroes on reads.
5367                 PSU_DDR_PHY_PGCR5_RESERVED_3                                                    0x0
5368
5369                 Internal VREF generator REFSEL ragne select
5370                 PSU_DDR_PHY_PGCR5_DXREFISELRANGE                                                0x1
5371
5372                 DDL Page Read Write select
5373                 PSU_DDR_PHY_PGCR5_DDLPGACT                                                      0x0
5374
5375                 DDL Page Read Write select
5376                 PSU_DDR_PHY_PGCR5_DDLPGRW                                                       0x0
5377
5378                 PHY General Configuration Register 5
5379                 (OFFSET, MASK, VALUE)      (0XFD080024, 0xFFFFFFFFU ,0x010100F4U)
5380                 RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK |  0 );
5381
5382                 RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT
5383                         | 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT
5384                         | 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
5385                         | 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
5386                         | 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT
5387                         | 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
5388                         | 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT
5389                         | 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT
5390                         |  0 ) & RegMask); */
5391                 PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U);
5392         /*############################################################################################################################ */
5393
5394                 /*Register : PTR0 @ 0XFD080040</p>
5395
5396                 PLL Power-Down Time
5397                 PSU_DDR_PHY_PTR0_TPLLPD                                                         0x2f0
5398
5399                 PLL Gear Shift Time
5400                 PSU_DDR_PHY_PTR0_TPLLGS                                                         0x60
5401
5402                 PHY Reset Time
5403                 PSU_DDR_PHY_PTR0_TPHYRST                                                        0x10
5404
5405                 PHY Timing Register 0
5406                 (OFFSET, MASK, VALUE)      (0XFD080040, 0xFFFFFFFFU ,0x5E001810U)
5407                 RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK |  0 );
5408
5409                 RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT
5410                         | 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT
5411                         | 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT
5412                         |  0 ) & RegMask); */
5413                 PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U);
5414         /*############################################################################################################################ */
5415
5416                 /*Register : PTR1 @ 0XFD080044</p>
5417
5418                 PLL Lock Time
5419                 PSU_DDR_PHY_PTR1_TPLLLOCK                                                       0x80
5420
5421                 Reserved. Returns zeroes on reads.
5422                 PSU_DDR_PHY_PTR1_RESERVED_15_13                                                 0x0
5423
5424                 PLL Reset Time
5425                 PSU_DDR_PHY_PTR1_TPLLRST                                                        0x5f0
5426
5427                 PHY Timing Register 1
5428                 (OFFSET, MASK, VALUE)      (0XFD080044, 0xFFFFFFFFU ,0x008005F0U)
5429                 RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK |  0 );
5430
5431                 RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT
5432                         | 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT
5433                         | 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT
5434                         |  0 ) & RegMask); */
5435                 PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U);
5436         /*############################################################################################################################ */
5437
5438                 /*Register : DSGCR @ 0XFD080090</p>
5439
5440                 Reserved. Return zeroes on reads.
5441                 PSU_DDR_PHY_DSGCR_RESERVED_31_28                                                0x0
5442
5443                 When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
5444                 fault calculation.
5445                 PSU_DDR_PHY_DSGCR_RDBICLSEL                                                     0x0
5446
5447                 When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
5448                 PSU_DDR_PHY_DSGCR_RDBICL                                                        0x2
5449
5450                 PHY Impedance Update Enable
5451                 PSU_DDR_PHY_DSGCR_PHYZUEN                                                       0x1
5452
5453                 Reserved. Return zeroes on reads.
5454                 PSU_DDR_PHY_DSGCR_RESERVED_22                                                   0x0
5455
5456                 SDRAM Reset Output Enable
5457                 PSU_DDR_PHY_DSGCR_RSTOE                                                         0x1
5458
5459                 Single Data Rate Mode
5460                 PSU_DDR_PHY_DSGCR_SDRMODE                                                       0x0
5461
5462                 Reserved. Return zeroes on reads.
5463                 PSU_DDR_PHY_DSGCR_RESERVED_18                                                   0x0
5464
5465                 ATO Analog Test Enable
5466                 PSU_DDR_PHY_DSGCR_ATOAE                                                         0x0
5467
5468                 DTO Output Enable
5469                 PSU_DDR_PHY_DSGCR_DTOOE                                                         0x0
5470
5471                 DTO I/O Mode
5472                 PSU_DDR_PHY_DSGCR_DTOIOM                                                        0x0
5473
5474                 DTO Power Down Receiver
5475                 PSU_DDR_PHY_DSGCR_DTOPDR                                                        0x1
5476
5477                 Reserved. Return zeroes on reads
5478                 PSU_DDR_PHY_DSGCR_RESERVED_13                                                   0x0
5479
5480                 DTO On-Die Termination
5481                 PSU_DDR_PHY_DSGCR_DTOODT                                                        0x0
5482
5483                 PHY Update Acknowledge Delay
5484                 PSU_DDR_PHY_DSGCR_PUAD                                                          0x4
5485
5486                 Controller Update Acknowledge Enable
5487                 PSU_DDR_PHY_DSGCR_CUAEN                                                         0x1
5488
5489                 Reserved. Return zeroes on reads
5490                 PSU_DDR_PHY_DSGCR_RESERVED_4_3                                                  0x0
5491
5492                 Controller Impedance Update Enable
5493                 PSU_DDR_PHY_DSGCR_CTLZUEN                                                       0x0
5494
5495                 Reserved. Return zeroes on reads
5496                 PSU_DDR_PHY_DSGCR_RESERVED_1                                                    0x0
5497
5498                 PHY Update Request Enable
5499                 PSU_DDR_PHY_DSGCR_PUREN                                                         0x1
5500
5501                 DDR System General Configuration Register
5502                 (OFFSET, MASK, VALUE)      (0XFD080090, 0xFFFFFFFFU ,0x02A04121U)
5503                 RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK |  0 );
5504
5505                 RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
5506                         | 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT
5507                         | 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT
5508                         | 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT
5509                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT
5510                         | 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT
5511                         | 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT
5512                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT
5513                         | 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT
5514                         | 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT
5515                         | 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT
5516                         | 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT
5517                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT
5518                         | 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT
5519                         | 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT
5520                         | 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT
5521                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
5522                         | 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT
5523                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT
5524                         | 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT
5525                         |  0 ) & RegMask); */
5526                 PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U);
5527         /*############################################################################################################################ */
5528
5529                 /*Register : DCR @ 0XFD080100</p>
5530
5531                 DDR4 Gear Down Timing.
5532                 PSU_DDR_PHY_DCR_GEARDN                                                          0x0
5533
5534                 Un-used Bank Group
5535                 PSU_DDR_PHY_DCR_UBG                                                             0x0
5536
5537                 Un-buffered DIMM Address Mirroring
5538                 PSU_DDR_PHY_DCR_UDIMM                                                           0x0
5539
5540                 DDR 2T Timing
5541                 PSU_DDR_PHY_DCR_DDR2T                                                           0x0
5542
5543                 No Simultaneous Rank Access
5544                 PSU_DDR_PHY_DCR_NOSRA                                                           0x1
5545
5546                 Reserved. Return zeroes on reads.
5547                 PSU_DDR_PHY_DCR_RESERVED_26_18                                                  0x0
5548
5549                 Byte Mask
5550                 PSU_DDR_PHY_DCR_BYTEMASK                                                        0x1
5551
5552                 DDR Type
5553                 PSU_DDR_PHY_DCR_DDRTYPE                                                         0x0
5554
5555                 Multi-Purpose Register (MPR) DQ (DDR3 Only)
5556                 PSU_DDR_PHY_DCR_MPRDQ                                                           0x0
5557
5558                 Primary DQ (DDR3 Only)
5559                 PSU_DDR_PHY_DCR_PDQ                                                             0x0
5560
5561                 DDR 8-Bank
5562                 PSU_DDR_PHY_DCR_DDR8BNK                                                         0x1
5563
5564                 DDR Mode
5565                 PSU_DDR_PHY_DCR_DDRMD                                                           0x4
5566
5567                 DRAM Configuration Register
5568                 (OFFSET, MASK, VALUE)      (0XFD080100, 0xFFFFFFFFU ,0x0800040CU)
5569                 RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK |  0 );
5570
5571                 RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT
5572                         | 0x00000000U << DDR_PHY_DCR_UBG_SHIFT
5573                         | 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT
5574                         | 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT
5575                         | 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT
5576                         | 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT
5577                         | 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT
5578                         | 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT
5579                         | 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT
5580                         | 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT
5581                         | 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT
5582                         | 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT
5583                         |  0 ) & RegMask); */
5584                 PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU);
5585         /*############################################################################################################################ */
5586
5587                 /*Register : DTPR0 @ 0XFD080110</p>
5588
5589                 Reserved. Return zeroes on reads.
5590                 PSU_DDR_PHY_DTPR0_RESERVED_31_29                                                0x0
5591
5592                 Activate to activate command delay (different banks)
5593                 PSU_DDR_PHY_DTPR0_TRRD                                                          0x6
5594
5595                 Reserved. Return zeroes on reads.
5596                 PSU_DDR_PHY_DTPR0_RESERVED_23                                                   0x0
5597
5598                 Activate to precharge command delay
5599                 PSU_DDR_PHY_DTPR0_TRAS                                                          0x24
5600
5601                 Reserved. Return zeroes on reads.
5602                 PSU_DDR_PHY_DTPR0_RESERVED_15                                                   0x0
5603
5604                 Precharge command period
5605                 PSU_DDR_PHY_DTPR0_TRP                                                           0xf
5606
5607                 Reserved. Return zeroes on reads.
5608                 PSU_DDR_PHY_DTPR0_RESERVED_7_5                                                  0x0
5609
5610                 Internal read to precharge command delay
5611                 PSU_DDR_PHY_DTPR0_TRTP                                                          0x9
5612
5613                 DRAM Timing Parameters Register 0
5614                 (OFFSET, MASK, VALUE)      (0XFD080110, 0xFFFFFFFFU ,0x06240F09U)
5615                 RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK |  0 );
5616
5617                 RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
5618                         | 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT
5619                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT
5620                         | 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT
5621                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT
5622                         | 0x0000000FU << DDR_PHY_DTPR0_TRP_SHIFT
5623                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
5624                         | 0x00000009U << DDR_PHY_DTPR0_TRTP_SHIFT
5625                         |  0 ) & RegMask); */
5626                 PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06240F09U);
5627         /*############################################################################################################################ */
5628
5629                 /*Register : DTPR1 @ 0XFD080114</p>
5630
5631                 Reserved. Return zeroes on reads.
5632                 PSU_DDR_PHY_DTPR1_RESERVED_31                                                   0x0
5633
5634                 Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
5635                 PSU_DDR_PHY_DTPR1_TWLMRD                                                        0x28
5636
5637                 Reserved. Return zeroes on reads.
5638                 PSU_DDR_PHY_DTPR1_RESERVED_23                                                   0x0
5639
5640                 4-bank activate period
5641                 PSU_DDR_PHY_DTPR1_TFAW                                                          0x22
5642
5643                 Reserved. Return zeroes on reads.
5644                 PSU_DDR_PHY_DTPR1_RESERVED_15_11                                                0x0
5645
5646                 Load mode update delay (DDR4 and DDR3 only)
5647                 PSU_DDR_PHY_DTPR1_TMOD                                                          0x7
5648
5649                 Reserved. Return zeroes on reads.
5650                 PSU_DDR_PHY_DTPR1_RESERVED_7_5                                                  0x0
5651
5652                 Load mode cycle time
5653                 PSU_DDR_PHY_DTPR1_TMRD                                                          0x8
5654
5655                 DRAM Timing Parameters Register 1
5656                 (OFFSET, MASK, VALUE)      (0XFD080114, 0xFFFFFFFFU ,0x28220708U)
5657                 RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK |  0 );
5658
5659                 RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT
5660                         | 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT
5661                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT
5662                         | 0x00000022U << DDR_PHY_DTPR1_TFAW_SHIFT
5663                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
5664                         | 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT
5665                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
5666                         | 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT
5667                         |  0 ) & RegMask); */
5668                 PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28220708U);
5669         /*############################################################################################################################ */
5670
5671                 /*Register : DTPR2 @ 0XFD080118</p>
5672
5673                 Reserved. Return zeroes on reads.
5674                 PSU_DDR_PHY_DTPR2_RESERVED_31_29                                                0x0
5675
5676                 Read to Write command delay. Valid values are
5677                 PSU_DDR_PHY_DTPR2_TRTW                                                          0x0
5678
5679                 Reserved. Return zeroes on reads.
5680                 PSU_DDR_PHY_DTPR2_RESERVED_27_25                                                0x0
5681
5682                 Read to ODT delay (DDR3 only)
5683                 PSU_DDR_PHY_DTPR2_TRTODT                                                        0x0
5684
5685                 Reserved. Return zeroes on reads.
5686                 PSU_DDR_PHY_DTPR2_RESERVED_23_20                                                0x0
5687
5688                 CKE minimum pulse width
5689                 PSU_DDR_PHY_DTPR2_TCKE                                                          0x8
5690
5691                 Reserved. Return zeroes on reads.
5692                 PSU_DDR_PHY_DTPR2_RESERVED_15_10                                                0x0
5693
5694                 Self refresh exit delay
5695                 PSU_DDR_PHY_DTPR2_TXS                                                           0x200
5696
5697                 DRAM Timing Parameters Register 2
5698                 (OFFSET, MASK, VALUE)      (0XFD080118, 0xFFFFFFFFU ,0x00080200U)
5699                 RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK |  0 );
5700
5701                 RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
5702                         | 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT
5703                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
5704                         | 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT
5705                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
5706                         | 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT
5707                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
5708                         | 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT
5709                         |  0 ) & RegMask); */
5710                 PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U);
5711         /*############################################################################################################################ */
5712
5713                 /*Register : DTPR3 @ 0XFD08011C</p>
5714
5715                 ODT turn-off delay extension
5716                 PSU_DDR_PHY_DTPR3_TOFDX                                                         0x4
5717
5718                 Read to read and write to write command delay
5719                 PSU_DDR_PHY_DTPR3_TCCD                                                          0x0
5720
5721                 DLL locking time
5722                 PSU_DDR_PHY_DTPR3_TDLLK                                                         0x300
5723
5724                 Reserved. Return zeroes on reads.
5725                 PSU_DDR_PHY_DTPR3_RESERVED_15_12                                                0x0
5726
5727                 Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
5728                 PSU_DDR_PHY_DTPR3_TDQSCKMAX                                                     0x8
5729
5730                 Reserved. Return zeroes on reads.
5731                 PSU_DDR_PHY_DTPR3_RESERVED_7_3                                                  0x0
5732
5733                 DQS output access time from CK/CK# (LPDDR2/3 only)
5734                 PSU_DDR_PHY_DTPR3_TDQSCK                                                        0x0
5735
5736                 DRAM Timing Parameters Register 3
5737                 (OFFSET, MASK, VALUE)      (0XFD08011C, 0xFFFFFFFFU ,0x83000800U)
5738                 RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK |  0 );
5739
5740                 RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT
5741                         | 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT
5742                         | 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT
5743                         | 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
5744                         | 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
5745                         | 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
5746                         | 0x00000000U << DDR_PHY_DTPR3_TDQSCK_SHIFT
5747                         |  0 ) & RegMask); */
5748                 PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000800U);
5749         /*############################################################################################################################ */
5750
5751                 /*Register : DTPR4 @ 0XFD080120</p>
5752
5753                 Reserved. Return zeroes on reads.
5754                 PSU_DDR_PHY_DTPR4_RESERVED_31_30                                                0x0
5755
5756                 ODT turn-on/turn-off delays (DDR2 only)
5757                 PSU_DDR_PHY_DTPR4_TAOND_TAOFD                                                   0x0
5758
5759                 Reserved. Return zeroes on reads.
5760                 PSU_DDR_PHY_DTPR4_RESERVED_27_26                                                0x0
5761
5762                 Refresh-to-Refresh
5763                 PSU_DDR_PHY_DTPR4_TRFC                                                          0x116
5764
5765                 Reserved. Return zeroes on reads.
5766                 PSU_DDR_PHY_DTPR4_RESERVED_15_14                                                0x0
5767
5768                 Write leveling output delay
5769                 PSU_DDR_PHY_DTPR4_TWLO                                                          0x2b
5770
5771                 Reserved. Return zeroes on reads.
5772                 PSU_DDR_PHY_DTPR4_RESERVED_7_5                                                  0x0
5773
5774                 Power down exit delay
5775                 PSU_DDR_PHY_DTPR4_TXP                                                           0x8
5776
5777                 DRAM Timing Parameters Register 4
5778                 (OFFSET, MASK, VALUE)      (0XFD080120, 0xFFFFFFFFU ,0x01162B08U)
5779                 RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK |  0 );
5780
5781                 RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
5782                         | 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
5783                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
5784                         | 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT
5785                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
5786                         | 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT
5787                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
5788                         | 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT
5789                         |  0 ) & RegMask); */
5790                 PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U);
5791         /*############################################################################################################################ */
5792
5793                 /*Register : DTPR5 @ 0XFD080124</p>
5794
5795                 Reserved. Return zeroes on reads.
5796                 PSU_DDR_PHY_DTPR5_RESERVED_31_24                                                0x0
5797
5798                 Activate to activate command delay (same bank)
5799                 PSU_DDR_PHY_DTPR5_TRC                                                           0x34
5800
5801                 Reserved. Return zeroes on reads.
5802                 PSU_DDR_PHY_DTPR5_RESERVED_15                                                   0x0
5803
5804                 Activate to read or write delay
5805                 PSU_DDR_PHY_DTPR5_TRCD                                                          0xf
5806
5807                 Reserved. Return zeroes on reads.
5808                 PSU_DDR_PHY_DTPR5_RESERVED_7_5                                                  0x0
5809
5810                 Internal write to read command delay
5811                 PSU_DDR_PHY_DTPR5_TWTR                                                          0x9
5812
5813                 DRAM Timing Parameters Register 5
5814                 (OFFSET, MASK, VALUE)      (0XFD080124, 0xFFFFFFFFU ,0x00340F09U)
5815                 RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK |  0 );
5816
5817                 RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
5818                         | 0x00000034U << DDR_PHY_DTPR5_TRC_SHIFT
5819                         | 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT
5820                         | 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT
5821                         | 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
5822                         | 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT
5823                         |  0 ) & RegMask); */
5824                 PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00340F09U);
5825         /*############################################################################################################################ */
5826
5827                 /*Register : DTPR6 @ 0XFD080128</p>
5828
5829                 PUB Write Latency Enable
5830                 PSU_DDR_PHY_DTPR6_PUBWLEN                                                       0x0
5831
5832                 PUB Read Latency Enable
5833                 PSU_DDR_PHY_DTPR6_PUBRLEN                                                       0x0
5834
5835                 Reserved. Return zeroes on reads.
5836                 PSU_DDR_PHY_DTPR6_RESERVED_29_14                                                0x0
5837
5838                 Write Latency
5839                 PSU_DDR_PHY_DTPR6_PUBWL                                                         0xe
5840
5841                 Reserved. Return zeroes on reads.
5842                 PSU_DDR_PHY_DTPR6_RESERVED_7_6                                                  0x0
5843
5844                 Read Latency
5845                 PSU_DDR_PHY_DTPR6_PUBRL                                                         0xf
5846
5847                 DRAM Timing Parameters Register 6
5848                 (OFFSET, MASK, VALUE)      (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU)
5849                 RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK |  0 );
5850
5851                 RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT
5852                         | 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT
5853                         | 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
5854                         | 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT
5855                         | 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
5856                         | 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT
5857                         |  0 ) & RegMask); */
5858                 PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU);
5859         /*############################################################################################################################ */
5860
5861                 /*Register : RDIMMGCR0 @ 0XFD080140</p>
5862
5863                 Reserved. Return zeroes on reads.
5864                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_31                                               0x0
5865
5866                 RDMIMM Quad CS Enable
5867                 PSU_DDR_PHY_RDIMMGCR0_QCSEN                                                     0x0
5868
5869                 Reserved. Return zeroes on reads.
5870                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28                                            0x0
5871
5872                 RDIMM Outputs I/O Mode
5873                 PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM                                                  0x1
5874
5875                 Reserved. Return zeroes on reads.
5876                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24                                            0x0
5877
5878                 ERROUT# Output Enable
5879                 PSU_DDR_PHY_RDIMMGCR0_ERROUTOE                                                  0x0
5880
5881                 ERROUT# I/O Mode
5882                 PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM                                                 0x1
5883
5884                 ERROUT# Power Down Receiver
5885                 PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR                                                 0x0
5886
5887                 Reserved. Return zeroes on reads.
5888                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_20                                               0x0
5889
5890                 ERROUT# On-Die Termination
5891                 PSU_DDR_PHY_RDIMMGCR0_ERROUTODT                                                 0x0
5892
5893                 Load Reduced DIMM
5894                 PSU_DDR_PHY_RDIMMGCR0_LRDIMM                                                    0x0
5895
5896                 PAR_IN I/O Mode
5897                 PSU_DDR_PHY_RDIMMGCR0_PARINIOM                                                  0x0
5898
5899                 Reserved. Return zeroes on reads.
5900                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8                                             0x0
5901
5902                 Reserved. Return zeroes on reads.
5903                 PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD                                             0x0
5904
5905                 Rank Mirror Enable.
5906                 PSU_DDR_PHY_RDIMMGCR0_RNKMRREN                                                  0x2
5907
5908                 Reserved. Return zeroes on reads.
5909                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_3                                                0x0
5910
5911                 Stop on Parity Error
5912                 PSU_DDR_PHY_RDIMMGCR0_SOPERR                                                    0x0
5913
5914                 Parity Error No Registering
5915                 PSU_DDR_PHY_RDIMMGCR0_ERRNOREG                                                  0x0
5916
5917                 Registered DIMM
5918                 PSU_DDR_PHY_RDIMMGCR0_RDIMM                                                     0x0
5919
5920                 RDIMM General Configuration Register 0
5921                 (OFFSET, MASK, VALUE)      (0XFD080140, 0xFFFFFFFFU ,0x08400020U)
5922                 RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK |  0 );
5923
5924                 RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
5925                         | 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
5926                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
5927                         | 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
5928                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
5929                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
5930                         | 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
5931                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
5932                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
5933                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
5934                         | 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
5935                         | 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
5936                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
5937                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
5938                         | 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
5939                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
5940                         | 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
5941                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
5942                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
5943                         |  0 ) & RegMask); */
5944                 PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U);
5945         /*############################################################################################################################ */
5946
5947                 /*Register : RDIMMGCR1 @ 0XFD080144</p>
5948
5949                 Reserved. Return zeroes on reads.
5950                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29                                            0x0
5951
5952                 Address [17] B-side Inversion Disable
5953                 PSU_DDR_PHY_RDIMMGCR1_A17BID                                                    0x0
5954
5955                 Reserved. Return zeroes on reads.
5956                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_27                                               0x0
5957
5958                 Command word to command word programming delay
5959                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2                                                 0x0
5960
5961                 Reserved. Return zeroes on reads.
5962                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_23                                               0x0
5963
5964                 Command word to command word programming delay
5965                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L                                                  0x0
5966
5967                 Reserved. Return zeroes on reads.
5968                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_19                                               0x0
5969
5970                 Command word to command word programming delay
5971                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD                                                    0x0
5972
5973                 Reserved. Return zeroes on reads.
5974                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14                                            0x0
5975
5976                 Stabilization time
5977                 PSU_DDR_PHY_RDIMMGCR1_TBCSTAB                                                   0xc80
5978
5979                 RDIMM General Configuration Register 1
5980                 (OFFSET, MASK, VALUE)      (0XFD080144, 0xFFFFFFFFU ,0x00000C80U)
5981                 RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK |  0 );
5982
5983                 RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
5984                         | 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT
5985                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
5986                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
5987                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
5988                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
5989                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
5990                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
5991                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
5992                         | 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
5993                         |  0 ) & RegMask); */
5994                 PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U);
5995         /*############################################################################################################################ */
5996
5997                 /*Register : RDIMMCR0 @ 0XFD080150</p>
5998
5999                 DDR4/DDR3 Control Word 7
6000                 PSU_DDR_PHY_RDIMMCR0_RC7                                                        0x0
6001
6002                 DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
6003                 PSU_DDR_PHY_RDIMMCR0_RC6                                                        0x0
6004
6005                 DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
6006                 PSU_DDR_PHY_RDIMMCR0_RC5                                                        0x0
6007
6008                 DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
6009                 aracteristics Control Word)
6010                 PSU_DDR_PHY_RDIMMCR0_RC4                                                        0x0
6011
6012                 DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
6013                 ver Characteristrics Control Word)
6014                 PSU_DDR_PHY_RDIMMCR0_RC3                                                        0x0
6015
6016                 DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)
6017                 PSU_DDR_PHY_RDIMMCR0_RC2                                                        0x0
6018
6019                 DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
6020                 PSU_DDR_PHY_RDIMMCR0_RC1                                                        0x0
6021
6022                 DDR4/DDR3 Control Word 0 (Global Features Control Word)
6023                 PSU_DDR_PHY_RDIMMCR0_RC0                                                        0x0
6024
6025                 RDIMM Control Register 0
6026                 (OFFSET, MASK, VALUE)      (0XFD080150, 0xFFFFFFFFU ,0x00000000U)
6027                 RegMask = (DDR_PHY_RDIMMCR0_RC7_MASK | DDR_PHY_RDIMMCR0_RC6_MASK | DDR_PHY_RDIMMCR0_RC5_MASK | DDR_PHY_RDIMMCR0_RC4_MASK | DDR_PHY_RDIMMCR0_RC3_MASK | DDR_PHY_RDIMMCR0_RC2_MASK | DDR_PHY_RDIMMCR0_RC1_MASK | DDR_PHY_RDIMMCR0_RC0_MASK |  0 );
6028
6029                 RegVal = ((0x00000000U << DDR_PHY_RDIMMCR0_RC7_SHIFT
6030                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC6_SHIFT
6031                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC5_SHIFT
6032                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC4_SHIFT
6033                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC3_SHIFT
6034                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC2_SHIFT
6035                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC1_SHIFT
6036                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC0_SHIFT
6037                         |  0 ) & RegMask); */
6038                 PSU_Mask_Write (DDR_PHY_RDIMMCR0_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6039         /*############################################################################################################################ */
6040
6041                 /*Register : RDIMMCR1 @ 0XFD080154</p>
6042
6043                 Control Word 15
6044                 PSU_DDR_PHY_RDIMMCR1_RC15                                                       0x0
6045
6046                 DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
6047                 PSU_DDR_PHY_RDIMMCR1_RC14                                                       0x0
6048
6049                 DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
6050                 PSU_DDR_PHY_RDIMMCR1_RC13                                                       0x0
6051
6052                 DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
6053                 PSU_DDR_PHY_RDIMMCR1_RC12                                                       0x0
6054
6055                 DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
6056                 rol Word)
6057                 PSU_DDR_PHY_RDIMMCR1_RC11                                                       0x0
6058
6059                 DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
6060                 PSU_DDR_PHY_RDIMMCR1_RC10                                                       0x2
6061
6062                 DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
6063                 PSU_DDR_PHY_RDIMMCR1_RC9                                                        0x0
6064
6065                 DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
6066                 Control Word)
6067                 PSU_DDR_PHY_RDIMMCR1_RC8                                                        0x0
6068
6069                 RDIMM Control Register 1
6070                 (OFFSET, MASK, VALUE)      (0XFD080154, 0xFFFFFFFFU ,0x00000200U)
6071                 RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK |  0 );
6072
6073                 RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT
6074                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT
6075                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT
6076                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT
6077                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT
6078                         | 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT
6079                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT
6080                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT
6081                         |  0 ) & RegMask); */
6082                 PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U);
6083         /*############################################################################################################################ */
6084
6085                 /*Register : MR0 @ 0XFD080180</p>
6086
6087                 Reserved. Return zeroes on reads.
6088                 PSU_DDR_PHY_MR0_RESERVED_31_8                                                   0x8
6089
6090                 CA Terminating Rank
6091                 PSU_DDR_PHY_MR0_CATR                                                            0x0
6092
6093                 Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6094                 PSU_DDR_PHY_MR0_RSVD_6_5                                                        0x1
6095
6096                 Built-in Self-Test for RZQ
6097                 PSU_DDR_PHY_MR0_RZQI                                                            0x2
6098
6099                 Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6100                 PSU_DDR_PHY_MR0_RSVD_2_0                                                        0x0
6101
6102                 LPDDR4 Mode Register 0
6103                 (OFFSET, MASK, VALUE)      (0XFD080180, 0xFFFFFFFFU ,0x00000830U)
6104                 RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK |  0 );
6105
6106                 RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT
6107                         | 0x00000000U << DDR_PHY_MR0_CATR_SHIFT
6108                         | 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT
6109                         | 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT
6110                         | 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT
6111                         |  0 ) & RegMask); */
6112                 PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U);
6113         /*############################################################################################################################ */
6114
6115                 /*Register : MR1 @ 0XFD080184</p>
6116
6117                 Reserved. Return zeroes on reads.
6118                 PSU_DDR_PHY_MR1_RESERVED_31_8                                                   0x3
6119
6120                 Read Postamble Length
6121                 PSU_DDR_PHY_MR1_RDPST                                                           0x0
6122
6123                 Write-recovery for auto-precharge command
6124                 PSU_DDR_PHY_MR1_NWR                                                             0x0
6125
6126                 Read Preamble Length
6127                 PSU_DDR_PHY_MR1_RDPRE                                                           0x0
6128
6129                 Write Preamble Length
6130                 PSU_DDR_PHY_MR1_WRPRE                                                           0x0
6131
6132                 Burst Length
6133                 PSU_DDR_PHY_MR1_BL                                                              0x1
6134
6135                 LPDDR4 Mode Register 1
6136                 (OFFSET, MASK, VALUE)      (0XFD080184, 0xFFFFFFFFU ,0x00000301U)
6137                 RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK |  0 );
6138
6139                 RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT
6140                         | 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT
6141                         | 0x00000000U << DDR_PHY_MR1_NWR_SHIFT
6142                         | 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT
6143                         | 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT
6144                         | 0x00000001U << DDR_PHY_MR1_BL_SHIFT
6145                         |  0 ) & RegMask); */
6146                 PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U);
6147         /*############################################################################################################################ */
6148
6149                 /*Register : MR2 @ 0XFD080188</p>
6150
6151                 Reserved. Return zeroes on reads.
6152                 PSU_DDR_PHY_MR2_RESERVED_31_8                                                   0x0
6153
6154                 Write Leveling
6155                 PSU_DDR_PHY_MR2_WRL                                                             0x0
6156
6157                 Write Latency Set
6158                 PSU_DDR_PHY_MR2_WLS                                                             0x0
6159
6160                 Write Latency
6161                 PSU_DDR_PHY_MR2_WL                                                              0x4
6162
6163                 Read Latency
6164                 PSU_DDR_PHY_MR2_RL                                                              0x0
6165
6166                 LPDDR4 Mode Register 2
6167                 (OFFSET, MASK, VALUE)      (0XFD080188, 0xFFFFFFFFU ,0x00000020U)
6168                 RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK |  0 );
6169
6170                 RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT
6171                         | 0x00000000U << DDR_PHY_MR2_WRL_SHIFT
6172                         | 0x00000000U << DDR_PHY_MR2_WLS_SHIFT
6173                         | 0x00000004U << DDR_PHY_MR2_WL_SHIFT
6174                         | 0x00000000U << DDR_PHY_MR2_RL_SHIFT
6175                         |  0 ) & RegMask); */
6176                 PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U);
6177         /*############################################################################################################################ */
6178
6179                 /*Register : MR3 @ 0XFD08018C</p>
6180
6181                 Reserved. Return zeroes on reads.
6182                 PSU_DDR_PHY_MR3_RESERVED_31_8                                                   0x2
6183
6184                 DBI-Write Enable
6185                 PSU_DDR_PHY_MR3_DBIWR                                                           0x0
6186
6187                 DBI-Read Enable
6188                 PSU_DDR_PHY_MR3_DBIRD                                                           0x0
6189
6190                 Pull-down Drive Strength
6191                 PSU_DDR_PHY_MR3_PDDS                                                            0x0
6192
6193                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6194                 PSU_DDR_PHY_MR3_RSVD                                                            0x0
6195
6196                 Write Postamble Length
6197                 PSU_DDR_PHY_MR3_WRPST                                                           0x0
6198
6199                 Pull-up Calibration Point
6200                 PSU_DDR_PHY_MR3_PUCAL                                                           0x0
6201
6202                 LPDDR4 Mode Register 3
6203                 (OFFSET, MASK, VALUE)      (0XFD08018C, 0xFFFFFFFFU ,0x00000200U)
6204                 RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK |  0 );
6205
6206                 RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT
6207                         | 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT
6208                         | 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT
6209                         | 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT
6210                         | 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT
6211                         | 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT
6212                         | 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT
6213                         |  0 ) & RegMask); */
6214                 PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U);
6215         /*############################################################################################################################ */
6216
6217                 /*Register : MR4 @ 0XFD080190</p>
6218
6219                 Reserved. Return zeroes on reads.
6220                 PSU_DDR_PHY_MR4_RESERVED_31_16                                                  0x0
6221
6222                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6223                 PSU_DDR_PHY_MR4_RSVD_15_13                                                      0x0
6224
6225                 Write Preamble
6226                 PSU_DDR_PHY_MR4_WRP                                                             0x0
6227
6228                 Read Preamble
6229                 PSU_DDR_PHY_MR4_RDP                                                             0x0
6230
6231                 Read Preamble Training Mode
6232                 PSU_DDR_PHY_MR4_RPTM                                                            0x0
6233
6234                 Self Refresh Abort
6235                 PSU_DDR_PHY_MR4_SRA                                                             0x0
6236
6237                 CS to Command Latency Mode
6238                 PSU_DDR_PHY_MR4_CS2CMDL                                                         0x0
6239
6240                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6241                 PSU_DDR_PHY_MR4_RSVD1                                                           0x0
6242
6243                 Internal VREF Monitor
6244                 PSU_DDR_PHY_MR4_IVM                                                             0x0
6245
6246                 Temperature Controlled Refresh Mode
6247                 PSU_DDR_PHY_MR4_TCRM                                                            0x0
6248
6249                 Temperature Controlled Refresh Range
6250                 PSU_DDR_PHY_MR4_TCRR                                                            0x0
6251
6252                 Maximum Power Down Mode
6253                 PSU_DDR_PHY_MR4_MPDM                                                            0x0
6254
6255                 This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
6256                 PSU_DDR_PHY_MR4_RSVD_0                                                          0x0
6257
6258                 DDR4 Mode Register 4
6259                 (OFFSET, MASK, VALUE)      (0XFD080190, 0xFFFFFFFFU ,0x00000000U)
6260                 RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK |  0 );
6261
6262                 RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT
6263                         | 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT
6264                         | 0x00000000U << DDR_PHY_MR4_WRP_SHIFT
6265                         | 0x00000000U << DDR_PHY_MR4_RDP_SHIFT
6266                         | 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT
6267                         | 0x00000000U << DDR_PHY_MR4_SRA_SHIFT
6268                         | 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT
6269                         | 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT
6270                         | 0x00000000U << DDR_PHY_MR4_IVM_SHIFT
6271                         | 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT
6272                         | 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT
6273                         | 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT
6274                         | 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT
6275                         |  0 ) & RegMask); */
6276                 PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6277         /*############################################################################################################################ */
6278
6279                 /*Register : MR5 @ 0XFD080194</p>
6280
6281                 Reserved. Return zeroes on reads.
6282                 PSU_DDR_PHY_MR5_RESERVED_31_16                                                  0x0
6283
6284                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6285                 PSU_DDR_PHY_MR5_RSVD                                                            0x0
6286
6287                 Read DBI
6288                 PSU_DDR_PHY_MR5_RDBI                                                            0x0
6289
6290                 Write DBI
6291                 PSU_DDR_PHY_MR5_WDBI                                                            0x0
6292
6293                 Data Mask
6294                 PSU_DDR_PHY_MR5_DM                                                              0x1
6295
6296                 CA Parity Persistent Error
6297                 PSU_DDR_PHY_MR5_CAPPE                                                           0x1
6298
6299                 RTT_PARK
6300                 PSU_DDR_PHY_MR5_RTTPARK                                                         0x3
6301
6302                 ODT Input Buffer during Power Down mode
6303                 PSU_DDR_PHY_MR5_ODTIBPD                                                         0x0
6304
6305                 C/A Parity Error Status
6306                 PSU_DDR_PHY_MR5_CAPES                                                           0x0
6307
6308                 CRC Error Clear
6309                 PSU_DDR_PHY_MR5_CRCEC                                                           0x0
6310
6311                 C/A Parity Latency Mode
6312                 PSU_DDR_PHY_MR5_CAPM                                                            0x0
6313
6314                 DDR4 Mode Register 5
6315                 (OFFSET, MASK, VALUE)      (0XFD080194, 0xFFFFFFFFU ,0x000006C0U)
6316                 RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK |  0 );
6317
6318                 RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT
6319                         | 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT
6320                         | 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT
6321                         | 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT
6322                         | 0x00000001U << DDR_PHY_MR5_DM_SHIFT
6323                         | 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT
6324                         | 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT
6325                         | 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT
6326                         | 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT
6327                         | 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT
6328                         | 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT
6329                         |  0 ) & RegMask); */
6330                 PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
6331         /*############################################################################################################################ */
6332
6333                 /*Register : MR6 @ 0XFD080198</p>
6334
6335                 Reserved. Return zeroes on reads.
6336                 PSU_DDR_PHY_MR6_RESERVED_31_16                                                  0x0
6337
6338                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6339                 PSU_DDR_PHY_MR6_RSVD_15_13                                                      0x0
6340
6341                 CAS_n to CAS_n command delay for same bank group (tCCD_L)
6342                 PSU_DDR_PHY_MR6_TCCDL                                                           0x2
6343
6344                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6345                 PSU_DDR_PHY_MR6_RSVD_9_8                                                        0x0
6346
6347                 VrefDQ Training Enable
6348                 PSU_DDR_PHY_MR6_VDDQTEN                                                         0x0
6349
6350                 VrefDQ Training Range
6351                 PSU_DDR_PHY_MR6_VDQTRG                                                          0x0
6352
6353                 VrefDQ Training Values
6354                 PSU_DDR_PHY_MR6_VDQTVAL                                                         0x19
6355
6356                 DDR4 Mode Register 6
6357                 (OFFSET, MASK, VALUE)      (0XFD080198, 0xFFFFFFFFU ,0x00000819U)
6358                 RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK |  0 );
6359
6360                 RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT
6361                         | 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT
6362                         | 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT
6363                         | 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT
6364                         | 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT
6365                         | 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT
6366                         | 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT
6367                         |  0 ) & RegMask); */
6368                 PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U);
6369         /*############################################################################################################################ */
6370
6371                 /*Register : MR11 @ 0XFD0801AC</p>
6372
6373                 Reserved. Return zeroes on reads.
6374                 PSU_DDR_PHY_MR11_RESERVED_31_8                                                  0x0
6375
6376                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6377                 PSU_DDR_PHY_MR11_RSVD                                                           0x0
6378
6379                 Power Down Control
6380                 PSU_DDR_PHY_MR11_PDCTL                                                          0x0
6381
6382                 DQ Bus Receiver On-Die-Termination
6383                 PSU_DDR_PHY_MR11_DQODT                                                          0x0
6384
6385                 LPDDR4 Mode Register 11
6386                 (OFFSET, MASK, VALUE)      (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U)
6387                 RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK |  0 );
6388
6389                 RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT
6390                         | 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT
6391                         | 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT
6392                         | 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT
6393                         |  0 ) & RegMask); */
6394                 PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6395         /*############################################################################################################################ */
6396
6397                 /*Register : MR12 @ 0XFD0801B0</p>
6398
6399                 Reserved. Return zeroes on reads.
6400                 PSU_DDR_PHY_MR12_RESERVED_31_8                                                  0x0
6401
6402                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6403                 PSU_DDR_PHY_MR12_RSVD                                                           0x0
6404
6405                 VREF_CA Range Select.
6406                 PSU_DDR_PHY_MR12_VR_CA                                                          0x1
6407
6408                 Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
6409                 PSU_DDR_PHY_MR12_VREF_CA                                                        0xd
6410
6411                 LPDDR4 Mode Register 12
6412                 (OFFSET, MASK, VALUE)      (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU)
6413                 RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK |  0 );
6414
6415                 RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT
6416                         | 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT
6417                         | 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT
6418                         | 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT
6419                         |  0 ) & RegMask); */
6420                 PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
6421         /*############################################################################################################################ */
6422
6423                 /*Register : MR13 @ 0XFD0801B4</p>
6424
6425                 Reserved. Return zeroes on reads.
6426                 PSU_DDR_PHY_MR13_RESERVED_31_8                                                  0x0
6427
6428                 Frequency Set Point Operation Mode
6429                 PSU_DDR_PHY_MR13_FSPOP                                                          0x0
6430
6431                 Frequency Set Point Write Enable
6432                 PSU_DDR_PHY_MR13_FSPWR                                                          0x0
6433
6434                 Data Mask Enable
6435                 PSU_DDR_PHY_MR13_DMD                                                            0x0
6436
6437                 Refresh Rate Option
6438                 PSU_DDR_PHY_MR13_RRO                                                            0x0
6439
6440                 VREF Current Generator
6441                 PSU_DDR_PHY_MR13_VRCG                                                           0x1
6442
6443                 VREF Output
6444                 PSU_DDR_PHY_MR13_VRO                                                            0x0
6445
6446                 Read Preamble Training Mode
6447                 PSU_DDR_PHY_MR13_RPT                                                            0x0
6448
6449                 Command Bus Training
6450                 PSU_DDR_PHY_MR13_CBT                                                            0x0
6451
6452                 LPDDR4 Mode Register 13
6453                 (OFFSET, MASK, VALUE)      (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U)
6454                 RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK |  0 );
6455
6456                 RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT
6457                         | 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT
6458                         | 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT
6459                         | 0x00000000U << DDR_PHY_MR13_DMD_SHIFT
6460                         | 0x00000000U << DDR_PHY_MR13_RRO_SHIFT
6461                         | 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT
6462                         | 0x00000000U << DDR_PHY_MR13_VRO_SHIFT
6463                         | 0x00000000U << DDR_PHY_MR13_RPT_SHIFT
6464                         | 0x00000000U << DDR_PHY_MR13_CBT_SHIFT
6465                         |  0 ) & RegMask); */
6466                 PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U);
6467         /*############################################################################################################################ */
6468
6469                 /*Register : MR14 @ 0XFD0801B8</p>
6470
6471                 Reserved. Return zeroes on reads.
6472                 PSU_DDR_PHY_MR14_RESERVED_31_8                                                  0x0
6473
6474                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6475                 PSU_DDR_PHY_MR14_RSVD                                                           0x0
6476
6477                 VREFDQ Range Selects.
6478                 PSU_DDR_PHY_MR14_VR_DQ                                                          0x1
6479
6480                 Reserved. Return zeroes on reads.
6481                 PSU_DDR_PHY_MR14_VREF_DQ                                                        0xd
6482
6483                 LPDDR4 Mode Register 14
6484                 (OFFSET, MASK, VALUE)      (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU)
6485                 RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK |  0 );
6486
6487                 RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT
6488                         | 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT
6489                         | 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT
6490                         | 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT
6491                         |  0 ) & RegMask); */
6492                 PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
6493         /*############################################################################################################################ */
6494
6495                 /*Register : MR22 @ 0XFD0801D8</p>
6496
6497                 Reserved. Return zeroes on reads.
6498                 PSU_DDR_PHY_MR22_RESERVED_31_8                                                  0x0
6499
6500                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6501                 PSU_DDR_PHY_MR22_RSVD                                                           0x0
6502
6503                 CA ODT termination disable.
6504                 PSU_DDR_PHY_MR22_ODTD_CA                                                        0x0
6505
6506                 ODT CS override.
6507                 PSU_DDR_PHY_MR22_ODTE_CS                                                        0x0
6508
6509                 ODT CK override.
6510                 PSU_DDR_PHY_MR22_ODTE_CK                                                        0x0
6511
6512                 Controller ODT value for VOH calibration.
6513                 PSU_DDR_PHY_MR22_CODT                                                           0x0
6514
6515                 LPDDR4 Mode Register 22
6516                 (OFFSET, MASK, VALUE)      (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U)
6517                 RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK |  0 );
6518
6519                 RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT
6520                         | 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT
6521                         | 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT
6522                         | 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT
6523                         | 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT
6524                         | 0x00000000U << DDR_PHY_MR22_CODT_SHIFT
6525                         |  0 ) & RegMask); */
6526                 PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6527         /*############################################################################################################################ */
6528
6529                 /*Register : DTCR0 @ 0XFD080200</p>
6530
6531                 Refresh During Training
6532                 PSU_DDR_PHY_DTCR0_RFSHDT                                                        0x8
6533
6534                 Reserved. Return zeroes on reads.
6535                 PSU_DDR_PHY_DTCR0_RESERVED_27_26                                                0x0
6536
6537                 Data Training Debug Rank Select
6538                 PSU_DDR_PHY_DTCR0_DTDRS                                                         0x0
6539
6540                 Data Training with Early/Extended Gate
6541                 PSU_DDR_PHY_DTCR0_DTEXG                                                         0x0
6542
6543                 Data Training Extended Write DQS
6544                 PSU_DDR_PHY_DTCR0_DTEXD                                                         0x0
6545
6546                 Data Training Debug Step
6547                 PSU_DDR_PHY_DTCR0_DTDSTP                                                        0x0
6548
6549                 Data Training Debug Enable
6550                 PSU_DDR_PHY_DTCR0_DTDEN                                                         0x0
6551
6552                 Data Training Debug Byte Select
6553                 PSU_DDR_PHY_DTCR0_DTDBS                                                         0x0
6554
6555                 Data Training read DBI deskewing configuration
6556                 PSU_DDR_PHY_DTCR0_DTRDBITR                                                      0x2
6557
6558                 Reserved. Return zeroes on reads.
6559                 PSU_DDR_PHY_DTCR0_RESERVED_13                                                   0x0
6560
6561                 Data Training Write Bit Deskew Data Mask
6562                 PSU_DDR_PHY_DTCR0_DTWBDDM                                                       0x1
6563
6564                 Refreshes Issued During Entry to Training
6565                 PSU_DDR_PHY_DTCR0_RFSHEN                                                        0x1
6566
6567                 Data Training Compare Data
6568                 PSU_DDR_PHY_DTCR0_DTCMPD                                                        0x1
6569
6570                 Data Training Using MPR
6571                 PSU_DDR_PHY_DTCR0_DTMPR                                                         0x1
6572
6573                 Reserved. Return zeroes on reads.
6574                 PSU_DDR_PHY_DTCR0_RESERVED_5_4                                                  0x0
6575
6576                 Data Training Repeat Number
6577                 PSU_DDR_PHY_DTCR0_DTRPTN                                                        0x7
6578
6579                 Data Training Configuration Register 0
6580                 (OFFSET, MASK, VALUE)      (0XFD080200, 0xFFFFFFFFU ,0x800091C7U)
6581                 RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK |  0 );
6582
6583                 RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT
6584                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
6585                         | 0x00000000U << DDR_PHY_DTCR0_DTDRS_SHIFT
6586                         | 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT
6587                         | 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT
6588                         | 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT
6589                         | 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT
6590                         | 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT
6591                         | 0x00000002U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
6592                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT
6593                         | 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT
6594                         | 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT
6595                         | 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT
6596                         | 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT
6597                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
6598                         | 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT
6599                         |  0 ) & RegMask); */
6600                 PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x800091C7U);
6601         /*############################################################################################################################ */
6602
6603                 /*Register : DTCR1 @ 0XFD080204</p>
6604
6605                 Rank Enable.
6606                 PSU_DDR_PHY_DTCR1_RANKEN_RSVD                                                   0x0
6607
6608                 Rank Enable.
6609                 PSU_DDR_PHY_DTCR1_RANKEN                                                        0x1
6610
6611                 Reserved. Return zeroes on reads.
6612                 PSU_DDR_PHY_DTCR1_RESERVED_15_14                                                0x0
6613
6614                 Data Training Rank
6615                 PSU_DDR_PHY_DTCR1_DTRANK                                                        0x0
6616
6617                 Reserved. Return zeroes on reads.
6618                 PSU_DDR_PHY_DTCR1_RESERVED_11                                                   0x0
6619
6620                 Read Leveling Gate Sampling Difference
6621                 PSU_DDR_PHY_DTCR1_RDLVLGDIFF                                                    0x2
6622
6623                 Reserved. Return zeroes on reads.
6624                 PSU_DDR_PHY_DTCR1_RESERVED_7                                                    0x0
6625
6626                 Read Leveling Gate Shift
6627                 PSU_DDR_PHY_DTCR1_RDLVLGS                                                       0x3
6628
6629                 Reserved. Return zeroes on reads.
6630                 PSU_DDR_PHY_DTCR1_RESERVED_3                                                    0x0
6631
6632                 Read Preamble Training enable
6633                 PSU_DDR_PHY_DTCR1_RDPRMVL_TRN                                                   0x1
6634
6635                 Read Leveling Enable
6636                 PSU_DDR_PHY_DTCR1_RDLVLEN                                                       0x1
6637
6638                 Basic Gate Training Enable
6639                 PSU_DDR_PHY_DTCR1_BSTEN                                                         0x0
6640
6641                 Data Training Configuration Register 1
6642                 (OFFSET, MASK, VALUE)      (0XFD080204, 0xFFFFFFFFU ,0x00010236U)
6643                 RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK |  0 );
6644
6645                 RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
6646                         | 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT
6647                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
6648                         | 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT
6649                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT
6650                         | 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
6651                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT
6652                         | 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT
6653                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT
6654                         | 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
6655                         | 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT
6656                         | 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT
6657                         |  0 ) & RegMask); */
6658                 PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U);
6659         /*############################################################################################################################ */
6660
6661                 /*Register : CATR0 @ 0XFD080240</p>
6662
6663                 Reserved. Return zeroes on reads.
6664                 PSU_DDR_PHY_CATR0_RESERVED_31_21                                                0x0
6665
6666                 Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
6667                 PSU_DDR_PHY_CATR0_CACD                                                          0x14
6668
6669                 Reserved. Return zeroes on reads.
6670                 PSU_DDR_PHY_CATR0_RESERVED_15_13                                                0x0
6671
6672                 Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
6673                  been sent to the memory
6674                 PSU_DDR_PHY_CATR0_CAADR                                                         0x10
6675
6676                 CA_1 Response Byte Lane 1
6677                 PSU_DDR_PHY_CATR0_CA1BYTE1                                                      0x5
6678
6679                 CA_1 Response Byte Lane 0
6680                 PSU_DDR_PHY_CATR0_CA1BYTE0                                                      0x4
6681
6682                 CA Training Register 0
6683                 (OFFSET, MASK, VALUE)      (0XFD080240, 0xFFFFFFFFU ,0x00141054U)
6684                 RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK |  0 );
6685
6686                 RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT
6687                         | 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT
6688                         | 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT
6689                         | 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT
6690                         | 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT
6691                         | 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT
6692                         |  0 ) & RegMask); */
6693                 PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U);
6694         /*############################################################################################################################ */
6695
6696                 /*Register : BISTLSR @ 0XFD080414</p>
6697
6698                 LFSR seed for pseudo-random BIST patterns
6699                 PSU_DDR_PHY_BISTLSR_SEED                                                        0x12341000
6700
6701                 BIST LFSR Seed Register
6702                 (OFFSET, MASK, VALUE)      (0XFD080414, 0xFFFFFFFFU ,0x12341000U)
6703                 RegMask = (DDR_PHY_BISTLSR_SEED_MASK |  0 );
6704
6705                 RegVal = ((0x12341000U << DDR_PHY_BISTLSR_SEED_SHIFT
6706                         |  0 ) & RegMask); */
6707                 PSU_Mask_Write (DDR_PHY_BISTLSR_OFFSET ,0xFFFFFFFFU ,0x12341000U);
6708         /*############################################################################################################################ */
6709
6710                 /*Register : RIOCR5 @ 0XFD0804F4</p>
6711
6712                 Reserved. Return zeroes on reads.
6713                 PSU_DDR_PHY_RIOCR5_RESERVED_31_16                                               0x0
6714
6715                 Reserved. Return zeros on reads.
6716                 PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD                                               0x0
6717
6718                 SDRAM On-die Termination Output Enable (OE) Mode Selection.
6719                 PSU_DDR_PHY_RIOCR5_ODTOEMODE                                                    0x5
6720
6721                 Rank I/O Configuration Register 5
6722                 (OFFSET, MASK, VALUE)      (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U)
6723                 RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK |  0 );
6724
6725                 RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
6726                         | 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
6727                         | 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
6728                         |  0 ) & RegMask); */
6729                 PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U);
6730         /*############################################################################################################################ */
6731
6732                 /*Register : ACIOCR0 @ 0XFD080500</p>
6733
6734                 Address/Command Slew Rate (D3F I/O Only)
6735                 PSU_DDR_PHY_ACIOCR0_ACSR                                                        0x0
6736
6737                 SDRAM Reset I/O Mode
6738                 PSU_DDR_PHY_ACIOCR0_RSTIOM                                                      0x1
6739
6740                 SDRAM Reset Power Down Receiver
6741                 PSU_DDR_PHY_ACIOCR0_RSTPDR                                                      0x1
6742
6743                 Reserved. Return zeroes on reads.
6744                 PSU_DDR_PHY_ACIOCR0_RESERVED_27                                                 0x0
6745
6746                 SDRAM Reset On-Die Termination
6747                 PSU_DDR_PHY_ACIOCR0_RSTODT                                                      0x0
6748
6749                 Reserved. Return zeroes on reads.
6750                 PSU_DDR_PHY_ACIOCR0_RESERVED_25_10                                              0x0
6751
6752                 CK Duty Cycle Correction
6753                 PSU_DDR_PHY_ACIOCR0_CKDCC                                                       0x0
6754
6755                 AC Power Down Receiver Mode
6756                 PSU_DDR_PHY_ACIOCR0_ACPDRMODE                                                   0x2
6757
6758                 AC On-die Termination Mode
6759                 PSU_DDR_PHY_ACIOCR0_ACODTMODE                                                   0x2
6760
6761                 Reserved. Return zeroes on reads.
6762                 PSU_DDR_PHY_ACIOCR0_RESERVED_1                                                  0x0
6763
6764                 Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
6765                 PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL                                                0x0
6766
6767                 AC I/O Configuration Register 0
6768                 (OFFSET, MASK, VALUE)      (0XFD080500, 0xFFFFFFFFU ,0x30000028U)
6769                 RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK |  0 );
6770
6771                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT
6772                         | 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT
6773                         | 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT
6774                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
6775                         | 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT
6776                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
6777                         | 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT
6778                         | 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
6779                         | 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
6780                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
6781                         | 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
6782                         |  0 ) & RegMask); */
6783                 PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U);
6784         /*############################################################################################################################ */
6785
6786                 /*Register : ACIOCR2 @ 0XFD080508</p>
6787
6788                 Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
6789                 PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE                                               0x0
6790
6791                 Clock gating for Output Enable D slices [0]
6792                 PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0                                                0x0
6793
6794                 Clock gating for Power Down Receiver D slices [0]
6795                 PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0                                               0x0
6796
6797                 Clock gating for Termination Enable D slices [0]
6798                 PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0                                                0x0
6799
6800                 Clock gating for CK# D slices [1:0]
6801                 PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0                                                 0x2
6802
6803                 Clock gating for CK D slices [1:0]
6804                 PSU_DDR_PHY_ACIOCR2_CKCLKGATE0                                                  0x2
6805
6806                 Clock gating for AC D slices [23:0]
6807                 PSU_DDR_PHY_ACIOCR2_ACCLKGATE0                                                  0x0
6808
6809                 AC I/O Configuration Register 2
6810                 (OFFSET, MASK, VALUE)      (0XFD080508, 0xFFFFFFFFU ,0x0A000000U)
6811                 RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK |  0 );
6812
6813                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
6814                         | 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
6815                         | 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
6816                         | 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
6817                         | 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
6818                         | 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
6819                         | 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
6820                         |  0 ) & RegMask); */
6821                 PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
6822         /*############################################################################################################################ */
6823
6824                 /*Register : ACIOCR3 @ 0XFD08050C</p>
6825
6826                 SDRAM Parity Output Enable (OE) Mode Selection
6827                 PSU_DDR_PHY_ACIOCR3_PAROEMODE                                                   0x0
6828
6829                 SDRAM Bank Group Output Enable (OE) Mode Selection
6830                 PSU_DDR_PHY_ACIOCR3_BGOEMODE                                                    0x0
6831
6832                 SDRAM Bank Address Output Enable (OE) Mode Selection
6833                 PSU_DDR_PHY_ACIOCR3_BAOEMODE                                                    0x0
6834
6835                 SDRAM A[17] Output Enable (OE) Mode Selection
6836                 PSU_DDR_PHY_ACIOCR3_A17OEMODE                                                   0x0
6837
6838                 SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
6839                 PSU_DDR_PHY_ACIOCR3_A16OEMODE                                                   0x0
6840
6841                 SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
6842                 PSU_DDR_PHY_ACIOCR3_ACTOEMODE                                                   0x0
6843
6844                 Reserved. Return zeroes on reads.
6845                 PSU_DDR_PHY_ACIOCR3_RESERVED_15_8                                               0x0
6846
6847                 Reserved. Return zeros on reads.
6848                 PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD                                               0x0
6849
6850                 SDRAM CK Output Enable (OE) Mode Selection.
6851                 PSU_DDR_PHY_ACIOCR3_CKOEMODE                                                    0x9
6852
6853                 AC I/O Configuration Register 3
6854                 (OFFSET, MASK, VALUE)      (0XFD08050C, 0xFFFFFFFFU ,0x00000009U)
6855                 RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK |  0 );
6856
6857                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
6858                         | 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
6859                         | 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
6860                         | 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
6861                         | 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
6862                         | 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
6863                         | 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
6864                         | 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
6865                         | 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
6866                         |  0 ) & RegMask); */
6867                 PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U);
6868         /*############################################################################################################################ */
6869
6870                 /*Register : ACIOCR4 @ 0XFD080510</p>
6871
6872                 Clock gating for AC LB slices and loopback read valid slices
6873                 PSU_DDR_PHY_ACIOCR4_LBCLKGATE                                                   0x0
6874
6875                 Clock gating for Output Enable D slices [1]
6876                 PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1                                                0x0
6877
6878                 Clock gating for Power Down Receiver D slices [1]
6879                 PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1                                               0x0
6880
6881                 Clock gating for Termination Enable D slices [1]
6882                 PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1                                                0x0
6883
6884                 Clock gating for CK# D slices [3:2]
6885                 PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1                                                 0x2
6886
6887                 Clock gating for CK D slices [3:2]
6888                 PSU_DDR_PHY_ACIOCR4_CKCLKGATE1                                                  0x2
6889
6890                 Clock gating for AC D slices [47:24]
6891                 PSU_DDR_PHY_ACIOCR4_ACCLKGATE1                                                  0x0
6892
6893                 AC I/O Configuration Register 4
6894                 (OFFSET, MASK, VALUE)      (0XFD080510, 0xFFFFFFFFU ,0x0A000000U)
6895                 RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK |  0 );
6896
6897                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
6898                         | 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
6899                         | 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
6900                         | 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
6901                         | 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
6902                         | 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
6903                         | 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
6904                         |  0 ) & RegMask); */
6905                 PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
6906         /*############################################################################################################################ */
6907
6908                 /*Register : IOVCR0 @ 0XFD080520</p>
6909
6910                 Reserved. Return zeroes on reads.
6911                 PSU_DDR_PHY_IOVCR0_RESERVED_31_29                                               0x0
6912
6913                 Address/command lane VREF Pad Enable
6914                 PSU_DDR_PHY_IOVCR0_ACREFPEN                                                     0x0
6915
6916                 Address/command lane Internal VREF Enable
6917                 PSU_DDR_PHY_IOVCR0_ACREFEEN                                                     0x0
6918
6919                 Address/command lane Single-End VREF Enable
6920                 PSU_DDR_PHY_IOVCR0_ACREFSEN                                                     0x1
6921
6922                 Address/command lane Internal VREF Enable
6923                 PSU_DDR_PHY_IOVCR0_ACREFIEN                                                     0x1
6924
6925                 External VREF generato REFSEL range select
6926                 PSU_DDR_PHY_IOVCR0_ACREFESELRANGE                                               0x0
6927
6928                 Address/command lane External VREF Select
6929                 PSU_DDR_PHY_IOVCR0_ACREFESEL                                                    0x0
6930
6931                 Single ended VREF generator REFSEL range select
6932                 PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE                                               0x1
6933
6934                 Address/command lane Single-End VREF Select
6935                 PSU_DDR_PHY_IOVCR0_ACREFSSEL                                                    0x30
6936
6937                 Internal VREF generator REFSEL ragne select
6938                 PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE                                              0x1
6939
6940                 REFSEL Control for internal AC IOs
6941                 PSU_DDR_PHY_IOVCR0_ACVREFISEL                                                   0x30
6942
6943                 IO VREF Control Register 0
6944                 (OFFSET, MASK, VALUE)      (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U)
6945                 RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK |  0 );
6946
6947                 RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
6948                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT
6949                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT
6950                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT
6951                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT
6952                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
6953                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT
6954                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
6955                         | 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
6956                         | 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
6957                         | 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
6958                         |  0 ) & RegMask); */
6959                 PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U);
6960         /*############################################################################################################################ */
6961
6962                 /*Register : VTCR0 @ 0XFD080528</p>
6963
6964                 Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
6965                 PSU_DDR_PHY_VTCR0_TVREF                                                         0x7
6966
6967                 DRM DQ VREF training Enable
6968                 PSU_DDR_PHY_VTCR0_DVEN                                                          0x1
6969
6970                 Per Device Addressability Enable
6971                 PSU_DDR_PHY_VTCR0_PDAEN                                                         0x1
6972
6973                 Reserved. Returns zeroes on reads.
6974                 PSU_DDR_PHY_VTCR0_RESERVED_26                                                   0x0
6975
6976                 VREF Word Count
6977                 PSU_DDR_PHY_VTCR0_VWCR                                                          0x4
6978
6979                 DRAM DQ VREF step size used during DRAM VREF training
6980                 PSU_DDR_PHY_VTCR0_DVSS                                                          0x0
6981
6982                 Maximum VREF limit value used during DRAM VREF training
6983                 PSU_DDR_PHY_VTCR0_DVMAX                                                         0x32
6984
6985                 Minimum VREF limit value used during DRAM VREF training
6986                 PSU_DDR_PHY_VTCR0_DVMIN                                                         0x0
6987
6988                 Initial DRAM DQ VREF value used during DRAM VREF training
6989                 PSU_DDR_PHY_VTCR0_DVINIT                                                        0x19
6990
6991                 VREF Training Control Register 0
6992                 (OFFSET, MASK, VALUE)      (0XFD080528, 0xFFFFFFFFU ,0xF9032019U)
6993                 RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK |  0 );
6994
6995                 RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT
6996                         | 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT
6997                         | 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT
6998                         | 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT
6999                         | 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT
7000                         | 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT
7001                         | 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT
7002                         | 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT
7003                         | 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT
7004                         |  0 ) & RegMask); */
7005                 PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U);
7006         /*############################################################################################################################ */
7007
7008                 /*Register : VTCR1 @ 0XFD08052C</p>
7009
7010                 Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
7011                 PSU_DDR_PHY_VTCR1_HVSS                                                          0x0
7012
7013                 Reserved. Returns zeroes on reads.
7014                 PSU_DDR_PHY_VTCR1_RESERVED_27                                                   0x0
7015
7016                 Maximum VREF limit value used during DRAM VREF training.
7017                 PSU_DDR_PHY_VTCR1_HVMAX                                                         0x7f
7018
7019                 Reserved. Returns zeroes on reads.
7020                 PSU_DDR_PHY_VTCR1_RESERVED_19                                                   0x0
7021
7022                 Minimum VREF limit value used during DRAM VREF training.
7023                 PSU_DDR_PHY_VTCR1_HVMIN                                                         0x0
7024
7025                 Reserved. Returns zeroes on reads.
7026                 PSU_DDR_PHY_VTCR1_RESERVED_11                                                   0x0
7027
7028                 Static Host Vref Rank Value
7029                 PSU_DDR_PHY_VTCR1_SHRNK                                                         0x0
7030
7031                 Static Host Vref Rank Enable
7032                 PSU_DDR_PHY_VTCR1_SHREN                                                         0x1
7033
7034                 Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
7035                 PSU_DDR_PHY_VTCR1_TVREFIO                                                       0x7
7036
7037                 Eye LCDL Offset value for VREF training
7038                 PSU_DDR_PHY_VTCR1_EOFF                                                          0x0
7039
7040                 Number of LCDL Eye points for which VREF training is repeated
7041                 PSU_DDR_PHY_VTCR1_ENUM                                                          0x0
7042
7043                 HOST (IO) internal VREF training Enable
7044                 PSU_DDR_PHY_VTCR1_HVEN                                                          0x1
7045
7046                 Host IO Type Control
7047                 PSU_DDR_PHY_VTCR1_HVIO                                                          0x1
7048
7049                 VREF Training Control Register 1
7050                 (OFFSET, MASK, VALUE)      (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U)
7051                 RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK |  0 );
7052
7053                 RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT
7054                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT
7055                         | 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT
7056                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT
7057                         | 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT
7058                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT
7059                         | 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT
7060                         | 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT
7061                         | 0x00000007U << DDR_PHY_VTCR1_TVREFIO_SHIFT
7062                         | 0x00000000U << DDR_PHY_VTCR1_EOFF_SHIFT
7063                         | 0x00000000U << DDR_PHY_VTCR1_ENUM_SHIFT
7064                         | 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT
7065                         | 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT
7066                         |  0 ) & RegMask); */
7067                 PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F001E3U);
7068         /*############################################################################################################################ */
7069
7070                 /*Register : ACBDLR1 @ 0XFD080544</p>
7071
7072                 Reserved. Return zeroes on reads.
7073                 PSU_DDR_PHY_ACBDLR1_RESERVED_31_30                                              0x0
7074
7075                 Delay select for the BDL on Parity.
7076                 PSU_DDR_PHY_ACBDLR1_PARBD                                                       0x0
7077
7078                 Reserved. Return zeroes on reads.
7079                 PSU_DDR_PHY_ACBDLR1_RESERVED_23_22                                              0x0
7080
7081                 Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.
7082                 PSU_DDR_PHY_ACBDLR1_A16BD                                                       0x0
7083
7084                 Reserved. Return zeroes on reads.
7085                 PSU_DDR_PHY_ACBDLR1_RESERVED_15_14                                              0x0
7086
7087                 Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.
7088                 PSU_DDR_PHY_ACBDLR1_A17BD                                                       0x0
7089
7090                 Reserved. Return zeroes on reads.
7091                 PSU_DDR_PHY_ACBDLR1_RESERVED_7_6                                                0x0
7092
7093                 Delay select for the BDL on ACTN.
7094                 PSU_DDR_PHY_ACBDLR1_ACTBD                                                       0x0
7095
7096                 AC Bit Delay Line Register 1
7097                 (OFFSET, MASK, VALUE)      (0XFD080544, 0xFFFFFFFFU ,0x00000000U)
7098                 RegMask = (DDR_PHY_ACBDLR1_RESERVED_31_30_MASK | DDR_PHY_ACBDLR1_PARBD_MASK | DDR_PHY_ACBDLR1_RESERVED_23_22_MASK | DDR_PHY_ACBDLR1_A16BD_MASK | DDR_PHY_ACBDLR1_RESERVED_15_14_MASK | DDR_PHY_ACBDLR1_A17BD_MASK | DDR_PHY_ACBDLR1_RESERVED_7_6_MASK | DDR_PHY_ACBDLR1_ACTBD_MASK |  0 );
7099
7100                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
7101                         | 0x00000000U << DDR_PHY_ACBDLR1_PARBD_SHIFT
7102                         | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
7103                         | 0x00000000U << DDR_PHY_ACBDLR1_A16BD_SHIFT
7104                         | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
7105                         | 0x00000000U << DDR_PHY_ACBDLR1_A17BD_SHIFT
7106                         | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
7107                         | 0x00000000U << DDR_PHY_ACBDLR1_ACTBD_SHIFT
7108                         |  0 ) & RegMask); */
7109                 PSU_Mask_Write (DDR_PHY_ACBDLR1_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7110         /*############################################################################################################################ */
7111
7112                 /*Register : ACBDLR2 @ 0XFD080548</p>
7113
7114                 Reserved. Return zeroes on reads.
7115                 PSU_DDR_PHY_ACBDLR2_RESERVED_31_30                                              0x0
7116
7117                 Delay select for the BDL on BG[1].
7118                 PSU_DDR_PHY_ACBDLR2_BG1BD                                                       0x0
7119
7120                 Reserved. Return zeroes on reads.
7121                 PSU_DDR_PHY_ACBDLR2_RESERVED_23_22                                              0x0
7122
7123                 Delay select for the BDL on BG[0].
7124                 PSU_DDR_PHY_ACBDLR2_BG0BD                                                       0x0
7125
7126                 Reser.ved Return zeroes on reads.
7127                 PSU_DDR_PHY_ACBDLR2_RESERVED_15_14                                              0x0
7128
7129                 Delay select for the BDL on BA[1].
7130                 PSU_DDR_PHY_ACBDLR2_BA1BD                                                       0x0
7131
7132                 Reserved. Return zeroes on reads.
7133                 PSU_DDR_PHY_ACBDLR2_RESERVED_7_6                                                0x0
7134
7135                 Delay select for the BDL on BA[0].
7136                 PSU_DDR_PHY_ACBDLR2_BA0BD                                                       0x0
7137
7138                 AC Bit Delay Line Register 2
7139                 (OFFSET, MASK, VALUE)      (0XFD080548, 0xFFFFFFFFU ,0x00000000U)
7140                 RegMask = (DDR_PHY_ACBDLR2_RESERVED_31_30_MASK | DDR_PHY_ACBDLR2_BG1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_23_22_MASK | DDR_PHY_ACBDLR2_BG0BD_MASK | DDR_PHY_ACBDLR2_RESERVED_15_14_MASK | DDR_PHY_ACBDLR2_BA1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_7_6_MASK | DDR_PHY_ACBDLR2_BA0BD_MASK |  0 );
7141
7142                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
7143                         | 0x00000000U << DDR_PHY_ACBDLR2_BG1BD_SHIFT
7144                         | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
7145                         | 0x00000000U << DDR_PHY_ACBDLR2_BG0BD_SHIFT
7146                         | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
7147                         | 0x00000000U << DDR_PHY_ACBDLR2_BA1BD_SHIFT
7148                         | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
7149                         | 0x00000000U << DDR_PHY_ACBDLR2_BA0BD_SHIFT
7150                         |  0 ) & RegMask); */
7151                 PSU_Mask_Write (DDR_PHY_ACBDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7152         /*############################################################################################################################ */
7153
7154                 /*Register : ACBDLR6 @ 0XFD080558</p>
7155
7156                 Reserved. Return zeroes on reads.
7157                 PSU_DDR_PHY_ACBDLR6_RESERVED_31_30                                              0x0
7158
7159                 Delay select for the BDL on Address A[3].
7160                 PSU_DDR_PHY_ACBDLR6_A03BD                                                       0x0
7161
7162                 Reserved. Return zeroes on reads.
7163                 PSU_DDR_PHY_ACBDLR6_RESERVED_23_22                                              0x0
7164
7165                 Delay select for the BDL on Address A[2].
7166                 PSU_DDR_PHY_ACBDLR6_A02BD                                                       0x0
7167
7168                 Reserved. Return zeroes on reads.
7169                 PSU_DDR_PHY_ACBDLR6_RESERVED_15_14                                              0x0
7170
7171                 Delay select for the BDL on Address A[1].
7172                 PSU_DDR_PHY_ACBDLR6_A01BD                                                       0x0
7173
7174                 Reserved. Return zeroes on reads.
7175                 PSU_DDR_PHY_ACBDLR6_RESERVED_7_6                                                0x0
7176
7177                 Delay select for the BDL on Address A[0].
7178                 PSU_DDR_PHY_ACBDLR6_A00BD                                                       0x0
7179
7180                 AC Bit Delay Line Register 6
7181                 (OFFSET, MASK, VALUE)      (0XFD080558, 0xFFFFFFFFU ,0x00000000U)
7182                 RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK |  0 );
7183
7184                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
7185                         | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT
7186                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
7187                         | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT
7188                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
7189                         | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT
7190                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
7191                         | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT
7192                         |  0 ) & RegMask); */
7193                 PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7194         /*############################################################################################################################ */
7195
7196                 /*Register : ACBDLR7 @ 0XFD08055C</p>
7197
7198                 Reserved. Return zeroes on reads.
7199                 PSU_DDR_PHY_ACBDLR7_RESERVED_31_30                                              0x0
7200
7201                 Delay select for the BDL on Address A[7].
7202                 PSU_DDR_PHY_ACBDLR7_A07BD                                                       0x0
7203
7204                 Reserved. Return zeroes on reads.
7205                 PSU_DDR_PHY_ACBDLR7_RESERVED_23_22                                              0x0
7206
7207                 Delay select for the BDL on Address A[6].
7208                 PSU_DDR_PHY_ACBDLR7_A06BD                                                       0x0
7209
7210                 Reserved. Return zeroes on reads.
7211                 PSU_DDR_PHY_ACBDLR7_RESERVED_15_14                                              0x0
7212
7213                 Delay select for the BDL on Address A[5].
7214                 PSU_DDR_PHY_ACBDLR7_A05BD                                                       0x0
7215
7216                 Reserved. Return zeroes on reads.
7217                 PSU_DDR_PHY_ACBDLR7_RESERVED_7_6                                                0x0
7218
7219                 Delay select for the BDL on Address A[4].
7220                 PSU_DDR_PHY_ACBDLR7_A04BD                                                       0x0
7221
7222                 AC Bit Delay Line Register 7
7223                 (OFFSET, MASK, VALUE)      (0XFD08055C, 0xFFFFFFFFU ,0x00000000U)
7224                 RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK |  0 );
7225
7226                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
7227                         | 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT
7228                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
7229                         | 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT
7230                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
7231                         | 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT
7232                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
7233                         | 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT
7234                         |  0 ) & RegMask); */
7235                 PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7236         /*############################################################################################################################ */
7237
7238                 /*Register : ACBDLR8 @ 0XFD080560</p>
7239
7240                 Reserved. Return zeroes on reads.
7241                 PSU_DDR_PHY_ACBDLR8_RESERVED_31_30                                              0x0
7242
7243                 Delay select for the BDL on Address A[11].
7244                 PSU_DDR_PHY_ACBDLR8_A11BD                                                       0x0
7245
7246                 Reserved. Return zeroes on reads.
7247                 PSU_DDR_PHY_ACBDLR8_RESERVED_23_22                                              0x0
7248
7249                 Delay select for the BDL on Address A[10].
7250                 PSU_DDR_PHY_ACBDLR8_A10BD                                                       0x0
7251
7252                 Reserved. Return zeroes on reads.
7253                 PSU_DDR_PHY_ACBDLR8_RESERVED_15_14                                              0x0
7254
7255                 Delay select for the BDL on Address A[9].
7256                 PSU_DDR_PHY_ACBDLR8_A09BD                                                       0x0
7257
7258                 Reserved. Return zeroes on reads.
7259                 PSU_DDR_PHY_ACBDLR8_RESERVED_7_6                                                0x0
7260
7261                 Delay select for the BDL on Address A[8].
7262                 PSU_DDR_PHY_ACBDLR8_A08BD                                                       0x0
7263
7264                 AC Bit Delay Line Register 8
7265                 (OFFSET, MASK, VALUE)      (0XFD080560, 0xFFFFFFFFU ,0x00000000U)
7266                 RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK |  0 );
7267
7268                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
7269                         | 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT
7270                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
7271                         | 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT
7272                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
7273                         | 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT
7274                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
7275                         | 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT
7276                         |  0 ) & RegMask); */
7277                 PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7278         /*############################################################################################################################ */
7279
7280                 /*Register : ACBDLR9 @ 0XFD080564</p>
7281
7282                 Reserved. Return zeroes on reads.
7283                 PSU_DDR_PHY_ACBDLR9_RESERVED_31_30                                              0x0
7284
7285                 Delay select for the BDL on Address A[15].
7286                 PSU_DDR_PHY_ACBDLR9_A15BD                                                       0x0
7287
7288                 Reserved. Return zeroes on reads.
7289                 PSU_DDR_PHY_ACBDLR9_RESERVED_23_22                                              0x0
7290
7291                 Delay select for the BDL on Address A[14].
7292                 PSU_DDR_PHY_ACBDLR9_A14BD                                                       0x0
7293
7294                 Reserved. Return zeroes on reads.
7295                 PSU_DDR_PHY_ACBDLR9_RESERVED_15_14                                              0x0
7296
7297                 Delay select for the BDL on Address A[13].
7298                 PSU_DDR_PHY_ACBDLR9_A13BD                                                       0x0
7299
7300                 Reserved. Return zeroes on reads.
7301                 PSU_DDR_PHY_ACBDLR9_RESERVED_7_6                                                0x0
7302
7303                 Delay select for the BDL on Address A[12].
7304                 PSU_DDR_PHY_ACBDLR9_A12BD                                                       0x0
7305
7306                 AC Bit Delay Line Register 9
7307                 (OFFSET, MASK, VALUE)      (0XFD080564, 0xFFFFFFFFU ,0x00000000U)
7308                 RegMask = (DDR_PHY_ACBDLR9_RESERVED_31_30_MASK | DDR_PHY_ACBDLR9_A15BD_MASK | DDR_PHY_ACBDLR9_RESERVED_23_22_MASK | DDR_PHY_ACBDLR9_A14BD_MASK | DDR_PHY_ACBDLR9_RESERVED_15_14_MASK | DDR_PHY_ACBDLR9_A13BD_MASK | DDR_PHY_ACBDLR9_RESERVED_7_6_MASK | DDR_PHY_ACBDLR9_A12BD_MASK |  0 );
7309
7310                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
7311                         | 0x00000000U << DDR_PHY_ACBDLR9_A15BD_SHIFT
7312                         | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
7313                         | 0x00000000U << DDR_PHY_ACBDLR9_A14BD_SHIFT
7314                         | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
7315                         | 0x00000000U << DDR_PHY_ACBDLR9_A13BD_SHIFT
7316                         | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
7317                         | 0x00000000U << DDR_PHY_ACBDLR9_A12BD_SHIFT
7318                         |  0 ) & RegMask); */
7319                 PSU_Mask_Write (DDR_PHY_ACBDLR9_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7320         /*############################################################################################################################ */
7321
7322                 /*Register : ZQCR @ 0XFD080680</p>
7323
7324                 Reserved. Return zeroes on reads.
7325                 PSU_DDR_PHY_ZQCR_RESERVED_31_26                                                 0x0
7326
7327                 ZQ VREF Range
7328                 PSU_DDR_PHY_ZQCR_ZQREFISELRANGE                                                 0x0
7329
7330                 Programmable Wait for Frequency B
7331                 PSU_DDR_PHY_ZQCR_PGWAIT_FRQB                                                    0x11
7332
7333                 Programmable Wait for Frequency A
7334                 PSU_DDR_PHY_ZQCR_PGWAIT_FRQA                                                    0x11
7335
7336                 ZQ VREF Pad Enable
7337                 PSU_DDR_PHY_ZQCR_ZQREFPEN                                                       0x0
7338
7339                 ZQ Internal VREF Enable
7340                 PSU_DDR_PHY_ZQCR_ZQREFIEN                                                       0x1
7341
7342                 Choice of termination mode
7343                 PSU_DDR_PHY_ZQCR_ODT_MODE                                                       0x1
7344
7345                 Force ZCAL VT update
7346                 PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE                                           0x0
7347
7348                 IO VT Drift Limit
7349                 PSU_DDR_PHY_ZQCR_IODLMT                                                         0x2
7350
7351                 Averaging algorithm enable, if set, enables averaging algorithm
7352                 PSU_DDR_PHY_ZQCR_AVGEN                                                          0x1
7353
7354                 Maximum number of averaging rounds to be used by averaging algorithm
7355                 PSU_DDR_PHY_ZQCR_AVGMAX                                                         0x2
7356
7357                 ZQ Calibration Type
7358                 PSU_DDR_PHY_ZQCR_ZCALT                                                          0x0
7359
7360                 ZQ Power Down
7361                 PSU_DDR_PHY_ZQCR_ZQPD                                                           0x0
7362
7363                 ZQ Impedance Control Register
7364                 (OFFSET, MASK, VALUE)      (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U)
7365                 RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK |  0 );
7366
7367                 RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
7368                         | 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
7369                         | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
7370                         | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
7371                         | 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT
7372                         | 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT
7373                         | 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT
7374                         | 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
7375                         | 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT
7376                         | 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT
7377                         | 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT
7378                         | 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT
7379                         | 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT
7380                         |  0 ) & RegMask); */
7381                 PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U);
7382         /*############################################################################################################################ */
7383
7384                 /*Register : ZQ0PR0 @ 0XFD080684</p>
7385
7386                 Pull-down drive strength ZCTRL over-ride enable
7387                 PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN                                                  0x0
7388
7389                 Pull-up drive strength ZCTRL over-ride enable
7390                 PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN                                                  0x0
7391
7392                 Pull-down termination ZCTRL over-ride enable
7393                 PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN                                                  0x0
7394
7395                 Pull-up termination ZCTRL over-ride enable
7396                 PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN                                                  0x0
7397
7398                 Calibration segment bypass
7399                 PSU_DDR_PHY_ZQ0PR0_ZSEGBYP                                                      0x0
7400
7401                 VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
7402                 PSU_DDR_PHY_ZQ0PR0_ZLE_MODE                                                     0x0
7403
7404                 Termination adjustment
7405                 PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST                                                   0x0
7406
7407                 Pulldown drive strength adjustment
7408                 PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST                                                0x0
7409
7410                 Pullup drive strength adjustment
7411                 PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST                                                0x0
7412
7413                 DRAM Impedance Divide Ratio
7414                 PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT                                               0x7
7415
7416                 HOST Impedance Divide Ratio
7417                 PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT                                               0x7
7418
7419                 Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
7420                 PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD                                            0xd
7421
7422                 Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
7423                 PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU                                            0xd
7424
7425                 ZQ n Impedance Control Program Register 0
7426                 (OFFSET, MASK, VALUE)      (0XFD080684, 0xFFFFFFFFU ,0x000077DDU)
7427                 RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
7428
7429                 RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
7430                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
7431                         | 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
7432                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
7433                         | 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
7434                         | 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
7435                         | 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
7436                         | 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
7437                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
7438                         | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
7439                         | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
7440                         | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
7441                         | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
7442                         |  0 ) & RegMask); */
7443                 PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU);
7444         /*############################################################################################################################ */
7445
7446                 /*Register : ZQ0OR0 @ 0XFD080694</p>
7447
7448                 Reserved. Return zeros on reads.
7449                 PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26                                               0x0
7450
7451                 Override value for the pull-up output impedance
7452                 PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD                                            0x1e1
7453
7454                 Reserved. Return zeros on reads.
7455                 PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10                                               0x0
7456
7457                 Override value for the pull-down output impedance
7458                 PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD                                            0x210
7459
7460                 ZQ n Impedance Control Override Data Register 0
7461                 (OFFSET, MASK, VALUE)      (0XFD080694, 0xFFFFFFFFU ,0x01E10210U)
7462                 RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK |  0 );
7463
7464                 RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
7465                         | 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
7466                         | 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
7467                         | 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
7468                         |  0 ) & RegMask); */
7469                 PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U);
7470         /*############################################################################################################################ */
7471
7472                 /*Register : ZQ0OR1 @ 0XFD080698</p>
7473
7474                 Reserved. Return zeros on reads.
7475                 PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26                                               0x0
7476
7477                 Override value for the pull-up termination
7478                 PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD                                            0x1e1
7479
7480                 Reserved. Return zeros on reads.
7481                 PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10                                               0x0
7482
7483                 Override value for the pull-down termination
7484                 PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD                                            0x0
7485
7486                 ZQ n Impedance Control Override Data Register 1
7487                 (OFFSET, MASK, VALUE)      (0XFD080698, 0xFFFFFFFFU ,0x01E10000U)
7488                 RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK |  0 );
7489
7490                 RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
7491                         | 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
7492                         | 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
7493                         | 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
7494                         |  0 ) & RegMask); */
7495                 PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U);
7496         /*############################################################################################################################ */
7497
7498                 /*Register : ZQ1PR0 @ 0XFD0806A4</p>
7499
7500                 Pull-down drive strength ZCTRL over-ride enable
7501                 PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN                                                  0x0
7502
7503                 Pull-up drive strength ZCTRL over-ride enable
7504                 PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN                                                  0x0
7505
7506                 Pull-down termination ZCTRL over-ride enable
7507                 PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN                                                  0x0
7508
7509                 Pull-up termination ZCTRL over-ride enable
7510                 PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN                                                  0x0
7511
7512                 Calibration segment bypass
7513                 PSU_DDR_PHY_ZQ1PR0_ZSEGBYP                                                      0x0
7514
7515                 VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
7516                 PSU_DDR_PHY_ZQ1PR0_ZLE_MODE                                                     0x0
7517
7518                 Termination adjustment
7519                 PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST                                                   0x0
7520
7521                 Pulldown drive strength adjustment
7522                 PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST                                                0x1
7523
7524                 Pullup drive strength adjustment
7525                 PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST                                                0x0
7526
7527                 DRAM Impedance Divide Ratio
7528                 PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT                                               0x7
7529
7530                 HOST Impedance Divide Ratio
7531                 PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT                                               0xb
7532
7533                 Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
7534                 PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD                                            0xd
7535
7536                 Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
7537                 PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU                                            0xb
7538
7539                 ZQ n Impedance Control Program Register 0
7540                 (OFFSET, MASK, VALUE)      (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU)
7541                 RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
7542
7543                 RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
7544                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
7545                         | 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
7546                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
7547                         | 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
7548                         | 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
7549                         | 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
7550                         | 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
7551                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
7552                         | 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
7553                         | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
7554                         | 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
7555                         | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
7556                         |  0 ) & RegMask); */
7557                 PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU);
7558         /*############################################################################################################################ */
7559
7560                 /*Register : DX0GCR0 @ 0XFD080700</p>
7561
7562                 Calibration Bypass
7563                 PSU_DDR_PHY_DX0GCR0_CALBYP                                                      0x0
7564
7565                 Master Delay Line Enable
7566                 PSU_DDR_PHY_DX0GCR0_MDLEN                                                       0x1
7567
7568                 Configurable ODT(TE) Phase Shift
7569                 PSU_DDR_PHY_DX0GCR0_CODTSHFT                                                    0x0
7570
7571                 DQS Duty Cycle Correction
7572                 PSU_DDR_PHY_DX0GCR0_DQSDCC                                                      0x0
7573
7574                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
7575                 PSU_DDR_PHY_DX0GCR0_RDDLY                                                       0x8
7576
7577                 Reserved. Return zeroes on reads.
7578                 PSU_DDR_PHY_DX0GCR0_RESERVED_19_14                                              0x0
7579
7580                 DQSNSE Power Down Receiver
7581                 PSU_DDR_PHY_DX0GCR0_DQSNSEPDR                                                   0x0
7582
7583                 DQSSE Power Down Receiver
7584                 PSU_DDR_PHY_DX0GCR0_DQSSEPDR                                                    0x0
7585
7586                 RTT On Additive Latency
7587                 PSU_DDR_PHY_DX0GCR0_RTTOAL                                                      0x0
7588
7589                 RTT Output Hold
7590                 PSU_DDR_PHY_DX0GCR0_RTTOH                                                       0x3
7591
7592                 Configurable PDR Phase Shift
7593                 PSU_DDR_PHY_DX0GCR0_CPDRSHFT                                                    0x0
7594
7595                 DQSR Power Down
7596                 PSU_DDR_PHY_DX0GCR0_DQSRPD                                                      0x0
7597
7598                 DQSG Power Down Receiver
7599                 PSU_DDR_PHY_DX0GCR0_DQSGPDR                                                     0x0
7600
7601                 Reserved. Return zeroes on reads.
7602                 PSU_DDR_PHY_DX0GCR0_RESERVED_4                                                  0x0
7603
7604                 DQSG On-Die Termination
7605                 PSU_DDR_PHY_DX0GCR0_DQSGODT                                                     0x0
7606
7607                 DQSG Output Enable
7608                 PSU_DDR_PHY_DX0GCR0_DQSGOE                                                      0x1
7609
7610                 Reserved. Return zeroes on reads.
7611                 PSU_DDR_PHY_DX0GCR0_RESERVED_1_0                                                0x0
7612
7613                 DATX8 n General Configuration Register 0
7614                 (OFFSET, MASK, VALUE)      (0XFD080700, 0xFFFFFFFFU ,0x40800604U)
7615                 RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK |  0 );
7616
7617                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT
7618                         | 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT
7619                         | 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
7620                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT
7621                         | 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT
7622                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
7623                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
7624                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
7625                         | 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT
7626                         | 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT
7627                         | 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
7628                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT
7629                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
7630                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
7631                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT
7632                         | 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT
7633                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
7634                         |  0 ) & RegMask); */
7635                 PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
7636         /*############################################################################################################################ */
7637
7638                 /*Register : DX0GCR4 @ 0XFD080710</p>
7639
7640                 Byte lane VREF IOM (Used only by D4MU IOs)
7641                 PSU_DDR_PHY_DX0GCR4_RESERVED_31_29                                              0x0
7642
7643                 Byte Lane VREF Pad Enable
7644                 PSU_DDR_PHY_DX0GCR4_DXREFPEN                                                    0x0
7645
7646                 Byte Lane Internal VREF Enable
7647                 PSU_DDR_PHY_DX0GCR4_DXREFEEN                                                    0x3
7648
7649                 Byte Lane Single-End VREF Enable
7650                 PSU_DDR_PHY_DX0GCR4_DXREFSEN                                                    0x1
7651
7652                 Reserved. Returns zeros on reads.
7653                 PSU_DDR_PHY_DX0GCR4_RESERVED_24                                                 0x0
7654
7655                 External VREF generator REFSEL range select
7656                 PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE                                              0x0
7657
7658                 Byte Lane External VREF Select
7659                 PSU_DDR_PHY_DX0GCR4_DXREFESEL                                                   0x0
7660
7661                 Single ended VREF generator REFSEL range select
7662                 PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE                                              0x1
7663
7664                 Byte Lane Single-End VREF Select
7665                 PSU_DDR_PHY_DX0GCR4_DXREFSSEL                                                   0x30
7666
7667                 Reserved. Returns zeros on reads.
7668                 PSU_DDR_PHY_DX0GCR4_RESERVED_7_6                                                0x0
7669
7670                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7671                 PSU_DDR_PHY_DX0GCR4_DXREFIEN                                                    0xf
7672
7673                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7674                 PSU_DDR_PHY_DX0GCR4_DXREFIMON                                                   0x0
7675
7676                 DATX8 n General Configuration Register 4
7677                 (OFFSET, MASK, VALUE)      (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU)
7678                 RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK |  0 );
7679
7680                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
7681                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
7682                         | 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
7683                         | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
7684                         | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
7685                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
7686                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
7687                         | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
7688                         | 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
7689                         | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
7690                         | 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
7691                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
7692                         |  0 ) & RegMask); */
7693                 PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
7694         /*############################################################################################################################ */
7695
7696                 /*Register : DX0GCR5 @ 0XFD080714</p>
7697
7698                 Reserved. Returns zeros on reads.
7699                 PSU_DDR_PHY_DX0GCR5_RESERVED_31                                                 0x0
7700
7701                 Byte Lane internal VREF Select for Rank 3
7702                 PSU_DDR_PHY_DX0GCR5_DXREFISELR3                                                 0x9
7703
7704                 Reserved. Returns zeros on reads.
7705                 PSU_DDR_PHY_DX0GCR5_RESERVED_23                                                 0x0
7706
7707                 Byte Lane internal VREF Select for Rank 2
7708                 PSU_DDR_PHY_DX0GCR5_DXREFISELR2                                                 0x9
7709
7710                 Reserved. Returns zeros on reads.
7711                 PSU_DDR_PHY_DX0GCR5_RESERVED_15                                                 0x0
7712
7713                 Byte Lane internal VREF Select for Rank 1
7714                 PSU_DDR_PHY_DX0GCR5_DXREFISELR1                                                 0x4f
7715
7716                 Reserved. Returns zeros on reads.
7717                 PSU_DDR_PHY_DX0GCR5_RESERVED_7                                                  0x0
7718
7719                 Byte Lane internal VREF Select for Rank 0
7720                 PSU_DDR_PHY_DX0GCR5_DXREFISELR0                                                 0x4f
7721
7722                 DATX8 n General Configuration Register 5
7723                 (OFFSET, MASK, VALUE)      (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU)
7724                 RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK |  0 );
7725
7726                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
7727                         | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
7728                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
7729                         | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
7730                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
7731                         | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
7732                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
7733                         | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
7734                         |  0 ) & RegMask); */
7735                 PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
7736         /*############################################################################################################################ */
7737
7738                 /*Register : DX0GCR6 @ 0XFD080718</p>
7739
7740                 Reserved. Returns zeros on reads.
7741                 PSU_DDR_PHY_DX0GCR6_RESERVED_31_30                                              0x0
7742
7743                 DRAM DQ VREF Select for Rank3
7744                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR3                                                  0x9
7745
7746                 Reserved. Returns zeros on reads.
7747                 PSU_DDR_PHY_DX0GCR6_RESERVED_23_22                                              0x0
7748
7749                 DRAM DQ VREF Select for Rank2
7750                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR2                                                  0x9
7751
7752                 Reserved. Returns zeros on reads.
7753                 PSU_DDR_PHY_DX0GCR6_RESERVED_15_14                                              0x0
7754
7755                 DRAM DQ VREF Select for Rank1
7756                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR1                                                  0x2b
7757
7758                 Reserved. Returns zeros on reads.
7759                 PSU_DDR_PHY_DX0GCR6_RESERVED_7_6                                                0x0
7760
7761                 DRAM DQ VREF Select for Rank0
7762                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR0                                                  0x2b
7763
7764                 DATX8 n General Configuration Register 6
7765                 (OFFSET, MASK, VALUE)      (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU)
7766                 RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK |  0 );
7767
7768                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
7769                         | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
7770                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
7771                         | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
7772                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
7773                         | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
7774                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
7775                         | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
7776                         |  0 ) & RegMask); */
7777                 PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
7778         /*############################################################################################################################ */
7779
7780                 /*Register : DX0LCDLR2 @ 0XFD080788</p>
7781
7782                 Reserved. Return zeroes on reads.
7783                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25                                            0x0
7784
7785                 Reserved. Caution, do not write to this register field.
7786                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16                                            0x0
7787
7788                 Reserved. Return zeroes on reads.
7789                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9                                             0x0
7790
7791                 Read DQS Gating Delay
7792                 PSU_DDR_PHY_DX0LCDLR2_DQSGD                                                     0x0
7793
7794                 DATX8 n Local Calibrated Delay Line Register 2
7795                 (OFFSET, MASK, VALUE)      (0XFD080788, 0xFFFFFFFFU ,0x00000000U)
7796                 RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK |  0 );
7797
7798                 RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT
7799                         | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT
7800                         | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT
7801                         | 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT
7802                         |  0 ) & RegMask); */
7803                 PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7804         /*############################################################################################################################ */
7805
7806                 /*Register : DX0GTR0 @ 0XFD0807C0</p>
7807
7808                 Reserved. Return zeroes on reads.
7809                 PSU_DDR_PHY_DX0GTR0_RESERVED_31_24                                              0x0
7810
7811                 DQ Write Path Latency Pipeline
7812                 PSU_DDR_PHY_DX0GTR0_WDQSL                                                       0x0
7813
7814                 Reserved. Caution, do not write to this register field.
7815                 PSU_DDR_PHY_DX0GTR0_RESERVED_23_20                                              0x0
7816
7817                 Write Leveling System Latency
7818                 PSU_DDR_PHY_DX0GTR0_WLSL                                                        0x2
7819
7820                 Reserved. Return zeroes on reads.
7821                 PSU_DDR_PHY_DX0GTR0_RESERVED_15_13                                              0x0
7822
7823                 Reserved. Caution, do not write to this register field.
7824                 PSU_DDR_PHY_DX0GTR0_RESERVED_12_8                                               0x0
7825
7826                 Reserved. Return zeroes on reads.
7827                 PSU_DDR_PHY_DX0GTR0_RESERVED_7_5                                                0x0
7828
7829                 DQS Gating System Latency
7830                 PSU_DDR_PHY_DX0GTR0_DGSL                                                        0x0
7831
7832                 DATX8 n General Timing Register 0
7833                 (OFFSET, MASK, VALUE)      (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U)
7834                 RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK |  0 );
7835
7836                 RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT
7837                         | 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT
7838                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT
7839                         | 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT
7840                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT
7841                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT
7842                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT
7843                         | 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT
7844                         |  0 ) & RegMask); */
7845                 PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
7846         /*############################################################################################################################ */
7847
7848                 /*Register : DX1GCR0 @ 0XFD080800</p>
7849
7850                 Calibration Bypass
7851                 PSU_DDR_PHY_DX1GCR0_CALBYP                                                      0x0
7852
7853                 Master Delay Line Enable
7854                 PSU_DDR_PHY_DX1GCR0_MDLEN                                                       0x1
7855
7856                 Configurable ODT(TE) Phase Shift
7857                 PSU_DDR_PHY_DX1GCR0_CODTSHFT                                                    0x0
7858
7859                 DQS Duty Cycle Correction
7860                 PSU_DDR_PHY_DX1GCR0_DQSDCC                                                      0x0
7861
7862                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
7863                 PSU_DDR_PHY_DX1GCR0_RDDLY                                                       0x8
7864
7865                 Reserved. Return zeroes on reads.
7866                 PSU_DDR_PHY_DX1GCR0_RESERVED_19_14                                              0x0
7867
7868                 DQSNSE Power Down Receiver
7869                 PSU_DDR_PHY_DX1GCR0_DQSNSEPDR                                                   0x0
7870
7871                 DQSSE Power Down Receiver
7872                 PSU_DDR_PHY_DX1GCR0_DQSSEPDR                                                    0x0
7873
7874                 RTT On Additive Latency
7875                 PSU_DDR_PHY_DX1GCR0_RTTOAL                                                      0x0
7876
7877                 RTT Output Hold
7878                 PSU_DDR_PHY_DX1GCR0_RTTOH                                                       0x3
7879
7880                 Configurable PDR Phase Shift
7881                 PSU_DDR_PHY_DX1GCR0_CPDRSHFT                                                    0x0
7882
7883                 DQSR Power Down
7884                 PSU_DDR_PHY_DX1GCR0_DQSRPD                                                      0x0
7885
7886                 DQSG Power Down Receiver
7887                 PSU_DDR_PHY_DX1GCR0_DQSGPDR                                                     0x0
7888
7889                 Reserved. Return zeroes on reads.
7890                 PSU_DDR_PHY_DX1GCR0_RESERVED_4                                                  0x0
7891
7892                 DQSG On-Die Termination
7893                 PSU_DDR_PHY_DX1GCR0_DQSGODT                                                     0x0
7894
7895                 DQSG Output Enable
7896                 PSU_DDR_PHY_DX1GCR0_DQSGOE                                                      0x1
7897
7898                 Reserved. Return zeroes on reads.
7899                 PSU_DDR_PHY_DX1GCR0_RESERVED_1_0                                                0x0
7900
7901                 DATX8 n General Configuration Register 0
7902                 (OFFSET, MASK, VALUE)      (0XFD080800, 0xFFFFFFFFU ,0x40800604U)
7903                 RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK |  0 );
7904
7905                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT
7906                         | 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT
7907                         | 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
7908                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT
7909                         | 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT
7910                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
7911                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
7912                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
7913                         | 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT
7914                         | 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT
7915                         | 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
7916                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT
7917                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
7918                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
7919                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT
7920                         | 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT
7921                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
7922                         |  0 ) & RegMask); */
7923                 PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
7924         /*############################################################################################################################ */
7925
7926                 /*Register : DX1GCR4 @ 0XFD080810</p>
7927
7928                 Byte lane VREF IOM (Used only by D4MU IOs)
7929                 PSU_DDR_PHY_DX1GCR4_RESERVED_31_29                                              0x0
7930
7931                 Byte Lane VREF Pad Enable
7932                 PSU_DDR_PHY_DX1GCR4_DXREFPEN                                                    0x0
7933
7934                 Byte Lane Internal VREF Enable
7935                 PSU_DDR_PHY_DX1GCR4_DXREFEEN                                                    0x3
7936
7937                 Byte Lane Single-End VREF Enable
7938                 PSU_DDR_PHY_DX1GCR4_DXREFSEN                                                    0x1
7939
7940                 Reserved. Returns zeros on reads.
7941                 PSU_DDR_PHY_DX1GCR4_RESERVED_24                                                 0x0
7942
7943                 External VREF generator REFSEL range select
7944                 PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE                                              0x0
7945
7946                 Byte Lane External VREF Select
7947                 PSU_DDR_PHY_DX1GCR4_DXREFESEL                                                   0x0
7948
7949                 Single ended VREF generator REFSEL range select
7950                 PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE                                              0x1
7951
7952                 Byte Lane Single-End VREF Select
7953                 PSU_DDR_PHY_DX1GCR4_DXREFSSEL                                                   0x30
7954
7955                 Reserved. Returns zeros on reads.
7956                 PSU_DDR_PHY_DX1GCR4_RESERVED_7_6                                                0x0
7957
7958                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7959                 PSU_DDR_PHY_DX1GCR4_DXREFIEN                                                    0xf
7960
7961                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7962                 PSU_DDR_PHY_DX1GCR4_DXREFIMON                                                   0x0
7963
7964                 DATX8 n General Configuration Register 4
7965                 (OFFSET, MASK, VALUE)      (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU)
7966                 RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK |  0 );
7967
7968                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
7969                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
7970                         | 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
7971                         | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
7972                         | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
7973                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
7974                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
7975                         | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
7976                         | 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
7977                         | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
7978                         | 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
7979                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
7980                         |  0 ) & RegMask); */
7981                 PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
7982         /*############################################################################################################################ */
7983
7984                 /*Register : DX1GCR5 @ 0XFD080814</p>
7985
7986                 Reserved. Returns zeros on reads.
7987                 PSU_DDR_PHY_DX1GCR5_RESERVED_31                                                 0x0
7988
7989                 Byte Lane internal VREF Select for Rank 3
7990                 PSU_DDR_PHY_DX1GCR5_DXREFISELR3                                                 0x9
7991
7992                 Reserved. Returns zeros on reads.
7993                 PSU_DDR_PHY_DX1GCR5_RESERVED_23                                                 0x0
7994
7995                 Byte Lane internal VREF Select for Rank 2
7996                 PSU_DDR_PHY_DX1GCR5_DXREFISELR2                                                 0x9
7997
7998                 Reserved. Returns zeros on reads.
7999                 PSU_DDR_PHY_DX1GCR5_RESERVED_15                                                 0x0
8000
8001                 Byte Lane internal VREF Select for Rank 1
8002                 PSU_DDR_PHY_DX1GCR5_DXREFISELR1                                                 0x4f
8003
8004                 Reserved. Returns zeros on reads.
8005                 PSU_DDR_PHY_DX1GCR5_RESERVED_7                                                  0x0
8006
8007                 Byte Lane internal VREF Select for Rank 0
8008                 PSU_DDR_PHY_DX1GCR5_DXREFISELR0                                                 0x4f
8009
8010                 DATX8 n General Configuration Register 5
8011                 (OFFSET, MASK, VALUE)      (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU)
8012                 RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK |  0 );
8013
8014                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
8015                         | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
8016                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
8017                         | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
8018                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
8019                         | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
8020                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
8021                         | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
8022                         |  0 ) & RegMask); */
8023                 PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
8024         /*############################################################################################################################ */
8025
8026                 /*Register : DX1GCR6 @ 0XFD080818</p>
8027
8028                 Reserved. Returns zeros on reads.
8029                 PSU_DDR_PHY_DX1GCR6_RESERVED_31_30                                              0x0
8030
8031                 DRAM DQ VREF Select for Rank3
8032                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR3                                                  0x9
8033
8034                 Reserved. Returns zeros on reads.
8035                 PSU_DDR_PHY_DX1GCR6_RESERVED_23_22                                              0x0
8036
8037                 DRAM DQ VREF Select for Rank2
8038                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR2                                                  0x9
8039
8040                 Reserved. Returns zeros on reads.
8041                 PSU_DDR_PHY_DX1GCR6_RESERVED_15_14                                              0x0
8042
8043                 DRAM DQ VREF Select for Rank1
8044                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR1                                                  0x2b
8045
8046                 Reserved. Returns zeros on reads.
8047                 PSU_DDR_PHY_DX1GCR6_RESERVED_7_6                                                0x0
8048
8049                 DRAM DQ VREF Select for Rank0
8050                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR0                                                  0x2b
8051
8052                 DATX8 n General Configuration Register 6
8053                 (OFFSET, MASK, VALUE)      (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU)
8054                 RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK |  0 );
8055
8056                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
8057                         | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
8058                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
8059                         | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
8060                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
8061                         | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
8062                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
8063                         | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
8064                         |  0 ) & RegMask); */
8065                 PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8066         /*############################################################################################################################ */
8067
8068                 /*Register : DX1LCDLR2 @ 0XFD080888</p>
8069
8070                 Reserved. Return zeroes on reads.
8071                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25                                            0x0
8072
8073                 Reserved. Caution, do not write to this register field.
8074                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16                                            0x0
8075
8076                 Reserved. Return zeroes on reads.
8077                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9                                             0x0
8078
8079                 Read DQS Gating Delay
8080                 PSU_DDR_PHY_DX1LCDLR2_DQSGD                                                     0x0
8081
8082                 DATX8 n Local Calibrated Delay Line Register 2
8083                 (OFFSET, MASK, VALUE)      (0XFD080888, 0xFFFFFFFFU ,0x00000000U)
8084                 RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK |  0 );
8085
8086                 RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT
8087                         | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT
8088                         | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT
8089                         | 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT
8090                         |  0 ) & RegMask); */
8091                 PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8092         /*############################################################################################################################ */
8093
8094                 /*Register : DX1GTR0 @ 0XFD0808C0</p>
8095
8096                 Reserved. Return zeroes on reads.
8097                 PSU_DDR_PHY_DX1GTR0_RESERVED_31_24                                              0x0
8098
8099                 DQ Write Path Latency Pipeline
8100                 PSU_DDR_PHY_DX1GTR0_WDQSL                                                       0x0
8101
8102                 Reserved. Caution, do not write to this register field.
8103                 PSU_DDR_PHY_DX1GTR0_RESERVED_23_20                                              0x0
8104
8105                 Write Leveling System Latency
8106                 PSU_DDR_PHY_DX1GTR0_WLSL                                                        0x2
8107
8108                 Reserved. Return zeroes on reads.
8109                 PSU_DDR_PHY_DX1GTR0_RESERVED_15_13                                              0x0
8110
8111                 Reserved. Caution, do not write to this register field.
8112                 PSU_DDR_PHY_DX1GTR0_RESERVED_12_8                                               0x0
8113
8114                 Reserved. Return zeroes on reads.
8115                 PSU_DDR_PHY_DX1GTR0_RESERVED_7_5                                                0x0
8116
8117                 DQS Gating System Latency
8118                 PSU_DDR_PHY_DX1GTR0_DGSL                                                        0x0
8119
8120                 DATX8 n General Timing Register 0
8121                 (OFFSET, MASK, VALUE)      (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U)
8122                 RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK |  0 );
8123
8124                 RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT
8125                         | 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT
8126                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT
8127                         | 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT
8128                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT
8129                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT
8130                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT
8131                         | 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT
8132                         |  0 ) & RegMask); */
8133                 PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8134         /*############################################################################################################################ */
8135
8136                 /*Register : DX2GCR0 @ 0XFD080900</p>
8137
8138                 Calibration Bypass
8139                 PSU_DDR_PHY_DX2GCR0_CALBYP                                                      0x0
8140
8141                 Master Delay Line Enable
8142                 PSU_DDR_PHY_DX2GCR0_MDLEN                                                       0x1
8143
8144                 Configurable ODT(TE) Phase Shift
8145                 PSU_DDR_PHY_DX2GCR0_CODTSHFT                                                    0x0
8146
8147                 DQS Duty Cycle Correction
8148                 PSU_DDR_PHY_DX2GCR0_DQSDCC                                                      0x0
8149
8150                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8151                 PSU_DDR_PHY_DX2GCR0_RDDLY                                                       0x8
8152
8153                 Reserved. Return zeroes on reads.
8154                 PSU_DDR_PHY_DX2GCR0_RESERVED_19_14                                              0x0
8155
8156                 DQSNSE Power Down Receiver
8157                 PSU_DDR_PHY_DX2GCR0_DQSNSEPDR                                                   0x0
8158
8159                 DQSSE Power Down Receiver
8160                 PSU_DDR_PHY_DX2GCR0_DQSSEPDR                                                    0x0
8161
8162                 RTT On Additive Latency
8163                 PSU_DDR_PHY_DX2GCR0_RTTOAL                                                      0x0
8164
8165                 RTT Output Hold
8166                 PSU_DDR_PHY_DX2GCR0_RTTOH                                                       0x3
8167
8168                 Configurable PDR Phase Shift
8169                 PSU_DDR_PHY_DX2GCR0_CPDRSHFT                                                    0x0
8170
8171                 DQSR Power Down
8172                 PSU_DDR_PHY_DX2GCR0_DQSRPD                                                      0x0
8173
8174                 DQSG Power Down Receiver
8175                 PSU_DDR_PHY_DX2GCR0_DQSGPDR                                                     0x0
8176
8177                 Reserved. Return zeroes on reads.
8178                 PSU_DDR_PHY_DX2GCR0_RESERVED_4                                                  0x0
8179
8180                 DQSG On-Die Termination
8181                 PSU_DDR_PHY_DX2GCR0_DQSGODT                                                     0x0
8182
8183                 DQSG Output Enable
8184                 PSU_DDR_PHY_DX2GCR0_DQSGOE                                                      0x1
8185
8186                 Reserved. Return zeroes on reads.
8187                 PSU_DDR_PHY_DX2GCR0_RESERVED_1_0                                                0x0
8188
8189                 DATX8 n General Configuration Register 0
8190                 (OFFSET, MASK, VALUE)      (0XFD080900, 0xFFFFFFFFU ,0x40800604U)
8191                 RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK |  0 );
8192
8193                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT
8194                         | 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT
8195                         | 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
8196                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT
8197                         | 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT
8198                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
8199                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
8200                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
8201                         | 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT
8202                         | 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT
8203                         | 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
8204                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT
8205                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
8206                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
8207                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT
8208                         | 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT
8209                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
8210                         |  0 ) & RegMask); */
8211                 PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8212         /*############################################################################################################################ */
8213
8214                 /*Register : DX2GCR1 @ 0XFD080904</p>
8215
8216                 Enables the PDR mode for DQ[7:0]
8217                 PSU_DDR_PHY_DX2GCR1_DXPDRMODE                                                   0x0
8218
8219                 Reserved. Returns zeroes on reads.
8220                 PSU_DDR_PHY_DX2GCR1_RESERVED_15                                                 0x0
8221
8222                 Select the delayed or non-delayed read data strobe #
8223                 PSU_DDR_PHY_DX2GCR1_QSNSEL                                                      0x1
8224
8225                 Select the delayed or non-delayed read data strobe
8226                 PSU_DDR_PHY_DX2GCR1_QSSEL                                                       0x1
8227
8228                 Enables Read Data Strobe in a byte lane
8229                 PSU_DDR_PHY_DX2GCR1_OEEN                                                        0x1
8230
8231                 Enables PDR in a byte lane
8232                 PSU_DDR_PHY_DX2GCR1_PDREN                                                       0x1
8233
8234                 Enables ODT/TE in a byte lane
8235                 PSU_DDR_PHY_DX2GCR1_TEEN                                                        0x1
8236
8237                 Enables Write Data strobe in a byte lane
8238                 PSU_DDR_PHY_DX2GCR1_DSEN                                                        0x1
8239
8240                 Enables DM pin in a byte lane
8241                 PSU_DDR_PHY_DX2GCR1_DMEN                                                        0x1
8242
8243                 Enables DQ corresponding to each bit in a byte
8244                 PSU_DDR_PHY_DX2GCR1_DQEN                                                        0xff
8245
8246                 DATX8 n General Configuration Register 1
8247                 (OFFSET, MASK, VALUE)      (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU)
8248                 RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK |  0 );
8249
8250                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
8251                         | 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
8252                         | 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT
8253                         | 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT
8254                         | 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT
8255                         | 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT
8256                         | 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT
8257                         | 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT
8258                         | 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT
8259                         | 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT
8260                         |  0 ) & RegMask); */
8261                 PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
8262         /*############################################################################################################################ */
8263
8264                 /*Register : DX2GCR4 @ 0XFD080910</p>
8265
8266                 Byte lane VREF IOM (Used only by D4MU IOs)
8267                 PSU_DDR_PHY_DX2GCR4_RESERVED_31_29                                              0x0
8268
8269                 Byte Lane VREF Pad Enable
8270                 PSU_DDR_PHY_DX2GCR4_DXREFPEN                                                    0x0
8271
8272                 Byte Lane Internal VREF Enable
8273                 PSU_DDR_PHY_DX2GCR4_DXREFEEN                                                    0x3
8274
8275                 Byte Lane Single-End VREF Enable
8276                 PSU_DDR_PHY_DX2GCR4_DXREFSEN                                                    0x1
8277
8278                 Reserved. Returns zeros on reads.
8279                 PSU_DDR_PHY_DX2GCR4_RESERVED_24                                                 0x0
8280
8281                 External VREF generator REFSEL range select
8282                 PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE                                              0x0
8283
8284                 Byte Lane External VREF Select
8285                 PSU_DDR_PHY_DX2GCR4_DXREFESEL                                                   0x0
8286
8287                 Single ended VREF generator REFSEL range select
8288                 PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE                                              0x1
8289
8290                 Byte Lane Single-End VREF Select
8291                 PSU_DDR_PHY_DX2GCR4_DXREFSSEL                                                   0x30
8292
8293                 Reserved. Returns zeros on reads.
8294                 PSU_DDR_PHY_DX2GCR4_RESERVED_7_6                                                0x0
8295
8296                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8297                 PSU_DDR_PHY_DX2GCR4_DXREFIEN                                                    0xf
8298
8299                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8300                 PSU_DDR_PHY_DX2GCR4_DXREFIMON                                                   0x0
8301
8302                 DATX8 n General Configuration Register 4
8303                 (OFFSET, MASK, VALUE)      (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU)
8304                 RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK |  0 );
8305
8306                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
8307                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
8308                         | 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
8309                         | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
8310                         | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
8311                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
8312                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
8313                         | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
8314                         | 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
8315                         | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
8316                         | 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
8317                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
8318                         |  0 ) & RegMask); */
8319                 PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8320         /*############################################################################################################################ */
8321
8322                 /*Register : DX2GCR5 @ 0XFD080914</p>
8323
8324                 Reserved. Returns zeros on reads.
8325                 PSU_DDR_PHY_DX2GCR5_RESERVED_31                                                 0x0
8326
8327                 Byte Lane internal VREF Select for Rank 3
8328                 PSU_DDR_PHY_DX2GCR5_DXREFISELR3                                                 0x9
8329
8330                 Reserved. Returns zeros on reads.
8331                 PSU_DDR_PHY_DX2GCR5_RESERVED_23                                                 0x0
8332
8333                 Byte Lane internal VREF Select for Rank 2
8334                 PSU_DDR_PHY_DX2GCR5_DXREFISELR2                                                 0x9
8335
8336                 Reserved. Returns zeros on reads.
8337                 PSU_DDR_PHY_DX2GCR5_RESERVED_15                                                 0x0
8338
8339                 Byte Lane internal VREF Select for Rank 1
8340                 PSU_DDR_PHY_DX2GCR5_DXREFISELR1                                                 0x4f
8341
8342                 Reserved. Returns zeros on reads.
8343                 PSU_DDR_PHY_DX2GCR5_RESERVED_7                                                  0x0
8344
8345                 Byte Lane internal VREF Select for Rank 0
8346                 PSU_DDR_PHY_DX2GCR5_DXREFISELR0                                                 0x4f
8347
8348                 DATX8 n General Configuration Register 5
8349                 (OFFSET, MASK, VALUE)      (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU)
8350                 RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK |  0 );
8351
8352                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
8353                         | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
8354                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
8355                         | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
8356                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
8357                         | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
8358                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
8359                         | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
8360                         |  0 ) & RegMask); */
8361                 PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
8362         /*############################################################################################################################ */
8363
8364                 /*Register : DX2GCR6 @ 0XFD080918</p>
8365
8366                 Reserved. Returns zeros on reads.
8367                 PSU_DDR_PHY_DX2GCR6_RESERVED_31_30                                              0x0
8368
8369                 DRAM DQ VREF Select for Rank3
8370                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR3                                                  0x9
8371
8372                 Reserved. Returns zeros on reads.
8373                 PSU_DDR_PHY_DX2GCR6_RESERVED_23_22                                              0x0
8374
8375                 DRAM DQ VREF Select for Rank2
8376                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR2                                                  0x9
8377
8378                 Reserved. Returns zeros on reads.
8379                 PSU_DDR_PHY_DX2GCR6_RESERVED_15_14                                              0x0
8380
8381                 DRAM DQ VREF Select for Rank1
8382                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR1                                                  0x2b
8383
8384                 Reserved. Returns zeros on reads.
8385                 PSU_DDR_PHY_DX2GCR6_RESERVED_7_6                                                0x0
8386
8387                 DRAM DQ VREF Select for Rank0
8388                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR0                                                  0x2b
8389
8390                 DATX8 n General Configuration Register 6
8391                 (OFFSET, MASK, VALUE)      (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU)
8392                 RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK |  0 );
8393
8394                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
8395                         | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
8396                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
8397                         | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
8398                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
8399                         | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
8400                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
8401                         | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
8402                         |  0 ) & RegMask); */
8403                 PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8404         /*############################################################################################################################ */
8405
8406                 /*Register : DX2LCDLR2 @ 0XFD080988</p>
8407
8408                 Reserved. Return zeroes on reads.
8409                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25                                            0x0
8410
8411                 Reserved. Caution, do not write to this register field.
8412                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16                                            0x0
8413
8414                 Reserved. Return zeroes on reads.
8415                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9                                             0x0
8416
8417                 Read DQS Gating Delay
8418                 PSU_DDR_PHY_DX2LCDLR2_DQSGD                                                     0x0
8419
8420                 DATX8 n Local Calibrated Delay Line Register 2
8421                 (OFFSET, MASK, VALUE)      (0XFD080988, 0xFFFFFFFFU ,0x00000000U)
8422                 RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK |  0 );
8423
8424                 RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT
8425                         | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT
8426                         | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT
8427                         | 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT
8428                         |  0 ) & RegMask); */
8429                 PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8430         /*############################################################################################################################ */
8431
8432                 /*Register : DX2GTR0 @ 0XFD0809C0</p>
8433
8434                 Reserved. Return zeroes on reads.
8435                 PSU_DDR_PHY_DX2GTR0_RESERVED_31_24                                              0x0
8436
8437                 DQ Write Path Latency Pipeline
8438                 PSU_DDR_PHY_DX2GTR0_WDQSL                                                       0x0
8439
8440                 Reserved. Caution, do not write to this register field.
8441                 PSU_DDR_PHY_DX2GTR0_RESERVED_23_20                                              0x0
8442
8443                 Write Leveling System Latency
8444                 PSU_DDR_PHY_DX2GTR0_WLSL                                                        0x2
8445
8446                 Reserved. Return zeroes on reads.
8447                 PSU_DDR_PHY_DX2GTR0_RESERVED_15_13                                              0x0
8448
8449                 Reserved. Caution, do not write to this register field.
8450                 PSU_DDR_PHY_DX2GTR0_RESERVED_12_8                                               0x0
8451
8452                 Reserved. Return zeroes on reads.
8453                 PSU_DDR_PHY_DX2GTR0_RESERVED_7_5                                                0x0
8454
8455                 DQS Gating System Latency
8456                 PSU_DDR_PHY_DX2GTR0_DGSL                                                        0x0
8457
8458                 DATX8 n General Timing Register 0
8459                 (OFFSET, MASK, VALUE)      (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U)
8460                 RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK |  0 );
8461
8462                 RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT
8463                         | 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT
8464                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT
8465                         | 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT
8466                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT
8467                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT
8468                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT
8469                         | 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT
8470                         |  0 ) & RegMask); */
8471                 PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8472         /*############################################################################################################################ */
8473
8474                 /*Register : DX3GCR0 @ 0XFD080A00</p>
8475
8476                 Calibration Bypass
8477                 PSU_DDR_PHY_DX3GCR0_CALBYP                                                      0x0
8478
8479                 Master Delay Line Enable
8480                 PSU_DDR_PHY_DX3GCR0_MDLEN                                                       0x1
8481
8482                 Configurable ODT(TE) Phase Shift
8483                 PSU_DDR_PHY_DX3GCR0_CODTSHFT                                                    0x0
8484
8485                 DQS Duty Cycle Correction
8486                 PSU_DDR_PHY_DX3GCR0_DQSDCC                                                      0x0
8487
8488                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8489                 PSU_DDR_PHY_DX3GCR0_RDDLY                                                       0x8
8490
8491                 Reserved. Return zeroes on reads.
8492                 PSU_DDR_PHY_DX3GCR0_RESERVED_19_14                                              0x0
8493
8494                 DQSNSE Power Down Receiver
8495                 PSU_DDR_PHY_DX3GCR0_DQSNSEPDR                                                   0x0
8496
8497                 DQSSE Power Down Receiver
8498                 PSU_DDR_PHY_DX3GCR0_DQSSEPDR                                                    0x0
8499
8500                 RTT On Additive Latency
8501                 PSU_DDR_PHY_DX3GCR0_RTTOAL                                                      0x0
8502
8503                 RTT Output Hold
8504                 PSU_DDR_PHY_DX3GCR0_RTTOH                                                       0x3
8505
8506                 Configurable PDR Phase Shift
8507                 PSU_DDR_PHY_DX3GCR0_CPDRSHFT                                                    0x0
8508
8509                 DQSR Power Down
8510                 PSU_DDR_PHY_DX3GCR0_DQSRPD                                                      0x0
8511
8512                 DQSG Power Down Receiver
8513                 PSU_DDR_PHY_DX3GCR0_DQSGPDR                                                     0x0
8514
8515                 Reserved. Return zeroes on reads.
8516                 PSU_DDR_PHY_DX3GCR0_RESERVED_4                                                  0x0
8517
8518                 DQSG On-Die Termination
8519                 PSU_DDR_PHY_DX3GCR0_DQSGODT                                                     0x0
8520
8521                 DQSG Output Enable
8522                 PSU_DDR_PHY_DX3GCR0_DQSGOE                                                      0x1
8523
8524                 Reserved. Return zeroes on reads.
8525                 PSU_DDR_PHY_DX3GCR0_RESERVED_1_0                                                0x0
8526
8527                 DATX8 n General Configuration Register 0
8528                 (OFFSET, MASK, VALUE)      (0XFD080A00, 0xFFFFFFFFU ,0x40800604U)
8529                 RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK |  0 );
8530
8531                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT
8532                         | 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT
8533                         | 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
8534                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT
8535                         | 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT
8536                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
8537                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
8538                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
8539                         | 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT
8540                         | 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT
8541                         | 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
8542                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT
8543                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
8544                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
8545                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT
8546                         | 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT
8547                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
8548                         |  0 ) & RegMask); */
8549                 PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8550         /*############################################################################################################################ */
8551
8552                 /*Register : DX3GCR1 @ 0XFD080A04</p>
8553
8554                 Enables the PDR mode for DQ[7:0]
8555                 PSU_DDR_PHY_DX3GCR1_DXPDRMODE                                                   0x0
8556
8557                 Reserved. Returns zeroes on reads.
8558                 PSU_DDR_PHY_DX3GCR1_RESERVED_15                                                 0x0
8559
8560                 Select the delayed or non-delayed read data strobe #
8561                 PSU_DDR_PHY_DX3GCR1_QSNSEL                                                      0x1
8562
8563                 Select the delayed or non-delayed read data strobe
8564                 PSU_DDR_PHY_DX3GCR1_QSSEL                                                       0x1
8565
8566                 Enables Read Data Strobe in a byte lane
8567                 PSU_DDR_PHY_DX3GCR1_OEEN                                                        0x1
8568
8569                 Enables PDR in a byte lane
8570                 PSU_DDR_PHY_DX3GCR1_PDREN                                                       0x1
8571
8572                 Enables ODT/TE in a byte lane
8573                 PSU_DDR_PHY_DX3GCR1_TEEN                                                        0x1
8574
8575                 Enables Write Data strobe in a byte lane
8576                 PSU_DDR_PHY_DX3GCR1_DSEN                                                        0x1
8577
8578                 Enables DM pin in a byte lane
8579                 PSU_DDR_PHY_DX3GCR1_DMEN                                                        0x1
8580
8581                 Enables DQ corresponding to each bit in a byte
8582                 PSU_DDR_PHY_DX3GCR1_DQEN                                                        0xff
8583
8584                 DATX8 n General Configuration Register 1
8585                 (OFFSET, MASK, VALUE)      (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU)
8586                 RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK |  0 );
8587
8588                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
8589                         | 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
8590                         | 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT
8591                         | 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT
8592                         | 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT
8593                         | 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT
8594                         | 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT
8595                         | 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT
8596                         | 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT
8597                         | 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT
8598                         |  0 ) & RegMask); */
8599                 PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
8600         /*############################################################################################################################ */
8601
8602                 /*Register : DX3GCR4 @ 0XFD080A10</p>
8603
8604                 Byte lane VREF IOM (Used only by D4MU IOs)
8605                 PSU_DDR_PHY_DX3GCR4_RESERVED_31_29                                              0x0
8606
8607                 Byte Lane VREF Pad Enable
8608                 PSU_DDR_PHY_DX3GCR4_DXREFPEN                                                    0x0
8609
8610                 Byte Lane Internal VREF Enable
8611                 PSU_DDR_PHY_DX3GCR4_DXREFEEN                                                    0x3
8612
8613                 Byte Lane Single-End VREF Enable
8614                 PSU_DDR_PHY_DX3GCR4_DXREFSEN                                                    0x1
8615
8616                 Reserved. Returns zeros on reads.
8617                 PSU_DDR_PHY_DX3GCR4_RESERVED_24                                                 0x0
8618
8619                 External VREF generator REFSEL range select
8620                 PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE                                              0x0
8621
8622                 Byte Lane External VREF Select
8623                 PSU_DDR_PHY_DX3GCR4_DXREFESEL                                                   0x0
8624
8625                 Single ended VREF generator REFSEL range select
8626                 PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE                                              0x1
8627
8628                 Byte Lane Single-End VREF Select
8629                 PSU_DDR_PHY_DX3GCR4_DXREFSSEL                                                   0x30
8630
8631                 Reserved. Returns zeros on reads.
8632                 PSU_DDR_PHY_DX3GCR4_RESERVED_7_6                                                0x0
8633
8634                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8635                 PSU_DDR_PHY_DX3GCR4_DXREFIEN                                                    0xf
8636
8637                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8638                 PSU_DDR_PHY_DX3GCR4_DXREFIMON                                                   0x0
8639
8640                 DATX8 n General Configuration Register 4
8641                 (OFFSET, MASK, VALUE)      (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU)
8642                 RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK |  0 );
8643
8644                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
8645                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
8646                         | 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
8647                         | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
8648                         | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
8649                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
8650                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
8651                         | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
8652                         | 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
8653                         | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
8654                         | 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
8655                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
8656                         |  0 ) & RegMask); */
8657                 PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8658         /*############################################################################################################################ */
8659
8660                 /*Register : DX3GCR5 @ 0XFD080A14</p>
8661
8662                 Reserved. Returns zeros on reads.
8663                 PSU_DDR_PHY_DX3GCR5_RESERVED_31                                                 0x0
8664
8665                 Byte Lane internal VREF Select for Rank 3
8666                 PSU_DDR_PHY_DX3GCR5_DXREFISELR3                                                 0x9
8667
8668                 Reserved. Returns zeros on reads.
8669                 PSU_DDR_PHY_DX3GCR5_RESERVED_23                                                 0x0
8670
8671                 Byte Lane internal VREF Select for Rank 2
8672                 PSU_DDR_PHY_DX3GCR5_DXREFISELR2                                                 0x9
8673
8674                 Reserved. Returns zeros on reads.
8675                 PSU_DDR_PHY_DX3GCR5_RESERVED_15                                                 0x0
8676
8677                 Byte Lane internal VREF Select for Rank 1
8678                 PSU_DDR_PHY_DX3GCR5_DXREFISELR1                                                 0x4f
8679
8680                 Reserved. Returns zeros on reads.
8681                 PSU_DDR_PHY_DX3GCR5_RESERVED_7                                                  0x0
8682
8683                 Byte Lane internal VREF Select for Rank 0
8684                 PSU_DDR_PHY_DX3GCR5_DXREFISELR0                                                 0x4f
8685
8686                 DATX8 n General Configuration Register 5
8687                 (OFFSET, MASK, VALUE)      (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU)
8688                 RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK |  0 );
8689
8690                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
8691                         | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
8692                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
8693                         | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
8694                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
8695                         | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
8696                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
8697                         | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
8698                         |  0 ) & RegMask); */
8699                 PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
8700         /*############################################################################################################################ */
8701
8702                 /*Register : DX3GCR6 @ 0XFD080A18</p>
8703
8704                 Reserved. Returns zeros on reads.
8705                 PSU_DDR_PHY_DX3GCR6_RESERVED_31_30                                              0x0
8706
8707                 DRAM DQ VREF Select for Rank3
8708                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR3                                                  0x9
8709
8710                 Reserved. Returns zeros on reads.
8711                 PSU_DDR_PHY_DX3GCR6_RESERVED_23_22                                              0x0
8712
8713                 DRAM DQ VREF Select for Rank2
8714                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR2                                                  0x9
8715
8716                 Reserved. Returns zeros on reads.
8717                 PSU_DDR_PHY_DX3GCR6_RESERVED_15_14                                              0x0
8718
8719                 DRAM DQ VREF Select for Rank1
8720                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR1                                                  0x2b
8721
8722                 Reserved. Returns zeros on reads.
8723                 PSU_DDR_PHY_DX3GCR6_RESERVED_7_6                                                0x0
8724
8725                 DRAM DQ VREF Select for Rank0
8726                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR0                                                  0x2b
8727
8728                 DATX8 n General Configuration Register 6
8729                 (OFFSET, MASK, VALUE)      (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU)
8730                 RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK |  0 );
8731
8732                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
8733                         | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
8734                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
8735                         | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
8736                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
8737                         | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
8738                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
8739                         | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
8740                         |  0 ) & RegMask); */
8741                 PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8742         /*############################################################################################################################ */
8743
8744                 /*Register : DX3LCDLR2 @ 0XFD080A88</p>
8745
8746                 Reserved. Return zeroes on reads.
8747                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25                                            0x0
8748
8749                 Reserved. Caution, do not write to this register field.
8750                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16                                            0x0
8751
8752                 Reserved. Return zeroes on reads.
8753                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9                                             0x0
8754
8755                 Read DQS Gating Delay
8756                 PSU_DDR_PHY_DX3LCDLR2_DQSGD                                                     0x0
8757
8758                 DATX8 n Local Calibrated Delay Line Register 2
8759                 (OFFSET, MASK, VALUE)      (0XFD080A88, 0xFFFFFFFFU ,0x00000000U)
8760                 RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK |  0 );
8761
8762                 RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT
8763                         | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT
8764                         | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT
8765                         | 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT
8766                         |  0 ) & RegMask); */
8767                 PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8768         /*############################################################################################################################ */
8769
8770                 /*Register : DX3GTR0 @ 0XFD080AC0</p>
8771
8772                 Reserved. Return zeroes on reads.
8773                 PSU_DDR_PHY_DX3GTR0_RESERVED_31_24                                              0x0
8774
8775                 DQ Write Path Latency Pipeline
8776                 PSU_DDR_PHY_DX3GTR0_WDQSL                                                       0x0
8777
8778                 Reserved. Caution, do not write to this register field.
8779                 PSU_DDR_PHY_DX3GTR0_RESERVED_23_20                                              0x0
8780
8781                 Write Leveling System Latency
8782                 PSU_DDR_PHY_DX3GTR0_WLSL                                                        0x2
8783
8784                 Reserved. Return zeroes on reads.
8785                 PSU_DDR_PHY_DX3GTR0_RESERVED_15_13                                              0x0
8786
8787                 Reserved. Caution, do not write to this register field.
8788                 PSU_DDR_PHY_DX3GTR0_RESERVED_12_8                                               0x0
8789
8790                 Reserved. Return zeroes on reads.
8791                 PSU_DDR_PHY_DX3GTR0_RESERVED_7_5                                                0x0
8792
8793                 DQS Gating System Latency
8794                 PSU_DDR_PHY_DX3GTR0_DGSL                                                        0x0
8795
8796                 DATX8 n General Timing Register 0
8797                 (OFFSET, MASK, VALUE)      (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U)
8798                 RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK |  0 );
8799
8800                 RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT
8801                         | 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT
8802                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT
8803                         | 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT
8804                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT
8805                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT
8806                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT
8807                         | 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT
8808                         |  0 ) & RegMask); */
8809                 PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8810         /*############################################################################################################################ */
8811
8812                 /*Register : DX4GCR0 @ 0XFD080B00</p>
8813
8814                 Calibration Bypass
8815                 PSU_DDR_PHY_DX4GCR0_CALBYP                                                      0x0
8816
8817                 Master Delay Line Enable
8818                 PSU_DDR_PHY_DX4GCR0_MDLEN                                                       0x1
8819
8820                 Configurable ODT(TE) Phase Shift
8821                 PSU_DDR_PHY_DX4GCR0_CODTSHFT                                                    0x0
8822
8823                 DQS Duty Cycle Correction
8824                 PSU_DDR_PHY_DX4GCR0_DQSDCC                                                      0x0
8825
8826                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8827                 PSU_DDR_PHY_DX4GCR0_RDDLY                                                       0x8
8828
8829                 Reserved. Return zeroes on reads.
8830                 PSU_DDR_PHY_DX4GCR0_RESERVED_19_14                                              0x0
8831
8832                 DQSNSE Power Down Receiver
8833                 PSU_DDR_PHY_DX4GCR0_DQSNSEPDR                                                   0x0
8834
8835                 DQSSE Power Down Receiver
8836                 PSU_DDR_PHY_DX4GCR0_DQSSEPDR                                                    0x0
8837
8838                 RTT On Additive Latency
8839                 PSU_DDR_PHY_DX4GCR0_RTTOAL                                                      0x0
8840
8841                 RTT Output Hold
8842                 PSU_DDR_PHY_DX4GCR0_RTTOH                                                       0x3
8843
8844                 Configurable PDR Phase Shift
8845                 PSU_DDR_PHY_DX4GCR0_CPDRSHFT                                                    0x0
8846
8847                 DQSR Power Down
8848                 PSU_DDR_PHY_DX4GCR0_DQSRPD                                                      0x0
8849
8850                 DQSG Power Down Receiver
8851                 PSU_DDR_PHY_DX4GCR0_DQSGPDR                                                     0x0
8852
8853                 Reserved. Return zeroes on reads.
8854                 PSU_DDR_PHY_DX4GCR0_RESERVED_4                                                  0x0
8855
8856                 DQSG On-Die Termination
8857                 PSU_DDR_PHY_DX4GCR0_DQSGODT                                                     0x0
8858
8859                 DQSG Output Enable
8860                 PSU_DDR_PHY_DX4GCR0_DQSGOE                                                      0x1
8861
8862                 Reserved. Return zeroes on reads.
8863                 PSU_DDR_PHY_DX4GCR0_RESERVED_1_0                                                0x0
8864
8865                 DATX8 n General Configuration Register 0
8866                 (OFFSET, MASK, VALUE)      (0XFD080B00, 0xFFFFFFFFU ,0x40800604U)
8867                 RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK |  0 );
8868
8869                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT
8870                         | 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT
8871                         | 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
8872                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT
8873                         | 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT
8874                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
8875                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
8876                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
8877                         | 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT
8878                         | 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT
8879                         | 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
8880                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT
8881                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
8882                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
8883                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT
8884                         | 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT
8885                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
8886                         |  0 ) & RegMask); */
8887                 PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8888         /*############################################################################################################################ */
8889
8890                 /*Register : DX4GCR1 @ 0XFD080B04</p>
8891
8892                 Enables the PDR mode for DQ[7:0]
8893                 PSU_DDR_PHY_DX4GCR1_DXPDRMODE                                                   0x0
8894
8895                 Reserved. Returns zeroes on reads.
8896                 PSU_DDR_PHY_DX4GCR1_RESERVED_15                                                 0x0
8897
8898                 Select the delayed or non-delayed read data strobe #
8899                 PSU_DDR_PHY_DX4GCR1_QSNSEL                                                      0x1
8900
8901                 Select the delayed or non-delayed read data strobe
8902                 PSU_DDR_PHY_DX4GCR1_QSSEL                                                       0x1
8903
8904                 Enables Read Data Strobe in a byte lane
8905                 PSU_DDR_PHY_DX4GCR1_OEEN                                                        0x1
8906
8907                 Enables PDR in a byte lane
8908                 PSU_DDR_PHY_DX4GCR1_PDREN                                                       0x1
8909
8910                 Enables ODT/TE in a byte lane
8911                 PSU_DDR_PHY_DX4GCR1_TEEN                                                        0x1
8912
8913                 Enables Write Data strobe in a byte lane
8914                 PSU_DDR_PHY_DX4GCR1_DSEN                                                        0x1
8915
8916                 Enables DM pin in a byte lane
8917                 PSU_DDR_PHY_DX4GCR1_DMEN                                                        0x1
8918
8919                 Enables DQ corresponding to each bit in a byte
8920                 PSU_DDR_PHY_DX4GCR1_DQEN                                                        0xff
8921
8922                 DATX8 n General Configuration Register 1
8923                 (OFFSET, MASK, VALUE)      (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU)
8924                 RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK |  0 );
8925
8926                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
8927                         | 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
8928                         | 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT
8929                         | 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT
8930                         | 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT
8931                         | 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT
8932                         | 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT
8933                         | 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT
8934                         | 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT
8935                         | 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT
8936                         |  0 ) & RegMask); */
8937                 PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
8938         /*############################################################################################################################ */
8939
8940                 /*Register : DX4GCR4 @ 0XFD080B10</p>
8941
8942                 Byte lane VREF IOM (Used only by D4MU IOs)
8943                 PSU_DDR_PHY_DX4GCR4_RESERVED_31_29                                              0x0
8944
8945                 Byte Lane VREF Pad Enable
8946                 PSU_DDR_PHY_DX4GCR4_DXREFPEN                                                    0x0
8947
8948                 Byte Lane Internal VREF Enable
8949                 PSU_DDR_PHY_DX4GCR4_DXREFEEN                                                    0x3
8950
8951                 Byte Lane Single-End VREF Enable
8952                 PSU_DDR_PHY_DX4GCR4_DXREFSEN                                                    0x1
8953
8954                 Reserved. Returns zeros on reads.
8955                 PSU_DDR_PHY_DX4GCR4_RESERVED_24                                                 0x0
8956
8957                 External VREF generator REFSEL range select
8958                 PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE                                              0x0
8959
8960                 Byte Lane External VREF Select
8961                 PSU_DDR_PHY_DX4GCR4_DXREFESEL                                                   0x0
8962
8963                 Single ended VREF generator REFSEL range select
8964                 PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE                                              0x1
8965
8966                 Byte Lane Single-End VREF Select
8967                 PSU_DDR_PHY_DX4GCR4_DXREFSSEL                                                   0x30
8968
8969                 Reserved. Returns zeros on reads.
8970                 PSU_DDR_PHY_DX4GCR4_RESERVED_7_6                                                0x0
8971
8972                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8973                 PSU_DDR_PHY_DX4GCR4_DXREFIEN                                                    0xf
8974
8975                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8976                 PSU_DDR_PHY_DX4GCR4_DXREFIMON                                                   0x0
8977
8978                 DATX8 n General Configuration Register 4
8979                 (OFFSET, MASK, VALUE)      (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU)
8980                 RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK |  0 );
8981
8982                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
8983                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
8984                         | 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
8985                         | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
8986                         | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
8987                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
8988                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
8989                         | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
8990                         | 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
8991                         | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
8992                         | 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
8993                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
8994                         |  0 ) & RegMask); */
8995                 PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8996         /*############################################################################################################################ */
8997
8998                 /*Register : DX4GCR5 @ 0XFD080B14</p>
8999
9000                 Reserved. Returns zeros on reads.
9001                 PSU_DDR_PHY_DX4GCR5_RESERVED_31                                                 0x0
9002
9003                 Byte Lane internal VREF Select for Rank 3
9004                 PSU_DDR_PHY_DX4GCR5_DXREFISELR3                                                 0x9
9005
9006                 Reserved. Returns zeros on reads.
9007                 PSU_DDR_PHY_DX4GCR5_RESERVED_23                                                 0x0
9008
9009                 Byte Lane internal VREF Select for Rank 2
9010                 PSU_DDR_PHY_DX4GCR5_DXREFISELR2                                                 0x9
9011
9012                 Reserved. Returns zeros on reads.
9013                 PSU_DDR_PHY_DX4GCR5_RESERVED_15                                                 0x0
9014
9015                 Byte Lane internal VREF Select for Rank 1
9016                 PSU_DDR_PHY_DX4GCR5_DXREFISELR1                                                 0x4f
9017
9018                 Reserved. Returns zeros on reads.
9019                 PSU_DDR_PHY_DX4GCR5_RESERVED_7                                                  0x0
9020
9021                 Byte Lane internal VREF Select for Rank 0
9022                 PSU_DDR_PHY_DX4GCR5_DXREFISELR0                                                 0x4f
9023
9024                 DATX8 n General Configuration Register 5
9025                 (OFFSET, MASK, VALUE)      (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU)
9026                 RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK |  0 );
9027
9028                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
9029                         | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
9030                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
9031                         | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
9032                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
9033                         | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
9034                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
9035                         | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
9036                         |  0 ) & RegMask); */
9037                 PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
9038         /*############################################################################################################################ */
9039
9040                 /*Register : DX4GCR6 @ 0XFD080B18</p>
9041
9042                 Reserved. Returns zeros on reads.
9043                 PSU_DDR_PHY_DX4GCR6_RESERVED_31_30                                              0x0
9044
9045                 DRAM DQ VREF Select for Rank3
9046                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR3                                                  0x9
9047
9048                 Reserved. Returns zeros on reads.
9049                 PSU_DDR_PHY_DX4GCR6_RESERVED_23_22                                              0x0
9050
9051                 DRAM DQ VREF Select for Rank2
9052                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR2                                                  0x9
9053
9054                 Reserved. Returns zeros on reads.
9055                 PSU_DDR_PHY_DX4GCR6_RESERVED_15_14                                              0x0
9056
9057                 DRAM DQ VREF Select for Rank1
9058                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR1                                                  0x2b
9059
9060                 Reserved. Returns zeros on reads.
9061                 PSU_DDR_PHY_DX4GCR6_RESERVED_7_6                                                0x0
9062
9063                 DRAM DQ VREF Select for Rank0
9064                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR0                                                  0x2b
9065
9066                 DATX8 n General Configuration Register 6
9067                 (OFFSET, MASK, VALUE)      (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU)
9068                 RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK |  0 );
9069
9070                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
9071                         | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
9072                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
9073                         | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
9074                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
9075                         | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
9076                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
9077                         | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
9078                         |  0 ) & RegMask); */
9079                 PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9080         /*############################################################################################################################ */
9081
9082                 /*Register : DX4LCDLR2 @ 0XFD080B88</p>
9083
9084                 Reserved. Return zeroes on reads.
9085                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25                                            0x0
9086
9087                 Reserved. Caution, do not write to this register field.
9088                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16                                            0x0
9089
9090                 Reserved. Return zeroes on reads.
9091                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9                                             0x0
9092
9093                 Read DQS Gating Delay
9094                 PSU_DDR_PHY_DX4LCDLR2_DQSGD                                                     0x0
9095
9096                 DATX8 n Local Calibrated Delay Line Register 2
9097                 (OFFSET, MASK, VALUE)      (0XFD080B88, 0xFFFFFFFFU ,0x00000000U)
9098                 RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK |  0 );
9099
9100                 RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT
9101                         | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT
9102                         | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT
9103                         | 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT
9104                         |  0 ) & RegMask); */
9105                 PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9106         /*############################################################################################################################ */
9107
9108                 /*Register : DX4GTR0 @ 0XFD080BC0</p>
9109
9110                 Reserved. Return zeroes on reads.
9111                 PSU_DDR_PHY_DX4GTR0_RESERVED_31_24                                              0x0
9112
9113                 DQ Write Path Latency Pipeline
9114                 PSU_DDR_PHY_DX4GTR0_WDQSL                                                       0x0
9115
9116                 Reserved. Caution, do not write to this register field.
9117                 PSU_DDR_PHY_DX4GTR0_RESERVED_23_20                                              0x0
9118
9119                 Write Leveling System Latency
9120                 PSU_DDR_PHY_DX4GTR0_WLSL                                                        0x2
9121
9122                 Reserved. Return zeroes on reads.
9123                 PSU_DDR_PHY_DX4GTR0_RESERVED_15_13                                              0x0
9124
9125                 Reserved. Caution, do not write to this register field.
9126                 PSU_DDR_PHY_DX4GTR0_RESERVED_12_8                                               0x0
9127
9128                 Reserved. Return zeroes on reads.
9129                 PSU_DDR_PHY_DX4GTR0_RESERVED_7_5                                                0x0
9130
9131                 DQS Gating System Latency
9132                 PSU_DDR_PHY_DX4GTR0_DGSL                                                        0x0
9133
9134                 DATX8 n General Timing Register 0
9135                 (OFFSET, MASK, VALUE)      (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U)
9136                 RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK |  0 );
9137
9138                 RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT
9139                         | 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT
9140                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT
9141                         | 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT
9142                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT
9143                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT
9144                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT
9145                         | 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT
9146                         |  0 ) & RegMask); */
9147                 PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9148         /*############################################################################################################################ */
9149
9150                 /*Register : DX5GCR0 @ 0XFD080C00</p>
9151
9152                 Calibration Bypass
9153                 PSU_DDR_PHY_DX5GCR0_CALBYP                                                      0x0
9154
9155                 Master Delay Line Enable
9156                 PSU_DDR_PHY_DX5GCR0_MDLEN                                                       0x1
9157
9158                 Configurable ODT(TE) Phase Shift
9159                 PSU_DDR_PHY_DX5GCR0_CODTSHFT                                                    0x0
9160
9161                 DQS Duty Cycle Correction
9162                 PSU_DDR_PHY_DX5GCR0_DQSDCC                                                      0x0
9163
9164                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9165                 PSU_DDR_PHY_DX5GCR0_RDDLY                                                       0x8
9166
9167                 Reserved. Return zeroes on reads.
9168                 PSU_DDR_PHY_DX5GCR0_RESERVED_19_14                                              0x0
9169
9170                 DQSNSE Power Down Receiver
9171                 PSU_DDR_PHY_DX5GCR0_DQSNSEPDR                                                   0x0
9172
9173                 DQSSE Power Down Receiver
9174                 PSU_DDR_PHY_DX5GCR0_DQSSEPDR                                                    0x0
9175
9176                 RTT On Additive Latency
9177                 PSU_DDR_PHY_DX5GCR0_RTTOAL                                                      0x0
9178
9179                 RTT Output Hold
9180                 PSU_DDR_PHY_DX5GCR0_RTTOH                                                       0x3
9181
9182                 Configurable PDR Phase Shift
9183                 PSU_DDR_PHY_DX5GCR0_CPDRSHFT                                                    0x0
9184
9185                 DQSR Power Down
9186                 PSU_DDR_PHY_DX5GCR0_DQSRPD                                                      0x0
9187
9188                 DQSG Power Down Receiver
9189                 PSU_DDR_PHY_DX5GCR0_DQSGPDR                                                     0x0
9190
9191                 Reserved. Return zeroes on reads.
9192                 PSU_DDR_PHY_DX5GCR0_RESERVED_4                                                  0x0
9193
9194                 DQSG On-Die Termination
9195                 PSU_DDR_PHY_DX5GCR0_DQSGODT                                                     0x0
9196
9197                 DQSG Output Enable
9198                 PSU_DDR_PHY_DX5GCR0_DQSGOE                                                      0x1
9199
9200                 Reserved. Return zeroes on reads.
9201                 PSU_DDR_PHY_DX5GCR0_RESERVED_1_0                                                0x0
9202
9203                 DATX8 n General Configuration Register 0
9204                 (OFFSET, MASK, VALUE)      (0XFD080C00, 0xFFFFFFFFU ,0x40800604U)
9205                 RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK |  0 );
9206
9207                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT
9208                         | 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT
9209                         | 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
9210                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT
9211                         | 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT
9212                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
9213                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
9214                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
9215                         | 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT
9216                         | 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT
9217                         | 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
9218                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT
9219                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
9220                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
9221                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT
9222                         | 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT
9223                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
9224                         |  0 ) & RegMask); */
9225                 PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9226         /*############################################################################################################################ */
9227
9228                 /*Register : DX5GCR1 @ 0XFD080C04</p>
9229
9230                 Enables the PDR mode for DQ[7:0]
9231                 PSU_DDR_PHY_DX5GCR1_DXPDRMODE                                                   0x0
9232
9233                 Reserved. Returns zeroes on reads.
9234                 PSU_DDR_PHY_DX5GCR1_RESERVED_15                                                 0x0
9235
9236                 Select the delayed or non-delayed read data strobe #
9237                 PSU_DDR_PHY_DX5GCR1_QSNSEL                                                      0x1
9238
9239                 Select the delayed or non-delayed read data strobe
9240                 PSU_DDR_PHY_DX5GCR1_QSSEL                                                       0x1
9241
9242                 Enables Read Data Strobe in a byte lane
9243                 PSU_DDR_PHY_DX5GCR1_OEEN                                                        0x1
9244
9245                 Enables PDR in a byte lane
9246                 PSU_DDR_PHY_DX5GCR1_PDREN                                                       0x1
9247
9248                 Enables ODT/TE in a byte lane
9249                 PSU_DDR_PHY_DX5GCR1_TEEN                                                        0x1
9250
9251                 Enables Write Data strobe in a byte lane
9252                 PSU_DDR_PHY_DX5GCR1_DSEN                                                        0x1
9253
9254                 Enables DM pin in a byte lane
9255                 PSU_DDR_PHY_DX5GCR1_DMEN                                                        0x1
9256
9257                 Enables DQ corresponding to each bit in a byte
9258                 PSU_DDR_PHY_DX5GCR1_DQEN                                                        0xff
9259
9260                 DATX8 n General Configuration Register 1
9261                 (OFFSET, MASK, VALUE)      (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU)
9262                 RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK |  0 );
9263
9264                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
9265                         | 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
9266                         | 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT
9267                         | 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT
9268                         | 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT
9269                         | 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT
9270                         | 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT
9271                         | 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT
9272                         | 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT
9273                         | 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT
9274                         |  0 ) & RegMask); */
9275                 PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9276         /*############################################################################################################################ */
9277
9278                 /*Register : DX5GCR4 @ 0XFD080C10</p>
9279
9280                 Byte lane VREF IOM (Used only by D4MU IOs)
9281                 PSU_DDR_PHY_DX5GCR4_RESERVED_31_29                                              0x0
9282
9283                 Byte Lane VREF Pad Enable
9284                 PSU_DDR_PHY_DX5GCR4_DXREFPEN                                                    0x0
9285
9286                 Byte Lane Internal VREF Enable
9287                 PSU_DDR_PHY_DX5GCR4_DXREFEEN                                                    0x3
9288
9289                 Byte Lane Single-End VREF Enable
9290                 PSU_DDR_PHY_DX5GCR4_DXREFSEN                                                    0x1
9291
9292                 Reserved. Returns zeros on reads.
9293                 PSU_DDR_PHY_DX5GCR4_RESERVED_24                                                 0x0
9294
9295                 External VREF generator REFSEL range select
9296                 PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE                                              0x0
9297
9298                 Byte Lane External VREF Select
9299                 PSU_DDR_PHY_DX5GCR4_DXREFESEL                                                   0x0
9300
9301                 Single ended VREF generator REFSEL range select
9302                 PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE                                              0x1
9303
9304                 Byte Lane Single-End VREF Select
9305                 PSU_DDR_PHY_DX5GCR4_DXREFSSEL                                                   0x30
9306
9307                 Reserved. Returns zeros on reads.
9308                 PSU_DDR_PHY_DX5GCR4_RESERVED_7_6                                                0x0
9309
9310                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9311                 PSU_DDR_PHY_DX5GCR4_DXREFIEN                                                    0xf
9312
9313                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9314                 PSU_DDR_PHY_DX5GCR4_DXREFIMON                                                   0x0
9315
9316                 DATX8 n General Configuration Register 4
9317                 (OFFSET, MASK, VALUE)      (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU)
9318                 RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK |  0 );
9319
9320                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
9321                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
9322                         | 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
9323                         | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
9324                         | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
9325                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
9326                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
9327                         | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
9328                         | 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
9329                         | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
9330                         | 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
9331                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
9332                         |  0 ) & RegMask); */
9333                 PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
9334         /*############################################################################################################################ */
9335
9336                 /*Register : DX5GCR5 @ 0XFD080C14</p>
9337
9338                 Reserved. Returns zeros on reads.
9339                 PSU_DDR_PHY_DX5GCR5_RESERVED_31                                                 0x0
9340
9341                 Byte Lane internal VREF Select for Rank 3
9342                 PSU_DDR_PHY_DX5GCR5_DXREFISELR3                                                 0x9
9343
9344                 Reserved. Returns zeros on reads.
9345                 PSU_DDR_PHY_DX5GCR5_RESERVED_23                                                 0x0
9346
9347                 Byte Lane internal VREF Select for Rank 2
9348                 PSU_DDR_PHY_DX5GCR5_DXREFISELR2                                                 0x9
9349
9350                 Reserved. Returns zeros on reads.
9351                 PSU_DDR_PHY_DX5GCR5_RESERVED_15                                                 0x0
9352
9353                 Byte Lane internal VREF Select for Rank 1
9354                 PSU_DDR_PHY_DX5GCR5_DXREFISELR1                                                 0x4f
9355
9356                 Reserved. Returns zeros on reads.
9357                 PSU_DDR_PHY_DX5GCR5_RESERVED_7                                                  0x0
9358
9359                 Byte Lane internal VREF Select for Rank 0
9360                 PSU_DDR_PHY_DX5GCR5_DXREFISELR0                                                 0x4f
9361
9362                 DATX8 n General Configuration Register 5
9363                 (OFFSET, MASK, VALUE)      (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU)
9364                 RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK |  0 );
9365
9366                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
9367                         | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
9368                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
9369                         | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
9370                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
9371                         | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
9372                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
9373                         | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
9374                         |  0 ) & RegMask); */
9375                 PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
9376         /*############################################################################################################################ */
9377
9378                 /*Register : DX5GCR6 @ 0XFD080C18</p>
9379
9380                 Reserved. Returns zeros on reads.
9381                 PSU_DDR_PHY_DX5GCR6_RESERVED_31_30                                              0x0
9382
9383                 DRAM DQ VREF Select for Rank3
9384                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR3                                                  0x9
9385
9386                 Reserved. Returns zeros on reads.
9387                 PSU_DDR_PHY_DX5GCR6_RESERVED_23_22                                              0x0
9388
9389                 DRAM DQ VREF Select for Rank2
9390                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR2                                                  0x9
9391
9392                 Reserved. Returns zeros on reads.
9393                 PSU_DDR_PHY_DX5GCR6_RESERVED_15_14                                              0x0
9394
9395                 DRAM DQ VREF Select for Rank1
9396                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR1                                                  0x2b
9397
9398                 Reserved. Returns zeros on reads.
9399                 PSU_DDR_PHY_DX5GCR6_RESERVED_7_6                                                0x0
9400
9401                 DRAM DQ VREF Select for Rank0
9402                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR0                                                  0x2b
9403
9404                 DATX8 n General Configuration Register 6
9405                 (OFFSET, MASK, VALUE)      (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU)
9406                 RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK |  0 );
9407
9408                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
9409                         | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
9410                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
9411                         | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
9412                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
9413                         | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
9414                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
9415                         | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
9416                         |  0 ) & RegMask); */
9417                 PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9418         /*############################################################################################################################ */
9419
9420                 /*Register : DX5LCDLR2 @ 0XFD080C88</p>
9421
9422                 Reserved. Return zeroes on reads.
9423                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25                                            0x0
9424
9425                 Reserved. Caution, do not write to this register field.
9426                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16                                            0x0
9427
9428                 Reserved. Return zeroes on reads.
9429                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9                                             0x0
9430
9431                 Read DQS Gating Delay
9432                 PSU_DDR_PHY_DX5LCDLR2_DQSGD                                                     0x0
9433
9434                 DATX8 n Local Calibrated Delay Line Register 2
9435                 (OFFSET, MASK, VALUE)      (0XFD080C88, 0xFFFFFFFFU ,0x00000000U)
9436                 RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK |  0 );
9437
9438                 RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT
9439                         | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT
9440                         | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT
9441                         | 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT
9442                         |  0 ) & RegMask); */
9443                 PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9444         /*############################################################################################################################ */
9445
9446                 /*Register : DX5GTR0 @ 0XFD080CC0</p>
9447
9448                 Reserved. Return zeroes on reads.
9449                 PSU_DDR_PHY_DX5GTR0_RESERVED_31_24                                              0x0
9450
9451                 DQ Write Path Latency Pipeline
9452                 PSU_DDR_PHY_DX5GTR0_WDQSL                                                       0x0
9453
9454                 Reserved. Caution, do not write to this register field.
9455                 PSU_DDR_PHY_DX5GTR0_RESERVED_23_20                                              0x0
9456
9457                 Write Leveling System Latency
9458                 PSU_DDR_PHY_DX5GTR0_WLSL                                                        0x2
9459
9460                 Reserved. Return zeroes on reads.
9461                 PSU_DDR_PHY_DX5GTR0_RESERVED_15_13                                              0x0
9462
9463                 Reserved. Caution, do not write to this register field.
9464                 PSU_DDR_PHY_DX5GTR0_RESERVED_12_8                                               0x0
9465
9466                 Reserved. Return zeroes on reads.
9467                 PSU_DDR_PHY_DX5GTR0_RESERVED_7_5                                                0x0
9468
9469                 DQS Gating System Latency
9470                 PSU_DDR_PHY_DX5GTR0_DGSL                                                        0x0
9471
9472                 DATX8 n General Timing Register 0
9473                 (OFFSET, MASK, VALUE)      (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U)
9474                 RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK |  0 );
9475
9476                 RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT
9477                         | 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT
9478                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT
9479                         | 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT
9480                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT
9481                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT
9482                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT
9483                         | 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT
9484                         |  0 ) & RegMask); */
9485                 PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9486         /*############################################################################################################################ */
9487
9488                 /*Register : DX6GCR0 @ 0XFD080D00</p>
9489
9490                 Calibration Bypass
9491                 PSU_DDR_PHY_DX6GCR0_CALBYP                                                      0x0
9492
9493                 Master Delay Line Enable
9494                 PSU_DDR_PHY_DX6GCR0_MDLEN                                                       0x1
9495
9496                 Configurable ODT(TE) Phase Shift
9497                 PSU_DDR_PHY_DX6GCR0_CODTSHFT                                                    0x0
9498
9499                 DQS Duty Cycle Correction
9500                 PSU_DDR_PHY_DX6GCR0_DQSDCC                                                      0x0
9501
9502                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9503                 PSU_DDR_PHY_DX6GCR0_RDDLY                                                       0x8
9504
9505                 Reserved. Return zeroes on reads.
9506                 PSU_DDR_PHY_DX6GCR0_RESERVED_19_14                                              0x0
9507
9508                 DQSNSE Power Down Receiver
9509                 PSU_DDR_PHY_DX6GCR0_DQSNSEPDR                                                   0x0
9510
9511                 DQSSE Power Down Receiver
9512                 PSU_DDR_PHY_DX6GCR0_DQSSEPDR                                                    0x0
9513
9514                 RTT On Additive Latency
9515                 PSU_DDR_PHY_DX6GCR0_RTTOAL                                                      0x0
9516
9517                 RTT Output Hold
9518                 PSU_DDR_PHY_DX6GCR0_RTTOH                                                       0x3
9519
9520                 Configurable PDR Phase Shift
9521                 PSU_DDR_PHY_DX6GCR0_CPDRSHFT                                                    0x0
9522
9523                 DQSR Power Down
9524                 PSU_DDR_PHY_DX6GCR0_DQSRPD                                                      0x0
9525
9526                 DQSG Power Down Receiver
9527                 PSU_DDR_PHY_DX6GCR0_DQSGPDR                                                     0x0
9528
9529                 Reserved. Return zeroes on reads.
9530                 PSU_DDR_PHY_DX6GCR0_RESERVED_4                                                  0x0
9531
9532                 DQSG On-Die Termination
9533                 PSU_DDR_PHY_DX6GCR0_DQSGODT                                                     0x0
9534
9535                 DQSG Output Enable
9536                 PSU_DDR_PHY_DX6GCR0_DQSGOE                                                      0x1
9537
9538                 Reserved. Return zeroes on reads.
9539                 PSU_DDR_PHY_DX6GCR0_RESERVED_1_0                                                0x0
9540
9541                 DATX8 n General Configuration Register 0
9542                 (OFFSET, MASK, VALUE)      (0XFD080D00, 0xFFFFFFFFU ,0x40800604U)
9543                 RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK |  0 );
9544
9545                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT
9546                         | 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT
9547                         | 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
9548                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT
9549                         | 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT
9550                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
9551                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
9552                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
9553                         | 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT
9554                         | 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT
9555                         | 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
9556                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT
9557                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
9558                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
9559                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT
9560                         | 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT
9561                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
9562                         |  0 ) & RegMask); */
9563                 PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9564         /*############################################################################################################################ */
9565
9566                 /*Register : DX6GCR1 @ 0XFD080D04</p>
9567
9568                 Enables the PDR mode for DQ[7:0]
9569                 PSU_DDR_PHY_DX6GCR1_DXPDRMODE                                                   0x0
9570
9571                 Reserved. Returns zeroes on reads.
9572                 PSU_DDR_PHY_DX6GCR1_RESERVED_15                                                 0x0
9573
9574                 Select the delayed or non-delayed read data strobe #
9575                 PSU_DDR_PHY_DX6GCR1_QSNSEL                                                      0x1
9576
9577                 Select the delayed or non-delayed read data strobe
9578                 PSU_DDR_PHY_DX6GCR1_QSSEL                                                       0x1
9579
9580                 Enables Read Data Strobe in a byte lane
9581                 PSU_DDR_PHY_DX6GCR1_OEEN                                                        0x1
9582
9583                 Enables PDR in a byte lane
9584                 PSU_DDR_PHY_DX6GCR1_PDREN                                                       0x1
9585
9586                 Enables ODT/TE in a byte lane
9587                 PSU_DDR_PHY_DX6GCR1_TEEN                                                        0x1
9588
9589                 Enables Write Data strobe in a byte lane
9590                 PSU_DDR_PHY_DX6GCR1_DSEN                                                        0x1
9591
9592                 Enables DM pin in a byte lane
9593                 PSU_DDR_PHY_DX6GCR1_DMEN                                                        0x1
9594
9595                 Enables DQ corresponding to each bit in a byte
9596                 PSU_DDR_PHY_DX6GCR1_DQEN                                                        0xff
9597
9598                 DATX8 n General Configuration Register 1
9599                 (OFFSET, MASK, VALUE)      (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU)
9600                 RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK |  0 );
9601
9602                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
9603                         | 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
9604                         | 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT
9605                         | 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT
9606                         | 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT
9607                         | 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT
9608                         | 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT
9609                         | 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT
9610                         | 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT
9611                         | 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT
9612                         |  0 ) & RegMask); */
9613                 PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9614         /*############################################################################################################################ */
9615
9616                 /*Register : DX6GCR4 @ 0XFD080D10</p>
9617
9618                 Byte lane VREF IOM (Used only by D4MU IOs)
9619                 PSU_DDR_PHY_DX6GCR4_RESERVED_31_29                                              0x0
9620
9621                 Byte Lane VREF Pad Enable
9622                 PSU_DDR_PHY_DX6GCR4_DXREFPEN                                                    0x0
9623
9624                 Byte Lane Internal VREF Enable
9625                 PSU_DDR_PHY_DX6GCR4_DXREFEEN                                                    0x3
9626
9627                 Byte Lane Single-End VREF Enable
9628                 PSU_DDR_PHY_DX6GCR4_DXREFSEN                                                    0x1
9629
9630                 Reserved. Returns zeros on reads.
9631                 PSU_DDR_PHY_DX6GCR4_RESERVED_24                                                 0x0
9632
9633                 External VREF generator REFSEL range select
9634                 PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE                                              0x0
9635
9636                 Byte Lane External VREF Select
9637                 PSU_DDR_PHY_DX6GCR4_DXREFESEL                                                   0x0
9638
9639                 Single ended VREF generator REFSEL range select
9640                 PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE                                              0x1
9641
9642                 Byte Lane Single-End VREF Select
9643                 PSU_DDR_PHY_DX6GCR4_DXREFSSEL                                                   0x30
9644
9645                 Reserved. Returns zeros on reads.
9646                 PSU_DDR_PHY_DX6GCR4_RESERVED_7_6                                                0x0
9647
9648                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9649                 PSU_DDR_PHY_DX6GCR4_DXREFIEN                                                    0xf
9650
9651                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9652                 PSU_DDR_PHY_DX6GCR4_DXREFIMON                                                   0x0
9653
9654                 DATX8 n General Configuration Register 4
9655                 (OFFSET, MASK, VALUE)      (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU)
9656                 RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK |  0 );
9657
9658                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
9659                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
9660                         | 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
9661                         | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
9662                         | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
9663                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
9664                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
9665                         | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
9666                         | 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
9667                         | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
9668                         | 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
9669                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
9670                         |  0 ) & RegMask); */
9671                 PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
9672         /*############################################################################################################################ */
9673
9674                 /*Register : DX6GCR5 @ 0XFD080D14</p>
9675
9676                 Reserved. Returns zeros on reads.
9677                 PSU_DDR_PHY_DX6GCR5_RESERVED_31                                                 0x0
9678
9679                 Byte Lane internal VREF Select for Rank 3
9680                 PSU_DDR_PHY_DX6GCR5_DXREFISELR3                                                 0x9
9681
9682                 Reserved. Returns zeros on reads.
9683                 PSU_DDR_PHY_DX6GCR5_RESERVED_23                                                 0x0
9684
9685                 Byte Lane internal VREF Select for Rank 2
9686                 PSU_DDR_PHY_DX6GCR5_DXREFISELR2                                                 0x9
9687
9688                 Reserved. Returns zeros on reads.
9689                 PSU_DDR_PHY_DX6GCR5_RESERVED_15                                                 0x0
9690
9691                 Byte Lane internal VREF Select for Rank 1
9692                 PSU_DDR_PHY_DX6GCR5_DXREFISELR1                                                 0x4f
9693
9694                 Reserved. Returns zeros on reads.
9695                 PSU_DDR_PHY_DX6GCR5_RESERVED_7                                                  0x0
9696
9697                 Byte Lane internal VREF Select for Rank 0
9698                 PSU_DDR_PHY_DX6GCR5_DXREFISELR0                                                 0x4f
9699
9700                 DATX8 n General Configuration Register 5
9701                 (OFFSET, MASK, VALUE)      (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU)
9702                 RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK |  0 );
9703
9704                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
9705                         | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
9706                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
9707                         | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
9708                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
9709                         | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
9710                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
9711                         | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
9712                         |  0 ) & RegMask); */
9713                 PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
9714         /*############################################################################################################################ */
9715
9716                 /*Register : DX6GCR6 @ 0XFD080D18</p>
9717
9718                 Reserved. Returns zeros on reads.
9719                 PSU_DDR_PHY_DX6GCR6_RESERVED_31_30                                              0x0
9720
9721                 DRAM DQ VREF Select for Rank3
9722                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR3                                                  0x9
9723
9724                 Reserved. Returns zeros on reads.
9725                 PSU_DDR_PHY_DX6GCR6_RESERVED_23_22                                              0x0
9726
9727                 DRAM DQ VREF Select for Rank2
9728                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR2                                                  0x9
9729
9730                 Reserved. Returns zeros on reads.
9731                 PSU_DDR_PHY_DX6GCR6_RESERVED_15_14                                              0x0
9732
9733                 DRAM DQ VREF Select for Rank1
9734                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR1                                                  0x2b
9735
9736                 Reserved. Returns zeros on reads.
9737                 PSU_DDR_PHY_DX6GCR6_RESERVED_7_6                                                0x0
9738
9739                 DRAM DQ VREF Select for Rank0
9740                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR0                                                  0x2b
9741
9742                 DATX8 n General Configuration Register 6
9743                 (OFFSET, MASK, VALUE)      (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU)
9744                 RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK |  0 );
9745
9746                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
9747                         | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
9748                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
9749                         | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
9750                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
9751                         | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
9752                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
9753                         | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
9754                         |  0 ) & RegMask); */
9755                 PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9756         /*############################################################################################################################ */
9757
9758                 /*Register : DX6LCDLR2 @ 0XFD080D88</p>
9759
9760                 Reserved. Return zeroes on reads.
9761                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25                                            0x0
9762
9763                 Reserved. Caution, do not write to this register field.
9764                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16                                            0x0
9765
9766                 Reserved. Return zeroes on reads.
9767                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9                                             0x0
9768
9769                 Read DQS Gating Delay
9770                 PSU_DDR_PHY_DX6LCDLR2_DQSGD                                                     0x0
9771
9772                 DATX8 n Local Calibrated Delay Line Register 2
9773                 (OFFSET, MASK, VALUE)      (0XFD080D88, 0xFFFFFFFFU ,0x00000000U)
9774                 RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK |  0 );
9775
9776                 RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT
9777                         | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT
9778                         | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT
9779                         | 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT
9780                         |  0 ) & RegMask); */
9781                 PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9782         /*############################################################################################################################ */
9783
9784                 /*Register : DX6GTR0 @ 0XFD080DC0</p>
9785
9786                 Reserved. Return zeroes on reads.
9787                 PSU_DDR_PHY_DX6GTR0_RESERVED_31_24                                              0x0
9788
9789                 DQ Write Path Latency Pipeline
9790                 PSU_DDR_PHY_DX6GTR0_WDQSL                                                       0x0
9791
9792                 Reserved. Caution, do not write to this register field.
9793                 PSU_DDR_PHY_DX6GTR0_RESERVED_23_20                                              0x0
9794
9795                 Write Leveling System Latency
9796                 PSU_DDR_PHY_DX6GTR0_WLSL                                                        0x2
9797
9798                 Reserved. Return zeroes on reads.
9799                 PSU_DDR_PHY_DX6GTR0_RESERVED_15_13                                              0x0
9800
9801                 Reserved. Caution, do not write to this register field.
9802                 PSU_DDR_PHY_DX6GTR0_RESERVED_12_8                                               0x0
9803
9804                 Reserved. Return zeroes on reads.
9805                 PSU_DDR_PHY_DX6GTR0_RESERVED_7_5                                                0x0
9806
9807                 DQS Gating System Latency
9808                 PSU_DDR_PHY_DX6GTR0_DGSL                                                        0x0
9809
9810                 DATX8 n General Timing Register 0
9811                 (OFFSET, MASK, VALUE)      (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U)
9812                 RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK |  0 );
9813
9814                 RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT
9815                         | 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT
9816                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT
9817                         | 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT
9818                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT
9819                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT
9820                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT
9821                         | 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT
9822                         |  0 ) & RegMask); */
9823                 PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9824         /*############################################################################################################################ */
9825
9826                 /*Register : DX7GCR0 @ 0XFD080E00</p>
9827
9828                 Calibration Bypass
9829                 PSU_DDR_PHY_DX7GCR0_CALBYP                                                      0x0
9830
9831                 Master Delay Line Enable
9832                 PSU_DDR_PHY_DX7GCR0_MDLEN                                                       0x1
9833
9834                 Configurable ODT(TE) Phase Shift
9835                 PSU_DDR_PHY_DX7GCR0_CODTSHFT                                                    0x0
9836
9837                 DQS Duty Cycle Correction
9838                 PSU_DDR_PHY_DX7GCR0_DQSDCC                                                      0x0
9839
9840                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9841                 PSU_DDR_PHY_DX7GCR0_RDDLY                                                       0x8
9842
9843                 Reserved. Return zeroes on reads.
9844                 PSU_DDR_PHY_DX7GCR0_RESERVED_19_14                                              0x0
9845
9846                 DQSNSE Power Down Receiver
9847                 PSU_DDR_PHY_DX7GCR0_DQSNSEPDR                                                   0x0
9848
9849                 DQSSE Power Down Receiver
9850                 PSU_DDR_PHY_DX7GCR0_DQSSEPDR                                                    0x0
9851
9852                 RTT On Additive Latency
9853                 PSU_DDR_PHY_DX7GCR0_RTTOAL                                                      0x0
9854
9855                 RTT Output Hold
9856                 PSU_DDR_PHY_DX7GCR0_RTTOH                                                       0x3
9857
9858                 Configurable PDR Phase Shift
9859                 PSU_DDR_PHY_DX7GCR0_CPDRSHFT                                                    0x0
9860
9861                 DQSR Power Down
9862                 PSU_DDR_PHY_DX7GCR0_DQSRPD                                                      0x0
9863
9864                 DQSG Power Down Receiver
9865                 PSU_DDR_PHY_DX7GCR0_DQSGPDR                                                     0x0
9866
9867                 Reserved. Return zeroes on reads.
9868                 PSU_DDR_PHY_DX7GCR0_RESERVED_4                                                  0x0
9869
9870                 DQSG On-Die Termination
9871                 PSU_DDR_PHY_DX7GCR0_DQSGODT                                                     0x0
9872
9873                 DQSG Output Enable
9874                 PSU_DDR_PHY_DX7GCR0_DQSGOE                                                      0x1
9875
9876                 Reserved. Return zeroes on reads.
9877                 PSU_DDR_PHY_DX7GCR0_RESERVED_1_0                                                0x0
9878
9879                 DATX8 n General Configuration Register 0
9880                 (OFFSET, MASK, VALUE)      (0XFD080E00, 0xFFFFFFFFU ,0x40800604U)
9881                 RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK |  0 );
9882
9883                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT
9884                         | 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT
9885                         | 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
9886                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT
9887                         | 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT
9888                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
9889                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
9890                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
9891                         | 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT
9892                         | 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT
9893                         | 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
9894                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT
9895                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
9896                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
9897                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT
9898                         | 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT
9899                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
9900                         |  0 ) & RegMask); */
9901                 PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9902         /*############################################################################################################################ */
9903
9904                 /*Register : DX7GCR1 @ 0XFD080E04</p>
9905
9906                 Enables the PDR mode for DQ[7:0]
9907                 PSU_DDR_PHY_DX7GCR1_DXPDRMODE                                                   0x0
9908
9909                 Reserved. Returns zeroes on reads.
9910                 PSU_DDR_PHY_DX7GCR1_RESERVED_15                                                 0x0
9911
9912                 Select the delayed or non-delayed read data strobe #
9913                 PSU_DDR_PHY_DX7GCR1_QSNSEL                                                      0x1
9914
9915                 Select the delayed or non-delayed read data strobe
9916                 PSU_DDR_PHY_DX7GCR1_QSSEL                                                       0x1
9917
9918                 Enables Read Data Strobe in a byte lane
9919                 PSU_DDR_PHY_DX7GCR1_OEEN                                                        0x1
9920
9921                 Enables PDR in a byte lane
9922                 PSU_DDR_PHY_DX7GCR1_PDREN                                                       0x1
9923
9924                 Enables ODT/TE in a byte lane
9925                 PSU_DDR_PHY_DX7GCR1_TEEN                                                        0x1
9926
9927                 Enables Write Data strobe in a byte lane
9928                 PSU_DDR_PHY_DX7GCR1_DSEN                                                        0x1
9929
9930                 Enables DM pin in a byte lane
9931                 PSU_DDR_PHY_DX7GCR1_DMEN                                                        0x1
9932
9933                 Enables DQ corresponding to each bit in a byte
9934                 PSU_DDR_PHY_DX7GCR1_DQEN                                                        0xff
9935
9936                 DATX8 n General Configuration Register 1
9937                 (OFFSET, MASK, VALUE)      (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU)
9938                 RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK |  0 );
9939
9940                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
9941                         | 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
9942                         | 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT
9943                         | 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT
9944                         | 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT
9945                         | 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT
9946                         | 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT
9947                         | 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT
9948                         | 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT
9949                         | 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT
9950                         |  0 ) & RegMask); */
9951                 PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9952         /*############################################################################################################################ */
9953
9954                 /*Register : DX7GCR4 @ 0XFD080E10</p>
9955
9956                 Byte lane VREF IOM (Used only by D4MU IOs)
9957                 PSU_DDR_PHY_DX7GCR4_RESERVED_31_29                                              0x0
9958
9959                 Byte Lane VREF Pad Enable
9960                 PSU_DDR_PHY_DX7GCR4_DXREFPEN                                                    0x0
9961
9962                 Byte Lane Internal VREF Enable
9963                 PSU_DDR_PHY_DX7GCR4_DXREFEEN                                                    0x3
9964
9965                 Byte Lane Single-End VREF Enable
9966                 PSU_DDR_PHY_DX7GCR4_DXREFSEN                                                    0x1
9967
9968                 Reserved. Returns zeros on reads.
9969                 PSU_DDR_PHY_DX7GCR4_RESERVED_24                                                 0x0
9970
9971                 External VREF generator REFSEL range select
9972                 PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE                                              0x0
9973
9974                 Byte Lane External VREF Select
9975                 PSU_DDR_PHY_DX7GCR4_DXREFESEL                                                   0x0
9976
9977                 Single ended VREF generator REFSEL range select
9978                 PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE                                              0x1
9979
9980                 Byte Lane Single-End VREF Select
9981                 PSU_DDR_PHY_DX7GCR4_DXREFSSEL                                                   0x30
9982
9983                 Reserved. Returns zeros on reads.
9984                 PSU_DDR_PHY_DX7GCR4_RESERVED_7_6                                                0x0
9985
9986                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9987                 PSU_DDR_PHY_DX7GCR4_DXREFIEN                                                    0xf
9988
9989                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9990                 PSU_DDR_PHY_DX7GCR4_DXREFIMON                                                   0x0
9991
9992                 DATX8 n General Configuration Register 4
9993                 (OFFSET, MASK, VALUE)      (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU)
9994                 RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK |  0 );
9995
9996                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
9997                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
9998                         | 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
9999                         | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
10000                         | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
10001                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
10002                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
10003                         | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
10004                         | 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
10005                         | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
10006                         | 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
10007                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
10008                         |  0 ) & RegMask); */
10009                 PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
10010         /*############################################################################################################################ */
10011
10012                 /*Register : DX7GCR5 @ 0XFD080E14</p>
10013
10014                 Reserved. Returns zeros on reads.
10015                 PSU_DDR_PHY_DX7GCR5_RESERVED_31                                                 0x0
10016
10017                 Byte Lane internal VREF Select for Rank 3
10018                 PSU_DDR_PHY_DX7GCR5_DXREFISELR3                                                 0x9
10019
10020                 Reserved. Returns zeros on reads.
10021                 PSU_DDR_PHY_DX7GCR5_RESERVED_23                                                 0x0
10022
10023                 Byte Lane internal VREF Select for Rank 2
10024                 PSU_DDR_PHY_DX7GCR5_DXREFISELR2                                                 0x9
10025
10026                 Reserved. Returns zeros on reads.
10027                 PSU_DDR_PHY_DX7GCR5_RESERVED_15                                                 0x0
10028
10029                 Byte Lane internal VREF Select for Rank 1
10030                 PSU_DDR_PHY_DX7GCR5_DXREFISELR1                                                 0x4f
10031
10032                 Reserved. Returns zeros on reads.
10033                 PSU_DDR_PHY_DX7GCR5_RESERVED_7                                                  0x0
10034
10035                 Byte Lane internal VREF Select for Rank 0
10036                 PSU_DDR_PHY_DX7GCR5_DXREFISELR0                                                 0x4f
10037
10038                 DATX8 n General Configuration Register 5
10039                 (OFFSET, MASK, VALUE)      (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU)
10040                 RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK |  0 );
10041
10042                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
10043                         | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
10044                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
10045                         | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
10046                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
10047                         | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
10048                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
10049                         | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
10050                         |  0 ) & RegMask); */
10051                 PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
10052         /*############################################################################################################################ */
10053
10054                 /*Register : DX7GCR6 @ 0XFD080E18</p>
10055
10056                 Reserved. Returns zeros on reads.
10057                 PSU_DDR_PHY_DX7GCR6_RESERVED_31_30                                              0x0
10058
10059                 DRAM DQ VREF Select for Rank3
10060                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR3                                                  0x9
10061
10062                 Reserved. Returns zeros on reads.
10063                 PSU_DDR_PHY_DX7GCR6_RESERVED_23_22                                              0x0
10064
10065                 DRAM DQ VREF Select for Rank2
10066                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR2                                                  0x9
10067
10068                 Reserved. Returns zeros on reads.
10069                 PSU_DDR_PHY_DX7GCR6_RESERVED_15_14                                              0x0
10070
10071                 DRAM DQ VREF Select for Rank1
10072                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR1                                                  0x2b
10073
10074                 Reserved. Returns zeros on reads.
10075                 PSU_DDR_PHY_DX7GCR6_RESERVED_7_6                                                0x0
10076
10077                 DRAM DQ VREF Select for Rank0
10078                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR0                                                  0x2b
10079
10080                 DATX8 n General Configuration Register 6
10081                 (OFFSET, MASK, VALUE)      (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU)
10082                 RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK |  0 );
10083
10084                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
10085                         | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
10086                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
10087                         | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
10088                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
10089                         | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
10090                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
10091                         | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
10092                         |  0 ) & RegMask); */
10093                 PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
10094         /*############################################################################################################################ */
10095
10096                 /*Register : DX7LCDLR2 @ 0XFD080E88</p>
10097
10098                 Reserved. Return zeroes on reads.
10099                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25                                            0x0
10100
10101                 Reserved. Caution, do not write to this register field.
10102                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16                                            0x0
10103
10104                 Reserved. Return zeroes on reads.
10105                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9                                             0x0
10106
10107                 Read DQS Gating Delay
10108                 PSU_DDR_PHY_DX7LCDLR2_DQSGD                                                     0xa
10109
10110                 DATX8 n Local Calibrated Delay Line Register 2
10111                 (OFFSET, MASK, VALUE)      (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU)
10112                 RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK |  0 );
10113
10114                 RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT
10115                         | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT
10116                         | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT
10117                         | 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT
10118                         |  0 ) & RegMask); */
10119                 PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU);
10120         /*############################################################################################################################ */
10121
10122                 /*Register : DX7GTR0 @ 0XFD080EC0</p>
10123
10124                 Reserved. Return zeroes on reads.
10125                 PSU_DDR_PHY_DX7GTR0_RESERVED_31_24                                              0x0
10126
10127                 DQ Write Path Latency Pipeline
10128                 PSU_DDR_PHY_DX7GTR0_WDQSL                                                       0x0
10129
10130                 Reserved. Caution, do not write to this register field.
10131                 PSU_DDR_PHY_DX7GTR0_RESERVED_23_20                                              0x0
10132
10133                 Write Leveling System Latency
10134                 PSU_DDR_PHY_DX7GTR0_WLSL                                                        0x2
10135
10136                 Reserved. Return zeroes on reads.
10137                 PSU_DDR_PHY_DX7GTR0_RESERVED_15_13                                              0x0
10138
10139                 Reserved. Caution, do not write to this register field.
10140                 PSU_DDR_PHY_DX7GTR0_RESERVED_12_8                                               0x0
10141
10142                 Reserved. Return zeroes on reads.
10143                 PSU_DDR_PHY_DX7GTR0_RESERVED_7_5                                                0x0
10144
10145                 DQS Gating System Latency
10146                 PSU_DDR_PHY_DX7GTR0_DGSL                                                        0x0
10147
10148                 DATX8 n General Timing Register 0
10149                 (OFFSET, MASK, VALUE)      (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U)
10150                 RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK |  0 );
10151
10152                 RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT
10153                         | 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT
10154                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT
10155                         | 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT
10156                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT
10157                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT
10158                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT
10159                         | 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT
10160                         |  0 ) & RegMask); */
10161                 PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
10162         /*############################################################################################################################ */
10163
10164                 /*Register : DX8GCR0 @ 0XFD080F00</p>
10165
10166                 Calibration Bypass
10167                 PSU_DDR_PHY_DX8GCR0_CALBYP                                                      0x0
10168
10169                 Master Delay Line Enable
10170                 PSU_DDR_PHY_DX8GCR0_MDLEN                                                       0x1
10171
10172                 Configurable ODT(TE) Phase Shift
10173                 PSU_DDR_PHY_DX8GCR0_CODTSHFT                                                    0x0
10174
10175                 DQS Duty Cycle Correction
10176                 PSU_DDR_PHY_DX8GCR0_DQSDCC                                                      0x0
10177
10178                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
10179                 PSU_DDR_PHY_DX8GCR0_RDDLY                                                       0x8
10180
10181                 Reserved. Return zeroes on reads.
10182                 PSU_DDR_PHY_DX8GCR0_RESERVED_19_14                                              0x0
10183
10184                 DQSNSE Power Down Receiver
10185                 PSU_DDR_PHY_DX8GCR0_DQSNSEPDR                                                   0x0
10186
10187                 DQSSE Power Down Receiver
10188                 PSU_DDR_PHY_DX8GCR0_DQSSEPDR                                                    0x0
10189
10190                 RTT On Additive Latency
10191                 PSU_DDR_PHY_DX8GCR0_RTTOAL                                                      0x0
10192
10193                 RTT Output Hold
10194                 PSU_DDR_PHY_DX8GCR0_RTTOH                                                       0x3
10195
10196                 Configurable PDR Phase Shift
10197                 PSU_DDR_PHY_DX8GCR0_CPDRSHFT                                                    0x0
10198
10199                 DQSR Power Down
10200                 PSU_DDR_PHY_DX8GCR0_DQSRPD                                                      0x0
10201
10202                 DQSG Power Down Receiver
10203                 PSU_DDR_PHY_DX8GCR0_DQSGPDR                                                     0x1
10204
10205                 Reserved. Return zeroes on reads.
10206                 PSU_DDR_PHY_DX8GCR0_RESERVED_4                                                  0x0
10207
10208                 DQSG On-Die Termination
10209                 PSU_DDR_PHY_DX8GCR0_DQSGODT                                                     0x0
10210
10211                 DQSG Output Enable
10212                 PSU_DDR_PHY_DX8GCR0_DQSGOE                                                      0x1
10213
10214                 Reserved. Return zeroes on reads.
10215                 PSU_DDR_PHY_DX8GCR0_RESERVED_1_0                                                0x0
10216
10217                 DATX8 n General Configuration Register 0
10218                 (OFFSET, MASK, VALUE)      (0XFD080F00, 0xFFFFFFFFU ,0x40800624U)
10219                 RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK |  0 );
10220
10221                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT
10222                         | 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT
10223                         | 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
10224                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT
10225                         | 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT
10226                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
10227                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
10228                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
10229                         | 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT
10230                         | 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT
10231                         | 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
10232                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT
10233                         | 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
10234                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
10235                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT
10236                         | 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT
10237                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
10238                         |  0 ) & RegMask); */
10239                 PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U);
10240         /*############################################################################################################################ */
10241
10242                 /*Register : DX8GCR1 @ 0XFD080F04</p>
10243
10244                 Enables the PDR mode for DQ[7:0]
10245                 PSU_DDR_PHY_DX8GCR1_DXPDRMODE                                                   0x0
10246
10247                 Reserved. Returns zeroes on reads.
10248                 PSU_DDR_PHY_DX8GCR1_RESERVED_15                                                 0x0
10249
10250                 Select the delayed or non-delayed read data strobe #
10251                 PSU_DDR_PHY_DX8GCR1_QSNSEL                                                      0x1
10252
10253                 Select the delayed or non-delayed read data strobe
10254                 PSU_DDR_PHY_DX8GCR1_QSSEL                                                       0x1
10255
10256                 Enables Read Data Strobe in a byte lane
10257                 PSU_DDR_PHY_DX8GCR1_OEEN                                                        0x1
10258
10259                 Enables PDR in a byte lane
10260                 PSU_DDR_PHY_DX8GCR1_PDREN                                                       0x1
10261
10262                 Enables ODT/TE in a byte lane
10263                 PSU_DDR_PHY_DX8GCR1_TEEN                                                        0x1
10264
10265                 Enables Write Data strobe in a byte lane
10266                 PSU_DDR_PHY_DX8GCR1_DSEN                                                        0x1
10267
10268                 Enables DM pin in a byte lane
10269                 PSU_DDR_PHY_DX8GCR1_DMEN                                                        0x1
10270
10271                 Enables DQ corresponding to each bit in a byte
10272                 PSU_DDR_PHY_DX8GCR1_DQEN                                                        0x0
10273
10274                 DATX8 n General Configuration Register 1
10275                 (OFFSET, MASK, VALUE)      (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U)
10276                 RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK |  0 );
10277
10278                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
10279                         | 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
10280                         | 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT
10281                         | 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT
10282                         | 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT
10283                         | 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT
10284                         | 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT
10285                         | 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT
10286                         | 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT
10287                         | 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT
10288                         |  0 ) & RegMask); */
10289                 PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U);
10290         /*############################################################################################################################ */
10291
10292                 /*Register : DX8GCR4 @ 0XFD080F10</p>
10293
10294                 Byte lane VREF IOM (Used only by D4MU IOs)
10295                 PSU_DDR_PHY_DX8GCR4_RESERVED_31_29                                              0x0
10296
10297                 Byte Lane VREF Pad Enable
10298                 PSU_DDR_PHY_DX8GCR4_DXREFPEN                                                    0x0
10299
10300                 Byte Lane Internal VREF Enable
10301                 PSU_DDR_PHY_DX8GCR4_DXREFEEN                                                    0x3
10302
10303                 Byte Lane Single-End VREF Enable
10304                 PSU_DDR_PHY_DX8GCR4_DXREFSEN                                                    0x1
10305
10306                 Reserved. Returns zeros on reads.
10307                 PSU_DDR_PHY_DX8GCR4_RESERVED_24                                                 0x0
10308
10309                 External VREF generator REFSEL range select
10310                 PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE                                              0x0
10311
10312                 Byte Lane External VREF Select
10313                 PSU_DDR_PHY_DX8GCR4_DXREFESEL                                                   0x0
10314
10315                 Single ended VREF generator REFSEL range select
10316                 PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE                                              0x1
10317
10318                 Byte Lane Single-End VREF Select
10319                 PSU_DDR_PHY_DX8GCR4_DXREFSSEL                                                   0x30
10320
10321                 Reserved. Returns zeros on reads.
10322                 PSU_DDR_PHY_DX8GCR4_RESERVED_7_6                                                0x0
10323
10324                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
10325                 PSU_DDR_PHY_DX8GCR4_DXREFIEN                                                    0xf
10326
10327                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
10328                 PSU_DDR_PHY_DX8GCR4_DXREFIMON                                                   0x0
10329
10330                 DATX8 n General Configuration Register 4
10331                 (OFFSET, MASK, VALUE)      (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU)
10332                 RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK |  0 );
10333
10334                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
10335                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
10336                         | 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
10337                         | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
10338                         | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
10339                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
10340                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
10341                         | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
10342                         | 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
10343                         | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
10344                         | 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
10345                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
10346                         |  0 ) & RegMask); */
10347                 PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
10348         /*############################################################################################################################ */
10349
10350                 /*Register : DX8GCR5 @ 0XFD080F14</p>
10351
10352                 Reserved. Returns zeros on reads.
10353                 PSU_DDR_PHY_DX8GCR5_RESERVED_31                                                 0x0
10354
10355                 Byte Lane internal VREF Select for Rank 3
10356                 PSU_DDR_PHY_DX8GCR5_DXREFISELR3                                                 0x9
10357
10358                 Reserved. Returns zeros on reads.
10359                 PSU_DDR_PHY_DX8GCR5_RESERVED_23                                                 0x0
10360
10361                 Byte Lane internal VREF Select for Rank 2
10362                 PSU_DDR_PHY_DX8GCR5_DXREFISELR2                                                 0x9
10363
10364                 Reserved. Returns zeros on reads.
10365                 PSU_DDR_PHY_DX8GCR5_RESERVED_15                                                 0x0
10366
10367                 Byte Lane internal VREF Select for Rank 1
10368                 PSU_DDR_PHY_DX8GCR5_DXREFISELR1                                                 0x4f
10369
10370                 Reserved. Returns zeros on reads.
10371                 PSU_DDR_PHY_DX8GCR5_RESERVED_7                                                  0x0
10372
10373                 Byte Lane internal VREF Select for Rank 0
10374                 PSU_DDR_PHY_DX8GCR5_DXREFISELR0                                                 0x4f
10375
10376                 DATX8 n General Configuration Register 5
10377                 (OFFSET, MASK, VALUE)      (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU)
10378                 RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK |  0 );
10379
10380                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
10381                         | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
10382                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
10383                         | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
10384                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
10385                         | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
10386                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
10387                         | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
10388                         |  0 ) & RegMask); */
10389                 PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
10390         /*############################################################################################################################ */
10391
10392                 /*Register : DX8GCR6 @ 0XFD080F18</p>
10393
10394                 Reserved. Returns zeros on reads.
10395                 PSU_DDR_PHY_DX8GCR6_RESERVED_31_30                                              0x0
10396
10397                 DRAM DQ VREF Select for Rank3
10398                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR3                                                  0x9
10399
10400                 Reserved. Returns zeros on reads.
10401                 PSU_DDR_PHY_DX8GCR6_RESERVED_23_22                                              0x0
10402
10403                 DRAM DQ VREF Select for Rank2
10404                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR2                                                  0x9
10405
10406                 Reserved. Returns zeros on reads.
10407                 PSU_DDR_PHY_DX8GCR6_RESERVED_15_14                                              0x0
10408
10409                 DRAM DQ VREF Select for Rank1
10410                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR1                                                  0x2b
10411
10412                 Reserved. Returns zeros on reads.
10413                 PSU_DDR_PHY_DX8GCR6_RESERVED_7_6                                                0x0
10414
10415                 DRAM DQ VREF Select for Rank0
10416                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR0                                                  0x2b
10417
10418                 DATX8 n General Configuration Register 6
10419                 (OFFSET, MASK, VALUE)      (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU)
10420                 RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK |  0 );
10421
10422                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
10423                         | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
10424                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
10425                         | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
10426                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
10427                         | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
10428                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
10429                         | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
10430                         |  0 ) & RegMask); */
10431                 PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
10432         /*############################################################################################################################ */
10433
10434                 /*Register : DX8LCDLR2 @ 0XFD080F88</p>
10435
10436                 Reserved. Return zeroes on reads.
10437                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25                                            0x0
10438
10439                 Reserved. Caution, do not write to this register field.
10440                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16                                            0x0
10441
10442                 Reserved. Return zeroes on reads.
10443                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9                                             0x0
10444
10445                 Read DQS Gating Delay
10446                 PSU_DDR_PHY_DX8LCDLR2_DQSGD                                                     0x0
10447
10448                 DATX8 n Local Calibrated Delay Line Register 2
10449                 (OFFSET, MASK, VALUE)      (0XFD080F88, 0xFFFFFFFFU ,0x00000000U)
10450                 RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK |  0 );
10451
10452                 RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT
10453                         | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT
10454                         | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT
10455                         | 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT
10456                         |  0 ) & RegMask); */
10457                 PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
10458         /*############################################################################################################################ */
10459
10460                 /*Register : DX8GTR0 @ 0XFD080FC0</p>
10461
10462                 Reserved. Return zeroes on reads.
10463                 PSU_DDR_PHY_DX8GTR0_RESERVED_31_24                                              0x0
10464
10465                 DQ Write Path Latency Pipeline
10466                 PSU_DDR_PHY_DX8GTR0_WDQSL                                                       0x0
10467
10468                 Reserved. Caution, do not write to this register field.
10469                 PSU_DDR_PHY_DX8GTR0_RESERVED_23_20                                              0x0
10470
10471                 Write Leveling System Latency
10472                 PSU_DDR_PHY_DX8GTR0_WLSL                                                        0x2
10473
10474                 Reserved. Return zeroes on reads.
10475                 PSU_DDR_PHY_DX8GTR0_RESERVED_15_13                                              0x0
10476
10477                 Reserved. Caution, do not write to this register field.
10478                 PSU_DDR_PHY_DX8GTR0_RESERVED_12_8                                               0x0
10479
10480                 Reserved. Return zeroes on reads.
10481                 PSU_DDR_PHY_DX8GTR0_RESERVED_7_5                                                0x0
10482
10483                 DQS Gating System Latency
10484                 PSU_DDR_PHY_DX8GTR0_DGSL                                                        0x0
10485
10486                 DATX8 n General Timing Register 0
10487                 (OFFSET, MASK, VALUE)      (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U)
10488                 RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK |  0 );
10489
10490                 RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT
10491                         | 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT
10492                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT
10493                         | 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT
10494                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT
10495                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT
10496                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT
10497                         | 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT
10498                         |  0 ) & RegMask); */
10499                 PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
10500         /*############################################################################################################################ */
10501
10502                 /*Register : DX8SL0OSC @ 0XFD081400</p>
10503
10504                 Reserved. Return zeroes on reads.
10505                 PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30                                            0x0
10506
10507                 Enable Clock Gating for DX ddr_clk
10508                 PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK                                               0x2
10509
10510                 Enable Clock Gating for DX ctl_rd_clk
10511                 PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK                                              0x2
10512
10513                 Enable Clock Gating for DX ctl_clk
10514                 PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK                                              0x2
10515
10516                 Selects the level to which clocks will be stalled when clock gating is enabled.
10517                 PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL                                                  0x0
10518
10519                 Loopback Mode
10520                 PSU_DDR_PHY_DX8SL0OSC_LBMODE                                                    0x0
10521
10522                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
10523                 PSU_DDR_PHY_DX8SL0OSC_LBGSDQS                                                   0x0
10524
10525                 Loopback DQS Gating
10526                 PSU_DDR_PHY_DX8SL0OSC_LBGDQS                                                    0x0
10527
10528                 Loopback DQS Shift
10529                 PSU_DDR_PHY_DX8SL0OSC_LBDQSS                                                    0x0
10530
10531                 PHY High-Speed Reset
10532                 PSU_DDR_PHY_DX8SL0OSC_PHYHRST                                                   0x1
10533
10534                 PHY FIFO Reset
10535                 PSU_DDR_PHY_DX8SL0OSC_PHYFRST                                                   0x1
10536
10537                 Delay Line Test Start
10538                 PSU_DDR_PHY_DX8SL0OSC_DLTST                                                     0x0
10539
10540                 Delay Line Test Mode
10541                 PSU_DDR_PHY_DX8SL0OSC_DLTMODE                                                   0x0
10542
10543                 Reserved. Caution, do not write to this register field.
10544                 PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11                                            0x3
10545
10546                 Oscillator Mode Write-Data Delay Line Select
10547                 PSU_DDR_PHY_DX8SL0OSC_OSCWDDL                                                   0x3
10548
10549                 Reserved. Caution, do not write to this register field.
10550                 PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7                                              0x3
10551
10552                 Oscillator Mode Write-Leveling Delay Line Select
10553                 PSU_DDR_PHY_DX8SL0OSC_OSCWDL                                                    0x3
10554
10555                 Oscillator Mode Division
10556                 PSU_DDR_PHY_DX8SL0OSC_OSCDIV                                                    0xf
10557
10558                 Oscillator Enable
10559                 PSU_DDR_PHY_DX8SL0OSC_OSCEN                                                     0x0
10560
10561                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
10562                 (OFFSET, MASK, VALUE)      (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU)
10563                 RegMask = (DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL0OSC_LBMODE_MASK | DDR_PHY_DX8SL0OSC_LBGSDQS_MASK | DDR_PHY_DX8SL0OSC_LBGDQS_MASK | DDR_PHY_DX8SL0OSC_LBDQSS_MASK | DDR_PHY_DX8SL0OSC_PHYHRST_MASK | DDR_PHY_DX8SL0OSC_PHYFRST_MASK | DDR_PHY_DX8SL0OSC_DLTST_MASK | DDR_PHY_DX8SL0OSC_DLTMODE_MASK | DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL0OSC_OSCWDDL_MASK | DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL0OSC_OSCWDL_MASK | DDR_PHY_DX8SL0OSC_OSCDIV_MASK | DDR_PHY_DX8SL0OSC_OSCEN_MASK |  0 );
10564
10565                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
10566                         | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
10567                         | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
10568                         | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
10569                         | 0x00000000U << DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
10570                         | 0x00000000U << DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
10571                         | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
10572                         | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
10573                         | 0x00000000U << DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
10574                         | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
10575                         | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
10576                         | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTST_SHIFT
10577                         | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
10578                         | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
10579                         | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
10580                         | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
10581                         | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
10582                         | 0x0000000FU << DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
10583                         | 0x00000000U << DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
10584                         |  0 ) & RegMask); */
10585                 PSU_Mask_Write (DDR_PHY_DX8SL0OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
10586         /*############################################################################################################################ */
10587
10588                 /*Register : DX8SL0DQSCTL @ 0XFD08141C</p>
10589
10590                 Reserved. Return zeroes on reads.
10591                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25                                         0x0
10592
10593                 Read Path Rise-to-Rise Mode
10594                 PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE                                                0x1
10595
10596                 Reserved. Return zeroes on reads.
10597                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22                                         0x0
10598
10599                 Write Path Rise-to-Rise Mode
10600                 PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE                                                0x1
10601
10602                 DQS Gate Extension
10603                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX                                                  0x0
10604
10605                 Low Power PLL Power Down
10606                 PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD                                                0x1
10607
10608                 Low Power I/O Power Down
10609                 PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD                                                 0x1
10610
10611                 Reserved. Return zeroes on reads.
10612                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15                                         0x0
10613
10614                 QS Counter Enable
10615                 PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN                                                0x1
10616
10617                 Unused DQ I/O Mode
10618                 PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM                                                 0x0
10619
10620                 Reserved. Return zeroes on reads.
10621                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10                                         0x0
10622
10623                 Data Slew Rate
10624                 PSU_DDR_PHY_DX8SL0DQSCTL_DXSR                                                   0x3
10625
10626                 DQS_N Resistor
10627                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES                                                0x0
10628
10629                 DQS Resistor
10630                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES                                                 0x0
10631
10632                 DATX8 0-1 DQS Control Register
10633                 (OFFSET, MASK, VALUE)      (0XFD08141C, 0xFFFFFFFFU ,0x01264300U)
10634                 RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK |  0 );
10635
10636                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
10637                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
10638                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
10639                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
10640                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
10641                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
10642                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
10643                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
10644                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
10645                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
10646                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
10647                         | 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
10648                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
10649                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
10650                         |  0 ) & RegMask); */
10651                 PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
10652         /*############################################################################################################################ */
10653
10654                 /*Register : DX8SL0DXCTL2 @ 0XFD08142C</p>
10655
10656                 Reserved. Return zeroes on reads.
10657                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24                                         0x0
10658
10659                 Configurable Read Data Enable
10660                 PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN                                                  0x0
10661
10662                 OX Extension during Post-amble
10663                 PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX                                                 0x0
10664
10665                 OE Extension during Pre-amble
10666                 PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX                                                 0x1
10667
10668                 Reserved. Return zeroes on reads.
10669                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17                                            0x0
10670
10671                 I/O Assisted Gate Select
10672                 PSU_DDR_PHY_DX8SL0DXCTL2_IOAG                                                   0x0
10673
10674                 I/O Loopback Select
10675                 PSU_DDR_PHY_DX8SL0DXCTL2_IOLB                                                   0x0
10676
10677                 Reserved. Return zeroes on reads.
10678                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13                                         0x0
10679
10680                 Low Power Wakeup Threshold
10681                 PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH                                         0xc
10682
10683                 Read Data Bus Inversion Enable
10684                 PSU_DDR_PHY_DX8SL0DXCTL2_RDBI                                                   0x0
10685
10686                 Write Data Bus Inversion Enable
10687                 PSU_DDR_PHY_DX8SL0DXCTL2_WDBI                                                   0x0
10688
10689                 PUB Read FIFO Bypass
10690                 PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP                                                 0x0
10691
10692                 DATX8 Receive FIFO Read Mode
10693                 PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE                                                 0x0
10694
10695                 Disables the Read FIFO Reset
10696                 PSU_DDR_PHY_DX8SL0DXCTL2_DISRST                                                 0x0
10697
10698                 Read DQS Gate I/O Loopback
10699                 PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB                                                 0x0
10700
10701                 Reserved. Return zeroes on reads.
10702                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0                                             0x0
10703
10704                 DATX8 0-1 DX Control Register 2
10705                 (OFFSET, MASK, VALUE)      (0XFD08142C, 0xFFFFFFFFU ,0x00041800U)
10706                 RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK |  0 );
10707
10708                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
10709                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
10710                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
10711                         | 0x00000001U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
10712                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
10713                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
10714                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
10715                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
10716                         | 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
10717                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
10718                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
10719                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
10720                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
10721                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
10722                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
10723                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
10724                         |  0 ) & RegMask); */
10725                 PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
10726         /*############################################################################################################################ */
10727
10728                 /*Register : DX8SL0IOCR @ 0XFD081430</p>
10729
10730                 Reserved. Return zeroes on reads.
10731                 PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31                                              0x0
10732
10733                 PVREF_DAC REFSEL range select
10734                 PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE                                               0x7
10735
10736                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10737                 PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM                                                0x0
10738
10739                 DX IO Mode
10740                 PSU_DDR_PHY_DX8SL0IOCR_DXIOM                                                    0x2
10741
10742                 DX IO Transmitter Mode
10743                 PSU_DDR_PHY_DX8SL0IOCR_DXTXM                                                    0x0
10744
10745                 DX IO Receiver Mode
10746                 PSU_DDR_PHY_DX8SL0IOCR_DXRXM                                                    0x0
10747
10748                 DATX8 0-1 I/O Configuration Register
10749                 (OFFSET, MASK, VALUE)      (0XFD081430, 0xFFFFFFFFU ,0x70800000U)
10750                 RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK |  0 );
10751
10752                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
10753                         | 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
10754                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
10755                         | 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
10756                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
10757                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
10758                         |  0 ) & RegMask); */
10759                 PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
10760         /*############################################################################################################################ */
10761
10762                 /*Register : DX8SL1OSC @ 0XFD081440</p>
10763
10764                 Reserved. Return zeroes on reads.
10765                 PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30                                            0x0
10766
10767                 Enable Clock Gating for DX ddr_clk
10768                 PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK                                               0x2
10769
10770                 Enable Clock Gating for DX ctl_rd_clk
10771                 PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK                                              0x2
10772
10773                 Enable Clock Gating for DX ctl_clk
10774                 PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK                                              0x2
10775
10776                 Selects the level to which clocks will be stalled when clock gating is enabled.
10777                 PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL                                                  0x0
10778
10779                 Loopback Mode
10780                 PSU_DDR_PHY_DX8SL1OSC_LBMODE                                                    0x0
10781
10782                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
10783                 PSU_DDR_PHY_DX8SL1OSC_LBGSDQS                                                   0x0
10784
10785                 Loopback DQS Gating
10786                 PSU_DDR_PHY_DX8SL1OSC_LBGDQS                                                    0x0
10787
10788                 Loopback DQS Shift
10789                 PSU_DDR_PHY_DX8SL1OSC_LBDQSS                                                    0x0
10790
10791                 PHY High-Speed Reset
10792                 PSU_DDR_PHY_DX8SL1OSC_PHYHRST                                                   0x1
10793
10794                 PHY FIFO Reset
10795                 PSU_DDR_PHY_DX8SL1OSC_PHYFRST                                                   0x1
10796
10797                 Delay Line Test Start
10798                 PSU_DDR_PHY_DX8SL1OSC_DLTST                                                     0x0
10799
10800                 Delay Line Test Mode
10801                 PSU_DDR_PHY_DX8SL1OSC_DLTMODE                                                   0x0
10802
10803                 Reserved. Caution, do not write to this register field.
10804                 PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11                                            0x3
10805
10806                 Oscillator Mode Write-Data Delay Line Select
10807                 PSU_DDR_PHY_DX8SL1OSC_OSCWDDL                                                   0x3
10808
10809                 Reserved. Caution, do not write to this register field.
10810                 PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7                                              0x3
10811
10812                 Oscillator Mode Write-Leveling Delay Line Select
10813                 PSU_DDR_PHY_DX8SL1OSC_OSCWDL                                                    0x3
10814
10815                 Oscillator Mode Division
10816                 PSU_DDR_PHY_DX8SL1OSC_OSCDIV                                                    0xf
10817
10818                 Oscillator Enable
10819                 PSU_DDR_PHY_DX8SL1OSC_OSCEN                                                     0x0
10820
10821                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
10822                 (OFFSET, MASK, VALUE)      (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU)
10823                 RegMask = (DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL1OSC_LBMODE_MASK | DDR_PHY_DX8SL1OSC_LBGSDQS_MASK | DDR_PHY_DX8SL1OSC_LBGDQS_MASK | DDR_PHY_DX8SL1OSC_LBDQSS_MASK | DDR_PHY_DX8SL1OSC_PHYHRST_MASK | DDR_PHY_DX8SL1OSC_PHYFRST_MASK | DDR_PHY_DX8SL1OSC_DLTST_MASK | DDR_PHY_DX8SL1OSC_DLTMODE_MASK | DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL1OSC_OSCWDDL_MASK | DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL1OSC_OSCWDL_MASK | DDR_PHY_DX8SL1OSC_OSCDIV_MASK | DDR_PHY_DX8SL1OSC_OSCEN_MASK |  0 );
10824
10825                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
10826                         | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
10827                         | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
10828                         | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
10829                         | 0x00000000U << DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
10830                         | 0x00000000U << DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
10831                         | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
10832                         | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
10833                         | 0x00000000U << DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
10834                         | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
10835                         | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
10836                         | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTST_SHIFT
10837                         | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
10838                         | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
10839                         | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
10840                         | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
10841                         | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
10842                         | 0x0000000FU << DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
10843                         | 0x00000000U << DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
10844                         |  0 ) & RegMask); */
10845                 PSU_Mask_Write (DDR_PHY_DX8SL1OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
10846         /*############################################################################################################################ */
10847
10848                 /*Register : DX8SL1DQSCTL @ 0XFD08145C</p>
10849
10850                 Reserved. Return zeroes on reads.
10851                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25                                         0x0
10852
10853                 Read Path Rise-to-Rise Mode
10854                 PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE                                                0x1
10855
10856                 Reserved. Return zeroes on reads.
10857                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22                                         0x0
10858
10859                 Write Path Rise-to-Rise Mode
10860                 PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE                                                0x1
10861
10862                 DQS Gate Extension
10863                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX                                                  0x0
10864
10865                 Low Power PLL Power Down
10866                 PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD                                                0x1
10867
10868                 Low Power I/O Power Down
10869                 PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD                                                 0x1
10870
10871                 Reserved. Return zeroes on reads.
10872                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15                                         0x0
10873
10874                 QS Counter Enable
10875                 PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN                                                0x1
10876
10877                 Unused DQ I/O Mode
10878                 PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM                                                 0x0
10879
10880                 Reserved. Return zeroes on reads.
10881                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10                                         0x0
10882
10883                 Data Slew Rate
10884                 PSU_DDR_PHY_DX8SL1DQSCTL_DXSR                                                   0x3
10885
10886                 DQS_N Resistor
10887                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES                                                0x0
10888
10889                 DQS Resistor
10890                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES                                                 0x0
10891
10892                 DATX8 0-1 DQS Control Register
10893                 (OFFSET, MASK, VALUE)      (0XFD08145C, 0xFFFFFFFFU ,0x01264300U)
10894                 RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK |  0 );
10895
10896                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
10897                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
10898                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
10899                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
10900                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
10901                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
10902                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
10903                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
10904                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
10905                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
10906                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
10907                         | 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
10908                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
10909                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
10910                         |  0 ) & RegMask); */
10911                 PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
10912         /*############################################################################################################################ */
10913
10914                 /*Register : DX8SL1DXCTL2 @ 0XFD08146C</p>
10915
10916                 Reserved. Return zeroes on reads.
10917                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24                                         0x0
10918
10919                 Configurable Read Data Enable
10920                 PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN                                                  0x0
10921
10922                 OX Extension during Post-amble
10923                 PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX                                                 0x0
10924
10925                 OE Extension during Pre-amble
10926                 PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX                                                 0x1
10927
10928                 Reserved. Return zeroes on reads.
10929                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17                                            0x0
10930
10931                 I/O Assisted Gate Select
10932                 PSU_DDR_PHY_DX8SL1DXCTL2_IOAG                                                   0x0
10933
10934                 I/O Loopback Select
10935                 PSU_DDR_PHY_DX8SL1DXCTL2_IOLB                                                   0x0
10936
10937                 Reserved. Return zeroes on reads.
10938                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13                                         0x0
10939
10940                 Low Power Wakeup Threshold
10941                 PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH                                         0xc
10942
10943                 Read Data Bus Inversion Enable
10944                 PSU_DDR_PHY_DX8SL1DXCTL2_RDBI                                                   0x0
10945
10946                 Write Data Bus Inversion Enable
10947                 PSU_DDR_PHY_DX8SL1DXCTL2_WDBI                                                   0x0
10948
10949                 PUB Read FIFO Bypass
10950                 PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP                                                 0x0
10951
10952                 DATX8 Receive FIFO Read Mode
10953                 PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE                                                 0x0
10954
10955                 Disables the Read FIFO Reset
10956                 PSU_DDR_PHY_DX8SL1DXCTL2_DISRST                                                 0x0
10957
10958                 Read DQS Gate I/O Loopback
10959                 PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB                                                 0x0
10960
10961                 Reserved. Return zeroes on reads.
10962                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0                                             0x0
10963
10964                 DATX8 0-1 DX Control Register 2
10965                 (OFFSET, MASK, VALUE)      (0XFD08146C, 0xFFFFFFFFU ,0x00041800U)
10966                 RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK |  0 );
10967
10968                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
10969                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
10970                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
10971                         | 0x00000001U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
10972                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
10973                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
10974                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
10975                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
10976                         | 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
10977                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
10978                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
10979                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
10980                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
10981                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
10982                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
10983                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
10984                         |  0 ) & RegMask); */
10985                 PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
10986         /*############################################################################################################################ */
10987
10988                 /*Register : DX8SL1IOCR @ 0XFD081470</p>
10989
10990                 Reserved. Return zeroes on reads.
10991                 PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31                                              0x0
10992
10993                 PVREF_DAC REFSEL range select
10994                 PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE                                               0x7
10995
10996                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10997                 PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM                                                0x0
10998
10999                 DX IO Mode
11000                 PSU_DDR_PHY_DX8SL1IOCR_DXIOM                                                    0x2
11001
11002                 DX IO Transmitter Mode
11003                 PSU_DDR_PHY_DX8SL1IOCR_DXTXM                                                    0x0
11004
11005                 DX IO Receiver Mode
11006                 PSU_DDR_PHY_DX8SL1IOCR_DXRXM                                                    0x0
11007
11008                 DATX8 0-1 I/O Configuration Register
11009                 (OFFSET, MASK, VALUE)      (0XFD081470, 0xFFFFFFFFU ,0x70800000U)
11010                 RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK |  0 );
11011
11012                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
11013                         | 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
11014                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
11015                         | 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
11016                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
11017                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
11018                         |  0 ) & RegMask); */
11019                 PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11020         /*############################################################################################################################ */
11021
11022                 /*Register : DX8SL2OSC @ 0XFD081480</p>
11023
11024                 Reserved. Return zeroes on reads.
11025                 PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30                                            0x0
11026
11027                 Enable Clock Gating for DX ddr_clk
11028                 PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK                                               0x2
11029
11030                 Enable Clock Gating for DX ctl_rd_clk
11031                 PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK                                              0x2
11032
11033                 Enable Clock Gating for DX ctl_clk
11034                 PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK                                              0x2
11035
11036                 Selects the level to which clocks will be stalled when clock gating is enabled.
11037                 PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL                                                  0x0
11038
11039                 Loopback Mode
11040                 PSU_DDR_PHY_DX8SL2OSC_LBMODE                                                    0x0
11041
11042                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
11043                 PSU_DDR_PHY_DX8SL2OSC_LBGSDQS                                                   0x0
11044
11045                 Loopback DQS Gating
11046                 PSU_DDR_PHY_DX8SL2OSC_LBGDQS                                                    0x0
11047
11048                 Loopback DQS Shift
11049                 PSU_DDR_PHY_DX8SL2OSC_LBDQSS                                                    0x0
11050
11051                 PHY High-Speed Reset
11052                 PSU_DDR_PHY_DX8SL2OSC_PHYHRST                                                   0x1
11053
11054                 PHY FIFO Reset
11055                 PSU_DDR_PHY_DX8SL2OSC_PHYFRST                                                   0x1
11056
11057                 Delay Line Test Start
11058                 PSU_DDR_PHY_DX8SL2OSC_DLTST                                                     0x0
11059
11060                 Delay Line Test Mode
11061                 PSU_DDR_PHY_DX8SL2OSC_DLTMODE                                                   0x0
11062
11063                 Reserved. Caution, do not write to this register field.
11064                 PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11                                            0x3
11065
11066                 Oscillator Mode Write-Data Delay Line Select
11067                 PSU_DDR_PHY_DX8SL2OSC_OSCWDDL                                                   0x3
11068
11069                 Reserved. Caution, do not write to this register field.
11070                 PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7                                              0x3
11071
11072                 Oscillator Mode Write-Leveling Delay Line Select
11073                 PSU_DDR_PHY_DX8SL2OSC_OSCWDL                                                    0x3
11074
11075                 Oscillator Mode Division
11076                 PSU_DDR_PHY_DX8SL2OSC_OSCDIV                                                    0xf
11077
11078                 Oscillator Enable
11079                 PSU_DDR_PHY_DX8SL2OSC_OSCEN                                                     0x0
11080
11081                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
11082                 (OFFSET, MASK, VALUE)      (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU)
11083                 RegMask = (DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL2OSC_LBMODE_MASK | DDR_PHY_DX8SL2OSC_LBGSDQS_MASK | DDR_PHY_DX8SL2OSC_LBGDQS_MASK | DDR_PHY_DX8SL2OSC_LBDQSS_MASK | DDR_PHY_DX8SL2OSC_PHYHRST_MASK | DDR_PHY_DX8SL2OSC_PHYFRST_MASK | DDR_PHY_DX8SL2OSC_DLTST_MASK | DDR_PHY_DX8SL2OSC_DLTMODE_MASK | DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL2OSC_OSCWDDL_MASK | DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL2OSC_OSCWDL_MASK | DDR_PHY_DX8SL2OSC_OSCDIV_MASK | DDR_PHY_DX8SL2OSC_OSCEN_MASK |  0 );
11084
11085                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
11086                         | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
11087                         | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
11088                         | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
11089                         | 0x00000000U << DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
11090                         | 0x00000000U << DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
11091                         | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
11092                         | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
11093                         | 0x00000000U << DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
11094                         | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
11095                         | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
11096                         | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTST_SHIFT
11097                         | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
11098                         | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
11099                         | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
11100                         | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
11101                         | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
11102                         | 0x0000000FU << DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
11103                         | 0x00000000U << DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
11104                         |  0 ) & RegMask); */
11105                 PSU_Mask_Write (DDR_PHY_DX8SL2OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
11106         /*############################################################################################################################ */
11107
11108                 /*Register : DX8SL2DQSCTL @ 0XFD08149C</p>
11109
11110                 Reserved. Return zeroes on reads.
11111                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25                                         0x0
11112
11113                 Read Path Rise-to-Rise Mode
11114                 PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE                                                0x1
11115
11116                 Reserved. Return zeroes on reads.
11117                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22                                         0x0
11118
11119                 Write Path Rise-to-Rise Mode
11120                 PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE                                                0x1
11121
11122                 DQS Gate Extension
11123                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX                                                  0x0
11124
11125                 Low Power PLL Power Down
11126                 PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD                                                0x1
11127
11128                 Low Power I/O Power Down
11129                 PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD                                                 0x1
11130
11131                 Reserved. Return zeroes on reads.
11132                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15                                         0x0
11133
11134                 QS Counter Enable
11135                 PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN                                                0x1
11136
11137                 Unused DQ I/O Mode
11138                 PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM                                                 0x0
11139
11140                 Reserved. Return zeroes on reads.
11141                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10                                         0x0
11142
11143                 Data Slew Rate
11144                 PSU_DDR_PHY_DX8SL2DQSCTL_DXSR                                                   0x3
11145
11146                 DQS_N Resistor
11147                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES                                                0x0
11148
11149                 DQS Resistor
11150                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES                                                 0x0
11151
11152                 DATX8 0-1 DQS Control Register
11153                 (OFFSET, MASK, VALUE)      (0XFD08149C, 0xFFFFFFFFU ,0x01264300U)
11154                 RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK |  0 );
11155
11156                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
11157                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
11158                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
11159                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
11160                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
11161                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
11162                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
11163                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
11164                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
11165                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
11166                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
11167                         | 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
11168                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
11169                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
11170                         |  0 ) & RegMask); */
11171                 PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
11172         /*############################################################################################################################ */
11173
11174                 /*Register : DX8SL2DXCTL2 @ 0XFD0814AC</p>
11175
11176                 Reserved. Return zeroes on reads.
11177                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24                                         0x0
11178
11179                 Configurable Read Data Enable
11180                 PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN                                                  0x0
11181
11182                 OX Extension during Post-amble
11183                 PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX                                                 0x0
11184
11185                 OE Extension during Pre-amble
11186                 PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX                                                 0x1
11187
11188                 Reserved. Return zeroes on reads.
11189                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17                                            0x0
11190
11191                 I/O Assisted Gate Select
11192                 PSU_DDR_PHY_DX8SL2DXCTL2_IOAG                                                   0x0
11193
11194                 I/O Loopback Select
11195                 PSU_DDR_PHY_DX8SL2DXCTL2_IOLB                                                   0x0
11196
11197                 Reserved. Return zeroes on reads.
11198                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13                                         0x0
11199
11200                 Low Power Wakeup Threshold
11201                 PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH                                         0xc
11202
11203                 Read Data Bus Inversion Enable
11204                 PSU_DDR_PHY_DX8SL2DXCTL2_RDBI                                                   0x0
11205
11206                 Write Data Bus Inversion Enable
11207                 PSU_DDR_PHY_DX8SL2DXCTL2_WDBI                                                   0x0
11208
11209                 PUB Read FIFO Bypass
11210                 PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP                                                 0x0
11211
11212                 DATX8 Receive FIFO Read Mode
11213                 PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE                                                 0x0
11214
11215                 Disables the Read FIFO Reset
11216                 PSU_DDR_PHY_DX8SL2DXCTL2_DISRST                                                 0x0
11217
11218                 Read DQS Gate I/O Loopback
11219                 PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB                                                 0x0
11220
11221                 Reserved. Return zeroes on reads.
11222                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0                                             0x0
11223
11224                 DATX8 0-1 DX Control Register 2
11225                 (OFFSET, MASK, VALUE)      (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U)
11226                 RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK |  0 );
11227
11228                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
11229                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
11230                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
11231                         | 0x00000001U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
11232                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
11233                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
11234                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
11235                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
11236                         | 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
11237                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
11238                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
11239                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
11240                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
11241                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
11242                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
11243                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
11244                         |  0 ) & RegMask); */
11245                 PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
11246         /*############################################################################################################################ */
11247
11248                 /*Register : DX8SL2IOCR @ 0XFD0814B0</p>
11249
11250                 Reserved. Return zeroes on reads.
11251                 PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31                                              0x0
11252
11253                 PVREF_DAC REFSEL range select
11254                 PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE                                               0x7
11255
11256                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11257                 PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM                                                0x0
11258
11259                 DX IO Mode
11260                 PSU_DDR_PHY_DX8SL2IOCR_DXIOM                                                    0x2
11261
11262                 DX IO Transmitter Mode
11263                 PSU_DDR_PHY_DX8SL2IOCR_DXTXM                                                    0x0
11264
11265                 DX IO Receiver Mode
11266                 PSU_DDR_PHY_DX8SL2IOCR_DXRXM                                                    0x0
11267
11268                 DATX8 0-1 I/O Configuration Register
11269                 (OFFSET, MASK, VALUE)      (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U)
11270                 RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK |  0 );
11271
11272                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
11273                         | 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
11274                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
11275                         | 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
11276                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
11277                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
11278                         |  0 ) & RegMask); */
11279                 PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11280         /*############################################################################################################################ */
11281
11282                 /*Register : DX8SL3OSC @ 0XFD0814C0</p>
11283
11284                 Reserved. Return zeroes on reads.
11285                 PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30                                            0x0
11286
11287                 Enable Clock Gating for DX ddr_clk
11288                 PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK                                               0x2
11289
11290                 Enable Clock Gating for DX ctl_rd_clk
11291                 PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK                                              0x2
11292
11293                 Enable Clock Gating for DX ctl_clk
11294                 PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK                                              0x2
11295
11296                 Selects the level to which clocks will be stalled when clock gating is enabled.
11297                 PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL                                                  0x0
11298
11299                 Loopback Mode
11300                 PSU_DDR_PHY_DX8SL3OSC_LBMODE                                                    0x0
11301
11302                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
11303                 PSU_DDR_PHY_DX8SL3OSC_LBGSDQS                                                   0x0
11304
11305                 Loopback DQS Gating
11306                 PSU_DDR_PHY_DX8SL3OSC_LBGDQS                                                    0x0
11307
11308                 Loopback DQS Shift
11309                 PSU_DDR_PHY_DX8SL3OSC_LBDQSS                                                    0x0
11310
11311                 PHY High-Speed Reset
11312                 PSU_DDR_PHY_DX8SL3OSC_PHYHRST                                                   0x1
11313
11314                 PHY FIFO Reset
11315                 PSU_DDR_PHY_DX8SL3OSC_PHYFRST                                                   0x1
11316
11317                 Delay Line Test Start
11318                 PSU_DDR_PHY_DX8SL3OSC_DLTST                                                     0x0
11319
11320                 Delay Line Test Mode
11321                 PSU_DDR_PHY_DX8SL3OSC_DLTMODE                                                   0x0
11322
11323                 Reserved. Caution, do not write to this register field.
11324                 PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11                                            0x3
11325
11326                 Oscillator Mode Write-Data Delay Line Select
11327                 PSU_DDR_PHY_DX8SL3OSC_OSCWDDL                                                   0x3
11328
11329                 Reserved. Caution, do not write to this register field.
11330                 PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7                                              0x3
11331
11332                 Oscillator Mode Write-Leveling Delay Line Select
11333                 PSU_DDR_PHY_DX8SL3OSC_OSCWDL                                                    0x3
11334
11335                 Oscillator Mode Division
11336                 PSU_DDR_PHY_DX8SL3OSC_OSCDIV                                                    0xf
11337
11338                 Oscillator Enable
11339                 PSU_DDR_PHY_DX8SL3OSC_OSCEN                                                     0x0
11340
11341                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
11342                 (OFFSET, MASK, VALUE)      (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU)
11343                 RegMask = (DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL3OSC_LBMODE_MASK | DDR_PHY_DX8SL3OSC_LBGSDQS_MASK | DDR_PHY_DX8SL3OSC_LBGDQS_MASK | DDR_PHY_DX8SL3OSC_LBDQSS_MASK | DDR_PHY_DX8SL3OSC_PHYHRST_MASK | DDR_PHY_DX8SL3OSC_PHYFRST_MASK | DDR_PHY_DX8SL3OSC_DLTST_MASK | DDR_PHY_DX8SL3OSC_DLTMODE_MASK | DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL3OSC_OSCWDDL_MASK | DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL3OSC_OSCWDL_MASK | DDR_PHY_DX8SL3OSC_OSCDIV_MASK | DDR_PHY_DX8SL3OSC_OSCEN_MASK |  0 );
11344
11345                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
11346                         | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
11347                         | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
11348                         | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
11349                         | 0x00000000U << DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
11350                         | 0x00000000U << DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
11351                         | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
11352                         | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
11353                         | 0x00000000U << DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
11354                         | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
11355                         | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
11356                         | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTST_SHIFT
11357                         | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
11358                         | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
11359                         | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
11360                         | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
11361                         | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
11362                         | 0x0000000FU << DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
11363                         | 0x00000000U << DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
11364                         |  0 ) & RegMask); */
11365                 PSU_Mask_Write (DDR_PHY_DX8SL3OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
11366         /*############################################################################################################################ */
11367
11368                 /*Register : DX8SL3DQSCTL @ 0XFD0814DC</p>
11369
11370                 Reserved. Return zeroes on reads.
11371                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25                                         0x0
11372
11373                 Read Path Rise-to-Rise Mode
11374                 PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE                                                0x1
11375
11376                 Reserved. Return zeroes on reads.
11377                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22                                         0x0
11378
11379                 Write Path Rise-to-Rise Mode
11380                 PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE                                                0x1
11381
11382                 DQS Gate Extension
11383                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX                                                  0x0
11384
11385                 Low Power PLL Power Down
11386                 PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD                                                0x1
11387
11388                 Low Power I/O Power Down
11389                 PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD                                                 0x1
11390
11391                 Reserved. Return zeroes on reads.
11392                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15                                         0x0
11393
11394                 QS Counter Enable
11395                 PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN                                                0x1
11396
11397                 Unused DQ I/O Mode
11398                 PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM                                                 0x0
11399
11400                 Reserved. Return zeroes on reads.
11401                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10                                         0x0
11402
11403                 Data Slew Rate
11404                 PSU_DDR_PHY_DX8SL3DQSCTL_DXSR                                                   0x3
11405
11406                 DQS_N Resistor
11407                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES                                                0x0
11408
11409                 DQS Resistor
11410                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES                                                 0x0
11411
11412                 DATX8 0-1 DQS Control Register
11413                 (OFFSET, MASK, VALUE)      (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U)
11414                 RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK |  0 );
11415
11416                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
11417                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
11418                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
11419                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
11420                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
11421                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
11422                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
11423                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
11424                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
11425                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
11426                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
11427                         | 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
11428                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
11429                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
11430                         |  0 ) & RegMask); */
11431                 PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
11432         /*############################################################################################################################ */
11433
11434                 /*Register : DX8SL3DXCTL2 @ 0XFD0814EC</p>
11435
11436                 Reserved. Return zeroes on reads.
11437                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24                                         0x0
11438
11439                 Configurable Read Data Enable
11440                 PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN                                                  0x0
11441
11442                 OX Extension during Post-amble
11443                 PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX                                                 0x0
11444
11445                 OE Extension during Pre-amble
11446                 PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX                                                 0x1
11447
11448                 Reserved. Return zeroes on reads.
11449                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17                                            0x0
11450
11451                 I/O Assisted Gate Select
11452                 PSU_DDR_PHY_DX8SL3DXCTL2_IOAG                                                   0x0
11453
11454                 I/O Loopback Select
11455                 PSU_DDR_PHY_DX8SL3DXCTL2_IOLB                                                   0x0
11456
11457                 Reserved. Return zeroes on reads.
11458                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13                                         0x0
11459
11460                 Low Power Wakeup Threshold
11461                 PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH                                         0xc
11462
11463                 Read Data Bus Inversion Enable
11464                 PSU_DDR_PHY_DX8SL3DXCTL2_RDBI                                                   0x0
11465
11466                 Write Data Bus Inversion Enable
11467                 PSU_DDR_PHY_DX8SL3DXCTL2_WDBI                                                   0x0
11468
11469                 PUB Read FIFO Bypass
11470                 PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP                                                 0x0
11471
11472                 DATX8 Receive FIFO Read Mode
11473                 PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE                                                 0x0
11474
11475                 Disables the Read FIFO Reset
11476                 PSU_DDR_PHY_DX8SL3DXCTL2_DISRST                                                 0x0
11477
11478                 Read DQS Gate I/O Loopback
11479                 PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB                                                 0x0
11480
11481                 Reserved. Return zeroes on reads.
11482                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0                                             0x0
11483
11484                 DATX8 0-1 DX Control Register 2
11485                 (OFFSET, MASK, VALUE)      (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U)
11486                 RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK |  0 );
11487
11488                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
11489                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
11490                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
11491                         | 0x00000001U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
11492                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
11493                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
11494                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
11495                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
11496                         | 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
11497                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
11498                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
11499                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
11500                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
11501                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
11502                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
11503                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
11504                         |  0 ) & RegMask); */
11505                 PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
11506         /*############################################################################################################################ */
11507
11508                 /*Register : DX8SL3IOCR @ 0XFD0814F0</p>
11509
11510                 Reserved. Return zeroes on reads.
11511                 PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31                                              0x0
11512
11513                 PVREF_DAC REFSEL range select
11514                 PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE                                               0x7
11515
11516                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11517                 PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM                                                0x0
11518
11519                 DX IO Mode
11520                 PSU_DDR_PHY_DX8SL3IOCR_DXIOM                                                    0x2
11521
11522                 DX IO Transmitter Mode
11523                 PSU_DDR_PHY_DX8SL3IOCR_DXTXM                                                    0x0
11524
11525                 DX IO Receiver Mode
11526                 PSU_DDR_PHY_DX8SL3IOCR_DXRXM                                                    0x0
11527
11528                 DATX8 0-1 I/O Configuration Register
11529                 (OFFSET, MASK, VALUE)      (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U)
11530                 RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK |  0 );
11531
11532                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
11533                         | 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
11534                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
11535                         | 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
11536                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
11537                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
11538                         |  0 ) & RegMask); */
11539                 PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11540         /*############################################################################################################################ */
11541
11542                 /*Register : DX8SL4OSC @ 0XFD081500</p>
11543
11544                 Reserved. Return zeroes on reads.
11545                 PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30                                            0x0
11546
11547                 Enable Clock Gating for DX ddr_clk
11548                 PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK                                               0x2
11549
11550                 Enable Clock Gating for DX ctl_rd_clk
11551                 PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK                                              0x2
11552
11553                 Enable Clock Gating for DX ctl_clk
11554                 PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK                                              0x2
11555
11556                 Selects the level to which clocks will be stalled when clock gating is enabled.
11557                 PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL                                                  0x0
11558
11559                 Loopback Mode
11560                 PSU_DDR_PHY_DX8SL4OSC_LBMODE                                                    0x0
11561
11562                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
11563                 PSU_DDR_PHY_DX8SL4OSC_LBGSDQS                                                   0x0
11564
11565                 Loopback DQS Gating
11566                 PSU_DDR_PHY_DX8SL4OSC_LBGDQS                                                    0x0
11567
11568                 Loopback DQS Shift
11569                 PSU_DDR_PHY_DX8SL4OSC_LBDQSS                                                    0x0
11570
11571                 PHY High-Speed Reset
11572                 PSU_DDR_PHY_DX8SL4OSC_PHYHRST                                                   0x1
11573
11574                 PHY FIFO Reset
11575                 PSU_DDR_PHY_DX8SL4OSC_PHYFRST                                                   0x1
11576
11577                 Delay Line Test Start
11578                 PSU_DDR_PHY_DX8SL4OSC_DLTST                                                     0x0
11579
11580                 Delay Line Test Mode
11581                 PSU_DDR_PHY_DX8SL4OSC_DLTMODE                                                   0x0
11582
11583                 Reserved. Caution, do not write to this register field.
11584                 PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11                                            0x3
11585
11586                 Oscillator Mode Write-Data Delay Line Select
11587                 PSU_DDR_PHY_DX8SL4OSC_OSCWDDL                                                   0x3
11588
11589                 Reserved. Caution, do not write to this register field.
11590                 PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7                                              0x3
11591
11592                 Oscillator Mode Write-Leveling Delay Line Select
11593                 PSU_DDR_PHY_DX8SL4OSC_OSCWDL                                                    0x3
11594
11595                 Oscillator Mode Division
11596                 PSU_DDR_PHY_DX8SL4OSC_OSCDIV                                                    0xf
11597
11598                 Oscillator Enable
11599                 PSU_DDR_PHY_DX8SL4OSC_OSCEN                                                     0x0
11600
11601                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
11602                 (OFFSET, MASK, VALUE)      (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU)
11603                 RegMask = (DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL4OSC_LBMODE_MASK | DDR_PHY_DX8SL4OSC_LBGSDQS_MASK | DDR_PHY_DX8SL4OSC_LBGDQS_MASK | DDR_PHY_DX8SL4OSC_LBDQSS_MASK | DDR_PHY_DX8SL4OSC_PHYHRST_MASK | DDR_PHY_DX8SL4OSC_PHYFRST_MASK | DDR_PHY_DX8SL4OSC_DLTST_MASK | DDR_PHY_DX8SL4OSC_DLTMODE_MASK | DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL4OSC_OSCWDDL_MASK | DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL4OSC_OSCWDL_MASK | DDR_PHY_DX8SL4OSC_OSCDIV_MASK | DDR_PHY_DX8SL4OSC_OSCEN_MASK |  0 );
11604
11605                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
11606                         | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
11607                         | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
11608                         | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
11609                         | 0x00000000U << DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
11610                         | 0x00000000U << DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
11611                         | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
11612                         | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
11613                         | 0x00000000U << DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
11614                         | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
11615                         | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
11616                         | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTST_SHIFT
11617                         | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
11618                         | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
11619                         | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
11620                         | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
11621                         | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
11622                         | 0x0000000FU << DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
11623                         | 0x00000000U << DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
11624                         |  0 ) & RegMask); */
11625                 PSU_Mask_Write (DDR_PHY_DX8SL4OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
11626         /*############################################################################################################################ */
11627
11628                 /*Register : DX8SL4DQSCTL @ 0XFD08151C</p>
11629
11630                 Reserved. Return zeroes on reads.
11631                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25                                         0x0
11632
11633                 Read Path Rise-to-Rise Mode
11634                 PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE                                                0x1
11635
11636                 Reserved. Return zeroes on reads.
11637                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22                                         0x0
11638
11639                 Write Path Rise-to-Rise Mode
11640                 PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE                                                0x1
11641
11642                 DQS Gate Extension
11643                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX                                                  0x0
11644
11645                 Low Power PLL Power Down
11646                 PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD                                                0x1
11647
11648                 Low Power I/O Power Down
11649                 PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD                                                 0x1
11650
11651                 Reserved. Return zeroes on reads.
11652                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15                                         0x0
11653
11654                 QS Counter Enable
11655                 PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN                                                0x1
11656
11657                 Unused DQ I/O Mode
11658                 PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM                                                 0x0
11659
11660                 Reserved. Return zeroes on reads.
11661                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10                                         0x0
11662
11663                 Data Slew Rate
11664                 PSU_DDR_PHY_DX8SL4DQSCTL_DXSR                                                   0x3
11665
11666                 DQS_N Resistor
11667                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES                                                0x0
11668
11669                 DQS Resistor
11670                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES                                                 0x0
11671
11672                 DATX8 0-1 DQS Control Register
11673                 (OFFSET, MASK, VALUE)      (0XFD08151C, 0xFFFFFFFFU ,0x01264300U)
11674                 RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK |  0 );
11675
11676                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
11677                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
11678                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
11679                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
11680                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
11681                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
11682                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
11683                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
11684                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
11685                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
11686                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
11687                         | 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
11688                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
11689                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
11690                         |  0 ) & RegMask); */
11691                 PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
11692         /*############################################################################################################################ */
11693
11694                 /*Register : DX8SL4DXCTL2 @ 0XFD08152C</p>
11695
11696                 Reserved. Return zeroes on reads.
11697                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24                                         0x0
11698
11699                 Configurable Read Data Enable
11700                 PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN                                                  0x0
11701
11702                 OX Extension during Post-amble
11703                 PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX                                                 0x0
11704
11705                 OE Extension during Pre-amble
11706                 PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX                                                 0x1
11707
11708                 Reserved. Return zeroes on reads.
11709                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17                                            0x0
11710
11711                 I/O Assisted Gate Select
11712                 PSU_DDR_PHY_DX8SL4DXCTL2_IOAG                                                   0x0
11713
11714                 I/O Loopback Select
11715                 PSU_DDR_PHY_DX8SL4DXCTL2_IOLB                                                   0x0
11716
11717                 Reserved. Return zeroes on reads.
11718                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13                                         0x0
11719
11720                 Low Power Wakeup Threshold
11721                 PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH                                         0xc
11722
11723                 Read Data Bus Inversion Enable
11724                 PSU_DDR_PHY_DX8SL4DXCTL2_RDBI                                                   0x0
11725
11726                 Write Data Bus Inversion Enable
11727                 PSU_DDR_PHY_DX8SL4DXCTL2_WDBI                                                   0x0
11728
11729                 PUB Read FIFO Bypass
11730                 PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP                                                 0x0
11731
11732                 DATX8 Receive FIFO Read Mode
11733                 PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE                                                 0x0
11734
11735                 Disables the Read FIFO Reset
11736                 PSU_DDR_PHY_DX8SL4DXCTL2_DISRST                                                 0x0
11737
11738                 Read DQS Gate I/O Loopback
11739                 PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB                                                 0x0
11740
11741                 Reserved. Return zeroes on reads.
11742                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0                                             0x0
11743
11744                 DATX8 0-1 DX Control Register 2
11745                 (OFFSET, MASK, VALUE)      (0XFD08152C, 0xFFFFFFFFU ,0x00041800U)
11746                 RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK |  0 );
11747
11748                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
11749                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
11750                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
11751                         | 0x00000001U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
11752                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
11753                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
11754                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
11755                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
11756                         | 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
11757                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
11758                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
11759                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
11760                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
11761                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
11762                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
11763                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
11764                         |  0 ) & RegMask); */
11765                 PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
11766         /*############################################################################################################################ */
11767
11768                 /*Register : DX8SL4IOCR @ 0XFD081530</p>
11769
11770                 Reserved. Return zeroes on reads.
11771                 PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31                                              0x0
11772
11773                 PVREF_DAC REFSEL range select
11774                 PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE                                               0x7
11775
11776                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11777                 PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM                                                0x0
11778
11779                 DX IO Mode
11780                 PSU_DDR_PHY_DX8SL4IOCR_DXIOM                                                    0x2
11781
11782                 DX IO Transmitter Mode
11783                 PSU_DDR_PHY_DX8SL4IOCR_DXTXM                                                    0x0
11784
11785                 DX IO Receiver Mode
11786                 PSU_DDR_PHY_DX8SL4IOCR_DXRXM                                                    0x0
11787
11788                 DATX8 0-1 I/O Configuration Register
11789                 (OFFSET, MASK, VALUE)      (0XFD081530, 0xFFFFFFFFU ,0x70800000U)
11790                 RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK |  0 );
11791
11792                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
11793                         | 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
11794                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
11795                         | 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
11796                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
11797                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
11798                         |  0 ) & RegMask); */
11799                 PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11800         /*############################################################################################################################ */
11801
11802                 /*Register : DX8SLbDQSCTL @ 0XFD0817DC</p>
11803
11804                 Reserved. Return zeroes on reads.
11805                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25                                         0x0
11806
11807                 Read Path Rise-to-Rise Mode
11808                 PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE                                                0x1
11809
11810                 Reserved. Return zeroes on reads.
11811                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22                                         0x0
11812
11813                 Write Path Rise-to-Rise Mode
11814                 PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE                                                0x1
11815
11816                 DQS Gate Extension
11817                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX                                                  0x0
11818
11819                 Low Power PLL Power Down
11820                 PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD                                                0x1
11821
11822                 Low Power I/O Power Down
11823                 PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD                                                 0x1
11824
11825                 Reserved. Return zeroes on reads.
11826                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15                                         0x0
11827
11828                 QS Counter Enable
11829                 PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN                                                0x1
11830
11831                 Unused DQ I/O Mode
11832                 PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM                                                 0x0
11833
11834                 Reserved. Return zeroes on reads.
11835                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10                                         0x0
11836
11837                 Data Slew Rate
11838                 PSU_DDR_PHY_DX8SLBDQSCTL_DXSR                                                   0x3
11839
11840                 DQS# Resistor
11841                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES                                                0xc
11842
11843                 DQS Resistor
11844                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES                                                 0x4
11845
11846                 DATX8 0-8 DQS Control Register
11847                 (OFFSET, MASK, VALUE)      (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U)
11848                 RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK |  0 );
11849
11850                 RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
11851                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
11852                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
11853                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
11854                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
11855                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
11856                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
11857                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
11858                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
11859                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
11860                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
11861                         | 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
11862                         | 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
11863                         | 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
11864                         |  0 ) & RegMask); */
11865                 PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
11866         /*############################################################################################################################ */
11867
11868                 /*Register : PIR @ 0XFD080004</p>
11869
11870                 Reserved. Return zeroes on reads.
11871                 PSU_DDR_PHY_PIR_RESERVED_31                                                     0x0
11872
11873                 Impedance Calibration Bypass
11874                 PSU_DDR_PHY_PIR_ZCALBYP                                                         0x0
11875
11876                 Digital Delay Line (DDL) Calibration Pause
11877                 PSU_DDR_PHY_PIR_DCALPSE                                                         0x0
11878
11879                 Reserved. Return zeroes on reads.
11880                 PSU_DDR_PHY_PIR_RESERVED_28_21                                                  0x0
11881
11882                 Write DQS2DQ Training
11883                 PSU_DDR_PHY_PIR_DQS2DQ                                                          0x0
11884
11885                 RDIMM Initialization
11886                 PSU_DDR_PHY_PIR_RDIMMINIT                                                       0x0
11887
11888                 Controller DRAM Initialization
11889                 PSU_DDR_PHY_PIR_CTLDINIT                                                        0x1
11890
11891                 VREF Training
11892                 PSU_DDR_PHY_PIR_VREF                                                            0x0
11893
11894                 Static Read Training
11895                 PSU_DDR_PHY_PIR_SRD                                                             0x0
11896
11897                 Write Data Eye Training
11898                 PSU_DDR_PHY_PIR_WREYE                                                           0x0
11899
11900                 Read Data Eye Training
11901                 PSU_DDR_PHY_PIR_RDEYE                                                           0x0
11902
11903                 Write Data Bit Deskew
11904                 PSU_DDR_PHY_PIR_WRDSKW                                                          0x0
11905
11906                 Read Data Bit Deskew
11907                 PSU_DDR_PHY_PIR_RDDSKW                                                          0x0
11908
11909                 Write Leveling Adjust
11910                 PSU_DDR_PHY_PIR_WLADJ                                                           0x0
11911
11912                 Read DQS Gate Training
11913                 PSU_DDR_PHY_PIR_QSGATE                                                          0x0
11914
11915                 Write Leveling
11916                 PSU_DDR_PHY_PIR_WL                                                              0x0
11917
11918                 DRAM Initialization
11919                 PSU_DDR_PHY_PIR_DRAMINIT                                                        0x0
11920
11921                 DRAM Reset (DDR3/DDR4/LPDDR4 Only)
11922                 PSU_DDR_PHY_PIR_DRAMRST                                                         0x0
11923
11924                 PHY Reset
11925                 PSU_DDR_PHY_PIR_PHYRST                                                          0x1
11926
11927                 Digital Delay Line (DDL) Calibration
11928                 PSU_DDR_PHY_PIR_DCAL                                                            0x1
11929
11930                 PLL Initialiazation
11931                 PSU_DDR_PHY_PIR_PLLINIT                                                         0x1
11932
11933                 Reserved. Return zeroes on reads.
11934                 PSU_DDR_PHY_PIR_RESERVED_3                                                      0x0
11935
11936                 CA Training
11937                 PSU_DDR_PHY_PIR_CA                                                              0x0
11938
11939                 Impedance Calibration
11940                 PSU_DDR_PHY_PIR_ZCAL                                                            0x1
11941
11942                 Initialization Trigger
11943                 PSU_DDR_PHY_PIR_INIT                                                            0x1
11944
11945                 PHY Initialization Register
11946                 (OFFSET, MASK, VALUE)      (0XFD080004, 0xFFFFFFFFU ,0x00040073U)
11947                 RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK |  0 );
11948
11949                 RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT
11950                         | 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT
11951                         | 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT
11952                         | 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT
11953                         | 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT
11954                         | 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT
11955                         | 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT
11956                         | 0x00000000U << DDR_PHY_PIR_VREF_SHIFT
11957                         | 0x00000000U << DDR_PHY_PIR_SRD_SHIFT
11958                         | 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT
11959                         | 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT
11960                         | 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT
11961                         | 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT
11962                         | 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT
11963                         | 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT
11964                         | 0x00000000U << DDR_PHY_PIR_WL_SHIFT
11965                         | 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT
11966                         | 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT
11967                         | 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT
11968                         | 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT
11969                         | 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT
11970                         | 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT
11971                         | 0x00000000U << DDR_PHY_PIR_CA_SHIFT
11972                         | 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT
11973                         | 0x00000001U << DDR_PHY_PIR_INIT_SHIFT
11974                         |  0 ) & RegMask); */
11975                 PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U);
11976         /*############################################################################################################################ */
11977
11978
11979   return 1;
11980 }
11981 unsigned long psu_mio_init_data() {
11982                 // : MIO PROGRAMMING
11983                 /*Register : MIO_PIN_0 @ 0XFF180000</p>
11984
11985                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
11986                 PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1
11987
11988                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11989                 PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0
11990
11991                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
11992                 t, test_scan_out[0]- (Test Scan Port) 3= Not Used
11993                 PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0
11994
11995                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
11996                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
11997                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
11998                 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
11999                 lk- (Trace Port Clock)
12000                 PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0
12001
12002                 Configures MIO Pin 0 peripheral interface mapping. S
12003                 (OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)
12004                 RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK |  0 );
12005
12006                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
12007                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
12008                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
12009                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
12010                         |  0 ) & RegMask); */
12011                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U);
12012         /*############################################################################################################################ */
12013
12014                 /*Register : MIO_PIN_1 @ 0XFF180004</p>
12015
12016                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
12017                 us)
12018                 PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1
12019
12020                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12021                 PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0
12022
12023                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
12024                 t, test_scan_out[1]- (Test Scan Port) 3= Not Used
12025                 PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0
12026
12027                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
12028                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12029                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
12030                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
12031                 Signal)
12032                 PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0
12033
12034                 Configures MIO Pin 1 peripheral interface mapping
12035                 (OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)
12036                 RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK |  0 );
12037
12038                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
12039                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
12040                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
12041                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
12042                         |  0 ) & RegMask); */
12043                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U);
12044         /*############################################################################################################################ */
12045
12046                 /*Register : MIO_PIN_2 @ 0XFF180008</p>
12047
12048                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
12049                 PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1
12050
12051                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12052                 PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0
12053
12054                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
12055                 t, test_scan_out[2]- (Test Scan Port) 3= Not Used
12056                 PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0
12057
12058                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
12059                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12060                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
12061                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
12062                 PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0
12063
12064                 Configures MIO Pin 2 peripheral interface mapping
12065                 (OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)
12066                 RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK |  0 );
12067
12068                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
12069                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
12070                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
12071                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
12072                         |  0 ) & RegMask); */
12073                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U);
12074         /*############################################################################################################################ */
12075
12076                 /*Register : MIO_PIN_3 @ 0XFF18000C</p>
12077
12078                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
12079                 PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1
12080
12081                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12082                 PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0
12083
12084                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
12085                 t, test_scan_out[3]- (Test Scan Port) 3= Not Used
12086                 PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0
12087
12088                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
12089                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12090                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
12091                 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
12092                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
12093                 PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0
12094
12095                 Configures MIO Pin 3 peripheral interface mapping
12096                 (OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)
12097                 RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK |  0 );
12098
12099                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
12100                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
12101                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
12102                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
12103                         |  0 ) & RegMask); */
12104                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U);
12105         /*############################################################################################################################ */
12106
12107                 /*Register : MIO_PIN_4 @ 0XFF180010</p>
12108
12109                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
12110                 us)
12111                 PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1
12112
12113                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12114                 PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0
12115
12116                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
12117                 t, test_scan_out[4]- (Test Scan Port) 3= Not Used
12118                 PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0
12119
12120                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
12121                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12122                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
12123                 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
12124                 utput, tracedq[2]- (Trace Port Databus)
12125                 PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0
12126
12127                 Configures MIO Pin 4 peripheral interface mapping
12128                 (OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)
12129                 RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK |  0 );
12130
12131                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
12132                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
12133                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
12134                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
12135                         |  0 ) & RegMask); */
12136                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U);
12137         /*############################################################################################################################ */
12138
12139                 /*Register : MIO_PIN_5 @ 0XFF180014</p>
12140
12141                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
12142                 PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1
12143
12144                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12145                 PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0
12146
12147                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
12148                 t, test_scan_out[5]- (Test Scan Port) 3= Not Used
12149                 PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0
12150
12151                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
12152                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12153                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
12154                 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
12155                  trace, Output, tracedq[3]- (Trace Port Databus)
12156                 PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0
12157
12158                 Configures MIO Pin 5 peripheral interface mapping
12159                 (OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)
12160                 RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK |  0 );
12161
12162                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
12163                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
12164                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
12165                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
12166                         |  0 ) & RegMask); */
12167                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U);
12168         /*############################################################################################################################ */
12169
12170                 /*Register : MIO_PIN_6 @ 0XFF180018</p>
12171
12172                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
12173                 PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   1
12174
12175                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12176                 PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0
12177
12178                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
12179                 t, test_scan_out[6]- (Test Scan Port) 3= Not Used
12180                 PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0
12181
12182                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
12183                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12184                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
12185                 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
12186                 Output, tracedq[4]- (Trace Port Databus)
12187                 PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0
12188
12189                 Configures MIO Pin 6 peripheral interface mapping
12190                 (OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000002U)
12191                 RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK |  0 );
12192
12193                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
12194                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
12195                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
12196                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
12197                         |  0 ) & RegMask); */
12198                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U);
12199         /*############################################################################################################################ */
12200
12201                 /*Register : MIO_PIN_7 @ 0XFF18001C</p>
12202
12203                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
12204                 PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   1
12205
12206                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12207                 PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0
12208
12209                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
12210                 t, test_scan_out[7]- (Test Scan Port) 3= Not Used
12211                 PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0
12212
12213                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
12214                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12215                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
12216                 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output,
12217                 racedq[5]- (Trace Port Databus)
12218                 PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0
12219
12220                 Configures MIO Pin 7 peripheral interface mapping
12221                 (OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000002U)
12222                 RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK |  0 );
12223
12224                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
12225                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
12226                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
12227                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
12228                         |  0 ) & RegMask); */
12229                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U);
12230         /*############################################################################################################################ */
12231
12232                 /*Register : MIO_PIN_8 @ 0XFF180020</p>
12233
12234                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
12235                 [0]- (QSPI Upper Databus)
12236                 PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   1
12237
12238                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12239                 PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0
12240
12241                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
12242                 t, test_scan_out[8]- (Test Scan Port) 3= Not Used
12243                 PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0
12244
12245                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
12246                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12247                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
12248                 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
12249                 ce Port Databus)
12250                 PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0
12251
12252                 Configures MIO Pin 8 peripheral interface mapping
12253                 (OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000002U)
12254                 RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK |  0 );
12255
12256                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
12257                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
12258                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
12259                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
12260                         |  0 ) & RegMask); */
12261                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U);
12262         /*############################################################################################################################ */
12263
12264                 /*Register : MIO_PIN_9 @ 0XFF180024</p>
12265
12266                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
12267                 [1]- (QSPI Upper Databus)
12268                 PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   1
12269
12270                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
12271                 PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0
12272
12273                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
12274                 t, test_scan_out[9]- (Test Scan Port) 3= Not Used
12275                 PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0
12276
12277                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
12278                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12279                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
12280                 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
12281                 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
12282                 PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0
12283
12284                 Configures MIO Pin 9 peripheral interface mapping
12285                 (OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000002U)
12286                 RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK |  0 );
12287
12288                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
12289                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
12290                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
12291                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
12292                         |  0 ) & RegMask); */
12293                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U);
12294         /*############################################################################################################################ */
12295
12296                 /*Register : MIO_PIN_10 @ 0XFF180028</p>
12297
12298                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
12299                 [2]- (QSPI Upper Databus)
12300                 PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  1
12301
12302                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
12303                 PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  0
12304
12305                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
12306                 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
12307                 PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0
12308
12309                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
12310                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12311                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
12312                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
12313                 t, tracedq[8]- (Trace Port Databus)
12314                 PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0
12315
12316                 Configures MIO Pin 10 peripheral interface mapping
12317                 (OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000002U)
12318                 RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK |  0 );
12319
12320                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
12321                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
12322                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
12323                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
12324                         |  0 ) & RegMask); */
12325                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U);
12326         /*############################################################################################################################ */
12327
12328                 /*Register : MIO_PIN_11 @ 0XFF18002C</p>
12329
12330                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
12331                 [3]- (QSPI Upper Databus)
12332                 PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  1
12333
12334                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
12335                 PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  0
12336
12337                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
12338                 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
12339                 PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0
12340
12341                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
12342                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12343                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
12344                 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
12345                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
12346                 PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0
12347
12348                 Configures MIO Pin 11 peripheral interface mapping
12349                 (OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000002U)
12350                 RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK |  0 );
12351
12352                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
12353                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
12354                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
12355                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
12356                         |  0 ) & RegMask); */
12357                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U);
12358         /*############################################################################################################################ */
12359
12360                 /*Register : MIO_PIN_12 @ 0XFF180030</p>
12361
12362                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
12363                 PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  1
12364
12365                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
12366
12367                 PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0
12368
12369                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
12370                 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
12371                 PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0
12372
12373                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
12374                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12375                 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
12376                 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
12377                 dq[10]- (Trace Port Databus)
12378                 PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0
12379
12380                 Configures MIO Pin 12 peripheral interface mapping
12381                 (OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000002U)
12382                 RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK |  0 );
12383
12384                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
12385                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
12386                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
12387                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
12388                         |  0 ) & RegMask); */
12389                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U);
12390         /*############################################################################################################################ */
12391
12392                 /*Register : MIO_PIN_13 @ 0XFF180034</p>
12393
12394                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12395                 PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0
12396
12397                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
12398                 PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  0
12399
12400                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
12401                 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
12402                  3= Not Used
12403                 PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0
12404
12405                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
12406                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12407                 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
12408                 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
12409                 bus)
12410                 PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0
12411
12412                 Configures MIO Pin 13 peripheral interface mapping
12413                 (OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000000U)
12414                 RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK |  0 );
12415
12416                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
12417                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
12418                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
12419                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
12420                         |  0 ) & RegMask); */
12421                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U);
12422         /*############################################################################################################################ */
12423
12424                 /*Register : MIO_PIN_14 @ 0XFF180038</p>
12425
12426                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12427                 PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0
12428
12429                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
12430                 PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  0
12431
12432                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
12433                 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
12434                  3= Not Used
12435                 PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0
12436
12437                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
12438                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12439                 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
12440                 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
12441                 PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  2
12442
12443                 Configures MIO Pin 14 peripheral interface mapping
12444                 (OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000040U)
12445                 RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK |  0 );
12446
12447                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
12448                         | 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
12449                         | 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
12450                         | 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
12451                         |  0 ) & RegMask); */
12452                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U);
12453         /*############################################################################################################################ */
12454
12455                 /*Register : MIO_PIN_15 @ 0XFF18003C</p>
12456
12457                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12458                 PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0
12459
12460                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
12461                 PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  0
12462
12463                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
12464                 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
12465                  3= Not Used
12466                 PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0
12467
12468                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
12469                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12470                 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
12471                 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
12472                 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
12473                 PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  2
12474
12475                 Configures MIO Pin 15 peripheral interface mapping
12476                 (OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000040U)
12477                 RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK |  0 );
12478
12479                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
12480                         | 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
12481                         | 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
12482                         | 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
12483                         |  0 ) & RegMask); */
12484                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U);
12485         /*############################################################################################################################ */
12486
12487                 /*Register : MIO_PIN_16 @ 0XFF180040</p>
12488
12489                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12490                 PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0
12491
12492                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND
12493                 ata Bus)
12494                 PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  0
12495
12496                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
12497                 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
12498                  3= Not Used
12499                 PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0
12500
12501                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
12502                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12503                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
12504                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
12505                  Output, tracedq[14]- (Trace Port Databus)
12506                 PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  2
12507
12508                 Configures MIO Pin 16 peripheral interface mapping
12509                 (OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000040U)
12510                 RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK |  0 );
12511
12512                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
12513                         | 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
12514                         | 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
12515                         | 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
12516                         |  0 ) & RegMask); */
12517                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U);
12518         /*############################################################################################################################ */
12519
12520                 /*Register : MIO_PIN_17 @ 0XFF180044</p>
12521
12522                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12523                 PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0
12524
12525                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND
12526                 ata Bus)
12527                 PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  0
12528
12529                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
12530                 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
12531                  3= Not Used
12532                 PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0
12533
12534                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
12535                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12536                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
12537                 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
12538                 7= trace, Output, tracedq[15]- (Trace Port Databus)
12539                 PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  2
12540
12541                 Configures MIO Pin 17 peripheral interface mapping
12542                 (OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000040U)
12543                 RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK |  0 );
12544
12545                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
12546                         | 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
12547                         | 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
12548                         | 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
12549                         |  0 ) & RegMask); */
12550                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U);
12551         /*############################################################################################################################ */
12552
12553                 /*Register : MIO_PIN_18 @ 0XFF180048</p>
12554
12555                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12556                 PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0
12557
12558                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND
12559                 ata Bus)
12560                 PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  0
12561
12562                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
12563                 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
12564                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12565                 PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0
12566
12567                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
12568                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12569                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
12570                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
12571                 PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  6
12572
12573                 Configures MIO Pin 18 peripheral interface mapping
12574                 (OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x000000C0U)
12575                 RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK |  0 );
12576
12577                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
12578                         | 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
12579                         | 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
12580                         | 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
12581                         |  0 ) & RegMask); */
12582                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U);
12583         /*############################################################################################################################ */
12584
12585                 /*Register : MIO_PIN_19 @ 0XFF18004C</p>
12586
12587                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12588                 PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0
12589
12590                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND
12591                 ata Bus)
12592                 PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  0
12593
12594                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
12595                 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
12596                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12597                 PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0
12598
12599                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
12600                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12601                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
12602                  ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
12603                 PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  6
12604
12605                 Configures MIO Pin 19 peripheral interface mapping
12606                 (OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x000000C0U)
12607                 RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK |  0 );
12608
12609                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
12610                         | 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
12611                         | 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
12612                         | 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
12613                         |  0 ) & RegMask); */
12614                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U);
12615         /*############################################################################################################################ */
12616
12617                 /*Register : MIO_PIN_20 @ 0XFF180050</p>
12618
12619                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12620                 PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0
12621
12622                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND
12623                 ata Bus)
12624                 PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  0
12625
12626                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
12627                 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
12628                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12629                 PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0
12630
12631                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
12632                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12633                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
12634                 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
12635                 PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  6
12636
12637                 Configures MIO Pin 20 peripheral interface mapping
12638                 (OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x000000C0U)
12639                 RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK |  0 );
12640
12641                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
12642                         | 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
12643                         | 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
12644                         | 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
12645                         |  0 ) & RegMask); */
12646                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U);
12647         /*############################################################################################################################ */
12648
12649                 /*Register : MIO_PIN_21 @ 0XFF180054</p>
12650
12651                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12652                 PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0
12653
12654                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND
12655                 ata Bus)
12656                 PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  0
12657
12658                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
12659                  Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port)
12660                 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12661                 PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0
12662
12663                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
12664                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12665                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
12666                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd-
12667                 UART receiver serial input) 7= Not Used
12668                 PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  6
12669
12670                 Configures MIO Pin 21 peripheral interface mapping
12671                 (OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x000000C0U)
12672                 RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK |  0 );
12673
12674                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
12675                         | 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
12676                         | 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
12677                         | 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
12678                         |  0 ) & RegMask); */
12679                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U);
12680         /*############################################################################################################################ */
12681
12682                 /*Register : MIO_PIN_22 @ 0XFF180058</p>
12683
12684                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12685                 PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0
12686
12687                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
12688                 PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  0
12689
12690                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
12691                 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12692                 PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0
12693
12694                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
12695                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12696                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
12697                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
12698                 sed
12699                 PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0
12700
12701                 Configures MIO Pin 22 peripheral interface mapping
12702                 (OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000000U)
12703                 RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK |  0 );
12704
12705                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
12706                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
12707                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
12708                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
12709                         |  0 ) & RegMask); */
12710                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U);
12711         /*############################################################################################################################ */
12712
12713                 /*Register : MIO_PIN_23 @ 0XFF18005C</p>
12714
12715                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12716                 PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0
12717
12718                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND
12719                 ata Bus)
12720                 PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  0
12721
12722                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
12723                 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
12724
12725                 PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0
12726
12727                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
12728                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12729                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
12730                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
12731                 tput) 7= Not Used
12732                 PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0
12733
12734                 Configures MIO Pin 23 peripheral interface mapping
12735                 (OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000000U)
12736                 RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK |  0 );
12737
12738                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
12739                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
12740                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
12741                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
12742                         |  0 ) & RegMask); */
12743                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U);
12744         /*############################################################################################################################ */
12745
12746                 /*Register : MIO_PIN_24 @ 0XFF180060</p>
12747
12748                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12749                 PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0
12750
12751                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND
12752                 ata Bus)
12753                 PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  0
12754
12755                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
12756                 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
12757                  Tamper)
12758                 PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0
12759
12760                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
12761                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12762                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
12763                 Output, ua1_txd- (UART transmitter serial output) 7= Not Used
12764                 PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  1
12765
12766                 Configures MIO Pin 24 peripheral interface mapping
12767                 (OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000020U)
12768                 RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK |  0 );
12769
12770                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
12771                         | 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
12772                         | 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
12773                         | 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
12774                         |  0 ) & RegMask); */
12775                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U);
12776         /*############################################################################################################################ */
12777
12778                 /*Register : MIO_PIN_25 @ 0XFF180064</p>
12779
12780                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12781                 PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0
12782
12783                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
12784                 PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  0
12785
12786                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
12787                 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
12788                 U Ext Tamper)
12789                 PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0
12790
12791                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
12792                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12793                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform
12794                 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
12795                 PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  1
12796
12797                 Configures MIO Pin 25 peripheral interface mapping
12798                 (OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000020U)
12799                 RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK |  0 );
12800
12801                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
12802                         | 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
12803                         | 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
12804                         | 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
12805                         |  0 ) & RegMask); */
12806                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U);
12807         /*############################################################################################################################ */
12808
12809                 /*Register : MIO_PIN_26 @ 0XFF180068</p>
12810
12811                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
12812                 PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0
12813
12814                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
12815                 PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  0
12816
12817                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
12818                 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12819                 PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  0
12820
12821                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
12822                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12823                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
12824                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
12825                 Trace Port Databus)
12826                 PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0
12827
12828                 Configures MIO Pin 26 peripheral interface mapping
12829                 (OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000000U)
12830                 RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK |  0 );
12831
12832                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
12833                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
12834                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
12835                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
12836                         |  0 ) & RegMask); */
12837                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U);
12838         /*############################################################################################################################ */
12839
12840                 /*Register : MIO_PIN_27 @ 0XFF18006C</p>
12841
12842                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
12843                 PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0
12844
12845                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
12846                 PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0
12847
12848                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
12849                 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
12850                 t, dp_aux_data_out- (Dp Aux Data)
12851                 PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  3
12852
12853                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
12854                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12855                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
12856                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
12857                 atabus)
12858                 PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0
12859
12860                 Configures MIO Pin 27 peripheral interface mapping
12861                 (OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000018U)
12862                 RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK |  0 );
12863
12864                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
12865                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
12866                         | 0x00000003U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
12867                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
12868                         |  0 ) & RegMask); */
12869                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000018U);
12870         /*############################################################################################################################ */
12871
12872                 /*Register : MIO_PIN_28 @ 0XFF180070</p>
12873
12874                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
12875                 PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0
12876
12877                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
12878                 PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0
12879
12880                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
12881                 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
12882                 PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  3
12883
12884                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
12885                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12886                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
12887                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
12888                 PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0
12889
12890                 Configures MIO Pin 28 peripheral interface mapping
12891                 (OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000018U)
12892                 RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK |  0 );
12893
12894                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
12895                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
12896                         | 0x00000003U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
12897                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
12898                         |  0 ) & RegMask); */
12899                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000018U);
12900         /*############################################################################################################################ */
12901
12902                 /*Register : MIO_PIN_29 @ 0XFF180074</p>
12903
12904                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
12905                 PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0
12906
12907                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12908                 PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0
12909
12910                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
12911                 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
12912                 t, dp_aux_data_out- (Dp Aux Data)
12913                 PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  3
12914
12915                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
12916                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12917                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
12918                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
12919                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
12920                 PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  0
12921
12922                 Configures MIO Pin 29 peripheral interface mapping
12923                 (OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000018U)
12924                 RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK |  0 );
12925
12926                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
12927                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
12928                         | 0x00000003U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
12929                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
12930                         |  0 ) & RegMask); */
12931                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000018U);
12932         /*############################################################################################################################ */
12933
12934                 /*Register : MIO_PIN_30 @ 0XFF180078</p>
12935
12936                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
12937                 PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0
12938
12939                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12940                 PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0
12941
12942                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
12943                 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
12944                 PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  3
12945
12946                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
12947                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12948                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
12949                  (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
12950                  tracedq[8]- (Trace Port Databus)
12951                 PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0
12952
12953                 Configures MIO Pin 30 peripheral interface mapping
12954                 (OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000018U)
12955                 RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK |  0 );
12956
12957                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
12958                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
12959                         | 0x00000003U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
12960                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
12961                         |  0 ) & RegMask); */
12962                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000018U);
12963         /*############################################################################################################################ */
12964
12965                 /*Register : MIO_PIN_31 @ 0XFF18007C</p>
12966
12967                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
12968                 PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0
12969
12970                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12971                 PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0
12972
12973                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
12974                 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12975                 PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0
12976
12977                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
12978                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12979                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
12980                 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
12981                 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
12982                 PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0
12983
12984                 Configures MIO Pin 31 peripheral interface mapping
12985                 (OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)
12986                 RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK |  0 );
12987
12988                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
12989                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
12990                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
12991                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
12992                         |  0 ) & RegMask); */
12993                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U);
12994         /*############################################################################################################################ */
12995
12996                 /*Register : MIO_PIN_32 @ 0XFF180080</p>
12997
12998                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
12999                 PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0
13000
13001                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
13002
13003                 PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  0
13004
13005                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
13006                 an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
13007                 PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  1
13008
13009                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
13010                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13011                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
13012                 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
13013                 race, Output, tracedq[10]- (Trace Port Databus)
13014                 PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0
13015
13016                 Configures MIO Pin 32 peripheral interface mapping
13017                 (OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000008U)
13018                 RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK |  0 );
13019
13020                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
13021                         | 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
13022                         | 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
13023                         | 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
13024                         |  0 ) & RegMask); */
13025                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U);
13026         /*############################################################################################################################ */
13027
13028                 /*Register : MIO_PIN_33 @ 0XFF180084</p>
13029
13030                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
13031                 PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0
13032
13033                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13034                 PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0
13035
13036                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
13037                 an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
13038                 PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  1
13039
13040                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
13041                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13042                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
13043                 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
13044                 [11]- (Trace Port Databus)
13045                 PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0
13046
13047                 Configures MIO Pin 33 peripheral interface mapping
13048                 (OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000008U)
13049                 RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK |  0 );
13050
13051                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
13052                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
13053                         | 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
13054                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
13055                         |  0 ) & RegMask); */
13056                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U);
13057         /*############################################################################################################################ */
13058
13059                 /*Register : MIO_PIN_34 @ 0XFF180088</p>
13060
13061                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
13062                 PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0
13063
13064                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13065                 PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0
13066
13067                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
13068                 an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
13069                 ut, dp_aux_data_out- (Dp Aux Data)
13070                 PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  1
13071
13072                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
13073                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
13074                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
13075                  Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
13076                 rt Databus)
13077                 PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0
13078
13079                 Configures MIO Pin 34 peripheral interface mapping
13080                 (OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000008U)
13081                 RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK |  0 );
13082
13083                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
13084                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
13085                         | 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
13086                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
13087                         |  0 ) & RegMask); */
13088                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U);
13089         /*############################################################################################################################ */
13090
13091                 /*Register : MIO_PIN_35 @ 0XFF18008C</p>
13092
13093                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
13094                 PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0
13095
13096                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13097                 PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0
13098
13099                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
13100                 an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
13101                 PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  1
13102
13103                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
13104                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13105                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
13106                 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
13107                 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
13108                 PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  0
13109
13110                 Configures MIO Pin 35 peripheral interface mapping
13111                 (OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000008U)
13112                 RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK |  0 );
13113
13114                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
13115                         | 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
13116                         | 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
13117                         | 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
13118                         |  0 ) & RegMask); */
13119                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U);
13120         /*############################################################################################################################ */
13121
13122                 /*Register : MIO_PIN_36 @ 0XFF180090</p>
13123
13124                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
13125                 PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0
13126
13127                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13128                 PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0
13129
13130                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
13131                 an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
13132                 ut, dp_aux_data_out- (Dp Aux Data)
13133                 PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  1
13134
13135                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
13136                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13137                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
13138                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
13139                  Output, tracedq[14]- (Trace Port Databus)
13140                 PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0
13141
13142                 Configures MIO Pin 36 peripheral interface mapping
13143                 (OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000008U)
13144                 RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK |  0 );
13145
13146                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
13147                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
13148                         | 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
13149                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
13150                         |  0 ) & RegMask); */
13151                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U);
13152         /*############################################################################################################################ */
13153
13154                 /*Register : MIO_PIN_37 @ 0XFF180094</p>
13155
13156                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
13157                 PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0
13158
13159                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13160                 PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0
13161
13162                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
13163                 an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
13164                 PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  1
13165
13166                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
13167                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13168                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
13169                 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
13170                 7= trace, Output, tracedq[15]- (Trace Port Databus)
13171                 PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0
13172
13173                 Configures MIO Pin 37 peripheral interface mapping
13174                 (OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000008U)
13175                 RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK |  0 );
13176
13177                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
13178                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
13179                         | 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
13180                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
13181                         |  0 ) & RegMask); */
13182                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U);
13183         /*############################################################################################################################ */
13184
13185                 /*Register : MIO_PIN_38 @ 0XFF180098</p>
13186
13187                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
13188                 PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0
13189
13190                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13191                 PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0
13192
13193                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
13194                 PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0
13195
13196                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
13197                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13198                 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
13199                 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
13200                 (Trace Port Clock)
13201                 PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0
13202
13203                 Configures MIO Pin 38 peripheral interface mapping
13204                 (OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)
13205                 RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK |  0 );
13206
13207                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
13208                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
13209                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
13210                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
13211                         |  0 ) & RegMask); */
13212                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U);
13213         /*############################################################################################################################ */
13214
13215                 /*Register : MIO_PIN_39 @ 0XFF18009C</p>
13216
13217                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
13218                 PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0
13219
13220                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13221                 PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0
13222
13223                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
13224                 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
13225                 PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  0
13226
13227                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
13228                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13229                 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
13230                 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
13231                 Control Signal)
13232                 PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0
13233
13234                 Configures MIO Pin 39 peripheral interface mapping
13235                 (OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000000U)
13236                 RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK |  0 );
13237
13238                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
13239                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
13240                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
13241                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
13242                         |  0 ) & RegMask); */
13243                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U);
13244         /*############################################################################################################################ */
13245
13246                 /*Register : MIO_PIN_40 @ 0XFF1800A0</p>
13247
13248                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
13249                 PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0
13250
13251                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13252                 PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0
13253
13254                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
13255                  Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
13256                 PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  0
13257
13258                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
13259                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13260                 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
13261                 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
13262                 PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0
13263
13264                 Configures MIO Pin 40 peripheral interface mapping
13265                 (OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000000U)
13266                 RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK |  0 );
13267
13268                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
13269                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
13270                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
13271                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
13272                         |  0 ) & RegMask); */
13273                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U);
13274         /*############################################################################################################################ */
13275
13276                 /*Register : MIO_PIN_41 @ 0XFF1800A4</p>
13277
13278                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
13279                 PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0
13280
13281                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13282                 PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0
13283
13284                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
13285                 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
13286                 PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  0
13287
13288                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
13289                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13290                 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
13291                 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
13292                 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
13293                 PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0
13294
13295                 Configures MIO Pin 41 peripheral interface mapping
13296                 (OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000000U)
13297                 RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK |  0 );
13298
13299                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
13300                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
13301                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
13302                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
13303                         |  0 ) & RegMask); */
13304                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U);
13305         /*############################################################################################################################ */
13306
13307                 /*Register : MIO_PIN_42 @ 0XFF1800A8</p>
13308
13309                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
13310                 PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0
13311
13312                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13313                 PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0
13314
13315                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
13316                 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
13317                 PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  0
13318
13319                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
13320                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13321                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
13322                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
13323                 t, tracedq[2]- (Trace Port Databus)
13324                 PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0
13325
13326                 Configures MIO Pin 42 peripheral interface mapping
13327                 (OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000000U)
13328                 RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK |  0 );
13329
13330                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
13331                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
13332                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
13333                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
13334                         |  0 ) & RegMask); */
13335                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U);
13336         /*############################################################################################################################ */
13337
13338                 /*Register : MIO_PIN_43 @ 0XFF1800AC</p>
13339
13340                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
13341                 PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0
13342
13343                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13344                 PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0
13345
13346                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
13347                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
13348                 PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2
13349
13350                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
13351                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13352                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
13353                 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
13354                 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
13355                 PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0
13356
13357                 Configures MIO Pin 43 peripheral interface mapping
13358                 (OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)
13359                 RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK |  0 );
13360
13361                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
13362                         | 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
13363                         | 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
13364                         | 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
13365                         |  0 ) & RegMask); */
13366                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U);
13367         /*############################################################################################################################ */
13368
13369                 /*Register : MIO_PIN_44 @ 0XFF1800B0</p>
13370
13371                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
13372                 PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0
13373
13374                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13375                 PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0
13376
13377                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
13378                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
13379                 PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  2
13380
13381                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
13382                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13383                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
13384                 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
13385                  Not Used
13386                 PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0
13387
13388                 Configures MIO Pin 44 peripheral interface mapping
13389                 (OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000010U)
13390                 RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK |  0 );
13391
13392                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
13393                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
13394                         | 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
13395                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
13396                         |  0 ) & RegMask); */
13397                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U);
13398         /*############################################################################################################################ */
13399
13400                 /*Register : MIO_PIN_45 @ 0XFF1800B4</p>
13401
13402                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
13403                 PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0
13404
13405                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13406                 PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0
13407
13408                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
13409                 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
13410                 PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  2
13411
13412                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
13413                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13414                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
13415                 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
13416                 PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0
13417
13418                 Configures MIO Pin 45 peripheral interface mapping
13419                 (OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000010U)
13420                 RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK |  0 );
13421
13422                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
13423                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
13424                         | 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
13425                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
13426                         |  0 ) & RegMask); */
13427                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U);
13428         /*############################################################################################################################ */
13429
13430                 /*Register : MIO_PIN_46 @ 0XFF1800B8</p>
13431
13432                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
13433                 PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0
13434
13435                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13436                 PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0
13437
13438                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
13439                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
13440                 PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2
13441
13442                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
13443                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13444                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
13445                 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
13446                 PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0
13447
13448                 Configures MIO Pin 46 peripheral interface mapping
13449                 (OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)
13450                 RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK |  0 );
13451
13452                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
13453                         | 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
13454                         | 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
13455                         | 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
13456                         |  0 ) & RegMask); */
13457                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U);
13458         /*############################################################################################################################ */
13459
13460                 /*Register : MIO_PIN_47 @ 0XFF1800BC</p>
13461
13462                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
13463                 PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0
13464
13465                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13466                 PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0
13467
13468                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
13469                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
13470                 PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2
13471
13472                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
13473                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13474                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
13475                 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
13476                  (UART transmitter serial output) 7= Not Used
13477                 PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0
13478
13479                 Configures MIO Pin 47 peripheral interface mapping
13480                 (OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)
13481                 RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK |  0 );
13482
13483                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
13484                         | 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
13485                         | 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
13486                         | 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
13487                         |  0 ) & RegMask); */
13488                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U);
13489         /*############################################################################################################################ */
13490
13491                 /*Register : MIO_PIN_48 @ 0XFF1800C0</p>
13492
13493                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
13494                 PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0
13495
13496                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13497                 PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0
13498
13499                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
13500                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
13501                 PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2
13502
13503                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
13504                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13505                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
13506                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
13507                 ed
13508                 PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0
13509
13510                 Configures MIO Pin 48 peripheral interface mapping
13511                 (OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)
13512                 RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK |  0 );
13513
13514                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
13515                         | 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
13516                         | 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
13517                         | 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
13518                         |  0 ) & RegMask); */
13519                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U);
13520         /*############################################################################################################################ */
13521
13522                 /*Register : MIO_PIN_49 @ 0XFF1800C4</p>
13523
13524                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
13525                 PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0
13526
13527                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13528                 PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0
13529
13530                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
13531                 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
13532                 PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2
13533
13534                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
13535                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13536                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
13537                 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
13538                 7= Not Used
13539                 PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0
13540
13541                 Configures MIO Pin 49 peripheral interface mapping
13542                 (OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)
13543                 RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK |  0 );
13544
13545                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
13546                         | 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
13547                         | 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
13548                         | 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
13549                         |  0 ) & RegMask); */
13550                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U);
13551         /*############################################################################################################################ */
13552
13553                 /*Register : MIO_PIN_50 @ 0XFF1800C8</p>
13554
13555                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
13556                 PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0
13557
13558                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13559                 PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0
13560
13561                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
13562                 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
13563                 PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2
13564
13565                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
13566                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13567                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
13568                 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
13569                 PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0
13570
13571                 Configures MIO Pin 50 peripheral interface mapping
13572                 (OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)
13573                 RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK |  0 );
13574
13575                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
13576                         | 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
13577                         | 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
13578                         | 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
13579                         |  0 ) & RegMask); */
13580                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U);
13581         /*############################################################################################################################ */
13582
13583                 /*Register : MIO_PIN_51 @ 0XFF1800CC</p>
13584
13585                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
13586                 PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0
13587
13588                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13589                 PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0
13590
13591                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
13592                 PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2
13593
13594                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
13595                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13596                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
13597                 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
13598                 serial output) 7= Not Used
13599                 PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0
13600
13601                 Configures MIO Pin 51 peripheral interface mapping
13602                 (OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)
13603                 RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK |  0 );
13604
13605                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
13606                         | 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
13607                         | 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
13608                         | 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
13609                         |  0 ) & RegMask); */
13610                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U);
13611         /*############################################################################################################################ */
13612
13613                 /*Register : MIO_PIN_52 @ 0XFF1800D0</p>
13614
13615                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
13616                 PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0
13617
13618                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
13619                 PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1
13620
13621                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13622                 PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0
13623
13624                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
13625                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13626                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
13627                 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
13628                 lk- (Trace Port Clock)
13629                 PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0
13630
13631                 Configures MIO Pin 52 peripheral interface mapping
13632                 (OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)
13633                 RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK |  0 );
13634
13635                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
13636                         | 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
13637                         | 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
13638                         | 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
13639                         |  0 ) & RegMask); */
13640                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U);
13641         /*############################################################################################################################ */
13642
13643                 /*Register : MIO_PIN_53 @ 0XFF1800D4</p>
13644
13645                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
13646                 PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0
13647
13648                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
13649                 PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1
13650
13651                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13652                 PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0
13653
13654                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
13655                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13656                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
13657                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
13658                 Signal)
13659                 PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0
13660
13661                 Configures MIO Pin 53 peripheral interface mapping
13662                 (OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)
13663                 RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK |  0 );
13664
13665                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
13666                         | 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
13667                         | 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
13668                         | 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
13669                         |  0 ) & RegMask); */
13670                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U);
13671         /*############################################################################################################################ */
13672
13673                 /*Register : MIO_PIN_54 @ 0XFF1800D8</p>
13674
13675                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
13676                 PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0
13677
13678                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13679                 ata[2]- (ULPI data bus)
13680                 PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1
13681
13682                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13683                 PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0
13684
13685                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
13686                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
13687                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
13688                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
13689                 PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0
13690
13691                 Configures MIO Pin 54 peripheral interface mapping
13692                 (OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)
13693                 RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK |  0 );
13694
13695                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
13696                         | 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
13697                         | 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
13698                         | 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
13699                         |  0 ) & RegMask); */
13700                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U);
13701         /*############################################################################################################################ */
13702
13703                 /*Register : MIO_PIN_55 @ 0XFF1800DC</p>
13704
13705                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
13706                 PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0
13707
13708                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
13709                 PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1
13710
13711                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13712                 PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0
13713
13714                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
13715                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13716                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
13717                 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
13718                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
13719                 PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0
13720
13721                 Configures MIO Pin 55 peripheral interface mapping
13722                 (OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)
13723                 RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK |  0 );
13724
13725                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
13726                         | 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
13727                         | 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
13728                         | 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
13729                         |  0 ) & RegMask); */
13730                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U);
13731         /*############################################################################################################################ */
13732
13733                 /*Register : MIO_PIN_56 @ 0XFF1800E0</p>
13734
13735                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
13736                 PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0
13737
13738                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13739                 ata[0]- (ULPI data bus)
13740                 PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1
13741
13742                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13743                 PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0
13744
13745                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
13746                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13747                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
13748                 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
13749                 utput, tracedq[2]- (Trace Port Databus)
13750                 PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0
13751
13752                 Configures MIO Pin 56 peripheral interface mapping
13753                 (OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)
13754                 RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK |  0 );
13755
13756                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
13757                         | 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
13758                         | 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
13759                         | 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
13760                         |  0 ) & RegMask); */
13761                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U);
13762         /*############################################################################################################################ */
13763
13764                 /*Register : MIO_PIN_57 @ 0XFF1800E4</p>
13765
13766                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
13767                 PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0
13768
13769                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13770                 ata[1]- (ULPI data bus)
13771                 PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1
13772
13773                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13774                 PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0
13775
13776                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
13777                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13778                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
13779                 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
13780                  trace, Output, tracedq[3]- (Trace Port Databus)
13781                 PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0
13782
13783                 Configures MIO Pin 57 peripheral interface mapping
13784                 (OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)
13785                 RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK |  0 );
13786
13787                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
13788                         | 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
13789                         | 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
13790                         | 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
13791                         |  0 ) & RegMask); */
13792                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U);
13793         /*############################################################################################################################ */
13794
13795                 /*Register : MIO_PIN_58 @ 0XFF1800E8</p>
13796
13797                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
13798                 PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0
13799
13800                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
13801                 PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1
13802
13803                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13804                 PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0
13805
13806                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
13807                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
13808                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
13809                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
13810                 Trace Port Databus)
13811                 PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0
13812
13813                 Configures MIO Pin 58 peripheral interface mapping
13814                 (OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)
13815                 RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK |  0 );
13816
13817                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
13818                         | 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
13819                         | 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
13820                         | 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
13821                         |  0 ) & RegMask); */
13822                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U);
13823         /*############################################################################################################################ */
13824
13825                 /*Register : MIO_PIN_59 @ 0XFF1800EC</p>
13826
13827                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
13828                 PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0
13829
13830                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13831                 ata[3]- (ULPI data bus)
13832                 PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1
13833
13834                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13835                 PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0
13836
13837                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
13838                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13839                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
13840                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
13841                 atabus)
13842                 PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0
13843
13844                 Configures MIO Pin 59 peripheral interface mapping
13845                 (OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)
13846                 RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK |  0 );
13847
13848                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
13849                         | 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
13850                         | 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
13851                         | 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
13852                         |  0 ) & RegMask); */
13853                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U);
13854         /*############################################################################################################################ */
13855
13856                 /*Register : MIO_PIN_60 @ 0XFF1800F0</p>
13857
13858                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
13859                 PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0
13860
13861                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13862                 ata[4]- (ULPI data bus)
13863                 PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1
13864
13865                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13866                 PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0
13867
13868                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
13869                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13870                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
13871                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
13872                 PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0
13873
13874                 Configures MIO Pin 60 peripheral interface mapping
13875                 (OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)
13876                 RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK |  0 );
13877
13878                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
13879                         | 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
13880                         | 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
13881                         | 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
13882                         |  0 ) & RegMask); */
13883                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U);
13884         /*############################################################################################################################ */
13885
13886                 /*Register : MIO_PIN_61 @ 0XFF1800F4</p>
13887
13888                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
13889                 PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0
13890
13891                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13892                 ata[5]- (ULPI data bus)
13893                 PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1
13894
13895                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13896                 PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0
13897
13898                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
13899                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13900                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
13901                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
13902                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
13903                 PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0
13904
13905                 Configures MIO Pin 61 peripheral interface mapping
13906                 (OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)
13907                 RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK |  0 );
13908
13909                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
13910                         | 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
13911                         | 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
13912                         | 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
13913                         |  0 ) & RegMask); */
13914                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U);
13915         /*############################################################################################################################ */
13916
13917                 /*Register : MIO_PIN_62 @ 0XFF1800F8</p>
13918
13919                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
13920                 PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0
13921
13922                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13923                 ata[6]- (ULPI data bus)
13924                 PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1
13925
13926                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13927                 PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0
13928
13929                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
13930                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13931                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
13932                 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
13933                 t, tracedq[8]- (Trace Port Databus)
13934                 PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0
13935
13936                 Configures MIO Pin 62 peripheral interface mapping
13937                 (OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)
13938                 RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK |  0 );
13939
13940                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
13941                         | 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
13942                         | 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
13943                         | 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
13944                         |  0 ) & RegMask); */
13945                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U);
13946         /*############################################################################################################################ */
13947
13948                 /*Register : MIO_PIN_63 @ 0XFF1800FC</p>
13949
13950                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
13951                 PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0
13952
13953                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13954                 ata[7]- (ULPI data bus)
13955                 PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1
13956
13957                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13958                 PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0
13959
13960                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
13961                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13962                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
13963                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
13964                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
13965                 PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0
13966
13967                 Configures MIO Pin 63 peripheral interface mapping
13968                 (OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)
13969                 RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK |  0 );
13970
13971                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
13972                         | 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
13973                         | 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
13974                         | 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
13975                         |  0 ) & RegMask); */
13976                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U);
13977         /*############################################################################################################################ */
13978
13979                 /*Register : MIO_PIN_64 @ 0XFF180100</p>
13980
13981                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
13982                 PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  1
13983
13984                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
13985                 PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0
13986
13987                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
13988                 PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  0
13989
13990                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
13991                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13992                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
13993                 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
13994                  trace, Output, tracedq[10]- (Trace Port Databus)
13995                 PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0
13996
13997                 Configures MIO Pin 64 peripheral interface mapping
13998                 (OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000002U)
13999                 RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK |  0 );
14000
14001                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
14002                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
14003                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
14004                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
14005                         |  0 ) & RegMask); */
14006                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U);
14007         /*############################################################################################################################ */
14008
14009                 /*Register : MIO_PIN_65 @ 0XFF180104</p>
14010
14011                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
14012                 PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  1
14013
14014                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
14015                 PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0
14016
14017                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
14018                 PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  0
14019
14020                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
14021                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14022                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
14023                 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
14024                 dq[11]- (Trace Port Databus)
14025                 PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0
14026
14027                 Configures MIO Pin 65 peripheral interface mapping
14028                 (OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000002U)
14029                 RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK |  0 );
14030
14031                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
14032                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
14033                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
14034                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
14035                         |  0 ) & RegMask); */
14036                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U);
14037         /*############################################################################################################################ */
14038
14039                 /*Register : MIO_PIN_66 @ 0XFF180108</p>
14040
14041                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
14042                 PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  1
14043
14044                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14045                 ata[2]- (ULPI data bus)
14046                 PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0
14047
14048                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
14049                  Indicator) 2= Not Used 3= Not Used
14050                 PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  0
14051
14052                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
14053                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
14054                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
14055                 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
14056                 Port Databus)
14057                 PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0
14058
14059                 Configures MIO Pin 66 peripheral interface mapping
14060                 (OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000002U)
14061                 RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK |  0 );
14062
14063                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
14064                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
14065                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
14066                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
14067                         |  0 ) & RegMask); */
14068                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U);
14069         /*############################################################################################################################ */
14070
14071                 /*Register : MIO_PIN_67 @ 0XFF18010C</p>
14072
14073                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
14074                 PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  1
14075
14076                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
14077                 PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0
14078
14079                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
14080                 bit Data bus) 2= Not Used 3= Not Used
14081                 PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  0
14082
14083                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
14084                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
14085                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
14086                 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
14087                  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
14088                 PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0
14089
14090                 Configures MIO Pin 67 peripheral interface mapping
14091                 (OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000002U)
14092                 RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK |  0 );
14093
14094                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
14095                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
14096                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
14097                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
14098                         |  0 ) & RegMask); */
14099                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U);
14100         /*############################################################################################################################ */
14101
14102                 /*Register : MIO_PIN_68 @ 0XFF180110</p>
14103
14104                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
14105                 PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  1
14106
14107                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14108                 ata[0]- (ULPI data bus)
14109                 PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0
14110
14111                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
14112                 bit Data bus) 2= Not Used 3= Not Used
14113                 PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  0
14114
14115                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
14116                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
14117                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
14118                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
14119                  Output, tracedq[14]- (Trace Port Databus)
14120                 PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0
14121
14122                 Configures MIO Pin 68 peripheral interface mapping
14123                 (OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000002U)
14124                 RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK |  0 );
14125
14126                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
14127                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
14128                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
14129                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
14130                         |  0 ) & RegMask); */
14131                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U);
14132         /*############################################################################################################################ */
14133
14134                 /*Register : MIO_PIN_69 @ 0XFF180114</p>
14135
14136                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
14137                 PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  1
14138
14139                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14140                 ata[1]- (ULPI data bus)
14141                 PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0
14142
14143                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
14144                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
14145                 PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  0
14146
14147                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
14148                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14149                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
14150                 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
14151                 7= trace, Output, tracedq[15]- (Trace Port Databus)
14152                 PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0
14153
14154                 Configures MIO Pin 69 peripheral interface mapping
14155                 (OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000002U)
14156                 RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK |  0 );
14157
14158                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
14159                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
14160                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
14161                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
14162                         |  0 ) & RegMask); */
14163                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U);
14164         /*############################################################################################################################ */
14165
14166                 /*Register : MIO_PIN_70 @ 0XFF180118</p>
14167
14168                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
14169                 PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  1
14170
14171                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
14172                 PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0
14173
14174                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
14175                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
14176                 PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  0
14177
14178                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
14179                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
14180                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
14181                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
14182                 sed
14183                 PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0
14184
14185                 Configures MIO Pin 70 peripheral interface mapping
14186                 (OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000002U)
14187                 RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK |  0 );
14188
14189                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
14190                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
14191                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
14192                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
14193                         |  0 ) & RegMask); */
14194                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U);
14195         /*############################################################################################################################ */
14196
14197                 /*Register : MIO_PIN_71 @ 0XFF18011C</p>
14198
14199                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
14200                 PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  1
14201
14202                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14203                 ata[3]- (ULPI data bus)
14204                 PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0
14205
14206                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
14207                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
14208                 PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  0
14209
14210                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
14211                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
14212                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
14213                  ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
14214                 PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0
14215
14216                 Configures MIO Pin 71 peripheral interface mapping
14217                 (OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000002U)
14218                 RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK |  0 );
14219
14220                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
14221                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
14222                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
14223                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
14224                         |  0 ) & RegMask); */
14225                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U);
14226         /*############################################################################################################################ */
14227
14228                 /*Register : MIO_PIN_72 @ 0XFF180120</p>
14229
14230                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
14231                 PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  1
14232
14233                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14234                 ata[4]- (ULPI data bus)
14235                 PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0
14236
14237                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
14238                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
14239                 PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  0
14240
14241                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
14242                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
14243                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
14244                 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
14245                 PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0
14246
14247                 Configures MIO Pin 72 peripheral interface mapping
14248                 (OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000002U)
14249                 RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK |  0 );
14250
14251                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
14252                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
14253                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
14254                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
14255                         |  0 ) & RegMask); */
14256                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U);
14257         /*############################################################################################################################ */
14258
14259                 /*Register : MIO_PIN_73 @ 0XFF180124</p>
14260
14261                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
14262                 PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  1
14263
14264                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14265                 ata[5]- (ULPI data bus)
14266                 PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0
14267
14268                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
14269                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
14270                 PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  0
14271
14272                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
14273                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14274                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
14275                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
14276                 PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0
14277
14278                 Configures MIO Pin 73 peripheral interface mapping
14279                 (OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000002U)
14280                 RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK |  0 );
14281
14282                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
14283                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
14284                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
14285                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
14286                         |  0 ) & RegMask); */
14287                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U);
14288         /*############################################################################################################################ */
14289
14290                 /*Register : MIO_PIN_74 @ 0XFF180128</p>
14291
14292                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
14293                 PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  1
14294
14295                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14296                 ata[6]- (ULPI data bus)
14297                 PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0
14298
14299                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
14300                 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
14301                 PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  0
14302
14303                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
14304                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
14305                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
14306                 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
14307                 PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0
14308
14309                 Configures MIO Pin 74 peripheral interface mapping
14310                 (OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000002U)
14311                 RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK |  0 );
14312
14313                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
14314                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
14315                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
14316                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
14317                         |  0 ) & RegMask); */
14318                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U);
14319         /*############################################################################################################################ */
14320
14321                 /*Register : MIO_PIN_75 @ 0XFF18012C</p>
14322
14323                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
14324                 PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  1
14325
14326                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14327                 ata[7]- (ULPI data bus)
14328                 PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0
14329
14330                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
14331                 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
14332                 PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  0
14333
14334                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
14335                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
14336                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
14337                 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
14338                 PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0
14339
14340                 Configures MIO Pin 75 peripheral interface mapping
14341                 (OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000002U)
14342                 RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK |  0 );
14343
14344                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
14345                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
14346                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
14347                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
14348                         |  0 ) & RegMask); */
14349                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U);
14350         /*############################################################################################################################ */
14351
14352                 /*Register : MIO_PIN_76 @ 0XFF180130</p>
14353
14354                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
14355                 PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0
14356
14357                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
14358                 PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0
14359
14360                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
14361                 _clk_out- (SDSDIO clock) 3= Not Used
14362                 PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  0
14363
14364                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
14365                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
14366                 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
14367                  6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
14368                 PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  6
14369
14370                 Configures MIO Pin 76 peripheral interface mapping
14371                 (OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x000000C0U)
14372                 RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK |  0 );
14373
14374                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
14375                         | 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
14376                         | 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
14377                         | 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
14378                         |  0 ) & RegMask); */
14379                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U);
14380         /*############################################################################################################################ */
14381
14382                 /*Register : MIO_PIN_77 @ 0XFF180134</p>
14383
14384                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
14385                 PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0
14386
14387                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
14388                 PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0
14389
14390                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
14391                 PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0
14392
14393                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
14394                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14395                 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
14396                 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
14397                 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
14398                 PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  6
14399
14400                 Configures MIO Pin 77 peripheral interface mapping
14401                 (OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x000000C0U)
14402                 RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK |  0 );
14403
14404                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
14405                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
14406                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
14407                         | 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
14408                         |  0 ) & RegMask); */
14409                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U);
14410         /*############################################################################################################################ */
14411
14412                 /*Register : MIO_MST_TRI0 @ 0XFF180204</p>
14413
14414                 Master Tri-state Enable for pin 0, active high
14415                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0
14416
14417                 Master Tri-state Enable for pin 1, active high
14418                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0
14419
14420                 Master Tri-state Enable for pin 2, active high
14421                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0
14422
14423                 Master Tri-state Enable for pin 3, active high
14424                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0
14425
14426                 Master Tri-state Enable for pin 4, active high
14427                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0
14428
14429                 Master Tri-state Enable for pin 5, active high
14430                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0
14431
14432                 Master Tri-state Enable for pin 6, active high
14433                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0
14434
14435                 Master Tri-state Enable for pin 7, active high
14436                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0
14437
14438                 Master Tri-state Enable for pin 8, active high
14439                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0
14440
14441                 Master Tri-state Enable for pin 9, active high
14442                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0
14443
14444                 Master Tri-state Enable for pin 10, active high
14445                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            0
14446
14447                 Master Tri-state Enable for pin 11, active high
14448                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            0
14449
14450                 Master Tri-state Enable for pin 12, active high
14451                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0
14452
14453                 Master Tri-state Enable for pin 13, active high
14454                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0
14455
14456                 Master Tri-state Enable for pin 14, active high
14457                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0
14458
14459                 Master Tri-state Enable for pin 15, active high
14460                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0
14461
14462                 Master Tri-state Enable for pin 16, active high
14463                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0
14464
14465                 Master Tri-state Enable for pin 17, active high
14466                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0
14467
14468                 Master Tri-state Enable for pin 18, active high
14469                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            1
14470
14471                 Master Tri-state Enable for pin 19, active high
14472                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0
14473
14474                 Master Tri-state Enable for pin 20, active high
14475                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0
14476
14477                 Master Tri-state Enable for pin 21, active high
14478                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            1
14479
14480                 Master Tri-state Enable for pin 22, active high
14481                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0
14482
14483                 Master Tri-state Enable for pin 23, active high
14484                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0
14485
14486                 Master Tri-state Enable for pin 24, active high
14487                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0
14488
14489                 Master Tri-state Enable for pin 25, active high
14490                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            1
14491
14492                 Master Tri-state Enable for pin 26, active high
14493                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            0
14494
14495                 Master Tri-state Enable for pin 27, active high
14496                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0
14497
14498                 Master Tri-state Enable for pin 28, active high
14499                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            1
14500
14501                 Master Tri-state Enable for pin 29, active high
14502                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0
14503
14504                 Master Tri-state Enable for pin 30, active high
14505                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            1
14506
14507                 Master Tri-state Enable for pin 31, active high
14508                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0
14509
14510                 MIO pin Tri-state Enables, 31:0
14511                 (OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x52240000U)
14512                 RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK |  0 );
14513
14514                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
14515                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
14516                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
14517                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
14518                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
14519                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
14520                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
14521                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
14522                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
14523                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
14524                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
14525                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
14526                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
14527                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
14528                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
14529                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
14530                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
14531                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
14532                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
14533                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
14534                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
14535                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
14536                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
14537                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
14538                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
14539                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
14540                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
14541                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
14542                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
14543                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
14544                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
14545                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
14546                         |  0 ) & RegMask); */
14547                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U);
14548         /*############################################################################################################################ */
14549
14550                 /*Register : MIO_MST_TRI1 @ 0XFF180208</p>
14551
14552                 Master Tri-state Enable for pin 32, active high
14553                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0
14554
14555                 Master Tri-state Enable for pin 33, active high
14556                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0
14557
14558                 Master Tri-state Enable for pin 34, active high
14559                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0
14560
14561                 Master Tri-state Enable for pin 35, active high
14562                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0
14563
14564                 Master Tri-state Enable for pin 36, active high
14565                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0
14566
14567                 Master Tri-state Enable for pin 37, active high
14568                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0
14569
14570                 Master Tri-state Enable for pin 38, active high
14571                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0
14572
14573                 Master Tri-state Enable for pin 39, active high
14574                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0
14575
14576                 Master Tri-state Enable for pin 40, active high
14577                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0
14578
14579                 Master Tri-state Enable for pin 41, active high
14580                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0
14581
14582                 Master Tri-state Enable for pin 42, active high
14583                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0
14584
14585                 Master Tri-state Enable for pin 43, active high
14586                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0
14587
14588                 Master Tri-state Enable for pin 44, active high
14589                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            1
14590
14591                 Master Tri-state Enable for pin 45, active high
14592                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            1
14593
14594                 Master Tri-state Enable for pin 46, active high
14595                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0
14596
14597                 Master Tri-state Enable for pin 47, active high
14598                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0
14599
14600                 Master Tri-state Enable for pin 48, active high
14601                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0
14602
14603                 Master Tri-state Enable for pin 49, active high
14604                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0
14605
14606                 Master Tri-state Enable for pin 50, active high
14607                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0
14608
14609                 Master Tri-state Enable for pin 51, active high
14610                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0
14611
14612                 Master Tri-state Enable for pin 52, active high
14613                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1
14614
14615                 Master Tri-state Enable for pin 53, active high
14616                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1
14617
14618                 Master Tri-state Enable for pin 54, active high
14619                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0
14620
14621                 Master Tri-state Enable for pin 55, active high
14622                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1
14623
14624                 Master Tri-state Enable for pin 56, active high
14625                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0
14626
14627                 Master Tri-state Enable for pin 57, active high
14628                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0
14629
14630                 Master Tri-state Enable for pin 58, active high
14631                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0
14632
14633                 Master Tri-state Enable for pin 59, active high
14634                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0
14635
14636                 Master Tri-state Enable for pin 60, active high
14637                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0
14638
14639                 Master Tri-state Enable for pin 61, active high
14640                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0
14641
14642                 Master Tri-state Enable for pin 62, active high
14643                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0
14644
14645                 Master Tri-state Enable for pin 63, active high
14646                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0
14647
14648                 MIO pin Tri-state Enables, 63:32
14649                 (OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B03000U)
14650                 RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK |  0 );
14651
14652                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
14653                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
14654                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
14655                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
14656                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
14657                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
14658                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
14659                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
14660                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
14661                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
14662                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
14663                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
14664                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
14665                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
14666                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
14667                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
14668                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
14669                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
14670                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
14671                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
14672                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
14673                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
14674                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
14675                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
14676                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
14677                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
14678                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
14679                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
14680                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
14681                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
14682                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
14683                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
14684                         |  0 ) & RegMask); */
14685                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U);
14686         /*############################################################################################################################ */
14687
14688                 /*Register : MIO_MST_TRI2 @ 0XFF18020C</p>
14689
14690                 Master Tri-state Enable for pin 64, active high
14691                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0
14692
14693                 Master Tri-state Enable for pin 65, active high
14694                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            0
14695
14696                 Master Tri-state Enable for pin 66, active high
14697                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0
14698
14699                 Master Tri-state Enable for pin 67, active high
14700                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0
14701
14702                 Master Tri-state Enable for pin 68, active high
14703                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0
14704
14705                 Master Tri-state Enable for pin 69, active high
14706                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0
14707
14708                 Master Tri-state Enable for pin 70, active high
14709                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            1
14710
14711                 Master Tri-state Enable for pin 71, active high
14712                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            1
14713
14714                 Master Tri-state Enable for pin 72, active high
14715                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            1
14716
14717                 Master Tri-state Enable for pin 73, active high
14718                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            1
14719
14720                 Master Tri-state Enable for pin 74, active high
14721                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            1
14722
14723                 Master Tri-state Enable for pin 75, active high
14724                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            1
14725
14726                 Master Tri-state Enable for pin 76, active high
14727                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            0
14728
14729                 Master Tri-state Enable for pin 77, active high
14730                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0
14731
14732                 MIO pin Tri-state Enables, 77:64
14733                 (OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00000FC0U)
14734                 RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK |  0 );
14735
14736                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
14737                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
14738                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
14739                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
14740                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
14741                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
14742                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
14743                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
14744                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
14745                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
14746                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
14747                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
14748                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
14749                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
14750                         |  0 ) & RegMask); */
14751                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U);
14752         /*############################################################################################################################ */
14753
14754                 /*Register : bank0_ctrl0 @ 0XFF180138</p>
14755
14756                 Each bit applies to a single IO. Bit 0 for MIO[0].
14757                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0                                           1
14758
14759                 Each bit applies to a single IO. Bit 0 for MIO[0].
14760                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1                                           1
14761
14762                 Each bit applies to a single IO. Bit 0 for MIO[0].
14763                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2                                           1
14764
14765                 Each bit applies to a single IO. Bit 0 for MIO[0].
14766                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3                                           1
14767
14768                 Each bit applies to a single IO. Bit 0 for MIO[0].
14769                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4                                           1
14770
14771                 Each bit applies to a single IO. Bit 0 for MIO[0].
14772                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5                                           1
14773
14774                 Each bit applies to a single IO. Bit 0 for MIO[0].
14775                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6                                           1
14776
14777                 Each bit applies to a single IO. Bit 0 for MIO[0].
14778                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7                                           1
14779
14780                 Each bit applies to a single IO. Bit 0 for MIO[0].
14781                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8                                           1
14782
14783                 Each bit applies to a single IO. Bit 0 for MIO[0].
14784                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9                                           1
14785
14786                 Each bit applies to a single IO. Bit 0 for MIO[0].
14787                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10                                          1
14788
14789                 Each bit applies to a single IO. Bit 0 for MIO[0].
14790                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11                                          1
14791
14792                 Each bit applies to a single IO. Bit 0 for MIO[0].
14793                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12                                          1
14794
14795                 Each bit applies to a single IO. Bit 0 for MIO[0].
14796                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13                                          1
14797
14798                 Each bit applies to a single IO. Bit 0 for MIO[0].
14799                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14                                          1
14800
14801                 Each bit applies to a single IO. Bit 0 for MIO[0].
14802                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15                                          1
14803
14804                 Each bit applies to a single IO. Bit 0 for MIO[0].
14805                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16                                          1
14806
14807                 Each bit applies to a single IO. Bit 0 for MIO[0].
14808                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17                                          1
14809
14810                 Each bit applies to a single IO. Bit 0 for MIO[0].
14811                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18                                          1
14812
14813                 Each bit applies to a single IO. Bit 0 for MIO[0].
14814                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19                                          1
14815
14816                 Each bit applies to a single IO. Bit 0 for MIO[0].
14817                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20                                          1
14818
14819                 Each bit applies to a single IO. Bit 0 for MIO[0].
14820                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21                                          1
14821
14822                 Each bit applies to a single IO. Bit 0 for MIO[0].
14823                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22                                          1
14824
14825                 Each bit applies to a single IO. Bit 0 for MIO[0].
14826                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23                                          1
14827
14828                 Each bit applies to a single IO. Bit 0 for MIO[0].
14829                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24                                          1
14830
14831                 Each bit applies to a single IO. Bit 0 for MIO[0].
14832                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25                                          1
14833
14834                 Drive0 control to MIO Bank 0 - control MIO[25:0]
14835                 (OFFSET, MASK, VALUE)      (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU)
14836                 RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK |  0 );
14837
14838                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
14839                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
14840                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
14841                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
14842                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
14843                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
14844                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
14845                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
14846                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
14847                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
14848                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
14849                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
14850                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
14851                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
14852                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
14853                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
14854                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
14855                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
14856                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
14857                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
14858                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
14859                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
14860                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
14861                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
14862                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
14863                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
14864                         |  0 ) & RegMask); */
14865                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
14866         /*############################################################################################################################ */
14867
14868                 /*Register : bank0_ctrl1 @ 0XFF18013C</p>
14869
14870                 Each bit applies to a single IO. Bit 0 for MIO[0].
14871                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0                                           1
14872
14873                 Each bit applies to a single IO. Bit 0 for MIO[0].
14874                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1                                           1
14875
14876                 Each bit applies to a single IO. Bit 0 for MIO[0].
14877                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2                                           1
14878
14879                 Each bit applies to a single IO. Bit 0 for MIO[0].
14880                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3                                           1
14881
14882                 Each bit applies to a single IO. Bit 0 for MIO[0].
14883                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4                                           1
14884
14885                 Each bit applies to a single IO. Bit 0 for MIO[0].
14886                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5                                           1
14887
14888                 Each bit applies to a single IO. Bit 0 for MIO[0].
14889                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6                                           1
14890
14891                 Each bit applies to a single IO. Bit 0 for MIO[0].
14892                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7                                           1
14893
14894                 Each bit applies to a single IO. Bit 0 for MIO[0].
14895                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8                                           1
14896
14897                 Each bit applies to a single IO. Bit 0 for MIO[0].
14898                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9                                           1
14899
14900                 Each bit applies to a single IO. Bit 0 for MIO[0].
14901                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10                                          1
14902
14903                 Each bit applies to a single IO. Bit 0 for MIO[0].
14904                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11                                          1
14905
14906                 Each bit applies to a single IO. Bit 0 for MIO[0].
14907                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12                                          1
14908
14909                 Each bit applies to a single IO. Bit 0 for MIO[0].
14910                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13                                          1
14911
14912                 Each bit applies to a single IO. Bit 0 for MIO[0].
14913                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14                                          1
14914
14915                 Each bit applies to a single IO. Bit 0 for MIO[0].
14916                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15                                          1
14917
14918                 Each bit applies to a single IO. Bit 0 for MIO[0].
14919                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16                                          1
14920
14921                 Each bit applies to a single IO. Bit 0 for MIO[0].
14922                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17                                          1
14923
14924                 Each bit applies to a single IO. Bit 0 for MIO[0].
14925                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18                                          1
14926
14927                 Each bit applies to a single IO. Bit 0 for MIO[0].
14928                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19                                          1
14929
14930                 Each bit applies to a single IO. Bit 0 for MIO[0].
14931                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20                                          1
14932
14933                 Each bit applies to a single IO. Bit 0 for MIO[0].
14934                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21                                          1
14935
14936                 Each bit applies to a single IO. Bit 0 for MIO[0].
14937                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22                                          1
14938
14939                 Each bit applies to a single IO. Bit 0 for MIO[0].
14940                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23                                          1
14941
14942                 Each bit applies to a single IO. Bit 0 for MIO[0].
14943                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24                                          1
14944
14945                 Each bit applies to a single IO. Bit 0 for MIO[0].
14946                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25                                          1
14947
14948                 Drive1 control to MIO Bank 0 - control MIO[25:0]
14949                 (OFFSET, MASK, VALUE)      (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU)
14950                 RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK |  0 );
14951
14952                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
14953                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
14954                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
14955                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
14956                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
14957                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
14958                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
14959                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
14960                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
14961                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
14962                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
14963                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
14964                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
14965                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
14966                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
14967                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
14968                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
14969                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
14970                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
14971                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
14972                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
14973                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
14974                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
14975                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
14976                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
14977                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
14978                         |  0 ) & RegMask); */
14979                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
14980         /*############################################################################################################################ */
14981
14982                 /*Register : bank0_ctrl3 @ 0XFF180140</p>
14983
14984                 Each bit applies to a single IO. Bit 0 for MIO[0].
14985                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
14986
14987                 Each bit applies to a single IO. Bit 0 for MIO[0].
14988                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
14989
14990                 Each bit applies to a single IO. Bit 0 for MIO[0].
14991                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
14992
14993                 Each bit applies to a single IO. Bit 0 for MIO[0].
14994                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
14995
14996                 Each bit applies to a single IO. Bit 0 for MIO[0].
14997                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
14998
14999                 Each bit applies to a single IO. Bit 0 for MIO[0].
15000                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
15001
15002                 Each bit applies to a single IO. Bit 0 for MIO[0].
15003                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
15004
15005                 Each bit applies to a single IO. Bit 0 for MIO[0].
15006                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
15007
15008                 Each bit applies to a single IO. Bit 0 for MIO[0].
15009                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
15010
15011                 Each bit applies to a single IO. Bit 0 for MIO[0].
15012                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
15013
15014                 Each bit applies to a single IO. Bit 0 for MIO[0].
15015                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
15016
15017                 Each bit applies to a single IO. Bit 0 for MIO[0].
15018                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
15019
15020                 Each bit applies to a single IO. Bit 0 for MIO[0].
15021                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
15022
15023                 Each bit applies to a single IO. Bit 0 for MIO[0].
15024                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
15025
15026                 Each bit applies to a single IO. Bit 0 for MIO[0].
15027                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
15028
15029                 Each bit applies to a single IO. Bit 0 for MIO[0].
15030                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
15031
15032                 Each bit applies to a single IO. Bit 0 for MIO[0].
15033                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
15034
15035                 Each bit applies to a single IO. Bit 0 for MIO[0].
15036                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
15037
15038                 Each bit applies to a single IO. Bit 0 for MIO[0].
15039                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
15040
15041                 Each bit applies to a single IO. Bit 0 for MIO[0].
15042                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
15043
15044                 Each bit applies to a single IO. Bit 0 for MIO[0].
15045                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
15046
15047                 Each bit applies to a single IO. Bit 0 for MIO[0].
15048                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
15049
15050                 Each bit applies to a single IO. Bit 0 for MIO[0].
15051                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
15052
15053                 Each bit applies to a single IO. Bit 0 for MIO[0].
15054                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
15055
15056                 Each bit applies to a single IO. Bit 0 for MIO[0].
15057                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
15058
15059                 Each bit applies to a single IO. Bit 0 for MIO[0].
15060                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
15061
15062                 Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
15063                 (OFFSET, MASK, VALUE)      (0XFF180140, 0x03FFFFFFU ,0x00000000U)
15064                 RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
15065
15066                 RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
15067                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
15068                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
15069                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
15070                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
15071                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
15072                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
15073                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
15074                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
15075                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
15076                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
15077                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
15078                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
15079                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
15080                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
15081                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
15082                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
15083                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
15084                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
15085                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
15086                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
15087                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
15088                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
15089                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
15090                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
15091                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
15092                         |  0 ) & RegMask); */
15093                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
15094         /*############################################################################################################################ */
15095
15096                 /*Register : bank0_ctrl4 @ 0XFF180144</p>
15097
15098                 Each bit applies to a single IO. Bit 0 for MIO[0].
15099                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
15100
15101                 Each bit applies to a single IO. Bit 0 for MIO[0].
15102                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
15103
15104                 Each bit applies to a single IO. Bit 0 for MIO[0].
15105                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
15106
15107                 Each bit applies to a single IO. Bit 0 for MIO[0].
15108                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
15109
15110                 Each bit applies to a single IO. Bit 0 for MIO[0].
15111                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
15112
15113                 Each bit applies to a single IO. Bit 0 for MIO[0].
15114                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
15115
15116                 Each bit applies to a single IO. Bit 0 for MIO[0].
15117                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
15118
15119                 Each bit applies to a single IO. Bit 0 for MIO[0].
15120                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
15121
15122                 Each bit applies to a single IO. Bit 0 for MIO[0].
15123                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
15124
15125                 Each bit applies to a single IO. Bit 0 for MIO[0].
15126                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
15127
15128                 Each bit applies to a single IO. Bit 0 for MIO[0].
15129                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
15130
15131                 Each bit applies to a single IO. Bit 0 for MIO[0].
15132                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
15133
15134                 Each bit applies to a single IO. Bit 0 for MIO[0].
15135                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
15136
15137                 Each bit applies to a single IO. Bit 0 for MIO[0].
15138                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
15139
15140                 Each bit applies to a single IO. Bit 0 for MIO[0].
15141                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
15142
15143                 Each bit applies to a single IO. Bit 0 for MIO[0].
15144                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
15145
15146                 Each bit applies to a single IO. Bit 0 for MIO[0].
15147                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
15148
15149                 Each bit applies to a single IO. Bit 0 for MIO[0].
15150                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
15151
15152                 Each bit applies to a single IO. Bit 0 for MIO[0].
15153                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
15154
15155                 Each bit applies to a single IO. Bit 0 for MIO[0].
15156                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
15157
15158                 Each bit applies to a single IO. Bit 0 for MIO[0].
15159                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
15160
15161                 Each bit applies to a single IO. Bit 0 for MIO[0].
15162                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
15163
15164                 Each bit applies to a single IO. Bit 0 for MIO[0].
15165                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
15166
15167                 Each bit applies to a single IO. Bit 0 for MIO[0].
15168                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
15169
15170                 Each bit applies to a single IO. Bit 0 for MIO[0].
15171                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
15172
15173                 Each bit applies to a single IO. Bit 0 for MIO[0].
15174                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
15175
15176                 When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
15177                 (OFFSET, MASK, VALUE)      (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU)
15178                 RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
15179
15180                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
15181                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
15182                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
15183                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
15184                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
15185                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
15186                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
15187                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
15188                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
15189                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
15190                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
15191                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
15192                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
15193                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
15194                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
15195                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
15196                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
15197                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
15198                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
15199                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
15200                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
15201                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
15202                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
15203                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
15204                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
15205                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
15206                         |  0 ) & RegMask); */
15207                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15208         /*############################################################################################################################ */
15209
15210                 /*Register : bank0_ctrl5 @ 0XFF180148</p>
15211
15212                 Each bit applies to a single IO. Bit 0 for MIO[0].
15213                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0                                      1
15214
15215                 Each bit applies to a single IO. Bit 0 for MIO[0].
15216                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1                                      1
15217
15218                 Each bit applies to a single IO. Bit 0 for MIO[0].
15219                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2                                      1
15220
15221                 Each bit applies to a single IO. Bit 0 for MIO[0].
15222                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3                                      1
15223
15224                 Each bit applies to a single IO. Bit 0 for MIO[0].
15225                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4                                      1
15226
15227                 Each bit applies to a single IO. Bit 0 for MIO[0].
15228                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5                                      1
15229
15230                 Each bit applies to a single IO. Bit 0 for MIO[0].
15231                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6                                      1
15232
15233                 Each bit applies to a single IO. Bit 0 for MIO[0].
15234                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7                                      1
15235
15236                 Each bit applies to a single IO. Bit 0 for MIO[0].
15237                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8                                      1
15238
15239                 Each bit applies to a single IO. Bit 0 for MIO[0].
15240                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9                                      1
15241
15242                 Each bit applies to a single IO. Bit 0 for MIO[0].
15243                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10                                     1
15244
15245                 Each bit applies to a single IO. Bit 0 for MIO[0].
15246                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11                                     1
15247
15248                 Each bit applies to a single IO. Bit 0 for MIO[0].
15249                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12                                     1
15250
15251                 Each bit applies to a single IO. Bit 0 for MIO[0].
15252                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13                                     1
15253
15254                 Each bit applies to a single IO. Bit 0 for MIO[0].
15255                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14                                     1
15256
15257                 Each bit applies to a single IO. Bit 0 for MIO[0].
15258                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15                                     1
15259
15260                 Each bit applies to a single IO. Bit 0 for MIO[0].
15261                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16                                     1
15262
15263                 Each bit applies to a single IO. Bit 0 for MIO[0].
15264                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17                                     1
15265
15266                 Each bit applies to a single IO. Bit 0 for MIO[0].
15267                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18                                     1
15268
15269                 Each bit applies to a single IO. Bit 0 for MIO[0].
15270                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19                                     1
15271
15272                 Each bit applies to a single IO. Bit 0 for MIO[0].
15273                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20                                     1
15274
15275                 Each bit applies to a single IO. Bit 0 for MIO[0].
15276                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21                                     1
15277
15278                 Each bit applies to a single IO. Bit 0 for MIO[0].
15279                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22                                     1
15280
15281                 Each bit applies to a single IO. Bit 0 for MIO[0].
15282                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23                                     1
15283
15284                 Each bit applies to a single IO. Bit 0 for MIO[0].
15285                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24                                     1
15286
15287                 Each bit applies to a single IO. Bit 0 for MIO[0].
15288                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25                                     1
15289
15290                 When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
15291                 (OFFSET, MASK, VALUE)      (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU)
15292                 RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
15293
15294                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
15295                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
15296                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
15297                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
15298                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
15299                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
15300                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
15301                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
15302                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
15303                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
15304                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
15305                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
15306                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
15307                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
15308                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
15309                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
15310                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
15311                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
15312                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
15313                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
15314                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
15315                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
15316                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
15317                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
15318                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
15319                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
15320                         |  0 ) & RegMask); */
15321                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15322         /*############################################################################################################################ */
15323
15324                 /*Register : bank0_ctrl6 @ 0XFF18014C</p>
15325
15326                 Each bit applies to a single IO. Bit 0 for MIO[0].
15327                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
15328
15329                 Each bit applies to a single IO. Bit 0 for MIO[0].
15330                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
15331
15332                 Each bit applies to a single IO. Bit 0 for MIO[0].
15333                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
15334
15335                 Each bit applies to a single IO. Bit 0 for MIO[0].
15336                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
15337
15338                 Each bit applies to a single IO. Bit 0 for MIO[0].
15339                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
15340
15341                 Each bit applies to a single IO. Bit 0 for MIO[0].
15342                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
15343
15344                 Each bit applies to a single IO. Bit 0 for MIO[0].
15345                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
15346
15347                 Each bit applies to a single IO. Bit 0 for MIO[0].
15348                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
15349
15350                 Each bit applies to a single IO. Bit 0 for MIO[0].
15351                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
15352
15353                 Each bit applies to a single IO. Bit 0 for MIO[0].
15354                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
15355
15356                 Each bit applies to a single IO. Bit 0 for MIO[0].
15357                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
15358
15359                 Each bit applies to a single IO. Bit 0 for MIO[0].
15360                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
15361
15362                 Each bit applies to a single IO. Bit 0 for MIO[0].
15363                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
15364
15365                 Each bit applies to a single IO. Bit 0 for MIO[0].
15366                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
15367
15368                 Each bit applies to a single IO. Bit 0 for MIO[0].
15369                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
15370
15371                 Each bit applies to a single IO. Bit 0 for MIO[0].
15372                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
15373
15374                 Each bit applies to a single IO. Bit 0 for MIO[0].
15375                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
15376
15377                 Each bit applies to a single IO. Bit 0 for MIO[0].
15378                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
15379
15380                 Each bit applies to a single IO. Bit 0 for MIO[0].
15381                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
15382
15383                 Each bit applies to a single IO. Bit 0 for MIO[0].
15384                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
15385
15386                 Each bit applies to a single IO. Bit 0 for MIO[0].
15387                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
15388
15389                 Each bit applies to a single IO. Bit 0 for MIO[0].
15390                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
15391
15392                 Each bit applies to a single IO. Bit 0 for MIO[0].
15393                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
15394
15395                 Each bit applies to a single IO. Bit 0 for MIO[0].
15396                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
15397
15398                 Each bit applies to a single IO. Bit 0 for MIO[0].
15399                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
15400
15401                 Each bit applies to a single IO. Bit 0 for MIO[0].
15402                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
15403
15404                 Slew rate control to MIO Bank 0 - control MIO[25:0]
15405                 (OFFSET, MASK, VALUE)      (0XFF18014C, 0x03FFFFFFU ,0x00000000U)
15406                 RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
15407
15408                 RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
15409                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
15410                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
15411                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
15412                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
15413                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
15414                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
15415                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
15416                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
15417                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
15418                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
15419                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
15420                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
15421                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
15422                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
15423                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
15424                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
15425                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
15426                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
15427                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
15428                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
15429                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
15430                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
15431                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
15432                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
15433                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
15434                         |  0 ) & RegMask); */
15435                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
15436         /*############################################################################################################################ */
15437
15438                 /*Register : bank1_ctrl0 @ 0XFF180154</p>
15439
15440                 Each bit applies to a single IO. Bit 0 for MIO[26].
15441                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0                                           1
15442
15443                 Each bit applies to a single IO. Bit 0 for MIO[26].
15444                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1                                           1
15445
15446                 Each bit applies to a single IO. Bit 0 for MIO[26].
15447                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2                                           1
15448
15449                 Each bit applies to a single IO. Bit 0 for MIO[26].
15450                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3                                           1
15451
15452                 Each bit applies to a single IO. Bit 0 for MIO[26].
15453                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4                                           1
15454
15455                 Each bit applies to a single IO. Bit 0 for MIO[26].
15456                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5                                           1
15457
15458                 Each bit applies to a single IO. Bit 0 for MIO[26].
15459                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6                                           1
15460
15461                 Each bit applies to a single IO. Bit 0 for MIO[26].
15462                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7                                           1
15463
15464                 Each bit applies to a single IO. Bit 0 for MIO[26].
15465                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8                                           1
15466
15467                 Each bit applies to a single IO. Bit 0 for MIO[26].
15468                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9                                           1
15469
15470                 Each bit applies to a single IO. Bit 0 for MIO[26].
15471                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10                                          1
15472
15473                 Each bit applies to a single IO. Bit 0 for MIO[26].
15474                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11                                          1
15475
15476                 Each bit applies to a single IO. Bit 0 for MIO[26].
15477                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12                                          1
15478
15479                 Each bit applies to a single IO. Bit 0 for MIO[26].
15480                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13                                          1
15481
15482                 Each bit applies to a single IO. Bit 0 for MIO[26].
15483                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14                                          1
15484
15485                 Each bit applies to a single IO. Bit 0 for MIO[26].
15486                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15                                          1
15487
15488                 Each bit applies to a single IO. Bit 0 for MIO[26].
15489                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16                                          1
15490
15491                 Each bit applies to a single IO. Bit 0 for MIO[26].
15492                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17                                          1
15493
15494                 Each bit applies to a single IO. Bit 0 for MIO[26].
15495                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18                                          1
15496
15497                 Each bit applies to a single IO. Bit 0 for MIO[26].
15498                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19                                          1
15499
15500                 Each bit applies to a single IO. Bit 0 for MIO[26].
15501                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20                                          1
15502
15503                 Each bit applies to a single IO. Bit 0 for MIO[26].
15504                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21                                          1
15505
15506                 Each bit applies to a single IO. Bit 0 for MIO[26].
15507                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22                                          1
15508
15509                 Each bit applies to a single IO. Bit 0 for MIO[26].
15510                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23                                          1
15511
15512                 Each bit applies to a single IO. Bit 0 for MIO[26].
15513                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24                                          1
15514
15515                 Each bit applies to a single IO. Bit 0 for MIO[26].
15516                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25                                          1
15517
15518                 Drive0 control to MIO Bank 1 - control MIO[51:26]
15519                 (OFFSET, MASK, VALUE)      (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU)
15520                 RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK |  0 );
15521
15522                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
15523                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
15524                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
15525                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
15526                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
15527                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
15528                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
15529                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
15530                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
15531                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
15532                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
15533                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
15534                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
15535                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
15536                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
15537                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
15538                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
15539                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
15540                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
15541                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
15542                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
15543                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
15544                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
15545                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
15546                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
15547                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
15548                         |  0 ) & RegMask); */
15549                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15550         /*############################################################################################################################ */
15551
15552                 /*Register : bank1_ctrl1 @ 0XFF180158</p>
15553
15554                 Each bit applies to a single IO. Bit 0 for MIO[26].
15555                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0                                           1
15556
15557                 Each bit applies to a single IO. Bit 0 for MIO[26].
15558                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1                                           1
15559
15560                 Each bit applies to a single IO. Bit 0 for MIO[26].
15561                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2                                           1
15562
15563                 Each bit applies to a single IO. Bit 0 for MIO[26].
15564                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3                                           1
15565
15566                 Each bit applies to a single IO. Bit 0 for MIO[26].
15567                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4                                           1
15568
15569                 Each bit applies to a single IO. Bit 0 for MIO[26].
15570                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5                                           1
15571
15572                 Each bit applies to a single IO. Bit 0 for MIO[26].
15573                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6                                           1
15574
15575                 Each bit applies to a single IO. Bit 0 for MIO[26].
15576                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7                                           1
15577
15578                 Each bit applies to a single IO. Bit 0 for MIO[26].
15579                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8                                           1
15580
15581                 Each bit applies to a single IO. Bit 0 for MIO[26].
15582                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9                                           1
15583
15584                 Each bit applies to a single IO. Bit 0 for MIO[26].
15585                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10                                          1
15586
15587                 Each bit applies to a single IO. Bit 0 for MIO[26].
15588                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11                                          1
15589
15590                 Each bit applies to a single IO. Bit 0 for MIO[26].
15591                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12                                          1
15592
15593                 Each bit applies to a single IO. Bit 0 for MIO[26].
15594                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13                                          1
15595
15596                 Each bit applies to a single IO. Bit 0 for MIO[26].
15597                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14                                          1
15598
15599                 Each bit applies to a single IO. Bit 0 for MIO[26].
15600                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15                                          1
15601
15602                 Each bit applies to a single IO. Bit 0 for MIO[26].
15603                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16                                          1
15604
15605                 Each bit applies to a single IO. Bit 0 for MIO[26].
15606                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17                                          1
15607
15608                 Each bit applies to a single IO. Bit 0 for MIO[26].
15609                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18                                          1
15610
15611                 Each bit applies to a single IO. Bit 0 for MIO[26].
15612                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19                                          1
15613
15614                 Each bit applies to a single IO. Bit 0 for MIO[26].
15615                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20                                          1
15616
15617                 Each bit applies to a single IO. Bit 0 for MIO[26].
15618                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21                                          1
15619
15620                 Each bit applies to a single IO. Bit 0 for MIO[26].
15621                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22                                          1
15622
15623                 Each bit applies to a single IO. Bit 0 for MIO[26].
15624                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23                                          1
15625
15626                 Each bit applies to a single IO. Bit 0 for MIO[26].
15627                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24                                          1
15628
15629                 Each bit applies to a single IO. Bit 0 for MIO[26].
15630                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25                                          1
15631
15632                 Drive1 control to MIO Bank 1 - control MIO[51:26]
15633                 (OFFSET, MASK, VALUE)      (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU)
15634                 RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK |  0 );
15635
15636                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
15637                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
15638                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
15639                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
15640                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
15641                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
15642                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
15643                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
15644                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
15645                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
15646                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
15647                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
15648                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
15649                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
15650                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
15651                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
15652                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
15653                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
15654                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
15655                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
15656                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
15657                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
15658                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
15659                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
15660                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
15661                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
15662                         |  0 ) & RegMask); */
15663                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15664         /*############################################################################################################################ */
15665
15666                 /*Register : bank1_ctrl3 @ 0XFF18015C</p>
15667
15668                 Each bit applies to a single IO. Bit 0 for MIO[26].
15669                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
15670
15671                 Each bit applies to a single IO. Bit 0 for MIO[26].
15672                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
15673
15674                 Each bit applies to a single IO. Bit 0 for MIO[26].
15675                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
15676
15677                 Each bit applies to a single IO. Bit 0 for MIO[26].
15678                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
15679
15680                 Each bit applies to a single IO. Bit 0 for MIO[26].
15681                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
15682
15683                 Each bit applies to a single IO. Bit 0 for MIO[26].
15684                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
15685
15686                 Each bit applies to a single IO. Bit 0 for MIO[26].
15687                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
15688
15689                 Each bit applies to a single IO. Bit 0 for MIO[26].
15690                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
15691
15692                 Each bit applies to a single IO. Bit 0 for MIO[26].
15693                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
15694
15695                 Each bit applies to a single IO. Bit 0 for MIO[26].
15696                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
15697
15698                 Each bit applies to a single IO. Bit 0 for MIO[26].
15699                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
15700
15701                 Each bit applies to a single IO. Bit 0 for MIO[26].
15702                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
15703
15704                 Each bit applies to a single IO. Bit 0 for MIO[26].
15705                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
15706
15707                 Each bit applies to a single IO. Bit 0 for MIO[26].
15708                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
15709
15710                 Each bit applies to a single IO. Bit 0 for MIO[26].
15711                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
15712
15713                 Each bit applies to a single IO. Bit 0 for MIO[26].
15714                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
15715
15716                 Each bit applies to a single IO. Bit 0 for MIO[26].
15717                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
15718
15719                 Each bit applies to a single IO. Bit 0 for MIO[26].
15720                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
15721
15722                 Each bit applies to a single IO. Bit 0 for MIO[26].
15723                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
15724
15725                 Each bit applies to a single IO. Bit 0 for MIO[26].
15726                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
15727
15728                 Each bit applies to a single IO. Bit 0 for MIO[26].
15729                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
15730
15731                 Each bit applies to a single IO. Bit 0 for MIO[26].
15732                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
15733
15734                 Each bit applies to a single IO. Bit 0 for MIO[26].
15735                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
15736
15737                 Each bit applies to a single IO. Bit 0 for MIO[26].
15738                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
15739
15740                 Each bit applies to a single IO. Bit 0 for MIO[26].
15741                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
15742
15743                 Each bit applies to a single IO. Bit 0 for MIO[26].
15744                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
15745
15746                 Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
15747                 (OFFSET, MASK, VALUE)      (0XFF18015C, 0x03FFFFFFU ,0x00000000U)
15748                 RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
15749
15750                 RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
15751                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
15752                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
15753                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
15754                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
15755                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
15756                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
15757                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
15758                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
15759                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
15760                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
15761                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
15762                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
15763                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
15764                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
15765                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
15766                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
15767                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
15768                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
15769                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
15770                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
15771                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
15772                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
15773                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
15774                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
15775                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
15776                         |  0 ) & RegMask); */
15777                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
15778         /*############################################################################################################################ */
15779
15780                 /*Register : bank1_ctrl4 @ 0XFF180160</p>
15781
15782                 Each bit applies to a single IO. Bit 0 for MIO[26].
15783                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
15784
15785                 Each bit applies to a single IO. Bit 0 for MIO[26].
15786                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
15787
15788                 Each bit applies to a single IO. Bit 0 for MIO[26].
15789                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
15790
15791                 Each bit applies to a single IO. Bit 0 for MIO[26].
15792                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
15793
15794                 Each bit applies to a single IO. Bit 0 for MIO[26].
15795                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
15796
15797                 Each bit applies to a single IO. Bit 0 for MIO[26].
15798                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
15799
15800                 Each bit applies to a single IO. Bit 0 for MIO[26].
15801                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
15802
15803                 Each bit applies to a single IO. Bit 0 for MIO[26].
15804                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
15805
15806                 Each bit applies to a single IO. Bit 0 for MIO[26].
15807                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
15808
15809                 Each bit applies to a single IO. Bit 0 for MIO[26].
15810                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
15811
15812                 Each bit applies to a single IO. Bit 0 for MIO[26].
15813                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
15814
15815                 Each bit applies to a single IO. Bit 0 for MIO[26].
15816                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
15817
15818                 Each bit applies to a single IO. Bit 0 for MIO[26].
15819                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
15820
15821                 Each bit applies to a single IO. Bit 0 for MIO[26].
15822                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
15823
15824                 Each bit applies to a single IO. Bit 0 for MIO[26].
15825                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
15826
15827                 Each bit applies to a single IO. Bit 0 for MIO[26].
15828                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
15829
15830                 Each bit applies to a single IO. Bit 0 for MIO[26].
15831                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
15832
15833                 Each bit applies to a single IO. Bit 0 for MIO[26].
15834                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
15835
15836                 Each bit applies to a single IO. Bit 0 for MIO[26].
15837                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
15838
15839                 Each bit applies to a single IO. Bit 0 for MIO[26].
15840                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
15841
15842                 Each bit applies to a single IO. Bit 0 for MIO[26].
15843                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
15844
15845                 Each bit applies to a single IO. Bit 0 for MIO[26].
15846                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
15847
15848                 Each bit applies to a single IO. Bit 0 for MIO[26].
15849                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
15850
15851                 Each bit applies to a single IO. Bit 0 for MIO[26].
15852                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
15853
15854                 Each bit applies to a single IO. Bit 0 for MIO[26].
15855                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
15856
15857                 Each bit applies to a single IO. Bit 0 for MIO[26].
15858                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
15859
15860                 When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
15861                 (OFFSET, MASK, VALUE)      (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU)
15862                 RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
15863
15864                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
15865                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
15866                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
15867                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
15868                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
15869                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
15870                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
15871                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
15872                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
15873                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
15874                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
15875                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
15876                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
15877                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
15878                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
15879                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
15880                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
15881                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
15882                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
15883                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
15884                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
15885                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
15886                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
15887                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
15888                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
15889                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
15890                         |  0 ) & RegMask); */
15891                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15892         /*############################################################################################################################ */
15893
15894                 /*Register : bank1_ctrl5 @ 0XFF180164</p>
15895
15896                 Each bit applies to a single IO. Bit 0 for MIO[26].
15897                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0                                      1
15898
15899                 Each bit applies to a single IO. Bit 0 for MIO[26].
15900                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1                                      1
15901
15902                 Each bit applies to a single IO. Bit 0 for MIO[26].
15903                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2                                      1
15904
15905                 Each bit applies to a single IO. Bit 0 for MIO[26].
15906                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3                                      1
15907
15908                 Each bit applies to a single IO. Bit 0 for MIO[26].
15909                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4                                      1
15910
15911                 Each bit applies to a single IO. Bit 0 for MIO[26].
15912                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5                                      1
15913
15914                 Each bit applies to a single IO. Bit 0 for MIO[26].
15915                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6                                      1
15916
15917                 Each bit applies to a single IO. Bit 0 for MIO[26].
15918                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7                                      1
15919
15920                 Each bit applies to a single IO. Bit 0 for MIO[26].
15921                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8                                      1
15922
15923                 Each bit applies to a single IO. Bit 0 for MIO[26].
15924                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9                                      1
15925
15926                 Each bit applies to a single IO. Bit 0 for MIO[26].
15927                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10                                     1
15928
15929                 Each bit applies to a single IO. Bit 0 for MIO[26].
15930                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11                                     1
15931
15932                 Each bit applies to a single IO. Bit 0 for MIO[26].
15933                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12                                     1
15934
15935                 Each bit applies to a single IO. Bit 0 for MIO[26].
15936                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13                                     1
15937
15938                 Each bit applies to a single IO. Bit 0 for MIO[26].
15939                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14                                     1
15940
15941                 Each bit applies to a single IO. Bit 0 for MIO[26].
15942                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15                                     1
15943
15944                 Each bit applies to a single IO. Bit 0 for MIO[26].
15945                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16                                     1
15946
15947                 Each bit applies to a single IO. Bit 0 for MIO[26].
15948                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17                                     1
15949
15950                 Each bit applies to a single IO. Bit 0 for MIO[26].
15951                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18                                     1
15952
15953                 Each bit applies to a single IO. Bit 0 for MIO[26].
15954                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19                                     1
15955
15956                 Each bit applies to a single IO. Bit 0 for MIO[26].
15957                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20                                     1
15958
15959                 Each bit applies to a single IO. Bit 0 for MIO[26].
15960                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21                                     1
15961
15962                 Each bit applies to a single IO. Bit 0 for MIO[26].
15963                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22                                     1
15964
15965                 Each bit applies to a single IO. Bit 0 for MIO[26].
15966                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23                                     1
15967
15968                 Each bit applies to a single IO. Bit 0 for MIO[26].
15969                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24                                     1
15970
15971                 Each bit applies to a single IO. Bit 0 for MIO[26].
15972                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25                                     1
15973
15974                 When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
15975                 (OFFSET, MASK, VALUE)      (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU)
15976                 RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
15977
15978                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
15979                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
15980                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
15981                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
15982                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
15983                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
15984                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
15985                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
15986                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
15987                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
15988                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
15989                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
15990                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
15991                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
15992                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
15993                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
15994                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
15995                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
15996                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
15997                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
15998                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
15999                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
16000                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
16001                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
16002                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
16003                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
16004                         |  0 ) & RegMask); */
16005                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16006         /*############################################################################################################################ */
16007
16008                 /*Register : bank1_ctrl6 @ 0XFF180168</p>
16009
16010                 Each bit applies to a single IO. Bit 0 for MIO[26].
16011                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
16012
16013                 Each bit applies to a single IO. Bit 0 for MIO[26].
16014                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
16015
16016                 Each bit applies to a single IO. Bit 0 for MIO[26].
16017                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
16018
16019                 Each bit applies to a single IO. Bit 0 for MIO[26].
16020                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
16021
16022                 Each bit applies to a single IO. Bit 0 for MIO[26].
16023                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
16024
16025                 Each bit applies to a single IO. Bit 0 for MIO[26].
16026                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
16027
16028                 Each bit applies to a single IO. Bit 0 for MIO[26].
16029                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
16030
16031                 Each bit applies to a single IO. Bit 0 for MIO[26].
16032                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
16033
16034                 Each bit applies to a single IO. Bit 0 for MIO[26].
16035                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
16036
16037                 Each bit applies to a single IO. Bit 0 for MIO[26].
16038                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
16039
16040                 Each bit applies to a single IO. Bit 0 for MIO[26].
16041                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
16042
16043                 Each bit applies to a single IO. Bit 0 for MIO[26].
16044                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
16045
16046                 Each bit applies to a single IO. Bit 0 for MIO[26].
16047                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
16048
16049                 Each bit applies to a single IO. Bit 0 for MIO[26].
16050                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
16051
16052                 Each bit applies to a single IO. Bit 0 for MIO[26].
16053                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
16054
16055                 Each bit applies to a single IO. Bit 0 for MIO[26].
16056                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
16057
16058                 Each bit applies to a single IO. Bit 0 for MIO[26].
16059                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
16060
16061                 Each bit applies to a single IO. Bit 0 for MIO[26].
16062                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
16063
16064                 Each bit applies to a single IO. Bit 0 for MIO[26].
16065                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
16066
16067                 Each bit applies to a single IO. Bit 0 for MIO[26].
16068                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
16069
16070                 Each bit applies to a single IO. Bit 0 for MIO[26].
16071                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
16072
16073                 Each bit applies to a single IO. Bit 0 for MIO[26].
16074                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
16075
16076                 Each bit applies to a single IO. Bit 0 for MIO[26].
16077                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
16078
16079                 Each bit applies to a single IO. Bit 0 for MIO[26].
16080                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
16081
16082                 Each bit applies to a single IO. Bit 0 for MIO[26].
16083                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
16084
16085                 Each bit applies to a single IO. Bit 0 for MIO[26].
16086                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
16087
16088                 Slew rate control to MIO Bank 1 - control MIO[51:26]
16089                 (OFFSET, MASK, VALUE)      (0XFF180168, 0x03FFFFFFU ,0x00000000U)
16090                 RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
16091
16092                 RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
16093                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
16094                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
16095                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
16096                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
16097                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
16098                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
16099                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
16100                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
16101                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
16102                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
16103                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
16104                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
16105                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
16106                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
16107                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
16108                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
16109                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
16110                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
16111                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
16112                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
16113                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
16114                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
16115                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
16116                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
16117                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
16118                         |  0 ) & RegMask); */
16119                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
16120         /*############################################################################################################################ */
16121
16122                 /*Register : bank2_ctrl0 @ 0XFF180170</p>
16123
16124                 Each bit applies to a single IO. Bit 0 for MIO[52].
16125                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0                                           1
16126
16127                 Each bit applies to a single IO. Bit 0 for MIO[52].
16128                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1                                           1
16129
16130                 Each bit applies to a single IO. Bit 0 for MIO[52].
16131                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2                                           1
16132
16133                 Each bit applies to a single IO. Bit 0 for MIO[52].
16134                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3                                           1
16135
16136                 Each bit applies to a single IO. Bit 0 for MIO[52].
16137                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4                                           1
16138
16139                 Each bit applies to a single IO. Bit 0 for MIO[52].
16140                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5                                           1
16141
16142                 Each bit applies to a single IO. Bit 0 for MIO[52].
16143                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6                                           1
16144
16145                 Each bit applies to a single IO. Bit 0 for MIO[52].
16146                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7                                           1
16147
16148                 Each bit applies to a single IO. Bit 0 for MIO[52].
16149                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8                                           1
16150
16151                 Each bit applies to a single IO. Bit 0 for MIO[52].
16152                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9                                           1
16153
16154                 Each bit applies to a single IO. Bit 0 for MIO[52].
16155                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10                                          1
16156
16157                 Each bit applies to a single IO. Bit 0 for MIO[52].
16158                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11                                          1
16159
16160                 Each bit applies to a single IO. Bit 0 for MIO[52].
16161                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12                                          1
16162
16163                 Each bit applies to a single IO. Bit 0 for MIO[52].
16164                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13                                          1
16165
16166                 Each bit applies to a single IO. Bit 0 for MIO[52].
16167                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14                                          1
16168
16169                 Each bit applies to a single IO. Bit 0 for MIO[52].
16170                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15                                          1
16171
16172                 Each bit applies to a single IO. Bit 0 for MIO[52].
16173                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16                                          1
16174
16175                 Each bit applies to a single IO. Bit 0 for MIO[52].
16176                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17                                          1
16177
16178                 Each bit applies to a single IO. Bit 0 for MIO[52].
16179                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18                                          1
16180
16181                 Each bit applies to a single IO. Bit 0 for MIO[52].
16182                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19                                          1
16183
16184                 Each bit applies to a single IO. Bit 0 for MIO[52].
16185                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20                                          1
16186
16187                 Each bit applies to a single IO. Bit 0 for MIO[52].
16188                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21                                          1
16189
16190                 Each bit applies to a single IO. Bit 0 for MIO[52].
16191                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22                                          1
16192
16193                 Each bit applies to a single IO. Bit 0 for MIO[52].
16194                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23                                          1
16195
16196                 Each bit applies to a single IO. Bit 0 for MIO[52].
16197                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24                                          1
16198
16199                 Each bit applies to a single IO. Bit 0 for MIO[52].
16200                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25                                          1
16201
16202                 Drive0 control to MIO Bank 2 - control MIO[77:52]
16203                 (OFFSET, MASK, VALUE)      (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU)
16204                 RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK |  0 );
16205
16206                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
16207                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
16208                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
16209                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
16210                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
16211                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
16212                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
16213                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
16214                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
16215                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
16216                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
16217                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
16218                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
16219                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
16220                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
16221                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
16222                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
16223                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
16224                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
16225                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
16226                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
16227                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
16228                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
16229                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
16230                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
16231                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
16232                         |  0 ) & RegMask); */
16233                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16234         /*############################################################################################################################ */
16235
16236                 /*Register : bank2_ctrl1 @ 0XFF180174</p>
16237
16238                 Each bit applies to a single IO. Bit 0 for MIO[52].
16239                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0                                           1
16240
16241                 Each bit applies to a single IO. Bit 0 for MIO[52].
16242                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1                                           1
16243
16244                 Each bit applies to a single IO. Bit 0 for MIO[52].
16245                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2                                           1
16246
16247                 Each bit applies to a single IO. Bit 0 for MIO[52].
16248                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3                                           1
16249
16250                 Each bit applies to a single IO. Bit 0 for MIO[52].
16251                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4                                           1
16252
16253                 Each bit applies to a single IO. Bit 0 for MIO[52].
16254                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5                                           1
16255
16256                 Each bit applies to a single IO. Bit 0 for MIO[52].
16257                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6                                           1
16258
16259                 Each bit applies to a single IO. Bit 0 for MIO[52].
16260                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7                                           1
16261
16262                 Each bit applies to a single IO. Bit 0 for MIO[52].
16263                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8                                           1
16264
16265                 Each bit applies to a single IO. Bit 0 for MIO[52].
16266                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9                                           1
16267
16268                 Each bit applies to a single IO. Bit 0 for MIO[52].
16269                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10                                          1
16270
16271                 Each bit applies to a single IO. Bit 0 for MIO[52].
16272                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11                                          1
16273
16274                 Each bit applies to a single IO. Bit 0 for MIO[52].
16275                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12                                          1
16276
16277                 Each bit applies to a single IO. Bit 0 for MIO[52].
16278                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13                                          1
16279
16280                 Each bit applies to a single IO. Bit 0 for MIO[52].
16281                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14                                          1
16282
16283                 Each bit applies to a single IO. Bit 0 for MIO[52].
16284                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15                                          1
16285
16286                 Each bit applies to a single IO. Bit 0 for MIO[52].
16287                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16                                          1
16288
16289                 Each bit applies to a single IO. Bit 0 for MIO[52].
16290                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17                                          1
16291
16292                 Each bit applies to a single IO. Bit 0 for MIO[52].
16293                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18                                          1
16294
16295                 Each bit applies to a single IO. Bit 0 for MIO[52].
16296                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19                                          1
16297
16298                 Each bit applies to a single IO. Bit 0 for MIO[52].
16299                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20                                          1
16300
16301                 Each bit applies to a single IO. Bit 0 for MIO[52].
16302                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21                                          1
16303
16304                 Each bit applies to a single IO. Bit 0 for MIO[52].
16305                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22                                          1
16306
16307                 Each bit applies to a single IO. Bit 0 for MIO[52].
16308                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23                                          1
16309
16310                 Each bit applies to a single IO. Bit 0 for MIO[52].
16311                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24                                          1
16312
16313                 Each bit applies to a single IO. Bit 0 for MIO[52].
16314                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25                                          1
16315
16316                 Drive1 control to MIO Bank 2 - control MIO[77:52]
16317                 (OFFSET, MASK, VALUE)      (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU)
16318                 RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK |  0 );
16319
16320                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
16321                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
16322                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
16323                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
16324                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
16325                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
16326                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
16327                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
16328                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
16329                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
16330                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
16331                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
16332                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
16333                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
16334                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
16335                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
16336                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
16337                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
16338                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
16339                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
16340                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
16341                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
16342                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
16343                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
16344                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
16345                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
16346                         |  0 ) & RegMask); */
16347                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16348         /*############################################################################################################################ */
16349
16350                 /*Register : bank2_ctrl3 @ 0XFF180178</p>
16351
16352                 Each bit applies to a single IO. Bit 0 for MIO[52].
16353                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
16354
16355                 Each bit applies to a single IO. Bit 0 for MIO[52].
16356                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
16357
16358                 Each bit applies to a single IO. Bit 0 for MIO[52].
16359                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
16360
16361                 Each bit applies to a single IO. Bit 0 for MIO[52].
16362                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
16363
16364                 Each bit applies to a single IO. Bit 0 for MIO[52].
16365                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
16366
16367                 Each bit applies to a single IO. Bit 0 for MIO[52].
16368                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
16369
16370                 Each bit applies to a single IO. Bit 0 for MIO[52].
16371                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
16372
16373                 Each bit applies to a single IO. Bit 0 for MIO[52].
16374                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
16375
16376                 Each bit applies to a single IO. Bit 0 for MIO[52].
16377                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
16378
16379                 Each bit applies to a single IO. Bit 0 for MIO[52].
16380                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
16381
16382                 Each bit applies to a single IO. Bit 0 for MIO[52].
16383                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
16384
16385                 Each bit applies to a single IO. Bit 0 for MIO[52].
16386                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
16387
16388                 Each bit applies to a single IO. Bit 0 for MIO[52].
16389                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
16390
16391                 Each bit applies to a single IO. Bit 0 for MIO[52].
16392                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
16393
16394                 Each bit applies to a single IO. Bit 0 for MIO[52].
16395                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
16396
16397                 Each bit applies to a single IO. Bit 0 for MIO[52].
16398                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
16399
16400                 Each bit applies to a single IO. Bit 0 for MIO[52].
16401                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
16402
16403                 Each bit applies to a single IO. Bit 0 for MIO[52].
16404                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
16405
16406                 Each bit applies to a single IO. Bit 0 for MIO[52].
16407                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
16408
16409                 Each bit applies to a single IO. Bit 0 for MIO[52].
16410                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
16411
16412                 Each bit applies to a single IO. Bit 0 for MIO[52].
16413                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
16414
16415                 Each bit applies to a single IO. Bit 0 for MIO[52].
16416                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
16417
16418                 Each bit applies to a single IO. Bit 0 for MIO[52].
16419                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
16420
16421                 Each bit applies to a single IO. Bit 0 for MIO[52].
16422                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
16423
16424                 Each bit applies to a single IO. Bit 0 for MIO[52].
16425                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
16426
16427                 Each bit applies to a single IO. Bit 0 for MIO[52].
16428                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
16429
16430                 Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
16431                 (OFFSET, MASK, VALUE)      (0XFF180178, 0x03FFFFFFU ,0x00000000U)
16432                 RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
16433
16434                 RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
16435                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
16436                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
16437                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
16438                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
16439                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
16440                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
16441                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
16442                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
16443                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
16444                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
16445                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
16446                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
16447                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
16448                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
16449                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
16450                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
16451                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
16452                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
16453                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
16454                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
16455                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
16456                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
16457                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
16458                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
16459                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
16460                         |  0 ) & RegMask); */
16461                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
16462         /*############################################################################################################################ */
16463
16464                 /*Register : bank2_ctrl4 @ 0XFF18017C</p>
16465
16466                 Each bit applies to a single IO. Bit 0 for MIO[52].
16467                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
16468
16469                 Each bit applies to a single IO. Bit 0 for MIO[52].
16470                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
16471
16472                 Each bit applies to a single IO. Bit 0 for MIO[52].
16473                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
16474
16475                 Each bit applies to a single IO. Bit 0 for MIO[52].
16476                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
16477
16478                 Each bit applies to a single IO. Bit 0 for MIO[52].
16479                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
16480
16481                 Each bit applies to a single IO. Bit 0 for MIO[52].
16482                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
16483
16484                 Each bit applies to a single IO. Bit 0 for MIO[52].
16485                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
16486
16487                 Each bit applies to a single IO. Bit 0 for MIO[52].
16488                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
16489
16490                 Each bit applies to a single IO. Bit 0 for MIO[52].
16491                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
16492
16493                 Each bit applies to a single IO. Bit 0 for MIO[52].
16494                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
16495
16496                 Each bit applies to a single IO. Bit 0 for MIO[52].
16497                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
16498
16499                 Each bit applies to a single IO. Bit 0 for MIO[52].
16500                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
16501
16502                 Each bit applies to a single IO. Bit 0 for MIO[52].
16503                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
16504
16505                 Each bit applies to a single IO. Bit 0 for MIO[52].
16506                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
16507
16508                 Each bit applies to a single IO. Bit 0 for MIO[52].
16509                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
16510
16511                 Each bit applies to a single IO. Bit 0 for MIO[52].
16512                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
16513
16514                 Each bit applies to a single IO. Bit 0 for MIO[52].
16515                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
16516
16517                 Each bit applies to a single IO. Bit 0 for MIO[52].
16518                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
16519
16520                 Each bit applies to a single IO. Bit 0 for MIO[52].
16521                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
16522
16523                 Each bit applies to a single IO. Bit 0 for MIO[52].
16524                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
16525
16526                 Each bit applies to a single IO. Bit 0 for MIO[52].
16527                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
16528
16529                 Each bit applies to a single IO. Bit 0 for MIO[52].
16530                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
16531
16532                 Each bit applies to a single IO. Bit 0 for MIO[52].
16533                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
16534
16535                 Each bit applies to a single IO. Bit 0 for MIO[52].
16536                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
16537
16538                 Each bit applies to a single IO. Bit 0 for MIO[52].
16539                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
16540
16541                 Each bit applies to a single IO. Bit 0 for MIO[52].
16542                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
16543
16544                 When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
16545                 (OFFSET, MASK, VALUE)      (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU)
16546                 RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
16547
16548                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
16549                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
16550                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
16551                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
16552                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
16553                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
16554                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
16555                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
16556                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
16557                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
16558                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
16559                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
16560                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
16561                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
16562                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
16563                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
16564                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
16565                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
16566                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
16567                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
16568                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
16569                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
16570                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
16571                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
16572                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
16573                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
16574                         |  0 ) & RegMask); */
16575                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16576         /*############################################################################################################################ */
16577
16578                 /*Register : bank2_ctrl5 @ 0XFF180180</p>
16579
16580                 Each bit applies to a single IO. Bit 0 for MIO[52].
16581                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0                                      1
16582
16583                 Each bit applies to a single IO. Bit 0 for MIO[52].
16584                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1                                      1
16585
16586                 Each bit applies to a single IO. Bit 0 for MIO[52].
16587                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2                                      1
16588
16589                 Each bit applies to a single IO. Bit 0 for MIO[52].
16590                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3                                      1
16591
16592                 Each bit applies to a single IO. Bit 0 for MIO[52].
16593                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4                                      1
16594
16595                 Each bit applies to a single IO. Bit 0 for MIO[52].
16596                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5                                      1
16597
16598                 Each bit applies to a single IO. Bit 0 for MIO[52].
16599                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6                                      1
16600
16601                 Each bit applies to a single IO. Bit 0 for MIO[52].
16602                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7                                      1
16603
16604                 Each bit applies to a single IO. Bit 0 for MIO[52].
16605                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8                                      1
16606
16607                 Each bit applies to a single IO. Bit 0 for MIO[52].
16608                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9                                      1
16609
16610                 Each bit applies to a single IO. Bit 0 for MIO[52].
16611                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10                                     1
16612
16613                 Each bit applies to a single IO. Bit 0 for MIO[52].
16614                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11                                     1
16615
16616                 Each bit applies to a single IO. Bit 0 for MIO[52].
16617                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12                                     1
16618
16619                 Each bit applies to a single IO. Bit 0 for MIO[52].
16620                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13                                     1
16621
16622                 Each bit applies to a single IO. Bit 0 for MIO[52].
16623                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14                                     1
16624
16625                 Each bit applies to a single IO. Bit 0 for MIO[52].
16626                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15                                     1
16627
16628                 Each bit applies to a single IO. Bit 0 for MIO[52].
16629                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16                                     1
16630
16631                 Each bit applies to a single IO. Bit 0 for MIO[52].
16632                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17                                     1
16633
16634                 Each bit applies to a single IO. Bit 0 for MIO[52].
16635                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18                                     1
16636
16637                 Each bit applies to a single IO. Bit 0 for MIO[52].
16638                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19                                     1
16639
16640                 Each bit applies to a single IO. Bit 0 for MIO[52].
16641                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20                                     1
16642
16643                 Each bit applies to a single IO. Bit 0 for MIO[52].
16644                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21                                     1
16645
16646                 Each bit applies to a single IO. Bit 0 for MIO[52].
16647                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22                                     1
16648
16649                 Each bit applies to a single IO. Bit 0 for MIO[52].
16650                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23                                     1
16651
16652                 Each bit applies to a single IO. Bit 0 for MIO[52].
16653                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24                                     1
16654
16655                 Each bit applies to a single IO. Bit 0 for MIO[52].
16656                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25                                     1
16657
16658                 When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
16659                 (OFFSET, MASK, VALUE)      (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU)
16660                 RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
16661
16662                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
16663                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
16664                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
16665                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
16666                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
16667                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
16668                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
16669                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
16670                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
16671                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
16672                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
16673                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
16674                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
16675                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
16676                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
16677                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
16678                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
16679                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
16680                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
16681                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
16682                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
16683                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
16684                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
16685                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
16686                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
16687                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
16688                         |  0 ) & RegMask); */
16689                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16690         /*############################################################################################################################ */
16691
16692                 /*Register : bank2_ctrl6 @ 0XFF180184</p>
16693
16694                 Each bit applies to a single IO. Bit 0 for MIO[52].
16695                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
16696
16697                 Each bit applies to a single IO. Bit 0 for MIO[52].
16698                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
16699
16700                 Each bit applies to a single IO. Bit 0 for MIO[52].
16701                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
16702
16703                 Each bit applies to a single IO. Bit 0 for MIO[52].
16704                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
16705
16706                 Each bit applies to a single IO. Bit 0 for MIO[52].
16707                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
16708
16709                 Each bit applies to a single IO. Bit 0 for MIO[52].
16710                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
16711
16712                 Each bit applies to a single IO. Bit 0 for MIO[52].
16713                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
16714
16715                 Each bit applies to a single IO. Bit 0 for MIO[52].
16716                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
16717
16718                 Each bit applies to a single IO. Bit 0 for MIO[52].
16719                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
16720
16721                 Each bit applies to a single IO. Bit 0 for MIO[52].
16722                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
16723
16724                 Each bit applies to a single IO. Bit 0 for MIO[52].
16725                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
16726
16727                 Each bit applies to a single IO. Bit 0 for MIO[52].
16728                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
16729
16730                 Each bit applies to a single IO. Bit 0 for MIO[52].
16731                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
16732
16733                 Each bit applies to a single IO. Bit 0 for MIO[52].
16734                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
16735
16736                 Each bit applies to a single IO. Bit 0 for MIO[52].
16737                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
16738
16739                 Each bit applies to a single IO. Bit 0 for MIO[52].
16740                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
16741
16742                 Each bit applies to a single IO. Bit 0 for MIO[52].
16743                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
16744
16745                 Each bit applies to a single IO. Bit 0 for MIO[52].
16746                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
16747
16748                 Each bit applies to a single IO. Bit 0 for MIO[52].
16749                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
16750
16751                 Each bit applies to a single IO. Bit 0 for MIO[52].
16752                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
16753
16754                 Each bit applies to a single IO. Bit 0 for MIO[52].
16755                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
16756
16757                 Each bit applies to a single IO. Bit 0 for MIO[52].
16758                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
16759
16760                 Each bit applies to a single IO. Bit 0 for MIO[52].
16761                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
16762
16763                 Each bit applies to a single IO. Bit 0 for MIO[52].
16764                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
16765
16766                 Each bit applies to a single IO. Bit 0 for MIO[52].
16767                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
16768
16769                 Each bit applies to a single IO. Bit 0 for MIO[52].
16770                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
16771
16772                 Slew rate control to MIO Bank 2 - control MIO[77:52]
16773                 (OFFSET, MASK, VALUE)      (0XFF180184, 0x03FFFFFFU ,0x00000000U)
16774                 RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
16775
16776                 RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
16777                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
16778                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
16779                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
16780                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
16781                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
16782                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
16783                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
16784                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
16785                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
16786                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
16787                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
16788                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
16789                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
16790                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
16791                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
16792                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
16793                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
16794                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
16795                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
16796                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
16797                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
16798                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
16799                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
16800                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
16801                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
16802                         |  0 ) & RegMask); */
16803                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
16804         /*############################################################################################################################ */
16805
16806                 // : LOOPBACK
16807                 /*Register : MIO_LOOPBACK @ 0XFF180200</p>
16808
16809                 I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
16810                 ts to I2C 0 inputs.
16811                 PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0
16812
16813                 CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
16814                 .
16815                 PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0
16816
16817                 UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
16818                 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
16819                 PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0
16820
16821                 SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
16822                 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
16823                 PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0
16824
16825                 Loopback function within MIO
16826                 (OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)
16827                 RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK |  0 );
16828
16829                 RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
16830                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
16831                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
16832                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
16833                         |  0 ) & RegMask); */
16834                 PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U);
16835         /*############################################################################################################################ */
16836
16837
16838   return 1;
16839 }
16840 unsigned long psu_peripherals_init_data() {
16841                 // : RESET BLOCKS
16842                 // : TIMESTAMP
16843                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16844
16845                 Block level reset
16846                 PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET                                        0
16847
16848                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16849                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00100000U ,0x00000000U)
16850                 RegMask = (CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK |  0 );
16851
16852                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
16853                         |  0 ) & RegMask); */
16854                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00100000U ,0x00000000U);
16855         /*############################################################################################################################ */
16856
16857                 // : ENET
16858                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
16859
16860                 GEM 3 reset
16861                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0
16862
16863                 Software controlled reset for the GEMs
16864                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)
16865                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
16866
16867                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
16868                         |  0 ) & RegMask); */
16869                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
16870         /*############################################################################################################################ */
16871
16872                 // : QSPI
16873                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16874
16875                 Block level reset
16876                 PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0
16877
16878                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16879                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)
16880                 RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK |  0 );
16881
16882                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
16883                         |  0 ) & RegMask); */
16884                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U);
16885         /*############################################################################################################################ */
16886
16887                 // : QSPI TAP DELAY
16888                 /*Register : IOU_TAPDLY_BYPASS @ 0XFF180390</p>
16889
16890                 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI
16891                 PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX                                         1
16892
16893                 IOU tap delay bypass for the LQSPI and NAND controllers
16894                 (OFFSET, MASK, VALUE)      (0XFF180390, 0x00000004U ,0x00000004U)
16895                 RegMask = (IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK |  0 );
16896
16897                 RegVal = ((0x00000001U << IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
16898                         |  0 ) & RegMask); */
16899                 PSU_Mask_Write (IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET ,0x00000004U ,0x00000004U);
16900         /*############################################################################################################################ */
16901
16902                 // : NAND
16903                 // : USB
16904                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
16905
16906                 USB 0 reset for control registers
16907                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0
16908
16909                 USB 0 sleep circuit reset
16910                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0
16911
16912                 USB 0 reset
16913                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0
16914
16915                 Software control register for the LPD block.
16916                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)
16917                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
16918
16919                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
16920                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
16921                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
16922                         |  0 ) & RegMask); */
16923                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U);
16924         /*############################################################################################################################ */
16925
16926                 // : FPD RESET
16927                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
16928
16929                 Display Port block level reset (includes DPDMA)
16930                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0
16931
16932                 FPD WDT reset
16933                 PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET                                              0
16934
16935                 GDMA block level reset
16936                 PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET                                              0
16937
16938                 Pixel Processor (submodule of GPU) block level reset
16939                 PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET                                           0
16940
16941                 Pixel Processor (submodule of GPU) block level reset
16942                 PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET                                           0
16943
16944                 GPU block level reset
16945                 PSU_CRF_APB_RST_FPD_TOP_GPU_RESET                                               0
16946
16947                 GT block level reset
16948                 PSU_CRF_APB_RST_FPD_TOP_GT_RESET                                                0
16949
16950                 Sata block level reset
16951                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0
16952
16953                 FPD Block level software controlled reset
16954                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x0001807EU ,0x00000000U)
16955                 RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
16956
16957                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
16958                         | 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
16959                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
16960                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
16961                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
16962                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
16963                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
16964                         | 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
16965                         |  0 ) & RegMask); */
16966                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x0001807EU ,0x00000000U);
16967         /*############################################################################################################################ */
16968
16969                 // : SD
16970                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16971
16972                 Block level reset
16973                 PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0
16974
16975                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16976                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000040U ,0x00000000U)
16977                 RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK |  0 );
16978
16979                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
16980                         |  0 ) & RegMask); */
16981                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U);
16982         /*############################################################################################################################ */
16983
16984                 /*Register : CTRL_REG_SD @ 0XFF180310</p>
16985
16986                 SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
16987                 PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0
16988
16989                 SD eMMC selection
16990                 (OFFSET, MASK, VALUE)      (0XFF180310, 0x00008000U ,0x00000000U)
16991                 RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK |  0 );
16992
16993                 RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
16994                         |  0 ) & RegMask); */
16995                 PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U);
16996         /*############################################################################################################################ */
16997
16998                 /*Register : SD_CONFIG_REG2 @ 0XFF180320</p>
16999
17000                 Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
17001                 t 11 - Reserved
17002                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0
17003
17004                 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
17005                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            0
17006
17007                 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
17008                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0
17009
17010                 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
17011                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1
17012
17013                 SD Config Register 2
17014                 (OFFSET, MASK, VALUE)      (0XFF180320, 0x33800000U ,0x00800000U)
17015                 RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK |  0 );
17016
17017                 RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
17018                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
17019                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
17020                         | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
17021                         |  0 ) & RegMask); */
17022                 PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U);
17023         /*############################################################################################################################ */
17024
17025                 // : SD1 BASE CLOCK
17026                 /*Register : SD_CONFIG_REG1 @ 0XFF18031C</p>
17027
17028                 Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
17029                 PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK                                         0xc7
17030
17031                 SD Config Register 1
17032                 (OFFSET, MASK, VALUE)      (0XFF18031C, 0x7F800000U ,0x63800000U)
17033                 RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK |  0 );
17034
17035                 RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
17036                         |  0 ) & RegMask); */
17037                 PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U);
17038         /*############################################################################################################################ */
17039
17040                 // : SD1 RETUNER
17041                 /*Register : SD_CONFIG_REG3 @ 0XFF180324</p>
17042
17043                 This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
17044                 rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
17045                 s Fh - Ch = Reserved
17046                 PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR                                       0X0
17047
17048                 SD Config Register 3
17049                 (OFFSET, MASK, VALUE)      (0XFF180324, 0x03C00000U ,0x00000000U)
17050                 RegMask = (IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK |  0 );
17051
17052                 RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
17053                         |  0 ) & RegMask); */
17054                 PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG3_OFFSET ,0x03C00000U ,0x00000000U);
17055         /*############################################################################################################################ */
17056
17057                 // : CAN
17058                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17059
17060                 Block level reset
17061                 PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0
17062
17063                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17064                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000100U ,0x00000000U)
17065                 RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK |  0 );
17066
17067                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
17068                         |  0 ) & RegMask); */
17069                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U);
17070         /*############################################################################################################################ */
17071
17072                 // : I2C
17073                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17074
17075                 Block level reset
17076                 PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0
17077
17078                 Block level reset
17079                 PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0
17080
17081                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17082                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)
17083                 RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK |  0 );
17084
17085                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
17086                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
17087                         |  0 ) & RegMask); */
17088                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U);
17089         /*############################################################################################################################ */
17090
17091                 // : SWDT
17092                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17093
17094                 Block level reset
17095                 PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET                                             0
17096
17097                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17098                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00008000U ,0x00000000U)
17099                 RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK |  0 );
17100
17101                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
17102                         |  0 ) & RegMask); */
17103                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U);
17104         /*############################################################################################################################ */
17105
17106                 // : SPI
17107                 // : TTC
17108                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17109
17110                 Block level reset
17111                 PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0
17112
17113                 Block level reset
17114                 PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0
17115
17116                 Block level reset
17117                 PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0
17118
17119                 Block level reset
17120                 PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0
17121
17122                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17123                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)
17124                 RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK |  0 );
17125
17126                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
17127                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
17128                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
17129                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
17130                         |  0 ) & RegMask); */
17131                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U);
17132         /*############################################################################################################################ */
17133
17134                 // : UART
17135                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17136
17137                 Block level reset
17138                 PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0
17139
17140                 Block level reset
17141                 PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0
17142
17143                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17144                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)
17145                 RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK |  0 );
17146
17147                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
17148                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
17149                         |  0 ) & RegMask); */
17150                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U);
17151         /*############################################################################################################################ */
17152
17153                 // : TPIU WIDTH
17154                 // : TRACE LOCK ACCESS REGISTER
17155                 /*Register : LAR @ 0XFE980FB0</p>
17156
17157                 A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the a
17158                 fect of removing write access.
17159                 PSU_TPIU_LAR_ACCESS_W                                                           0XC5ACCE55
17160
17161                 This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject t
17162                  the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the compo
17163                 ent.
17164                 (OFFSET, MASK, VALUE)      (0XFE980FB0, 0xFFFFFFFFU ,0xC5ACCE55U)
17165                 RegMask = (TPIU_LAR_ACCESS_W_MASK |  0 );
17166
17167                 RegVal = ((0xC5ACCE55U << TPIU_LAR_ACCESS_W_SHIFT
17168                         |  0 ) & RegMask); */
17169                 PSU_Mask_Write (TPIU_LAR_OFFSET ,0xFFFFFFFFU ,0xC5ACCE55U);
17170         /*############################################################################################################################ */
17171
17172                 // : TRACE CURRENT PORT SIZE
17173                 /*Register : Current_port_size @ 0XFE980004</p>
17174
17175                 Indicates whether the current port size of the TPIU is 32 bits.
17176                 PSU_TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32                                         1
17177
17178                 The Current Port Size Register has the same format as the Supported Port Sizes register but only one bit is set, and all othe
17179                 s must be zero. Writing values with more than one bit set or setting a bit that is not indicated as supported is not supporte
17180                  and causes unpredictable behavior.On reset this defaults to the smallest possible port size, 1 bit, and so reads as 0x000000
17181                 1.Note : Do not modify the value while the Trace Port is still active, or without correctly stopping the formatter (see Forma
17182                 ter and Flush Control Register, 0x304). This can result in data not being aligned to the port width. For example, data on an
17183                 -bit Trace Port might not be byte aligned.
17184                 (OFFSET, MASK, VALUE)      (0XFE980004, 0x80000000U ,0x80000000U)
17185                 RegMask = (TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_MASK |  0 );
17186
17187                 RegVal = ((0x00000001U << TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_SHIFT
17188                         |  0 ) & RegMask); */
17189                 PSU_Mask_Write (TPIU_CURRENT_PORT_SIZE_OFFSET ,0x80000000U ,0x80000000U);
17190         /*############################################################################################################################ */
17191
17192                 // : TRACE LOCK ACCESS REGISTER
17193                 /*Register : LAR @ 0XFE980FB0</p>
17194
17195                 A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the a
17196                 fect of removing write access.
17197                 PSU_TPIU_LAR_ACCESS_W                                                           0X0
17198
17199                 This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject t
17200                  the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the compo
17201                 ent.
17202                 (OFFSET, MASK, VALUE)      (0XFE980FB0, 0xFFFFFFFFU ,0x00000000U)
17203                 RegMask = (TPIU_LAR_ACCESS_W_MASK |  0 );
17204
17205                 RegVal = ((0x00000000U << TPIU_LAR_ACCESS_W_SHIFT
17206                         |  0 ) & RegMask); */
17207                 PSU_Mask_Write (TPIU_LAR_OFFSET ,0xFFFFFFFFU ,0x00000000U);
17208         /*############################################################################################################################ */
17209
17210                 // : UART BAUD RATE
17211                 /*Register : Baud_rate_divider_reg0 @ 0XFF000034</p>
17212
17213                 Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
17214                 PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
17215
17216                 Baud Rate Divider Register
17217                 (OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000005U)
17218                 RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
17219
17220                 RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
17221                         |  0 ) & RegMask); */
17222                 PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
17223         /*############################################################################################################################ */
17224
17225                 /*Register : Baud_rate_gen_reg0 @ 0XFF000018</p>
17226
17227                 Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
17228                 PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x8f
17229
17230                 Baud Rate Generator Register.
17231                 (OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x0000008FU)
17232                 RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
17233
17234                 RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
17235                         |  0 ) & RegMask); */
17236                 PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
17237         /*############################################################################################################################ */
17238
17239                 /*Register : Control_reg0 @ 0XFF000000</p>
17240
17241                 Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
17242                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.
17243                 PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0
17244
17245                 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
17246                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
17247                 PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0
17248
17249                 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
17250                 pleted.
17251                 PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0
17252
17253                 Transmit disable: 0: enable transmitter 1: disable transmitter
17254                 PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0
17255
17256                 Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
17257                 PSU_UART0_CONTROL_REG0_TXEN                                                     0x1
17258
17259                 Receive disable: 0: enable 1: disable, regardless of the value of RXEN
17260                 PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0
17261
17262                 Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
17263                 PSU_UART0_CONTROL_REG0_RXEN                                                     0x1
17264
17265                 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
17266                  bit is self clearing once the reset has completed.
17267                 PSU_UART0_CONTROL_REG0_TXRES                                                    0x1
17268
17269                 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
17270                 is self clearing once the reset has completed.
17271                 PSU_UART0_CONTROL_REG0_RXRES                                                    0x1
17272
17273                 UART Control Register
17274                 (OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)
17275                 RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK |  0 );
17276
17277                 RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT
17278                         | 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT
17279                         | 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT
17280                         | 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT
17281                         | 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT
17282                         | 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT
17283                         | 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT
17284                         | 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT
17285                         | 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT
17286                         |  0 ) & RegMask); */
17287                 PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
17288         /*############################################################################################################################ */
17289
17290                 /*Register : mode_reg0 @ 0XFF000004</p>
17291
17292                 Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
17293                 PSU_UART0_MODE_REG0_CHMODE                                                      0x0
17294
17295                 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
17296                 stop bits 10: 2 stop bits 11: reserved
17297                 PSU_UART0_MODE_REG0_NBSTOP                                                      0x0
17298
17299                 Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
17300                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
17301                 PSU_UART0_MODE_REG0_PAR                                                         0x4
17302
17303                 Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
17304                 PSU_UART0_MODE_REG0_CHRL                                                        0x0
17305
17306                 Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
17307                 source is uart_ref_clk 1: clock source is uart_ref_clk/8
17308                 PSU_UART0_MODE_REG0_CLKS                                                        0x0
17309
17310                 UART Mode Register
17311                 (OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)
17312                 RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK |  0 );
17313
17314                 RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT
17315                         | 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT
17316                         | 0x00000004U << UART0_MODE_REG0_PAR_SHIFT
17317                         | 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT
17318                         | 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT
17319                         |  0 ) & RegMask); */
17320                 PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
17321         /*############################################################################################################################ */
17322
17323                 /*Register : Baud_rate_divider_reg0 @ 0XFF010034</p>
17324
17325                 Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
17326                 PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
17327
17328                 Baud Rate Divider Register
17329                 (OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000005U)
17330                 RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
17331
17332                 RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
17333                         |  0 ) & RegMask); */
17334                 PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
17335         /*############################################################################################################################ */
17336
17337                 /*Register : Baud_rate_gen_reg0 @ 0XFF010018</p>
17338
17339                 Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
17340                 PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x8f
17341
17342                 Baud Rate Generator Register.
17343                 (OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x0000008FU)
17344                 RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
17345
17346                 RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
17347                         |  0 ) & RegMask); */
17348                 PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
17349         /*############################################################################################################################ */
17350
17351                 /*Register : Control_reg0 @ 0XFF010000</p>
17352
17353                 Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
17354                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.
17355                 PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0
17356
17357                 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
17358                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
17359                 PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0
17360
17361                 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
17362                 pleted.
17363                 PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0
17364
17365                 Transmit disable: 0: enable transmitter 1: disable transmitter
17366                 PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0
17367
17368                 Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
17369                 PSU_UART1_CONTROL_REG0_TXEN                                                     0x1
17370
17371                 Receive disable: 0: enable 1: disable, regardless of the value of RXEN
17372                 PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0
17373
17374                 Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
17375                 PSU_UART1_CONTROL_REG0_RXEN                                                     0x1
17376
17377                 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
17378                  bit is self clearing once the reset has completed.
17379                 PSU_UART1_CONTROL_REG0_TXRES                                                    0x1
17380
17381                 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
17382                 is self clearing once the reset has completed.
17383                 PSU_UART1_CONTROL_REG0_RXRES                                                    0x1
17384
17385                 UART Control Register
17386                 (OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)
17387                 RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK |  0 );
17388
17389                 RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT
17390                         | 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT
17391                         | 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT
17392                         | 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT
17393                         | 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT
17394                         | 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT
17395                         | 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT
17396                         | 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT
17397                         | 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT
17398                         |  0 ) & RegMask); */
17399                 PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
17400         /*############################################################################################################################ */
17401
17402                 /*Register : mode_reg0 @ 0XFF010004</p>
17403
17404                 Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
17405                 PSU_UART1_MODE_REG0_CHMODE                                                      0x0
17406
17407                 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
17408                 stop bits 10: 2 stop bits 11: reserved
17409                 PSU_UART1_MODE_REG0_NBSTOP                                                      0x0
17410
17411                 Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
17412                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
17413                 PSU_UART1_MODE_REG0_PAR                                                         0x4
17414
17415                 Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
17416                 PSU_UART1_MODE_REG0_CHRL                                                        0x0
17417
17418                 Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
17419                 source is uart_ref_clk 1: clock source is uart_ref_clk/8
17420                 PSU_UART1_MODE_REG0_CLKS                                                        0x0
17421
17422                 UART Mode Register
17423                 (OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)
17424                 RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK |  0 );
17425
17426                 RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT
17427                         | 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT
17428                         | 0x00000004U << UART1_MODE_REG0_PAR_SHIFT
17429                         | 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT
17430                         | 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT
17431                         |  0 ) & RegMask); */
17432                 PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
17433         /*############################################################################################################################ */
17434
17435                 // : GPIO
17436                 // : ADMA TZ
17437                 /*Register : slcr_adma @ 0XFF4B0024</p>
17438
17439                 TrustZone Classification for ADMA
17440                 PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF
17441
17442                 RPU TrustZone settings
17443                 (OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)
17444                 RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK |  0 );
17445
17446                 RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
17447                         |  0 ) & RegMask); */
17448                 PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU);
17449         /*############################################################################################################################ */
17450
17451                 // : CSU TAMPERING
17452                 // : CSU TAMPER STATUS
17453                 /*Register : tamper_status @ 0XFFCA5000</p>
17454
17455                 CSU regsiter
17456                 PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0
17457
17458                 External MIO
17459                 PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0
17460
17461                 JTAG toggle detect
17462                 PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0
17463
17464                 PL SEU error
17465                 PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0
17466
17467                 AMS over temperature alarm for LPD
17468                 PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0
17469
17470                 AMS over temperature alarm for APU
17471                 PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0
17472
17473                 AMS voltage alarm for VCCPINT_FPD
17474                 PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0
17475
17476                 AMS voltage alarm for VCCPINT_LPD
17477                 PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0
17478
17479                 AMS voltage alarm for VCCPAUX
17480                 PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0
17481
17482                 AMS voltage alarm for DDRPHY
17483                 PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0
17484
17485                 AMS voltage alarm for PSIO bank 0/1/2
17486                 PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0
17487
17488                 AMS voltage alarm for PSIO bank 3 (dedicated pins)
17489                 PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0
17490
17491                 AMS voltaage alarm for GT
17492                 PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0
17493
17494                 Tamper Response Status
17495                 (OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)
17496                 RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK |  0 );
17497
17498                 RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT
17499                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT
17500                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT
17501                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT
17502                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT
17503                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT
17504                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT
17505                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT
17506                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT
17507                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT
17508                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT
17509                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT
17510                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT
17511                         |  0 ) & RegMask); */
17512                 PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U);
17513         /*############################################################################################################################ */
17514
17515                 // : CSU TAMPER RESPONSE
17516                 // : CPU QOS DEFAULT
17517                 /*Register : ACE_CTRL @ 0XFD5C0060</p>
17518
17519                 Set ACE outgoing AWQOS value
17520                 PSU_APU_ACE_CTRL_AWQOS                                                          0X0
17521
17522                 Set ACE outgoing ARQOS value
17523                 PSU_APU_ACE_CTRL_ARQOS                                                          0X0
17524
17525                 ACE Control Register
17526                 (OFFSET, MASK, VALUE)      (0XFD5C0060, 0x000F000FU ,0x00000000U)
17527                 RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK |  0 );
17528
17529                 RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT
17530                         | 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT
17531                         |  0 ) & RegMask); */
17532                 PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U);
17533         /*############################################################################################################################ */
17534
17535                 // : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
17536                 /*Register : CONTROL @ 0XFFA60040</p>
17537
17538                 Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from
17539                 he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
17540                 pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
17541                 g a 0 to this bit.
17542                 PSU_RTC_CONTROL_BATTERY_DISABLE                                                 0X1
17543
17544                 This register controls various functionalities within the RTC
17545                 (OFFSET, MASK, VALUE)      (0XFFA60040, 0x80000000U ,0x80000000U)
17546                 RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK |  0 );
17547
17548                 RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT
17549                         |  0 ) & RegMask); */
17550                 PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U);
17551         /*############################################################################################################################ */
17552
17553                 // : TIMESTAMP COUNTER
17554                 /*Register : base_frequency_ID_register @ 0XFF260020</p>
17555
17556                 Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.
17557                 PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ                                  0x5f5e100
17558
17559                 Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz
17560                 clock, program 0x02FAF080. This register is not accessible to the read-only programming interface.
17561                 (OFFSET, MASK, VALUE)      (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U)
17562                 RegMask = (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK |  0 );
17563
17564                 RegVal = ((0x05F5E100U << IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
17565                         |  0 ) & RegMask); */
17566                 PSU_Mask_Write (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET ,0xFFFFFFFFU ,0x05F5E100U);
17567         /*############################################################################################################################ */
17568
17569                 /*Register : counter_control_register @ 0XFF260000</p>
17570
17571                 Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.
17572                 PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN                                      0x1
17573
17574                 Controls the counter increments. This register is not accessible to the read-only programming interface.
17575                 (OFFSET, MASK, VALUE)      (0XFF260000, 0x00000001U ,0x00000001U)
17576                 RegMask = (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK |  0 );
17577
17578                 RegVal = ((0x00000001U << IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
17579                         |  0 ) & RegMask); */
17580                 PSU_Mask_Write (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET ,0x00000001U ,0x00000001U);
17581         /*############################################################################################################################ */
17582
17583                 // : TTC SRC SELECT
17584
17585   return 1;
17586 }
17587 unsigned long psu_post_config_data() {
17588                 // : POST_CONFIG
17589
17590   return 1;
17591 }
17592 unsigned long psu_peripherals_powerdwn_data() {
17593                 // : POWER DOWN REQUEST INTERRUPT ENABLE
17594                 // : POWER DOWN TRIGGER
17595
17596   return 1;
17597 }
17598 unsigned long psu_lpd_xppu_data() {
17599                 // : MASTER ID LIST
17600                 /*Register : MASTER_ID00 @ 0XFF980100</p>
17601
17602                 If set, only read transactions are allowed for the masters matching this register
17603                 PSU_LPD_XPPU_CFG_MASTER_ID00_MIDR                                               1
17604
17605                 Mask to be applied before comparing
17606                 PSU_LPD_XPPU_CFG_MASTER_ID00_MIDM                                               960
17607
17608                 Predefined Master ID for PMU
17609                 PSU_LPD_XPPU_CFG_MASTER_ID00_MID                                                128
17610
17611                 Master ID 00 Register
17612                 (OFFSET, MASK, VALUE)      (0XFF980100, 0x43FF03FFU ,0x43C00080U)
17613                 RegMask = (LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID00_MID_MASK |  0 );
17614
17615                 RegVal = ((0x00000001U << LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT
17616                         | 0x000003C0U << LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT
17617                         | 0x00000080U << LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT
17618                         |  0 ) & RegMask); */
17619                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID00_OFFSET ,0x43FF03FFU ,0x43C00080U);
17620         /*############################################################################################################################ */
17621
17622                 /*Register : MASTER_ID01 @ 0XFF980104</p>
17623
17624                 If set, only read transactions are allowed for the masters matching this register
17625                 PSU_LPD_XPPU_CFG_MASTER_ID01_MIDR                                               1
17626
17627                 Mask to be applied before comparing
17628                 PSU_LPD_XPPU_CFG_MASTER_ID01_MIDM                                               1023
17629
17630                 Predefined Master ID for RPU0
17631                 PSU_LPD_XPPU_CFG_MASTER_ID01_MID                                                64
17632
17633                 Master ID 01 Register
17634                 (OFFSET, MASK, VALUE)      (0XFF980104, 0x43FF03FFU ,0x43FF0040U)
17635                 RegMask = (LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID01_MID_MASK |  0 );
17636
17637                 RegVal = ((0x00000001U << LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT
17638                         | 0x000003FFU << LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT
17639                         | 0x00000040U << LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT
17640                         |  0 ) & RegMask); */
17641                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID01_OFFSET ,0x43FF03FFU ,0x43FF0040U);
17642         /*############################################################################################################################ */
17643
17644                 /*Register : MASTER_ID02 @ 0XFF980108</p>
17645
17646                 If set, only read transactions are allowed for the masters matching this register
17647                 PSU_LPD_XPPU_CFG_MASTER_ID02_MIDR                                               1
17648
17649                 Mask to be applied before comparing
17650                 PSU_LPD_XPPU_CFG_MASTER_ID02_MIDM                                               1008
17651
17652                 Predefined Master ID for RPU1
17653                 PSU_LPD_XPPU_CFG_MASTER_ID02_MID                                                0
17654
17655                 Master ID 02 Register
17656                 (OFFSET, MASK, VALUE)      (0XFF980108, 0x43FF03FFU ,0x43F00000U)
17657                 RegMask = (LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID02_MID_MASK |  0 );
17658
17659                 RegVal = ((0x00000001U << LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT
17660                         | 0x000003F0U << LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT
17661                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT
17662                         |  0 ) & RegMask); */
17663                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID02_OFFSET ,0x43FF03FFU ,0x43F00000U);
17664         /*############################################################################################################################ */
17665
17666                 /*Register : MASTER_ID03 @ 0XFF98010C</p>
17667
17668                 If set, only read transactions are allowed for the masters matching this register
17669                 PSU_LPD_XPPU_CFG_MASTER_ID03_MIDR                                               1
17670
17671                 Mask to be applied before comparing
17672                 PSU_LPD_XPPU_CFG_MASTER_ID03_MIDM                                               1008
17673
17674                 Predefined Master ID for APU
17675                 PSU_LPD_XPPU_CFG_MASTER_ID03_MID                                                16
17676
17677                 Master ID 03 Register
17678                 (OFFSET, MASK, VALUE)      (0XFF98010C, 0x43FF03FFU ,0x43F00010U)
17679                 RegMask = (LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID03_MID_MASK |  0 );
17680
17681                 RegVal = ((0x00000001U << LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT
17682                         | 0x000003F0U << LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT
17683                         | 0x00000010U << LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT
17684                         |  0 ) & RegMask); */
17685                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID03_OFFSET ,0x43FF03FFU ,0x43F00010U);
17686         /*############################################################################################################################ */
17687
17688                 /*Register : MASTER_ID04 @ 0XFF980110</p>
17689
17690                 If set, only read transactions are allowed for the masters matching this register
17691                 PSU_LPD_XPPU_CFG_MASTER_ID04_MIDR                                               0
17692
17693                 Mask to be applied before comparing
17694                 PSU_LPD_XPPU_CFG_MASTER_ID04_MIDM                                               960
17695
17696                 Predefined Master ID for A53 Core 0
17697                 PSU_LPD_XPPU_CFG_MASTER_ID04_MID                                                128
17698
17699                 Master ID 04 Register
17700                 (OFFSET, MASK, VALUE)      (0XFF980110, 0x43FF03FFU ,0x03C00080U)
17701                 RegMask = (LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID04_MID_MASK |  0 );
17702
17703                 RegVal = ((0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT
17704                         | 0x000003C0U << LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT
17705                         | 0x00000080U << LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT
17706                         |  0 ) & RegMask); */
17707                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID04_OFFSET ,0x43FF03FFU ,0x03C00080U);
17708         /*############################################################################################################################ */
17709
17710                 /*Register : MASTER_ID05 @ 0XFF980114</p>
17711
17712                 If set, only read transactions are allowed for the masters matching this register
17713                 PSU_LPD_XPPU_CFG_MASTER_ID05_MIDR                                               0
17714
17715                 Mask to be applied before comparing
17716                 PSU_LPD_XPPU_CFG_MASTER_ID05_MIDM                                               1023
17717
17718                 Predefined Master ID for A53 Core 1
17719                 PSU_LPD_XPPU_CFG_MASTER_ID05_MID                                                64
17720
17721                 Master ID 05 Register
17722                 (OFFSET, MASK, VALUE)      (0XFF980114, 0x43FF03FFU ,0x03FF0040U)
17723                 RegMask = (LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID05_MID_MASK |  0 );
17724
17725                 RegVal = ((0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT
17726                         | 0x000003FFU << LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT
17727                         | 0x00000040U << LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT
17728                         |  0 ) & RegMask); */
17729                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID05_OFFSET ,0x43FF03FFU ,0x03FF0040U);
17730         /*############################################################################################################################ */
17731
17732                 /*Register : MASTER_ID06 @ 0XFF980118</p>
17733
17734                 If set, only read transactions are allowed for the masters matching this register
17735                 PSU_LPD_XPPU_CFG_MASTER_ID06_MIDR                                               0
17736
17737                 Mask to be applied before comparing
17738                 PSU_LPD_XPPU_CFG_MASTER_ID06_MIDM                                               1008
17739
17740                 Predefined Master ID for A53 Core 2
17741                 PSU_LPD_XPPU_CFG_MASTER_ID06_MID                                                0
17742
17743                 Master ID 06 Register
17744                 (OFFSET, MASK, VALUE)      (0XFF980118, 0x43FF03FFU ,0x03F00000U)
17745                 RegMask = (LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID06_MID_MASK |  0 );
17746
17747                 RegVal = ((0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT
17748                         | 0x000003F0U << LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT
17749                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT
17750                         |  0 ) & RegMask); */
17751                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID06_OFFSET ,0x43FF03FFU ,0x03F00000U);
17752         /*############################################################################################################################ */
17753
17754                 /*Register : MASTER_ID07 @ 0XFF98011C</p>
17755
17756                 If set, only read transactions are allowed for the masters matching this register
17757                 PSU_LPD_XPPU_CFG_MASTER_ID07_MIDR                                               0
17758
17759                 Mask to be applied before comparing
17760                 PSU_LPD_XPPU_CFG_MASTER_ID07_MIDM                                               1008
17761
17762                 Predefined Master ID for A53 Core 3
17763                 PSU_LPD_XPPU_CFG_MASTER_ID07_MID                                                16
17764
17765                 Master ID 07 Register
17766                 (OFFSET, MASK, VALUE)      (0XFF98011C, 0x43FF03FFU ,0x03F00010U)
17767                 RegMask = (LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID07_MID_MASK |  0 );
17768
17769                 RegVal = ((0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT
17770                         | 0x000003F0U << LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT
17771                         | 0x00000010U << LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT
17772                         |  0 ) & RegMask); */
17773                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID07_OFFSET ,0x43FF03FFU ,0x03F00010U);
17774         /*############################################################################################################################ */
17775
17776                 /*Register : MASTER_ID19 @ 0XFF98014C</p>
17777
17778                 If set, only read transactions are allowed for the masters matching this register
17779                 PSU_LPD_XPPU_CFG_MASTER_ID19_MIDR                                               0
17780
17781                 Mask to be applied before comparing
17782                 PSU_LPD_XPPU_CFG_MASTER_ID19_MIDM                                               0
17783
17784                 Programmable Master ID
17785                 PSU_LPD_XPPU_CFG_MASTER_ID19_MID                                                0
17786
17787                 Master ID 19 Register
17788                 (OFFSET, MASK, VALUE)      (0XFF98014C, 0x43FF03FFU ,0x00000000U)
17789                 RegMask = (LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID19_MID_MASK |  0 );
17790
17791                 RegVal = ((0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT
17792                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT
17793                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT
17794                         |  0 ) & RegMask); */
17795                 PSU_Mask_Write (LPD_XPPU_CFG_MASTER_ID19_OFFSET ,0x43FF03FFU ,0x00000000U);
17796         /*############################################################################################################################ */
17797
17798                 // : APERTURE PERMISIION LIST
17799                 // : APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF
17800                 // : APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF
17801                 // : APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF
17802                 // : APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF
17803                 // : APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF
17804                 // : APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF
17805                 // : APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF
17806                 // : APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF
17807                 // : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF
17808                 // : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF
17809                 // : APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF
17810                 // : APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF
17811                 // : APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF
17812                 // : APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF
17813                 // : APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF
17814                 // : APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF
17815                 // : APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF
17816                 // : APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF
17817                 // : APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF
17818                 // : APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF
17819                 // : APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF
17820                 // : APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF
17821                 // : APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF
17822                 // : APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF
17823                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17824                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17825                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17826                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17827                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17828                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17829                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17830                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17831                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17832                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17833                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17834                 // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
17835                 // : APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF24FFFF
17836                 // : APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF
17837                 // : APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFFF
17838                 // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
17839                 // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
17840                 // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
17841                 // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
17842                 // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
17843                 // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
17844                 // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
17845                 // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
17846                 // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
17847                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17848                 /*Register : APERPERM_048 @ 0XFF9810C0</p>
17849
17850                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
17851                 h.
17852                 PSU_LPD_XPPU_CFG_APERPERM_048_PERMISSION                                        0x10
17853
17854                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
17855                 PSU_LPD_XPPU_CFG_APERPERM_048_TRUSTZONE                                         0x1
17856
17857                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
17858                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
17859                 PSU_LPD_XPPU_CFG_APERPERM_048_PARITY                                            0x0
17860
17861                 Entry 048 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00300000
17862                 (OFFSET, MASK, VALUE)      (0XFF9810C0, 0xF80FFFFFU ,0x08000010U)
17863                 RegMask = (LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_048_PARITY_MASK |  0 );
17864
17865                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT
17866                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT
17867                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT
17868                         |  0 ) & RegMask); */
17869                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_048_OFFSET ,0xF80FFFFFU ,0x08000010U);
17870         /*############################################################################################################################ */
17871
17872                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
17873                 /*Register : APERPERM_049 @ 0XFF9810C4</p>
17874
17875                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
17876                 h.
17877                 PSU_LPD_XPPU_CFG_APERPERM_049_PERMISSION                                        0x40
17878
17879                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
17880                 PSU_LPD_XPPU_CFG_APERPERM_049_TRUSTZONE                                         0x1
17881
17882                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
17883                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
17884                 PSU_LPD_XPPU_CFG_APERPERM_049_PARITY                                            0x0
17885
17886                 Entry 049 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00310000
17887                 (OFFSET, MASK, VALUE)      (0XFF9810C4, 0xF80FFFFFU ,0x08000040U)
17888                 RegMask = (LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_049_PARITY_MASK |  0 );
17889
17890                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT
17891                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT
17892                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT
17893                         |  0 ) & RegMask); */
17894                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_049_OFFSET ,0xF80FFFFFU ,0x08000040U);
17895         /*############################################################################################################################ */
17896
17897                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17898                 /*Register : APERPERM_050 @ 0XFF9810C8</p>
17899
17900                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
17901                 h.
17902                 PSU_LPD_XPPU_CFG_APERPERM_050_PERMISSION                                        0x80
17903
17904                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
17905                 PSU_LPD_XPPU_CFG_APERPERM_050_TRUSTZONE                                         0x1
17906
17907                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
17908                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
17909                 PSU_LPD_XPPU_CFG_APERPERM_050_PARITY                                            0x0
17910
17911                 Entry 050 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00320000
17912                 (OFFSET, MASK, VALUE)      (0XFF9810C8, 0xF80FFFFFU ,0x08000080U)
17913                 RegMask = (LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_050_PARITY_MASK |  0 );
17914
17915                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT
17916                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT
17917                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT
17918                         |  0 ) & RegMask); */
17919                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_050_OFFSET ,0xF80FFFFFU ,0x08000080U);
17920         /*############################################################################################################################ */
17921
17922                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17923                 /*Register : APERPERM_051 @ 0XFF9810CC</p>
17924
17925                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
17926                 h.
17927                 PSU_LPD_XPPU_CFG_APERPERM_051_PERMISSION                                        0x20
17928
17929                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
17930                 PSU_LPD_XPPU_CFG_APERPERM_051_TRUSTZONE                                         0x1
17931
17932                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
17933                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
17934                 PSU_LPD_XPPU_CFG_APERPERM_051_PARITY                                            0x0
17935
17936                 Entry 051 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00330000
17937                 (OFFSET, MASK, VALUE)      (0XFF9810CC, 0xF80FFFFFU ,0x08000020U)
17938                 RegMask = (LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_051_PARITY_MASK |  0 );
17939
17940                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT
17941                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT
17942                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT
17943                         |  0 ) & RegMask); */
17944                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_051_OFFSET ,0xF80FFFFFU ,0x08000020U);
17945         /*############################################################################################################################ */
17946
17947                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17948                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17949                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17950                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17951                 // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
17952                 // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
17953                 // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
17954                 // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
17955                 // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
17956                 // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
17957                 // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
17958                 // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
17959                 // : APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40FFFF
17960                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17961                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17962                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17963                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17964                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17965                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17966                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17967                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17968                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17969                 // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
17970                 // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
17971                 // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
17972                 // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
17973                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17974                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17975                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17976                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17977                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17978                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17979                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17980                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17981                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17982                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17983                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17984                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17985                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17986                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17987                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17988                 // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
17989                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17990                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17991                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17992                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17993                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17994                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17995                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17996                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17997                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17998                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
17999                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18000                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18001                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18002                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18003                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18004                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18005                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18006                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18007                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18008                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18009                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18010                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18011                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18012                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18013                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18014                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18015                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18016                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18017                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18018                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18019                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18020                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18021                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18022                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18023                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18024                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18025                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18026                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18027                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18028                 // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
18029                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18030                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18031                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18032                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18033                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18034                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18035                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18036                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18037                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18038                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18039                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18040                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18041                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18042                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18043                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18044                 // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
18045                 // : APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF
18046                 // : APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97FFFF
18047                 // : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
18048                 // : APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF
18049                 // : APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF
18050                 // : APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9CFFFF
18051                 // : APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF
18052                 // : APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF
18053                 // : APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FFFFF
18054                 // : APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF
18055                 // : APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF
18056                 // : APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2FFFF
18057                 // : APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FFFF
18058                 // : APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4FFFF
18059                 // : APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF
18060                 // : APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF
18061                 // : APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7FFFF
18062                 // : APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF
18063                 // : APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF
18064                 // : APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF
18065                 // : APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF
18066                 // : APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF
18067                 // : APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF
18068                 // : APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF
18069                 // : APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF
18070                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18071                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18072                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18073                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18074                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18075                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18076                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18077                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18078                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18079                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18080                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18081                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18082                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18083                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18084                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18085                 // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
18086                 // : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
18087                 // : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
18088                 // : APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF
18089                 // : APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF
18090                 // : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
18091                 // : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
18092                 // : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF
18093                 // : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF
18094                 // : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
18095                 // : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
18096                 // : APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF
18097                 // : APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF
18098                 // : APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF
18099                 // : APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF
18100                 // : APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF
18101                 // : APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF
18102                 // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
18103                 // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
18104                 // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
18105                 // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
18106                 // : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF
18107                 // : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF
18108                 // : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
18109                 // : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
18110                 // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
18111                 // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
18112                 // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
18113                 // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
18114                 // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
18115                 // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
18116                 // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
18117                 // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
18118                 // : APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF
18119                 // : APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: FFE1FFFF
18120                 // : APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF
18121                 // : APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: FFE3FFFF
18122                 // : APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDRESS: FFE4FFFF
18123                 // : APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FFE5FFFF
18124                 // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
18125                 // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
18126                 // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
18127                 // : APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFFF
18128                 // : APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEAFFFF
18129                 // : APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFFF
18130                 // : APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDRESS: FFECFFFF
18131                 // : APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FFEDFFFF
18132                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18133                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18134                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18135                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18136                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18137                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18138                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18139                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18140                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18141                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18142                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18143                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18144                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18145                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18146                 // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
18147                 // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
18148                 // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
18149                 // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
18150                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18151                 /*Register : APERPERM_256 @ 0XFF981400</p>
18152
18153                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18154                 h.
18155                 PSU_LPD_XPPU_CFG_APERPERM_256_PERMISSION                                        0x40
18156
18157                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18158                 PSU_LPD_XPPU_CFG_APERPERM_256_TRUSTZONE                                         0x1
18159
18160                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18161                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18162                 PSU_LPD_XPPU_CFG_APERPERM_256_PARITY                                            0x0
18163
18164                 Entry 256 of the Aperture Permission List, for 32-byte IPI buffer 000 at BASE_32B + 0x00000000
18165                 (OFFSET, MASK, VALUE)      (0XFF981400, 0xF80FFFFFU ,0x08000040U)
18166                 RegMask = (LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_256_PARITY_MASK |  0 );
18167
18168                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT
18169                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT
18170                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT
18171                         |  0 ) & RegMask); */
18172                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_256_OFFSET ,0xF80FFFFFU ,0x08000040U);
18173         /*############################################################################################################################ */
18174
18175                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18176                 /*Register : APERPERM_257 @ 0XFF981404</p>
18177
18178                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18179                 h.
18180                 PSU_LPD_XPPU_CFG_APERPERM_257_PERMISSION                                        0x40
18181
18182                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18183                 PSU_LPD_XPPU_CFG_APERPERM_257_TRUSTZONE                                         0x1
18184
18185                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18186                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18187                 PSU_LPD_XPPU_CFG_APERPERM_257_PARITY                                            0x0
18188
18189                 Entry 257 of the Aperture Permission List, for 32-byte IPI buffer 001 at BASE_32B + 0x00000020
18190                 (OFFSET, MASK, VALUE)      (0XFF981404, 0xF80FFFFFU ,0x08000040U)
18191                 RegMask = (LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_257_PARITY_MASK |  0 );
18192
18193                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT
18194                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT
18195                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT
18196                         |  0 ) & RegMask); */
18197                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_257_OFFSET ,0xF80FFFFFU ,0x08000040U);
18198         /*############################################################################################################################ */
18199
18200                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18201                 /*Register : APERPERM_258 @ 0XFF981408</p>
18202
18203                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18204                 h.
18205                 PSU_LPD_XPPU_CFG_APERPERM_258_PERMISSION                                        0x48
18206
18207                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18208                 PSU_LPD_XPPU_CFG_APERPERM_258_TRUSTZONE                                         0x1
18209
18210                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18211                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18212                 PSU_LPD_XPPU_CFG_APERPERM_258_PARITY                                            0x0
18213
18214                 Entry 258 of the Aperture Permission List, for 32-byte IPI buffer 002 at BASE_32B + 0x00000040
18215                 (OFFSET, MASK, VALUE)      (0XFF981408, 0xF80FFFFFU ,0x08000048U)
18216                 RegMask = (LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_258_PARITY_MASK |  0 );
18217
18218                 RegVal = ((0x00000048U << LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT
18219                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT
18220                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT
18221                         |  0 ) & RegMask); */
18222                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_258_OFFSET ,0xF80FFFFFU ,0x08000048U);
18223         /*############################################################################################################################ */
18224
18225                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18226                 /*Register : APERPERM_259 @ 0XFF98140C</p>
18227
18228                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18229                 h.
18230                 PSU_LPD_XPPU_CFG_APERPERM_259_PERMISSION                                        0x84
18231
18232                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18233                 PSU_LPD_XPPU_CFG_APERPERM_259_TRUSTZONE                                         0x1
18234
18235                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18236                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18237                 PSU_LPD_XPPU_CFG_APERPERM_259_PARITY                                            0x0
18238
18239                 Entry 259 of the Aperture Permission List, for 32-byte IPI buffer 003 at BASE_32B + 0x00000060
18240                 (OFFSET, MASK, VALUE)      (0XFF98140C, 0xF80FFFFFU ,0x08000084U)
18241                 RegMask = (LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_259_PARITY_MASK |  0 );
18242
18243                 RegVal = ((0x00000084U << LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT
18244                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT
18245                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT
18246                         |  0 ) & RegMask); */
18247                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_259_OFFSET ,0xF80FFFFFU ,0x08000084U);
18248         /*############################################################################################################################ */
18249
18250                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18251                 /*Register : APERPERM_260 @ 0XFF981410</p>
18252
18253                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18254                 h.
18255                 PSU_LPD_XPPU_CFG_APERPERM_260_PERMISSION                                        0x41
18256
18257                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18258                 PSU_LPD_XPPU_CFG_APERPERM_260_TRUSTZONE                                         0x1
18259
18260                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18261                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18262                 PSU_LPD_XPPU_CFG_APERPERM_260_PARITY                                            0x0
18263
18264                 Entry 260 of the Aperture Permission List, for 32-byte IPI buffer 004 at BASE_32B + 0x00000080
18265                 (OFFSET, MASK, VALUE)      (0XFF981410, 0xF80FFFFFU ,0x08000041U)
18266                 RegMask = (LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_260_PARITY_MASK |  0 );
18267
18268                 RegVal = ((0x00000041U << LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT
18269                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT
18270                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT
18271                         |  0 ) & RegMask); */
18272                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_260_OFFSET ,0xF80FFFFFU ,0x08000041U);
18273         /*############################################################################################################################ */
18274
18275                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18276                 /*Register : APERPERM_261 @ 0XFF981414</p>
18277
18278                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18279                 h.
18280                 PSU_LPD_XPPU_CFG_APERPERM_261_PERMISSION                                        0x14
18281
18282                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18283                 PSU_LPD_XPPU_CFG_APERPERM_261_TRUSTZONE                                         0x1
18284
18285                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18286                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18287                 PSU_LPD_XPPU_CFG_APERPERM_261_PARITY                                            0x0
18288
18289                 Entry 261 of the Aperture Permission List, for 32-byte IPI buffer 005 at BASE_32B + 0x000000A0
18290                 (OFFSET, MASK, VALUE)      (0XFF981414, 0xF80FFFFFU ,0x08000014U)
18291                 RegMask = (LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_261_PARITY_MASK |  0 );
18292
18293                 RegVal = ((0x00000014U << LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT
18294                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT
18295                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT
18296                         |  0 ) & RegMask); */
18297                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_261_OFFSET ,0xF80FFFFFU ,0x08000014U);
18298         /*############################################################################################################################ */
18299
18300                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18301                 /*Register : APERPERM_262 @ 0XFF981418</p>
18302
18303                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18304                 h.
18305                 PSU_LPD_XPPU_CFG_APERPERM_262_PERMISSION                                        0x40
18306
18307                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18308                 PSU_LPD_XPPU_CFG_APERPERM_262_TRUSTZONE                                         0x1
18309
18310                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18311                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18312                 PSU_LPD_XPPU_CFG_APERPERM_262_PARITY                                            0x0
18313
18314                 Entry 262 of the Aperture Permission List, for 32-byte IPI buffer 006 at BASE_32B + 0x000000C0
18315                 (OFFSET, MASK, VALUE)      (0XFF981418, 0xF80FFFFFU ,0x08000040U)
18316                 RegMask = (LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_262_PARITY_MASK |  0 );
18317
18318                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT
18319                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT
18320                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT
18321                         |  0 ) & RegMask); */
18322                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_262_OFFSET ,0xF80FFFFFU ,0x08000040U);
18323         /*############################################################################################################################ */
18324
18325                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18326                 /*Register : APERPERM_263 @ 0XFF98141C</p>
18327
18328                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18329                 h.
18330                 PSU_LPD_XPPU_CFG_APERPERM_263_PERMISSION                                        0x4
18331
18332                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18333                 PSU_LPD_XPPU_CFG_APERPERM_263_TRUSTZONE                                         0x1
18334
18335                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18336                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18337                 PSU_LPD_XPPU_CFG_APERPERM_263_PARITY                                            0x0
18338
18339                 Entry 263 of the Aperture Permission List, for 32-byte IPI buffer 007 at BASE_32B + 0x000000E0
18340                 (OFFSET, MASK, VALUE)      (0XFF98141C, 0xF80FFFFFU ,0x08000004U)
18341                 RegMask = (LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_263_PARITY_MASK |  0 );
18342
18343                 RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT
18344                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT
18345                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT
18346                         |  0 ) & RegMask); */
18347                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_263_OFFSET ,0xF80FFFFFU ,0x08000004U);
18348         /*############################################################################################################################ */
18349
18350                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18351                 /*Register : APERPERM_264 @ 0XFF981420</p>
18352
18353                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18354                 h.
18355                 PSU_LPD_XPPU_CFG_APERPERM_264_PERMISSION                                        0x40
18356
18357                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18358                 PSU_LPD_XPPU_CFG_APERPERM_264_TRUSTZONE                                         0x1
18359
18360                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18361                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18362                 PSU_LPD_XPPU_CFG_APERPERM_264_PARITY                                            0x0
18363
18364                 Entry 264 of the Aperture Permission List, for 32-byte IPI buffer 008 at BASE_32B + 0x00000100
18365                 (OFFSET, MASK, VALUE)      (0XFF981420, 0xF80FFFFFU ,0x08000040U)
18366                 RegMask = (LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_264_PARITY_MASK |  0 );
18367
18368                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT
18369                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT
18370                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT
18371                         |  0 ) & RegMask); */
18372                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_264_OFFSET ,0xF80FFFFFU ,0x08000040U);
18373         /*############################################################################################################################ */
18374
18375                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18376                 /*Register : APERPERM_265 @ 0XFF981424</p>
18377
18378                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18379                 h.
18380                 PSU_LPD_XPPU_CFG_APERPERM_265_PERMISSION                                        0x4
18381
18382                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18383                 PSU_LPD_XPPU_CFG_APERPERM_265_TRUSTZONE                                         0x1
18384
18385                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18386                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18387                 PSU_LPD_XPPU_CFG_APERPERM_265_PARITY                                            0x0
18388
18389                 Entry 265 of the Aperture Permission List, for 32-byte IPI buffer 009 at BASE_32B + 0x00000120
18390                 (OFFSET, MASK, VALUE)      (0XFF981424, 0xF80FFFFFU ,0x08000004U)
18391                 RegMask = (LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_265_PARITY_MASK |  0 );
18392
18393                 RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT
18394                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT
18395                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_265_PARITY_SHIFT
18396                         |  0 ) & RegMask); */
18397                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_265_OFFSET ,0xF80FFFFFU ,0x08000004U);
18398         /*############################################################################################################################ */
18399
18400                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18401                 /*Register : APERPERM_266 @ 0XFF981428</p>
18402
18403                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18404                 h.
18405                 PSU_LPD_XPPU_CFG_APERPERM_266_PERMISSION                                        0x40
18406
18407                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18408                 PSU_LPD_XPPU_CFG_APERPERM_266_TRUSTZONE                                         0x1
18409
18410                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18411                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18412                 PSU_LPD_XPPU_CFG_APERPERM_266_PARITY                                            0x0
18413
18414                 Entry 266 of the Aperture Permission List, for 32-byte IPI buffer 010 at BASE_32B + 0x00000140
18415                 (OFFSET, MASK, VALUE)      (0XFF981428, 0xF80FFFFFU ,0x08000040U)
18416                 RegMask = (LPD_XPPU_CFG_APERPERM_266_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_266_PARITY_MASK |  0 );
18417
18418                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_266_PERMISSION_SHIFT
18419                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_SHIFT
18420                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_266_PARITY_SHIFT
18421                         |  0 ) & RegMask); */
18422                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_266_OFFSET ,0xF80FFFFFU ,0x08000040U);
18423         /*############################################################################################################################ */
18424
18425                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18426                 /*Register : APERPERM_267 @ 0XFF98142C</p>
18427
18428                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18429                 h.
18430                 PSU_LPD_XPPU_CFG_APERPERM_267_PERMISSION                                        0x4
18431
18432                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18433                 PSU_LPD_XPPU_CFG_APERPERM_267_TRUSTZONE                                         0x1
18434
18435                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18436                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18437                 PSU_LPD_XPPU_CFG_APERPERM_267_PARITY                                            0x0
18438
18439                 Entry 267 of the Aperture Permission List, for 32-byte IPI buffer 011 at BASE_32B + 0x00000160
18440                 (OFFSET, MASK, VALUE)      (0XFF98142C, 0xF80FFFFFU ,0x08000004U)
18441                 RegMask = (LPD_XPPU_CFG_APERPERM_267_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_267_PARITY_MASK |  0 );
18442
18443                 RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_267_PERMISSION_SHIFT
18444                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_SHIFT
18445                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_267_PARITY_SHIFT
18446                         |  0 ) & RegMask); */
18447                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_267_OFFSET ,0xF80FFFFFU ,0x08000004U);
18448         /*############################################################################################################################ */
18449
18450                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18451                 /*Register : APERPERM_268 @ 0XFF981430</p>
18452
18453                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18454                 h.
18455                 PSU_LPD_XPPU_CFG_APERPERM_268_PERMISSION                                        0x40
18456
18457                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18458                 PSU_LPD_XPPU_CFG_APERPERM_268_TRUSTZONE                                         0x1
18459
18460                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18461                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18462                 PSU_LPD_XPPU_CFG_APERPERM_268_PARITY                                            0x0
18463
18464                 Entry 268 of the Aperture Permission List, for 32-byte IPI buffer 012 at BASE_32B + 0x00000180
18465                 (OFFSET, MASK, VALUE)      (0XFF981430, 0xF80FFFFFU ,0x08000040U)
18466                 RegMask = (LPD_XPPU_CFG_APERPERM_268_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_268_PARITY_MASK |  0 );
18467
18468                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_268_PERMISSION_SHIFT
18469                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_SHIFT
18470                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_268_PARITY_SHIFT
18471                         |  0 ) & RegMask); */
18472                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_268_OFFSET ,0xF80FFFFFU ,0x08000040U);
18473         /*############################################################################################################################ */
18474
18475                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18476                 /*Register : APERPERM_269 @ 0XFF981434</p>
18477
18478                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18479                 h.
18480                 PSU_LPD_XPPU_CFG_APERPERM_269_PERMISSION                                        0x4
18481
18482                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18483                 PSU_LPD_XPPU_CFG_APERPERM_269_TRUSTZONE                                         0x1
18484
18485                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18486                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18487                 PSU_LPD_XPPU_CFG_APERPERM_269_PARITY                                            0x0
18488
18489                 Entry 269 of the Aperture Permission List, for 32-byte IPI buffer 013 at BASE_32B + 0x000001A0
18490                 (OFFSET, MASK, VALUE)      (0XFF981434, 0xF80FFFFFU ,0x08000004U)
18491                 RegMask = (LPD_XPPU_CFG_APERPERM_269_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_269_PARITY_MASK |  0 );
18492
18493                 RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_269_PERMISSION_SHIFT
18494                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_SHIFT
18495                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_269_PARITY_SHIFT
18496                         |  0 ) & RegMask); */
18497                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_269_OFFSET ,0xF80FFFFFU ,0x08000004U);
18498         /*############################################################################################################################ */
18499
18500                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18501                 /*Register : APERPERM_270 @ 0XFF981438</p>
18502
18503                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18504                 h.
18505                 PSU_LPD_XPPU_CFG_APERPERM_270_PERMISSION                                        0x42
18506
18507                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18508                 PSU_LPD_XPPU_CFG_APERPERM_270_TRUSTZONE                                         0x1
18509
18510                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18511                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18512                 PSU_LPD_XPPU_CFG_APERPERM_270_PARITY                                            0x0
18513
18514                 Entry 270 of the Aperture Permission List, for 32-byte IPI buffer 014 at BASE_32B + 0x000001C0
18515                 (OFFSET, MASK, VALUE)      (0XFF981438, 0xF80FFFFFU ,0x08000042U)
18516                 RegMask = (LPD_XPPU_CFG_APERPERM_270_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_270_PARITY_MASK |  0 );
18517
18518                 RegVal = ((0x00000042U << LPD_XPPU_CFG_APERPERM_270_PERMISSION_SHIFT
18519                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_SHIFT
18520                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_270_PARITY_SHIFT
18521                         |  0 ) & RegMask); */
18522                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_270_OFFSET ,0xF80FFFFFU ,0x08000042U);
18523         /*############################################################################################################################ */
18524
18525                 // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
18526                 /*Register : APERPERM_271 @ 0XFF98143C</p>
18527
18528                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18529                 h.
18530                 PSU_LPD_XPPU_CFG_APERPERM_271_PERMISSION                                        0x24
18531
18532                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18533                 PSU_LPD_XPPU_CFG_APERPERM_271_TRUSTZONE                                         0x1
18534
18535                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18536                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18537                 PSU_LPD_XPPU_CFG_APERPERM_271_PARITY                                            0x0
18538
18539                 Entry 271 of the Aperture Permission List, for 32-byte IPI buffer 015 at BASE_32B + 0x000001E0
18540                 (OFFSET, MASK, VALUE)      (0XFF98143C, 0xF80FFFFFU ,0x08000024U)
18541                 RegMask = (LPD_XPPU_CFG_APERPERM_271_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_271_PARITY_MASK |  0 );
18542
18543                 RegVal = ((0x00000024U << LPD_XPPU_CFG_APERPERM_271_PERMISSION_SHIFT
18544                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_SHIFT
18545                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_271_PARITY_SHIFT
18546                         |  0 ) & RegMask); */
18547                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_271_OFFSET ,0xF80FFFFFU ,0x08000024U);
18548         /*############################################################################################################################ */
18549
18550                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18551                 /*Register : APERPERM_272 @ 0XFF981440</p>
18552
18553                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18554                 h.
18555                 PSU_LPD_XPPU_CFG_APERPERM_272_PERMISSION                                        0x84
18556
18557                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18558                 PSU_LPD_XPPU_CFG_APERPERM_272_TRUSTZONE                                         0x1
18559
18560                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18561                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18562                 PSU_LPD_XPPU_CFG_APERPERM_272_PARITY                                            0x0
18563
18564                 Entry 272 of the Aperture Permission List, for 32-byte IPI buffer 016 at BASE_32B + 0x00000200
18565                 (OFFSET, MASK, VALUE)      (0XFF981440, 0xF80FFFFFU ,0x08000084U)
18566                 RegMask = (LPD_XPPU_CFG_APERPERM_272_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_272_PARITY_MASK |  0 );
18567
18568                 RegVal = ((0x00000084U << LPD_XPPU_CFG_APERPERM_272_PERMISSION_SHIFT
18569                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_SHIFT
18570                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_272_PARITY_SHIFT
18571                         |  0 ) & RegMask); */
18572                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_272_OFFSET ,0xF80FFFFFU ,0x08000084U);
18573         /*############################################################################################################################ */
18574
18575                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18576                 /*Register : APERPERM_273 @ 0XFF981444</p>
18577
18578                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18579                 h.
18580                 PSU_LPD_XPPU_CFG_APERPERM_273_PERMISSION                                        0x48
18581
18582                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18583                 PSU_LPD_XPPU_CFG_APERPERM_273_TRUSTZONE                                         0x1
18584
18585                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18586                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18587                 PSU_LPD_XPPU_CFG_APERPERM_273_PARITY                                            0x0
18588
18589                 Entry 273 of the Aperture Permission List, for 32-byte IPI buffer 017 at BASE_32B + 0x00000220
18590                 (OFFSET, MASK, VALUE)      (0XFF981444, 0xF80FFFFFU ,0x08000048U)
18591                 RegMask = (LPD_XPPU_CFG_APERPERM_273_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_273_PARITY_MASK |  0 );
18592
18593                 RegVal = ((0x00000048U << LPD_XPPU_CFG_APERPERM_273_PERMISSION_SHIFT
18594                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_SHIFT
18595                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_273_PARITY_SHIFT
18596                         |  0 ) & RegMask); */
18597                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_273_OFFSET ,0xF80FFFFFU ,0x08000048U);
18598         /*############################################################################################################################ */
18599
18600                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18601                 /*Register : APERPERM_274 @ 0XFF981448</p>
18602
18603                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18604                 h.
18605                 PSU_LPD_XPPU_CFG_APERPERM_274_PERMISSION                                        0x80
18606
18607                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18608                 PSU_LPD_XPPU_CFG_APERPERM_274_TRUSTZONE                                         0x1
18609
18610                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18611                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18612                 PSU_LPD_XPPU_CFG_APERPERM_274_PARITY                                            0x0
18613
18614                 Entry 274 of the Aperture Permission List, for 32-byte IPI buffer 018 at BASE_32B + 0x00000240
18615                 (OFFSET, MASK, VALUE)      (0XFF981448, 0xF80FFFFFU ,0x08000080U)
18616                 RegMask = (LPD_XPPU_CFG_APERPERM_274_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_274_PARITY_MASK |  0 );
18617
18618                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_274_PERMISSION_SHIFT
18619                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_SHIFT
18620                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_274_PARITY_SHIFT
18621                         |  0 ) & RegMask); */
18622                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_274_OFFSET ,0xF80FFFFFU ,0x08000080U);
18623         /*############################################################################################################################ */
18624
18625                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18626                 /*Register : APERPERM_275 @ 0XFF98144C</p>
18627
18628                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18629                 h.
18630                 PSU_LPD_XPPU_CFG_APERPERM_275_PERMISSION                                        0x80
18631
18632                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18633                 PSU_LPD_XPPU_CFG_APERPERM_275_TRUSTZONE                                         0x1
18634
18635                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18636                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18637                 PSU_LPD_XPPU_CFG_APERPERM_275_PARITY                                            0x0
18638
18639                 Entry 275 of the Aperture Permission List, for 32-byte IPI buffer 019 at BASE_32B + 0x00000260
18640                 (OFFSET, MASK, VALUE)      (0XFF98144C, 0xF80FFFFFU ,0x08000080U)
18641                 RegMask = (LPD_XPPU_CFG_APERPERM_275_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_275_PARITY_MASK |  0 );
18642
18643                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_275_PERMISSION_SHIFT
18644                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_SHIFT
18645                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_275_PARITY_SHIFT
18646                         |  0 ) & RegMask); */
18647                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_275_OFFSET ,0xF80FFFFFU ,0x08000080U);
18648         /*############################################################################################################################ */
18649
18650                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18651                 /*Register : APERPERM_276 @ 0XFF981450</p>
18652
18653                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18654                 h.
18655                 PSU_LPD_XPPU_CFG_APERPERM_276_PERMISSION                                        0x81
18656
18657                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18658                 PSU_LPD_XPPU_CFG_APERPERM_276_TRUSTZONE                                         0x1
18659
18660                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18661                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18662                 PSU_LPD_XPPU_CFG_APERPERM_276_PARITY                                            0x0
18663
18664                 Entry 276 of the Aperture Permission List, for 32-byte IPI buffer 020 at BASE_32B + 0x00000280
18665                 (OFFSET, MASK, VALUE)      (0XFF981450, 0xF80FFFFFU ,0x08000081U)
18666                 RegMask = (LPD_XPPU_CFG_APERPERM_276_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_276_PARITY_MASK |  0 );
18667
18668                 RegVal = ((0x00000081U << LPD_XPPU_CFG_APERPERM_276_PERMISSION_SHIFT
18669                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_SHIFT
18670                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_276_PARITY_SHIFT
18671                         |  0 ) & RegMask); */
18672                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_276_OFFSET ,0xF80FFFFFU ,0x08000081U);
18673         /*############################################################################################################################ */
18674
18675                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18676                 /*Register : APERPERM_277 @ 0XFF981454</p>
18677
18678                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18679                 h.
18680                 PSU_LPD_XPPU_CFG_APERPERM_277_PERMISSION                                        0x18
18681
18682                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18683                 PSU_LPD_XPPU_CFG_APERPERM_277_TRUSTZONE                                         0x1
18684
18685                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18686                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18687                 PSU_LPD_XPPU_CFG_APERPERM_277_PARITY                                            0x0
18688
18689                 Entry 277 of the Aperture Permission List, for 32-byte IPI buffer 021 at BASE_32B + 0x000002A0
18690                 (OFFSET, MASK, VALUE)      (0XFF981454, 0xF80FFFFFU ,0x08000018U)
18691                 RegMask = (LPD_XPPU_CFG_APERPERM_277_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_277_PARITY_MASK |  0 );
18692
18693                 RegVal = ((0x00000018U << LPD_XPPU_CFG_APERPERM_277_PERMISSION_SHIFT
18694                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_SHIFT
18695                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_277_PARITY_SHIFT
18696                         |  0 ) & RegMask); */
18697                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_277_OFFSET ,0xF80FFFFFU ,0x08000018U);
18698         /*############################################################################################################################ */
18699
18700                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18701                 /*Register : APERPERM_278 @ 0XFF981458</p>
18702
18703                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18704                 h.
18705                 PSU_LPD_XPPU_CFG_APERPERM_278_PERMISSION                                        0x80
18706
18707                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18708                 PSU_LPD_XPPU_CFG_APERPERM_278_TRUSTZONE                                         0x1
18709
18710                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18711                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18712                 PSU_LPD_XPPU_CFG_APERPERM_278_PARITY                                            0x0
18713
18714                 Entry 278 of the Aperture Permission List, for 32-byte IPI buffer 022 at BASE_32B + 0x000002C0
18715                 (OFFSET, MASK, VALUE)      (0XFF981458, 0xF80FFFFFU ,0x08000080U)
18716                 RegMask = (LPD_XPPU_CFG_APERPERM_278_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_278_PARITY_MASK |  0 );
18717
18718                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_278_PERMISSION_SHIFT
18719                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_SHIFT
18720                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_278_PARITY_SHIFT
18721                         |  0 ) & RegMask); */
18722                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_278_OFFSET ,0xF80FFFFFU ,0x08000080U);
18723         /*############################################################################################################################ */
18724
18725                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18726                 /*Register : APERPERM_279 @ 0XFF98145C</p>
18727
18728                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18729                 h.
18730                 PSU_LPD_XPPU_CFG_APERPERM_279_PERMISSION                                        0x8
18731
18732                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18733                 PSU_LPD_XPPU_CFG_APERPERM_279_TRUSTZONE                                         0x1
18734
18735                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18736                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18737                 PSU_LPD_XPPU_CFG_APERPERM_279_PARITY                                            0x0
18738
18739                 Entry 279 of the Aperture Permission List, for 32-byte IPI buffer 023 at BASE_32B + 0x000002E0
18740                 (OFFSET, MASK, VALUE)      (0XFF98145C, 0xF80FFFFFU ,0x08000008U)
18741                 RegMask = (LPD_XPPU_CFG_APERPERM_279_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_279_PARITY_MASK |  0 );
18742
18743                 RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_279_PERMISSION_SHIFT
18744                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_SHIFT
18745                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_279_PARITY_SHIFT
18746                         |  0 ) & RegMask); */
18747                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_279_OFFSET ,0xF80FFFFFU ,0x08000008U);
18748         /*############################################################################################################################ */
18749
18750                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18751                 /*Register : APERPERM_280 @ 0XFF981460</p>
18752
18753                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18754                 h.
18755                 PSU_LPD_XPPU_CFG_APERPERM_280_PERMISSION                                        0x80
18756
18757                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18758                 PSU_LPD_XPPU_CFG_APERPERM_280_TRUSTZONE                                         0x1
18759
18760                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18761                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18762                 PSU_LPD_XPPU_CFG_APERPERM_280_PARITY                                            0x0
18763
18764                 Entry 280 of the Aperture Permission List, for 32-byte IPI buffer 024 at BASE_32B + 0x00000300
18765                 (OFFSET, MASK, VALUE)      (0XFF981460, 0xF80FFFFFU ,0x08000080U)
18766                 RegMask = (LPD_XPPU_CFG_APERPERM_280_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_280_PARITY_MASK |  0 );
18767
18768                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_280_PERMISSION_SHIFT
18769                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_SHIFT
18770                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_280_PARITY_SHIFT
18771                         |  0 ) & RegMask); */
18772                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_280_OFFSET ,0xF80FFFFFU ,0x08000080U);
18773         /*############################################################################################################################ */
18774
18775                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18776                 /*Register : APERPERM_281 @ 0XFF981464</p>
18777
18778                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18779                 h.
18780                 PSU_LPD_XPPU_CFG_APERPERM_281_PERMISSION                                        0x8
18781
18782                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18783                 PSU_LPD_XPPU_CFG_APERPERM_281_TRUSTZONE                                         0x1
18784
18785                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18786                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18787                 PSU_LPD_XPPU_CFG_APERPERM_281_PARITY                                            0x0
18788
18789                 Entry 281 of the Aperture Permission List, for 32-byte IPI buffer 025 at BASE_32B + 0x00000320
18790                 (OFFSET, MASK, VALUE)      (0XFF981464, 0xF80FFFFFU ,0x08000008U)
18791                 RegMask = (LPD_XPPU_CFG_APERPERM_281_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_281_PARITY_MASK |  0 );
18792
18793                 RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_281_PERMISSION_SHIFT
18794                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_SHIFT
18795                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_281_PARITY_SHIFT
18796                         |  0 ) & RegMask); */
18797                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_281_OFFSET ,0xF80FFFFFU ,0x08000008U);
18798         /*############################################################################################################################ */
18799
18800                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18801                 /*Register : APERPERM_282 @ 0XFF981468</p>
18802
18803                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18804                 h.
18805                 PSU_LPD_XPPU_CFG_APERPERM_282_PERMISSION                                        0x80
18806
18807                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18808                 PSU_LPD_XPPU_CFG_APERPERM_282_TRUSTZONE                                         0x1
18809
18810                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18811                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18812                 PSU_LPD_XPPU_CFG_APERPERM_282_PARITY                                            0x0
18813
18814                 Entry 282 of the Aperture Permission List, for 32-byte IPI buffer 026 at BASE_32B + 0x00000340
18815                 (OFFSET, MASK, VALUE)      (0XFF981468, 0xF80FFFFFU ,0x08000080U)
18816                 RegMask = (LPD_XPPU_CFG_APERPERM_282_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_282_PARITY_MASK |  0 );
18817
18818                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_282_PERMISSION_SHIFT
18819                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_SHIFT
18820                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_282_PARITY_SHIFT
18821                         |  0 ) & RegMask); */
18822                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_282_OFFSET ,0xF80FFFFFU ,0x08000080U);
18823         /*############################################################################################################################ */
18824
18825                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18826                 /*Register : APERPERM_283 @ 0XFF98146C</p>
18827
18828                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18829                 h.
18830                 PSU_LPD_XPPU_CFG_APERPERM_283_PERMISSION                                        0x8
18831
18832                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18833                 PSU_LPD_XPPU_CFG_APERPERM_283_TRUSTZONE                                         0x1
18834
18835                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18836                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18837                 PSU_LPD_XPPU_CFG_APERPERM_283_PARITY                                            0x0
18838
18839                 Entry 283 of the Aperture Permission List, for 32-byte IPI buffer 027 at BASE_32B + 0x00000360
18840                 (OFFSET, MASK, VALUE)      (0XFF98146C, 0xF80FFFFFU ,0x08000008U)
18841                 RegMask = (LPD_XPPU_CFG_APERPERM_283_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_283_PARITY_MASK |  0 );
18842
18843                 RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_283_PERMISSION_SHIFT
18844                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_SHIFT
18845                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_283_PARITY_SHIFT
18846                         |  0 ) & RegMask); */
18847                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_283_OFFSET ,0xF80FFFFFU ,0x08000008U);
18848         /*############################################################################################################################ */
18849
18850                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18851                 /*Register : APERPERM_284 @ 0XFF981470</p>
18852
18853                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18854                 h.
18855                 PSU_LPD_XPPU_CFG_APERPERM_284_PERMISSION                                        0x80
18856
18857                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18858                 PSU_LPD_XPPU_CFG_APERPERM_284_TRUSTZONE                                         0x1
18859
18860                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18861                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18862                 PSU_LPD_XPPU_CFG_APERPERM_284_PARITY                                            0x0
18863
18864                 Entry 284 of the Aperture Permission List, for 32-byte IPI buffer 028 at BASE_32B + 0x00000380
18865                 (OFFSET, MASK, VALUE)      (0XFF981470, 0xF80FFFFFU ,0x08000080U)
18866                 RegMask = (LPD_XPPU_CFG_APERPERM_284_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_284_PARITY_MASK |  0 );
18867
18868                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_284_PERMISSION_SHIFT
18869                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_SHIFT
18870                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_284_PARITY_SHIFT
18871                         |  0 ) & RegMask); */
18872                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_284_OFFSET ,0xF80FFFFFU ,0x08000080U);
18873         /*############################################################################################################################ */
18874
18875                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18876                 /*Register : APERPERM_285 @ 0XFF981474</p>
18877
18878                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18879                 h.
18880                 PSU_LPD_XPPU_CFG_APERPERM_285_PERMISSION                                        0x8
18881
18882                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18883                 PSU_LPD_XPPU_CFG_APERPERM_285_TRUSTZONE                                         0x1
18884
18885                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18886                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18887                 PSU_LPD_XPPU_CFG_APERPERM_285_PARITY                                            0x0
18888
18889                 Entry 285 of the Aperture Permission List, for 32-byte IPI buffer 029 at BASE_32B + 0x000003A0
18890                 (OFFSET, MASK, VALUE)      (0XFF981474, 0xF80FFFFFU ,0x08000008U)
18891                 RegMask = (LPD_XPPU_CFG_APERPERM_285_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_285_PARITY_MASK |  0 );
18892
18893                 RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_285_PERMISSION_SHIFT
18894                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_SHIFT
18895                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_285_PARITY_SHIFT
18896                         |  0 ) & RegMask); */
18897                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_285_OFFSET ,0xF80FFFFFU ,0x08000008U);
18898         /*############################################################################################################################ */
18899
18900                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18901                 /*Register : APERPERM_286 @ 0XFF981478</p>
18902
18903                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18904                 h.
18905                 PSU_LPD_XPPU_CFG_APERPERM_286_PERMISSION                                        0x82
18906
18907                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18908                 PSU_LPD_XPPU_CFG_APERPERM_286_TRUSTZONE                                         0x1
18909
18910                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18911                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18912                 PSU_LPD_XPPU_CFG_APERPERM_286_PARITY                                            0x0
18913
18914                 Entry 286 of the Aperture Permission List, for 32-byte IPI buffer 030 at BASE_32B + 0x000003C0
18915                 (OFFSET, MASK, VALUE)      (0XFF981478, 0xF80FFFFFU ,0x08000082U)
18916                 RegMask = (LPD_XPPU_CFG_APERPERM_286_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_286_PARITY_MASK |  0 );
18917
18918                 RegVal = ((0x00000082U << LPD_XPPU_CFG_APERPERM_286_PERMISSION_SHIFT
18919                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_SHIFT
18920                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_286_PARITY_SHIFT
18921                         |  0 ) & RegMask); */
18922                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_286_OFFSET ,0xF80FFFFFU ,0x08000082U);
18923         /*############################################################################################################################ */
18924
18925                 // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
18926                 /*Register : APERPERM_287 @ 0XFF98147C</p>
18927
18928                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18929                 h.
18930                 PSU_LPD_XPPU_CFG_APERPERM_287_PERMISSION                                        0x28
18931
18932                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18933                 PSU_LPD_XPPU_CFG_APERPERM_287_TRUSTZONE                                         0x1
18934
18935                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18936                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18937                 PSU_LPD_XPPU_CFG_APERPERM_287_PARITY                                            0x0
18938
18939                 Entry 287 of the Aperture Permission List, for 32-byte IPI buffer 031 at BASE_32B + 0x000003E0
18940                 (OFFSET, MASK, VALUE)      (0XFF98147C, 0xF80FFFFFU ,0x08000028U)
18941                 RegMask = (LPD_XPPU_CFG_APERPERM_287_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_287_PARITY_MASK |  0 );
18942
18943                 RegVal = ((0x00000028U << LPD_XPPU_CFG_APERPERM_287_PERMISSION_SHIFT
18944                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_SHIFT
18945                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_287_PARITY_SHIFT
18946                         |  0 ) & RegMask); */
18947                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_287_OFFSET ,0xF80FFFFFU ,0x08000028U);
18948         /*############################################################################################################################ */
18949
18950                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
18951                 /*Register : APERPERM_288 @ 0XFF981480</p>
18952
18953                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18954                 h.
18955                 PSU_LPD_XPPU_CFG_APERPERM_288_PERMISSION                                        0x14
18956
18957                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18958                 PSU_LPD_XPPU_CFG_APERPERM_288_TRUSTZONE                                         0x1
18959
18960                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18961                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18962                 PSU_LPD_XPPU_CFG_APERPERM_288_PARITY                                            0x0
18963
18964                 Entry 288 of the Aperture Permission List, for 32-byte IPI buffer 032 at BASE_32B + 0x00000400
18965                 (OFFSET, MASK, VALUE)      (0XFF981480, 0xF80FFFFFU ,0x08000014U)
18966                 RegMask = (LPD_XPPU_CFG_APERPERM_288_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_288_PARITY_MASK |  0 );
18967
18968                 RegVal = ((0x00000014U << LPD_XPPU_CFG_APERPERM_288_PERMISSION_SHIFT
18969                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_SHIFT
18970                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_288_PARITY_SHIFT
18971                         |  0 ) & RegMask); */
18972                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_288_OFFSET ,0xF80FFFFFU ,0x08000014U);
18973         /*############################################################################################################################ */
18974
18975                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
18976                 /*Register : APERPERM_289 @ 0XFF981484</p>
18977
18978                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
18979                 h.
18980                 PSU_LPD_XPPU_CFG_APERPERM_289_PERMISSION                                        0x41
18981
18982                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
18983                 PSU_LPD_XPPU_CFG_APERPERM_289_TRUSTZONE                                         0x1
18984
18985                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
18986                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
18987                 PSU_LPD_XPPU_CFG_APERPERM_289_PARITY                                            0x0
18988
18989                 Entry 289 of the Aperture Permission List, for 32-byte IPI buffer 033 at BASE_32B + 0x00000420
18990                 (OFFSET, MASK, VALUE)      (0XFF981484, 0xF80FFFFFU ,0x08000041U)
18991                 RegMask = (LPD_XPPU_CFG_APERPERM_289_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_289_PARITY_MASK |  0 );
18992
18993                 RegVal = ((0x00000041U << LPD_XPPU_CFG_APERPERM_289_PERMISSION_SHIFT
18994                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_SHIFT
18995                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_289_PARITY_SHIFT
18996                         |  0 ) & RegMask); */
18997                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_289_OFFSET ,0xF80FFFFFU ,0x08000041U);
18998         /*############################################################################################################################ */
18999
19000                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19001                 /*Register : APERPERM_290 @ 0XFF981488</p>
19002
19003                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19004                 h.
19005                 PSU_LPD_XPPU_CFG_APERPERM_290_PERMISSION                                        0x18
19006
19007                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19008                 PSU_LPD_XPPU_CFG_APERPERM_290_TRUSTZONE                                         0x1
19009
19010                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19011                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19012                 PSU_LPD_XPPU_CFG_APERPERM_290_PARITY                                            0x0
19013
19014                 Entry 290 of the Aperture Permission List, for 32-byte IPI buffer 034 at BASE_32B + 0x00000440
19015                 (OFFSET, MASK, VALUE)      (0XFF981488, 0xF80FFFFFU ,0x08000018U)
19016                 RegMask = (LPD_XPPU_CFG_APERPERM_290_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_290_PARITY_MASK |  0 );
19017
19018                 RegVal = ((0x00000018U << LPD_XPPU_CFG_APERPERM_290_PERMISSION_SHIFT
19019                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_SHIFT
19020                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_290_PARITY_SHIFT
19021                         |  0 ) & RegMask); */
19022                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_290_OFFSET ,0xF80FFFFFU ,0x08000018U);
19023         /*############################################################################################################################ */
19024
19025                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19026                 /*Register : APERPERM_291 @ 0XFF98148C</p>
19027
19028                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19029                 h.
19030                 PSU_LPD_XPPU_CFG_APERPERM_291_PERMISSION                                        0x81
19031
19032                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19033                 PSU_LPD_XPPU_CFG_APERPERM_291_TRUSTZONE                                         0x1
19034
19035                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19036                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19037                 PSU_LPD_XPPU_CFG_APERPERM_291_PARITY                                            0x0
19038
19039                 Entry 291 of the Aperture Permission List, for 32-byte IPI buffer 035 at BASE_32B + 0x00000460
19040                 (OFFSET, MASK, VALUE)      (0XFF98148C, 0xF80FFFFFU ,0x08000081U)
19041                 RegMask = (LPD_XPPU_CFG_APERPERM_291_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_291_PARITY_MASK |  0 );
19042
19043                 RegVal = ((0x00000081U << LPD_XPPU_CFG_APERPERM_291_PERMISSION_SHIFT
19044                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_SHIFT
19045                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_291_PARITY_SHIFT
19046                         |  0 ) & RegMask); */
19047                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_291_OFFSET ,0xF80FFFFFU ,0x08000081U);
19048         /*############################################################################################################################ */
19049
19050                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19051                 /*Register : APERPERM_292 @ 0XFF981490</p>
19052
19053                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19054                 h.
19055                 PSU_LPD_XPPU_CFG_APERPERM_292_PERMISSION                                        0x10
19056
19057                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19058                 PSU_LPD_XPPU_CFG_APERPERM_292_TRUSTZONE                                         0x1
19059
19060                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19061                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19062                 PSU_LPD_XPPU_CFG_APERPERM_292_PARITY                                            0x0
19063
19064                 Entry 292 of the Aperture Permission List, for 32-byte IPI buffer 036 at BASE_32B + 0x00000480
19065                 (OFFSET, MASK, VALUE)      (0XFF981490, 0xF80FFFFFU ,0x08000010U)
19066                 RegMask = (LPD_XPPU_CFG_APERPERM_292_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_292_PARITY_MASK |  0 );
19067
19068                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_292_PERMISSION_SHIFT
19069                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_SHIFT
19070                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_292_PARITY_SHIFT
19071                         |  0 ) & RegMask); */
19072                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_292_OFFSET ,0xF80FFFFFU ,0x08000010U);
19073         /*############################################################################################################################ */
19074
19075                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19076                 /*Register : APERPERM_293 @ 0XFF981494</p>
19077
19078                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19079                 h.
19080                 PSU_LPD_XPPU_CFG_APERPERM_293_PERMISSION                                        0x10
19081
19082                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19083                 PSU_LPD_XPPU_CFG_APERPERM_293_TRUSTZONE                                         0x1
19084
19085                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19086                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19087                 PSU_LPD_XPPU_CFG_APERPERM_293_PARITY                                            0x0
19088
19089                 Entry 293 of the Aperture Permission List, for 32-byte IPI buffer 037 at BASE_32B + 0x000004A0
19090                 (OFFSET, MASK, VALUE)      (0XFF981494, 0xF80FFFFFU ,0x08000010U)
19091                 RegMask = (LPD_XPPU_CFG_APERPERM_293_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_293_PARITY_MASK |  0 );
19092
19093                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_293_PERMISSION_SHIFT
19094                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_SHIFT
19095                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_293_PARITY_SHIFT
19096                         |  0 ) & RegMask); */
19097                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_293_OFFSET ,0xF80FFFFFU ,0x08000010U);
19098         /*############################################################################################################################ */
19099
19100                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19101                 /*Register : APERPERM_294 @ 0XFF981498</p>
19102
19103                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19104                 h.
19105                 PSU_LPD_XPPU_CFG_APERPERM_294_PERMISSION                                        0x10
19106
19107                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19108                 PSU_LPD_XPPU_CFG_APERPERM_294_TRUSTZONE                                         0x1
19109
19110                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19111                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19112                 PSU_LPD_XPPU_CFG_APERPERM_294_PARITY                                            0x0
19113
19114                 Entry 294 of the Aperture Permission List, for 32-byte IPI buffer 038 at BASE_32B + 0x000004C0
19115                 (OFFSET, MASK, VALUE)      (0XFF981498, 0xF80FFFFFU ,0x08000010U)
19116                 RegMask = (LPD_XPPU_CFG_APERPERM_294_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_294_PARITY_MASK |  0 );
19117
19118                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_294_PERMISSION_SHIFT
19119                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_SHIFT
19120                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_294_PARITY_SHIFT
19121                         |  0 ) & RegMask); */
19122                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_294_OFFSET ,0xF80FFFFFU ,0x08000010U);
19123         /*############################################################################################################################ */
19124
19125                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19126                 /*Register : APERPERM_295 @ 0XFF98149C</p>
19127
19128                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19129                 h.
19130                 PSU_LPD_XPPU_CFG_APERPERM_295_PERMISSION                                        0x1
19131
19132                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19133                 PSU_LPD_XPPU_CFG_APERPERM_295_TRUSTZONE                                         0x1
19134
19135                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19136                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19137                 PSU_LPD_XPPU_CFG_APERPERM_295_PARITY                                            0x0
19138
19139                 Entry 295 of the Aperture Permission List, for 32-byte IPI buffer 039 at BASE_32B + 0x000004E0
19140                 (OFFSET, MASK, VALUE)      (0XFF98149C, 0xF80FFFFFU ,0x08000001U)
19141                 RegMask = (LPD_XPPU_CFG_APERPERM_295_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_295_PARITY_MASK |  0 );
19142
19143                 RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_295_PERMISSION_SHIFT
19144                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_SHIFT
19145                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_295_PARITY_SHIFT
19146                         |  0 ) & RegMask); */
19147                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_295_OFFSET ,0xF80FFFFFU ,0x08000001U);
19148         /*############################################################################################################################ */
19149
19150                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19151                 /*Register : APERPERM_296 @ 0XFF9814A0</p>
19152
19153                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19154                 h.
19155                 PSU_LPD_XPPU_CFG_APERPERM_296_PERMISSION                                        0x10
19156
19157                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19158                 PSU_LPD_XPPU_CFG_APERPERM_296_TRUSTZONE                                         0x1
19159
19160                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19161                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19162                 PSU_LPD_XPPU_CFG_APERPERM_296_PARITY                                            0x0
19163
19164                 Entry 296 of the Aperture Permission List, for 32-byte IPI buffer 040 at BASE_32B + 0x00000500
19165                 (OFFSET, MASK, VALUE)      (0XFF9814A0, 0xF80FFFFFU ,0x08000010U)
19166                 RegMask = (LPD_XPPU_CFG_APERPERM_296_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_296_PARITY_MASK |  0 );
19167
19168                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_296_PERMISSION_SHIFT
19169                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_SHIFT
19170                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_296_PARITY_SHIFT
19171                         |  0 ) & RegMask); */
19172                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_296_OFFSET ,0xF80FFFFFU ,0x08000010U);
19173         /*############################################################################################################################ */
19174
19175                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19176                 /*Register : APERPERM_297 @ 0XFF9814A4</p>
19177
19178                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19179                 h.
19180                 PSU_LPD_XPPU_CFG_APERPERM_297_PERMISSION                                        0x1
19181
19182                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19183                 PSU_LPD_XPPU_CFG_APERPERM_297_TRUSTZONE                                         0x1
19184
19185                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19186                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19187                 PSU_LPD_XPPU_CFG_APERPERM_297_PARITY                                            0x0
19188
19189                 Entry 297 of the Aperture Permission List, for 32-byte IPI buffer 041 at BASE_32B + 0x00000520
19190                 (OFFSET, MASK, VALUE)      (0XFF9814A4, 0xF80FFFFFU ,0x08000001U)
19191                 RegMask = (LPD_XPPU_CFG_APERPERM_297_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_297_PARITY_MASK |  0 );
19192
19193                 RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_297_PERMISSION_SHIFT
19194                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_SHIFT
19195                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_297_PARITY_SHIFT
19196                         |  0 ) & RegMask); */
19197                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_297_OFFSET ,0xF80FFFFFU ,0x08000001U);
19198         /*############################################################################################################################ */
19199
19200                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19201                 /*Register : APERPERM_298 @ 0XFF9814A8</p>
19202
19203                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19204                 h.
19205                 PSU_LPD_XPPU_CFG_APERPERM_298_PERMISSION                                        0x10
19206
19207                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19208                 PSU_LPD_XPPU_CFG_APERPERM_298_TRUSTZONE                                         0x1
19209
19210                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19211                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19212                 PSU_LPD_XPPU_CFG_APERPERM_298_PARITY                                            0x0
19213
19214                 Entry 298 of the Aperture Permission List, for 32-byte IPI buffer 042 at BASE_32B + 0x00000540
19215                 (OFFSET, MASK, VALUE)      (0XFF9814A8, 0xF80FFFFFU ,0x08000010U)
19216                 RegMask = (LPD_XPPU_CFG_APERPERM_298_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_298_PARITY_MASK |  0 );
19217
19218                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_298_PERMISSION_SHIFT
19219                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_SHIFT
19220                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_298_PARITY_SHIFT
19221                         |  0 ) & RegMask); */
19222                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_298_OFFSET ,0xF80FFFFFU ,0x08000010U);
19223         /*############################################################################################################################ */
19224
19225                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19226                 /*Register : APERPERM_299 @ 0XFF9814AC</p>
19227
19228                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19229                 h.
19230                 PSU_LPD_XPPU_CFG_APERPERM_299_PERMISSION                                        0x1
19231
19232                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19233                 PSU_LPD_XPPU_CFG_APERPERM_299_TRUSTZONE                                         0x1
19234
19235                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19236                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19237                 PSU_LPD_XPPU_CFG_APERPERM_299_PARITY                                            0x0
19238
19239                 Entry 299 of the Aperture Permission List, for 32-byte IPI buffer 043 at BASE_32B + 0x00000560
19240                 (OFFSET, MASK, VALUE)      (0XFF9814AC, 0xF80FFFFFU ,0x08000001U)
19241                 RegMask = (LPD_XPPU_CFG_APERPERM_299_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_299_PARITY_MASK |  0 );
19242
19243                 RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_299_PERMISSION_SHIFT
19244                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_SHIFT
19245                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_299_PARITY_SHIFT
19246                         |  0 ) & RegMask); */
19247                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_299_OFFSET ,0xF80FFFFFU ,0x08000001U);
19248         /*############################################################################################################################ */
19249
19250                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19251                 /*Register : APERPERM_300 @ 0XFF9814B0</p>
19252
19253                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19254                 h.
19255                 PSU_LPD_XPPU_CFG_APERPERM_300_PERMISSION                                        0x10
19256
19257                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19258                 PSU_LPD_XPPU_CFG_APERPERM_300_TRUSTZONE                                         0x1
19259
19260                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19261                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19262                 PSU_LPD_XPPU_CFG_APERPERM_300_PARITY                                            0x0
19263
19264                 Entry 300 of the Aperture Permission List, for 32-byte IPI buffer 044 at BASE_32B + 0x00000580
19265                 (OFFSET, MASK, VALUE)      (0XFF9814B0, 0xF80FFFFFU ,0x08000010U)
19266                 RegMask = (LPD_XPPU_CFG_APERPERM_300_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_300_PARITY_MASK |  0 );
19267
19268                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_300_PERMISSION_SHIFT
19269                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_SHIFT
19270                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_300_PARITY_SHIFT
19271                         |  0 ) & RegMask); */
19272                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_300_OFFSET ,0xF80FFFFFU ,0x08000010U);
19273         /*############################################################################################################################ */
19274
19275                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19276                 /*Register : APERPERM_301 @ 0XFF9814B4</p>
19277
19278                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19279                 h.
19280                 PSU_LPD_XPPU_CFG_APERPERM_301_PERMISSION                                        0x1
19281
19282                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19283                 PSU_LPD_XPPU_CFG_APERPERM_301_TRUSTZONE                                         0x1
19284
19285                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19286                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19287                 PSU_LPD_XPPU_CFG_APERPERM_301_PARITY                                            0x0
19288
19289                 Entry 301 of the Aperture Permission List, for 32-byte IPI buffer 045 at BASE_32B + 0x000005A0
19290                 (OFFSET, MASK, VALUE)      (0XFF9814B4, 0xF80FFFFFU ,0x08000001U)
19291                 RegMask = (LPD_XPPU_CFG_APERPERM_301_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_301_PARITY_MASK |  0 );
19292
19293                 RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_301_PERMISSION_SHIFT
19294                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_SHIFT
19295                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_301_PARITY_SHIFT
19296                         |  0 ) & RegMask); */
19297                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_301_OFFSET ,0xF80FFFFFU ,0x08000001U);
19298         /*############################################################################################################################ */
19299
19300                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19301                 /*Register : APERPERM_302 @ 0XFF9814B8</p>
19302
19303                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19304                 h.
19305                 PSU_LPD_XPPU_CFG_APERPERM_302_PERMISSION                                        0x12
19306
19307                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19308                 PSU_LPD_XPPU_CFG_APERPERM_302_TRUSTZONE                                         0x1
19309
19310                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19311                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19312                 PSU_LPD_XPPU_CFG_APERPERM_302_PARITY                                            0x0
19313
19314                 Entry 302 of the Aperture Permission List, for 32-byte IPI buffer 046 at BASE_32B + 0x000005C0
19315                 (OFFSET, MASK, VALUE)      (0XFF9814B8, 0xF80FFFFFU ,0x08000012U)
19316                 RegMask = (LPD_XPPU_CFG_APERPERM_302_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_302_PARITY_MASK |  0 );
19317
19318                 RegVal = ((0x00000012U << LPD_XPPU_CFG_APERPERM_302_PERMISSION_SHIFT
19319                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_SHIFT
19320                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_302_PARITY_SHIFT
19321                         |  0 ) & RegMask); */
19322                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_302_OFFSET ,0xF80FFFFFU ,0x08000012U);
19323         /*############################################################################################################################ */
19324
19325                 // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
19326                 /*Register : APERPERM_303 @ 0XFF9814BC</p>
19327
19328                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19329                 h.
19330                 PSU_LPD_XPPU_CFG_APERPERM_303_PERMISSION                                        0x21
19331
19332                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19333                 PSU_LPD_XPPU_CFG_APERPERM_303_TRUSTZONE                                         0x1
19334
19335                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19336                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19337                 PSU_LPD_XPPU_CFG_APERPERM_303_PARITY                                            0x0
19338
19339                 Entry 303 of the Aperture Permission List, for 32-byte IPI buffer 047 at BASE_32B + 0x000005E0
19340                 (OFFSET, MASK, VALUE)      (0XFF9814BC, 0xF80FFFFFU ,0x08000021U)
19341                 RegMask = (LPD_XPPU_CFG_APERPERM_303_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_303_PARITY_MASK |  0 );
19342
19343                 RegVal = ((0x00000021U << LPD_XPPU_CFG_APERPERM_303_PERMISSION_SHIFT
19344                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_SHIFT
19345                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_303_PARITY_SHIFT
19346                         |  0 ) & RegMask); */
19347                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_303_OFFSET ,0xF80FFFFFU ,0x08000021U);
19348         /*############################################################################################################################ */
19349
19350                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19351                 /*Register : APERPERM_304 @ 0XFF9814C0</p>
19352
19353                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19354                 h.
19355                 PSU_LPD_XPPU_CFG_APERPERM_304_PERMISSION                                        0x4
19356
19357                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19358                 PSU_LPD_XPPU_CFG_APERPERM_304_TRUSTZONE                                         0x1
19359
19360                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19361                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19362                 PSU_LPD_XPPU_CFG_APERPERM_304_PARITY                                            0x0
19363
19364                 Entry 304 of the Aperture Permission List, for 32-byte IPI buffer 048 at BASE_32B + 0x00000600
19365                 (OFFSET, MASK, VALUE)      (0XFF9814C0, 0xF80FFFFFU ,0x08000004U)
19366                 RegMask = (LPD_XPPU_CFG_APERPERM_304_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_304_PARITY_MASK |  0 );
19367
19368                 RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_304_PERMISSION_SHIFT
19369                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_SHIFT
19370                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_304_PARITY_SHIFT
19371                         |  0 ) & RegMask); */
19372                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_304_OFFSET ,0xF80FFFFFU ,0x08000004U);
19373         /*############################################################################################################################ */
19374
19375                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19376                 /*Register : APERPERM_305 @ 0XFF9814C4</p>
19377
19378                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19379                 h.
19380                 PSU_LPD_XPPU_CFG_APERPERM_305_PERMISSION                                        0x40
19381
19382                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19383                 PSU_LPD_XPPU_CFG_APERPERM_305_TRUSTZONE                                         0x1
19384
19385                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19386                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19387                 PSU_LPD_XPPU_CFG_APERPERM_305_PARITY                                            0x0
19388
19389                 Entry 305 of the Aperture Permission List, for 32-byte IPI buffer 049 at BASE_32B + 0x00000620
19390                 (OFFSET, MASK, VALUE)      (0XFF9814C4, 0xF80FFFFFU ,0x08000040U)
19391                 RegMask = (LPD_XPPU_CFG_APERPERM_305_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_305_PARITY_MASK |  0 );
19392
19393                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_305_PERMISSION_SHIFT
19394                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_SHIFT
19395                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_305_PARITY_SHIFT
19396                         |  0 ) & RegMask); */
19397                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_305_OFFSET ,0xF80FFFFFU ,0x08000040U);
19398         /*############################################################################################################################ */
19399
19400                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19401                 /*Register : APERPERM_306 @ 0XFF9814C8</p>
19402
19403                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19404                 h.
19405                 PSU_LPD_XPPU_CFG_APERPERM_306_PERMISSION                                        0x8
19406
19407                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19408                 PSU_LPD_XPPU_CFG_APERPERM_306_TRUSTZONE                                         0x1
19409
19410                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19411                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19412                 PSU_LPD_XPPU_CFG_APERPERM_306_PARITY                                            0x0
19413
19414                 Entry 306 of the Aperture Permission List, for 32-byte IPI buffer 050 at BASE_32B + 0x00000640
19415                 (OFFSET, MASK, VALUE)      (0XFF9814C8, 0xF80FFFFFU ,0x08000008U)
19416                 RegMask = (LPD_XPPU_CFG_APERPERM_306_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_306_PARITY_MASK |  0 );
19417
19418                 RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_306_PERMISSION_SHIFT
19419                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_SHIFT
19420                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_306_PARITY_SHIFT
19421                         |  0 ) & RegMask); */
19422                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_306_OFFSET ,0xF80FFFFFU ,0x08000008U);
19423         /*############################################################################################################################ */
19424
19425                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19426                 /*Register : APERPERM_307 @ 0XFF9814CC</p>
19427
19428                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19429                 h.
19430                 PSU_LPD_XPPU_CFG_APERPERM_307_PERMISSION                                        0x80
19431
19432                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19433                 PSU_LPD_XPPU_CFG_APERPERM_307_TRUSTZONE                                         0x1
19434
19435                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19436                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19437                 PSU_LPD_XPPU_CFG_APERPERM_307_PARITY                                            0x0
19438
19439                 Entry 307 of the Aperture Permission List, for 32-byte IPI buffer 051 at BASE_32B + 0x00000660
19440                 (OFFSET, MASK, VALUE)      (0XFF9814CC, 0xF80FFFFFU ,0x08000080U)
19441                 RegMask = (LPD_XPPU_CFG_APERPERM_307_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_307_PARITY_MASK |  0 );
19442
19443                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_307_PERMISSION_SHIFT
19444                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_SHIFT
19445                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_307_PARITY_SHIFT
19446                         |  0 ) & RegMask); */
19447                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_307_OFFSET ,0xF80FFFFFU ,0x08000080U);
19448         /*############################################################################################################################ */
19449
19450                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19451                 /*Register : APERPERM_308 @ 0XFF9814D0</p>
19452
19453                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19454                 h.
19455                 PSU_LPD_XPPU_CFG_APERPERM_308_PERMISSION                                        0x1
19456
19457                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19458                 PSU_LPD_XPPU_CFG_APERPERM_308_TRUSTZONE                                         0x1
19459
19460                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19461                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19462                 PSU_LPD_XPPU_CFG_APERPERM_308_PARITY                                            0x0
19463
19464                 Entry 308 of the Aperture Permission List, for 32-byte IPI buffer 052 at BASE_32B + 0x00000680
19465                 (OFFSET, MASK, VALUE)      (0XFF9814D0, 0xF80FFFFFU ,0x08000001U)
19466                 RegMask = (LPD_XPPU_CFG_APERPERM_308_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_308_PARITY_MASK |  0 );
19467
19468                 RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_308_PERMISSION_SHIFT
19469                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_SHIFT
19470                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_308_PARITY_SHIFT
19471                         |  0 ) & RegMask); */
19472                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_308_OFFSET ,0xF80FFFFFU ,0x08000001U);
19473         /*############################################################################################################################ */
19474
19475                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19476                 /*Register : APERPERM_309 @ 0XFF9814D4</p>
19477
19478                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19479                 h.
19480                 PSU_LPD_XPPU_CFG_APERPERM_309_PERMISSION                                        0x10
19481
19482                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19483                 PSU_LPD_XPPU_CFG_APERPERM_309_TRUSTZONE                                         0x1
19484
19485                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19486                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19487                 PSU_LPD_XPPU_CFG_APERPERM_309_PARITY                                            0x0
19488
19489                 Entry 309 of the Aperture Permission List, for 32-byte IPI buffer 053 at BASE_32B + 0x000006A0
19490                 (OFFSET, MASK, VALUE)      (0XFF9814D4, 0xF80FFFFFU ,0x08000010U)
19491                 RegMask = (LPD_XPPU_CFG_APERPERM_309_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_309_PARITY_MASK |  0 );
19492
19493                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_309_PERMISSION_SHIFT
19494                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_SHIFT
19495                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_309_PARITY_SHIFT
19496                         |  0 ) & RegMask); */
19497                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_309_OFFSET ,0xF80FFFFFU ,0x08000010U);
19498         /*############################################################################################################################ */
19499
19500                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19501                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19502                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19503                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19504                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19505                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19506                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19507                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19508                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19509                 /*Register : APERPERM_318 @ 0XFF9814F8</p>
19510
19511                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19512                 h.
19513                 PSU_LPD_XPPU_CFG_APERPERM_318_PERMISSION                                        0x2
19514
19515                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19516                 PSU_LPD_XPPU_CFG_APERPERM_318_TRUSTZONE                                         0x1
19517
19518                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19519                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19520                 PSU_LPD_XPPU_CFG_APERPERM_318_PARITY                                            0x0
19521
19522                 Entry 318 of the Aperture Permission List, for 32-byte IPI buffer 062 at BASE_32B + 0x000007C0
19523                 (OFFSET, MASK, VALUE)      (0XFF9814F8, 0xF80FFFFFU ,0x08000002U)
19524                 RegMask = (LPD_XPPU_CFG_APERPERM_318_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_318_PARITY_MASK |  0 );
19525
19526                 RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_318_PERMISSION_SHIFT
19527                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_SHIFT
19528                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_318_PARITY_SHIFT
19529                         |  0 ) & RegMask); */
19530                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_318_OFFSET ,0xF80FFFFFU ,0x08000002U);
19531         /*############################################################################################################################ */
19532
19533                 // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
19534                 /*Register : APERPERM_319 @ 0XFF9814FC</p>
19535
19536                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19537                 h.
19538                 PSU_LPD_XPPU_CFG_APERPERM_319_PERMISSION                                        0x20
19539
19540                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19541                 PSU_LPD_XPPU_CFG_APERPERM_319_TRUSTZONE                                         0x1
19542
19543                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19544                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19545                 PSU_LPD_XPPU_CFG_APERPERM_319_PARITY                                            0x0
19546
19547                 Entry 319 of the Aperture Permission List, for 32-byte IPI buffer 063 at BASE_32B + 0x000007E0
19548                 (OFFSET, MASK, VALUE)      (0XFF9814FC, 0xF80FFFFFU ,0x08000020U)
19549                 RegMask = (LPD_XPPU_CFG_APERPERM_319_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_319_PARITY_MASK |  0 );
19550
19551                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_319_PERMISSION_SHIFT
19552                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_SHIFT
19553                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_319_PARITY_SHIFT
19554                         |  0 ) & RegMask); */
19555                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_319_OFFSET ,0xF80FFFFFU ,0x08000020U);
19556         /*############################################################################################################################ */
19557
19558                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19559                 /*Register : APERPERM_320 @ 0XFF981500</p>
19560
19561                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19562                 h.
19563                 PSU_LPD_XPPU_CFG_APERPERM_320_PERMISSION                                        0x4
19564
19565                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19566                 PSU_LPD_XPPU_CFG_APERPERM_320_TRUSTZONE                                         0x1
19567
19568                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19569                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19570                 PSU_LPD_XPPU_CFG_APERPERM_320_PARITY                                            0x0
19571
19572                 Entry 320 of the Aperture Permission List, for 32-byte IPI buffer 064 at BASE_32B + 0x00000800
19573                 (OFFSET, MASK, VALUE)      (0XFF981500, 0xF80FFFFFU ,0x08000004U)
19574                 RegMask = (LPD_XPPU_CFG_APERPERM_320_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_320_PARITY_MASK |  0 );
19575
19576                 RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_320_PERMISSION_SHIFT
19577                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_SHIFT
19578                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_320_PARITY_SHIFT
19579                         |  0 ) & RegMask); */
19580                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_320_OFFSET ,0xF80FFFFFU ,0x08000004U);
19581         /*############################################################################################################################ */
19582
19583                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19584                 /*Register : APERPERM_321 @ 0XFF981504</p>
19585
19586                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19587                 h.
19588                 PSU_LPD_XPPU_CFG_APERPERM_321_PERMISSION                                        0x40
19589
19590                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19591                 PSU_LPD_XPPU_CFG_APERPERM_321_TRUSTZONE                                         0x1
19592
19593                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19594                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19595                 PSU_LPD_XPPU_CFG_APERPERM_321_PARITY                                            0x0
19596
19597                 Entry 321 of the Aperture Permission List, for 32-byte IPI buffer 065 at BASE_32B + 0x00000820
19598                 (OFFSET, MASK, VALUE)      (0XFF981504, 0xF80FFFFFU ,0x08000040U)
19599                 RegMask = (LPD_XPPU_CFG_APERPERM_321_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_321_PARITY_MASK |  0 );
19600
19601                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_321_PERMISSION_SHIFT
19602                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_SHIFT
19603                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_321_PARITY_SHIFT
19604                         |  0 ) & RegMask); */
19605                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_321_OFFSET ,0xF80FFFFFU ,0x08000040U);
19606         /*############################################################################################################################ */
19607
19608                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19609                 /*Register : APERPERM_322 @ 0XFF981508</p>
19610
19611                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19612                 h.
19613                 PSU_LPD_XPPU_CFG_APERPERM_322_PERMISSION                                        0x8
19614
19615                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19616                 PSU_LPD_XPPU_CFG_APERPERM_322_TRUSTZONE                                         0x1
19617
19618                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19619                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19620                 PSU_LPD_XPPU_CFG_APERPERM_322_PARITY                                            0x0
19621
19622                 Entry 322 of the Aperture Permission List, for 32-byte IPI buffer 066 at BASE_32B + 0x00000840
19623                 (OFFSET, MASK, VALUE)      (0XFF981508, 0xF80FFFFFU ,0x08000008U)
19624                 RegMask = (LPD_XPPU_CFG_APERPERM_322_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_322_PARITY_MASK |  0 );
19625
19626                 RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_322_PERMISSION_SHIFT
19627                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_SHIFT
19628                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_322_PARITY_SHIFT
19629                         |  0 ) & RegMask); */
19630                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_322_OFFSET ,0xF80FFFFFU ,0x08000008U);
19631         /*############################################################################################################################ */
19632
19633                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19634                 /*Register : APERPERM_323 @ 0XFF98150C</p>
19635
19636                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19637                 h.
19638                 PSU_LPD_XPPU_CFG_APERPERM_323_PERMISSION                                        0x80
19639
19640                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19641                 PSU_LPD_XPPU_CFG_APERPERM_323_TRUSTZONE                                         0x1
19642
19643                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19644                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19645                 PSU_LPD_XPPU_CFG_APERPERM_323_PARITY                                            0x0
19646
19647                 Entry 323 of the Aperture Permission List, for 32-byte IPI buffer 067 at BASE_32B + 0x00000860
19648                 (OFFSET, MASK, VALUE)      (0XFF98150C, 0xF80FFFFFU ,0x08000080U)
19649                 RegMask = (LPD_XPPU_CFG_APERPERM_323_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_323_PARITY_MASK |  0 );
19650
19651                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_323_PERMISSION_SHIFT
19652                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_SHIFT
19653                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_323_PARITY_SHIFT
19654                         |  0 ) & RegMask); */
19655                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_323_OFFSET ,0xF80FFFFFU ,0x08000080U);
19656         /*############################################################################################################################ */
19657
19658                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19659                 /*Register : APERPERM_324 @ 0XFF981510</p>
19660
19661                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19662                 h.
19663                 PSU_LPD_XPPU_CFG_APERPERM_324_PERMISSION                                        0x1
19664
19665                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19666                 PSU_LPD_XPPU_CFG_APERPERM_324_TRUSTZONE                                         0x1
19667
19668                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19669                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19670                 PSU_LPD_XPPU_CFG_APERPERM_324_PARITY                                            0x0
19671
19672                 Entry 324 of the Aperture Permission List, for 32-byte IPI buffer 068 at BASE_32B + 0x00000880
19673                 (OFFSET, MASK, VALUE)      (0XFF981510, 0xF80FFFFFU ,0x08000001U)
19674                 RegMask = (LPD_XPPU_CFG_APERPERM_324_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_324_PARITY_MASK |  0 );
19675
19676                 RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_324_PERMISSION_SHIFT
19677                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_SHIFT
19678                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_324_PARITY_SHIFT
19679                         |  0 ) & RegMask); */
19680                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_324_OFFSET ,0xF80FFFFFU ,0x08000001U);
19681         /*############################################################################################################################ */
19682
19683                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19684                 /*Register : APERPERM_325 @ 0XFF981514</p>
19685
19686                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19687                 h.
19688                 PSU_LPD_XPPU_CFG_APERPERM_325_PERMISSION                                        0x10
19689
19690                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19691                 PSU_LPD_XPPU_CFG_APERPERM_325_TRUSTZONE                                         0x1
19692
19693                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19694                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19695                 PSU_LPD_XPPU_CFG_APERPERM_325_PARITY                                            0x0
19696
19697                 Entry 325 of the Aperture Permission List, for 32-byte IPI buffer 069 at BASE_32B + 0x000008A0
19698                 (OFFSET, MASK, VALUE)      (0XFF981514, 0xF80FFFFFU ,0x08000010U)
19699                 RegMask = (LPD_XPPU_CFG_APERPERM_325_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_325_PARITY_MASK |  0 );
19700
19701                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_325_PERMISSION_SHIFT
19702                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_SHIFT
19703                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_325_PARITY_SHIFT
19704                         |  0 ) & RegMask); */
19705                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_325_OFFSET ,0xF80FFFFFU ,0x08000010U);
19706         /*############################################################################################################################ */
19707
19708                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19709                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19710                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19711                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19712                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19713                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19714                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19715                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19716                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19717                 /*Register : APERPERM_334 @ 0XFF981538</p>
19718
19719                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19720                 h.
19721                 PSU_LPD_XPPU_CFG_APERPERM_334_PERMISSION                                        0x2
19722
19723                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19724                 PSU_LPD_XPPU_CFG_APERPERM_334_TRUSTZONE                                         0x1
19725
19726                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19727                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19728                 PSU_LPD_XPPU_CFG_APERPERM_334_PARITY                                            0x0
19729
19730                 Entry 334 of the Aperture Permission List, for 32-byte IPI buffer 078 at BASE_32B + 0x000009C0
19731                 (OFFSET, MASK, VALUE)      (0XFF981538, 0xF80FFFFFU ,0x08000002U)
19732                 RegMask = (LPD_XPPU_CFG_APERPERM_334_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_334_PARITY_MASK |  0 );
19733
19734                 RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_334_PERMISSION_SHIFT
19735                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_SHIFT
19736                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_334_PARITY_SHIFT
19737                         |  0 ) & RegMask); */
19738                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_334_OFFSET ,0xF80FFFFFU ,0x08000002U);
19739         /*############################################################################################################################ */
19740
19741                 // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
19742                 /*Register : APERPERM_335 @ 0XFF98153C</p>
19743
19744                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19745                 h.
19746                 PSU_LPD_XPPU_CFG_APERPERM_335_PERMISSION                                        0x20
19747
19748                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19749                 PSU_LPD_XPPU_CFG_APERPERM_335_TRUSTZONE                                         0x1
19750
19751                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19752                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19753                 PSU_LPD_XPPU_CFG_APERPERM_335_PARITY                                            0x0
19754
19755                 Entry 335 of the Aperture Permission List, for 32-byte IPI buffer 079 at BASE_32B + 0x000009E0
19756                 (OFFSET, MASK, VALUE)      (0XFF98153C, 0xF80FFFFFU ,0x08000020U)
19757                 RegMask = (LPD_XPPU_CFG_APERPERM_335_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_335_PARITY_MASK |  0 );
19758
19759                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_335_PERMISSION_SHIFT
19760                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_SHIFT
19761                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_335_PARITY_SHIFT
19762                         |  0 ) & RegMask); */
19763                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_335_OFFSET ,0xF80FFFFFU ,0x08000020U);
19764         /*############################################################################################################################ */
19765
19766                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19767                 /*Register : APERPERM_336 @ 0XFF981540</p>
19768
19769                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19770                 h.
19771                 PSU_LPD_XPPU_CFG_APERPERM_336_PERMISSION                                        0x4
19772
19773                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19774                 PSU_LPD_XPPU_CFG_APERPERM_336_TRUSTZONE                                         0x1
19775
19776                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19777                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19778                 PSU_LPD_XPPU_CFG_APERPERM_336_PARITY                                            0x0
19779
19780                 Entry 336 of the Aperture Permission List, for 32-byte IPI buffer 080 at BASE_32B + 0x00000A00
19781                 (OFFSET, MASK, VALUE)      (0XFF981540, 0xF80FFFFFU ,0x08000004U)
19782                 RegMask = (LPD_XPPU_CFG_APERPERM_336_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_336_PARITY_MASK |  0 );
19783
19784                 RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_336_PERMISSION_SHIFT
19785                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_SHIFT
19786                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_336_PARITY_SHIFT
19787                         |  0 ) & RegMask); */
19788                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_336_OFFSET ,0xF80FFFFFU ,0x08000004U);
19789         /*############################################################################################################################ */
19790
19791                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19792                 /*Register : APERPERM_337 @ 0XFF981544</p>
19793
19794                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19795                 h.
19796                 PSU_LPD_XPPU_CFG_APERPERM_337_PERMISSION                                        0x40
19797
19798                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19799                 PSU_LPD_XPPU_CFG_APERPERM_337_TRUSTZONE                                         0x1
19800
19801                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19802                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19803                 PSU_LPD_XPPU_CFG_APERPERM_337_PARITY                                            0x0
19804
19805                 Entry 337 of the Aperture Permission List, for 32-byte IPI buffer 081 at BASE_32B + 0x00000A20
19806                 (OFFSET, MASK, VALUE)      (0XFF981544, 0xF80FFFFFU ,0x08000040U)
19807                 RegMask = (LPD_XPPU_CFG_APERPERM_337_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_337_PARITY_MASK |  0 );
19808
19809                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_337_PERMISSION_SHIFT
19810                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_SHIFT
19811                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_337_PARITY_SHIFT
19812                         |  0 ) & RegMask); */
19813                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_337_OFFSET ,0xF80FFFFFU ,0x08000040U);
19814         /*############################################################################################################################ */
19815
19816                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19817                 /*Register : APERPERM_338 @ 0XFF981548</p>
19818
19819                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19820                 h.
19821                 PSU_LPD_XPPU_CFG_APERPERM_338_PERMISSION                                        0x8
19822
19823                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19824                 PSU_LPD_XPPU_CFG_APERPERM_338_TRUSTZONE                                         0x1
19825
19826                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19827                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19828                 PSU_LPD_XPPU_CFG_APERPERM_338_PARITY                                            0x0
19829
19830                 Entry 338 of the Aperture Permission List, for 32-byte IPI buffer 082 at BASE_32B + 0x00000A40
19831                 (OFFSET, MASK, VALUE)      (0XFF981548, 0xF80FFFFFU ,0x08000008U)
19832                 RegMask = (LPD_XPPU_CFG_APERPERM_338_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_338_PARITY_MASK |  0 );
19833
19834                 RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_338_PERMISSION_SHIFT
19835                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_SHIFT
19836                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_338_PARITY_SHIFT
19837                         |  0 ) & RegMask); */
19838                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_338_OFFSET ,0xF80FFFFFU ,0x08000008U);
19839         /*############################################################################################################################ */
19840
19841                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19842                 /*Register : APERPERM_339 @ 0XFF98154C</p>
19843
19844                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19845                 h.
19846                 PSU_LPD_XPPU_CFG_APERPERM_339_PERMISSION                                        0x80
19847
19848                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19849                 PSU_LPD_XPPU_CFG_APERPERM_339_TRUSTZONE                                         0x1
19850
19851                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19852                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19853                 PSU_LPD_XPPU_CFG_APERPERM_339_PARITY                                            0x0
19854
19855                 Entry 339 of the Aperture Permission List, for 32-byte IPI buffer 083 at BASE_32B + 0x00000A60
19856                 (OFFSET, MASK, VALUE)      (0XFF98154C, 0xF80FFFFFU ,0x08000080U)
19857                 RegMask = (LPD_XPPU_CFG_APERPERM_339_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_339_PARITY_MASK |  0 );
19858
19859                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_339_PERMISSION_SHIFT
19860                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_SHIFT
19861                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_339_PARITY_SHIFT
19862                         |  0 ) & RegMask); */
19863                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_339_OFFSET ,0xF80FFFFFU ,0x08000080U);
19864         /*############################################################################################################################ */
19865
19866                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19867                 /*Register : APERPERM_340 @ 0XFF981550</p>
19868
19869                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19870                 h.
19871                 PSU_LPD_XPPU_CFG_APERPERM_340_PERMISSION                                        0x1
19872
19873                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19874                 PSU_LPD_XPPU_CFG_APERPERM_340_TRUSTZONE                                         0x1
19875
19876                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19877                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19878                 PSU_LPD_XPPU_CFG_APERPERM_340_PARITY                                            0x0
19879
19880                 Entry 340 of the Aperture Permission List, for 32-byte IPI buffer 084 at BASE_32B + 0x00000A80
19881                 (OFFSET, MASK, VALUE)      (0XFF981550, 0xF80FFFFFU ,0x08000001U)
19882                 RegMask = (LPD_XPPU_CFG_APERPERM_340_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_340_PARITY_MASK |  0 );
19883
19884                 RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_340_PERMISSION_SHIFT
19885                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_SHIFT
19886                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_340_PARITY_SHIFT
19887                         |  0 ) & RegMask); */
19888                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_340_OFFSET ,0xF80FFFFFU ,0x08000001U);
19889         /*############################################################################################################################ */
19890
19891                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19892                 /*Register : APERPERM_341 @ 0XFF981554</p>
19893
19894                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19895                 h.
19896                 PSU_LPD_XPPU_CFG_APERPERM_341_PERMISSION                                        0x10
19897
19898                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19899                 PSU_LPD_XPPU_CFG_APERPERM_341_TRUSTZONE                                         0x1
19900
19901                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19902                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19903                 PSU_LPD_XPPU_CFG_APERPERM_341_PARITY                                            0x0
19904
19905                 Entry 341 of the Aperture Permission List, for 32-byte IPI buffer 085 at BASE_32B + 0x00000AA0
19906                 (OFFSET, MASK, VALUE)      (0XFF981554, 0xF80FFFFFU ,0x08000010U)
19907                 RegMask = (LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_341_PARITY_MASK |  0 );
19908
19909                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT
19910                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT
19911                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT
19912                         |  0 ) & RegMask); */
19913                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_341_OFFSET ,0xF80FFFFFU ,0x08000010U);
19914         /*############################################################################################################################ */
19915
19916                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19917                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19918                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19919                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19920                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19921                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19922                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19923                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19924                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19925                 /*Register : APERPERM_350 @ 0XFF981578</p>
19926
19927                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19928                 h.
19929                 PSU_LPD_XPPU_CFG_APERPERM_350_PERMISSION                                        0x2
19930
19931                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19932                 PSU_LPD_XPPU_CFG_APERPERM_350_TRUSTZONE                                         0x1
19933
19934                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19935                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19936                 PSU_LPD_XPPU_CFG_APERPERM_350_PARITY                                            0x0
19937
19938                 Entry 350 of the Aperture Permission List, for 32-byte IPI buffer 094 at BASE_32B + 0x00000BC0
19939                 (OFFSET, MASK, VALUE)      (0XFF981578, 0xF80FFFFFU ,0x08000002U)
19940                 RegMask = (LPD_XPPU_CFG_APERPERM_350_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_350_PARITY_MASK |  0 );
19941
19942                 RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_350_PERMISSION_SHIFT
19943                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_SHIFT
19944                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_350_PARITY_SHIFT
19945                         |  0 ) & RegMask); */
19946                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_350_OFFSET ,0xF80FFFFFU ,0x08000002U);
19947         /*############################################################################################################################ */
19948
19949                 // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
19950                 /*Register : APERPERM_351 @ 0XFF98157C</p>
19951
19952                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19953                 h.
19954                 PSU_LPD_XPPU_CFG_APERPERM_351_PERMISSION                                        0x20
19955
19956                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19957                 PSU_LPD_XPPU_CFG_APERPERM_351_TRUSTZONE                                         0x1
19958
19959                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19960                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19961                 PSU_LPD_XPPU_CFG_APERPERM_351_PARITY                                            0x0
19962
19963                 Entry 351 of the Aperture Permission List, for 32-byte IPI buffer 095 at BASE_32B + 0x00000BE0
19964                 (OFFSET, MASK, VALUE)      (0XFF98157C, 0xF80FFFFFU ,0x08000020U)
19965                 RegMask = (LPD_XPPU_CFG_APERPERM_351_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_351_PARITY_MASK |  0 );
19966
19967                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_351_PERMISSION_SHIFT
19968                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_SHIFT
19969                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_351_PARITY_SHIFT
19970                         |  0 ) & RegMask); */
19971                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_351_OFFSET ,0xF80FFFFFU ,0x08000020U);
19972         /*############################################################################################################################ */
19973
19974                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
19975                 /*Register : APERPERM_352 @ 0XFF981580</p>
19976
19977                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
19978                 h.
19979                 PSU_LPD_XPPU_CFG_APERPERM_352_PERMISSION                                        0x4
19980
19981                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
19982                 PSU_LPD_XPPU_CFG_APERPERM_352_TRUSTZONE                                         0x1
19983
19984                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
19985                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
19986                 PSU_LPD_XPPU_CFG_APERPERM_352_PARITY                                            0x0
19987
19988                 Entry 352 of the Aperture Permission List, for 32-byte IPI buffer 096 at BASE_32B + 0x00000C00
19989                 (OFFSET, MASK, VALUE)      (0XFF981580, 0xF80FFFFFU ,0x08000004U)
19990                 RegMask = (LPD_XPPU_CFG_APERPERM_352_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_352_PARITY_MASK |  0 );
19991
19992                 RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_352_PERMISSION_SHIFT
19993                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_SHIFT
19994                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_352_PARITY_SHIFT
19995                         |  0 ) & RegMask); */
19996                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_352_OFFSET ,0xF80FFFFFU ,0x08000004U);
19997         /*############################################################################################################################ */
19998
19999                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20000                 /*Register : APERPERM_353 @ 0XFF981584</p>
20001
20002                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20003                 h.
20004                 PSU_LPD_XPPU_CFG_APERPERM_353_PERMISSION                                        0x40
20005
20006                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20007                 PSU_LPD_XPPU_CFG_APERPERM_353_TRUSTZONE                                         0x1
20008
20009                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20010                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20011                 PSU_LPD_XPPU_CFG_APERPERM_353_PARITY                                            0x0
20012
20013                 Entry 353 of the Aperture Permission List, for 32-byte IPI buffer 097 at BASE_32B + 0x00000C20
20014                 (OFFSET, MASK, VALUE)      (0XFF981584, 0xF80FFFFFU ,0x08000040U)
20015                 RegMask = (LPD_XPPU_CFG_APERPERM_353_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_353_PARITY_MASK |  0 );
20016
20017                 RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_353_PERMISSION_SHIFT
20018                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_SHIFT
20019                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_353_PARITY_SHIFT
20020                         |  0 ) & RegMask); */
20021                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_353_OFFSET ,0xF80FFFFFU ,0x08000040U);
20022         /*############################################################################################################################ */
20023
20024                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20025                 /*Register : APERPERM_354 @ 0XFF981588</p>
20026
20027                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20028                 h.
20029                 PSU_LPD_XPPU_CFG_APERPERM_354_PERMISSION                                        0x8
20030
20031                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20032                 PSU_LPD_XPPU_CFG_APERPERM_354_TRUSTZONE                                         0x1
20033
20034                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20035                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20036                 PSU_LPD_XPPU_CFG_APERPERM_354_PARITY                                            0x0
20037
20038                 Entry 354 of the Aperture Permission List, for 32-byte IPI buffer 098 at BASE_32B + 0x00000C40
20039                 (OFFSET, MASK, VALUE)      (0XFF981588, 0xF80FFFFFU ,0x08000008U)
20040                 RegMask = (LPD_XPPU_CFG_APERPERM_354_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_354_PARITY_MASK |  0 );
20041
20042                 RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_354_PERMISSION_SHIFT
20043                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_SHIFT
20044                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_354_PARITY_SHIFT
20045                         |  0 ) & RegMask); */
20046                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_354_OFFSET ,0xF80FFFFFU ,0x08000008U);
20047         /*############################################################################################################################ */
20048
20049                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20050                 /*Register : APERPERM_355 @ 0XFF98158C</p>
20051
20052                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20053                 h.
20054                 PSU_LPD_XPPU_CFG_APERPERM_355_PERMISSION                                        0x80
20055
20056                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20057                 PSU_LPD_XPPU_CFG_APERPERM_355_TRUSTZONE                                         0x1
20058
20059                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20060                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20061                 PSU_LPD_XPPU_CFG_APERPERM_355_PARITY                                            0x0
20062
20063                 Entry 355 of the Aperture Permission List, for 32-byte IPI buffer 099 at BASE_32B + 0x00000C60
20064                 (OFFSET, MASK, VALUE)      (0XFF98158C, 0xF80FFFFFU ,0x08000080U)
20065                 RegMask = (LPD_XPPU_CFG_APERPERM_355_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_355_PARITY_MASK |  0 );
20066
20067                 RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_355_PERMISSION_SHIFT
20068                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_SHIFT
20069                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_355_PARITY_SHIFT
20070                         |  0 ) & RegMask); */
20071                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_355_OFFSET ,0xF80FFFFFU ,0x08000080U);
20072         /*############################################################################################################################ */
20073
20074                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20075                 /*Register : APERPERM_356 @ 0XFF981590</p>
20076
20077                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20078                 h.
20079                 PSU_LPD_XPPU_CFG_APERPERM_356_PERMISSION                                        0x1
20080
20081                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20082                 PSU_LPD_XPPU_CFG_APERPERM_356_TRUSTZONE                                         0x1
20083
20084                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20085                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20086                 PSU_LPD_XPPU_CFG_APERPERM_356_PARITY                                            0x0
20087
20088                 Entry 356 of the Aperture Permission List, for 32-byte IPI buffer 100 at BASE_32B + 0x00000C80
20089                 (OFFSET, MASK, VALUE)      (0XFF981590, 0xF80FFFFFU ,0x08000001U)
20090                 RegMask = (LPD_XPPU_CFG_APERPERM_356_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_356_PARITY_MASK |  0 );
20091
20092                 RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_356_PERMISSION_SHIFT
20093                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_SHIFT
20094                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_356_PARITY_SHIFT
20095                         |  0 ) & RegMask); */
20096                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_356_OFFSET ,0xF80FFFFFU ,0x08000001U);
20097         /*############################################################################################################################ */
20098
20099                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20100                 /*Register : APERPERM_357 @ 0XFF981594</p>
20101
20102                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20103                 h.
20104                 PSU_LPD_XPPU_CFG_APERPERM_357_PERMISSION                                        0x10
20105
20106                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20107                 PSU_LPD_XPPU_CFG_APERPERM_357_TRUSTZONE                                         0x1
20108
20109                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20110                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20111                 PSU_LPD_XPPU_CFG_APERPERM_357_PARITY                                            0x0
20112
20113                 Entry 357 of the Aperture Permission List, for 32-byte IPI buffer 101 at BASE_32B + 0x00000CA0
20114                 (OFFSET, MASK, VALUE)      (0XFF981594, 0xF80FFFFFU ,0x08000010U)
20115                 RegMask = (LPD_XPPU_CFG_APERPERM_357_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_357_PARITY_MASK |  0 );
20116
20117                 RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_357_PERMISSION_SHIFT
20118                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_SHIFT
20119                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_357_PARITY_SHIFT
20120                         |  0 ) & RegMask); */
20121                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_357_OFFSET ,0xF80FFFFFU ,0x08000010U);
20122         /*############################################################################################################################ */
20123
20124                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20125                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20126                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20127                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20128                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20129                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20130                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20131                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20132                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20133                 /*Register : APERPERM_366 @ 0XFF9815B8</p>
20134
20135                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20136                 h.
20137                 PSU_LPD_XPPU_CFG_APERPERM_366_PERMISSION                                        0x2
20138
20139                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20140                 PSU_LPD_XPPU_CFG_APERPERM_366_TRUSTZONE                                         0x1
20141
20142                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20143                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20144                 PSU_LPD_XPPU_CFG_APERPERM_366_PARITY                                            0x0
20145
20146                 Entry 366 of the Aperture Permission List, for 32-byte IPI buffer 110 at BASE_32B + 0x00000DC0
20147                 (OFFSET, MASK, VALUE)      (0XFF9815B8, 0xF80FFFFFU ,0x08000002U)
20148                 RegMask = (LPD_XPPU_CFG_APERPERM_366_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_366_PARITY_MASK |  0 );
20149
20150                 RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_366_PERMISSION_SHIFT
20151                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_SHIFT
20152                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_366_PARITY_SHIFT
20153                         |  0 ) & RegMask); */
20154                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_366_OFFSET ,0xF80FFFFFU ,0x08000002U);
20155         /*############################################################################################################################ */
20156
20157                 // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
20158                 /*Register : APERPERM_367 @ 0XFF9815BC</p>
20159
20160                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20161                 h.
20162                 PSU_LPD_XPPU_CFG_APERPERM_367_PERMISSION                                        0x20
20163
20164                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20165                 PSU_LPD_XPPU_CFG_APERPERM_367_TRUSTZONE                                         0x1
20166
20167                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20168                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20169                 PSU_LPD_XPPU_CFG_APERPERM_367_PARITY                                            0x0
20170
20171                 Entry 367 of the Aperture Permission List, for 32-byte IPI buffer 111 at BASE_32B + 0x00000DE0
20172                 (OFFSET, MASK, VALUE)      (0XFF9815BC, 0xF80FFFFFU ,0x08000020U)
20173                 RegMask = (LPD_XPPU_CFG_APERPERM_367_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_367_PARITY_MASK |  0 );
20174
20175                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_367_PERMISSION_SHIFT
20176                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_SHIFT
20177                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_367_PARITY_SHIFT
20178                         |  0 ) & RegMask); */
20179                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_367_OFFSET ,0xF80FFFFFU ,0x08000020U);
20180         /*############################################################################################################################ */
20181
20182                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20183                 /*Register : APERPERM_368 @ 0XFF9815C0</p>
20184
20185                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20186                 h.
20187                 PSU_LPD_XPPU_CFG_APERPERM_368_PERMISSION                                        0x24
20188
20189                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20190                 PSU_LPD_XPPU_CFG_APERPERM_368_TRUSTZONE                                         0x1
20191
20192                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20193                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20194                 PSU_LPD_XPPU_CFG_APERPERM_368_PARITY                                            0x0
20195
20196                 Entry 368 of the Aperture Permission List, for 32-byte IPI buffer 112 at BASE_32B + 0x00000E00
20197                 (OFFSET, MASK, VALUE)      (0XFF9815C0, 0xF80FFFFFU ,0x08000024U)
20198                 RegMask = (LPD_XPPU_CFG_APERPERM_368_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_368_PARITY_MASK |  0 );
20199
20200                 RegVal = ((0x00000024U << LPD_XPPU_CFG_APERPERM_368_PERMISSION_SHIFT
20201                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_SHIFT
20202                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_368_PARITY_SHIFT
20203                         |  0 ) & RegMask); */
20204                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_368_OFFSET ,0xF80FFFFFU ,0x08000024U);
20205         /*############################################################################################################################ */
20206
20207                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20208                 /*Register : APERPERM_369 @ 0XFF9815C4</p>
20209
20210                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20211                 h.
20212                 PSU_LPD_XPPU_CFG_APERPERM_369_PERMISSION                                        0x42
20213
20214                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20215                 PSU_LPD_XPPU_CFG_APERPERM_369_TRUSTZONE                                         0x1
20216
20217                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20218                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20219                 PSU_LPD_XPPU_CFG_APERPERM_369_PARITY                                            0x0
20220
20221                 Entry 369 of the Aperture Permission List, for 32-byte IPI buffer 113 at BASE_32B + 0x00000E20
20222                 (OFFSET, MASK, VALUE)      (0XFF9815C4, 0xF80FFFFFU ,0x08000042U)
20223                 RegMask = (LPD_XPPU_CFG_APERPERM_369_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_369_PARITY_MASK |  0 );
20224
20225                 RegVal = ((0x00000042U << LPD_XPPU_CFG_APERPERM_369_PERMISSION_SHIFT
20226                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_SHIFT
20227                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_369_PARITY_SHIFT
20228                         |  0 ) & RegMask); */
20229                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_369_OFFSET ,0xF80FFFFFU ,0x08000042U);
20230         /*############################################################################################################################ */
20231
20232                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20233                 /*Register : APERPERM_370 @ 0XFF9815C8</p>
20234
20235                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20236                 h.
20237                 PSU_LPD_XPPU_CFG_APERPERM_370_PERMISSION                                        0x28
20238
20239                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20240                 PSU_LPD_XPPU_CFG_APERPERM_370_TRUSTZONE                                         0x1
20241
20242                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20243                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20244                 PSU_LPD_XPPU_CFG_APERPERM_370_PARITY                                            0x0
20245
20246                 Entry 370 of the Aperture Permission List, for 32-byte IPI buffer 114 at BASE_32B + 0x00000E40
20247                 (OFFSET, MASK, VALUE)      (0XFF9815C8, 0xF80FFFFFU ,0x08000028U)
20248                 RegMask = (LPD_XPPU_CFG_APERPERM_370_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_370_PARITY_MASK |  0 );
20249
20250                 RegVal = ((0x00000028U << LPD_XPPU_CFG_APERPERM_370_PERMISSION_SHIFT
20251                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_SHIFT
20252                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_370_PARITY_SHIFT
20253                         |  0 ) & RegMask); */
20254                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_370_OFFSET ,0xF80FFFFFU ,0x08000028U);
20255         /*############################################################################################################################ */
20256
20257                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20258                 /*Register : APERPERM_371 @ 0XFF9815CC</p>
20259
20260                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20261                 h.
20262                 PSU_LPD_XPPU_CFG_APERPERM_371_PERMISSION                                        0x82
20263
20264                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20265                 PSU_LPD_XPPU_CFG_APERPERM_371_TRUSTZONE                                         0x1
20266
20267                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20268                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20269                 PSU_LPD_XPPU_CFG_APERPERM_371_PARITY                                            0x0
20270
20271                 Entry 371 of the Aperture Permission List, for 32-byte IPI buffer 115 at BASE_32B + 0x00000E60
20272                 (OFFSET, MASK, VALUE)      (0XFF9815CC, 0xF80FFFFFU ,0x08000082U)
20273                 RegMask = (LPD_XPPU_CFG_APERPERM_371_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_371_PARITY_MASK |  0 );
20274
20275                 RegVal = ((0x00000082U << LPD_XPPU_CFG_APERPERM_371_PERMISSION_SHIFT
20276                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_SHIFT
20277                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_371_PARITY_SHIFT
20278                         |  0 ) & RegMask); */
20279                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_371_OFFSET ,0xF80FFFFFU ,0x08000082U);
20280         /*############################################################################################################################ */
20281
20282                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20283                 /*Register : APERPERM_372 @ 0XFF9815D0</p>
20284
20285                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20286                 h.
20287                 PSU_LPD_XPPU_CFG_APERPERM_372_PERMISSION                                        0x21
20288
20289                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20290                 PSU_LPD_XPPU_CFG_APERPERM_372_TRUSTZONE                                         0x1
20291
20292                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20293                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20294                 PSU_LPD_XPPU_CFG_APERPERM_372_PARITY                                            0x0
20295
20296                 Entry 372 of the Aperture Permission List, for 32-byte IPI buffer 116 at BASE_32B + 0x00000E80
20297                 (OFFSET, MASK, VALUE)      (0XFF9815D0, 0xF80FFFFFU ,0x08000021U)
20298                 RegMask = (LPD_XPPU_CFG_APERPERM_372_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_372_PARITY_MASK |  0 );
20299
20300                 RegVal = ((0x00000021U << LPD_XPPU_CFG_APERPERM_372_PERMISSION_SHIFT
20301                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_SHIFT
20302                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_372_PARITY_SHIFT
20303                         |  0 ) & RegMask); */
20304                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_372_OFFSET ,0xF80FFFFFU ,0x08000021U);
20305         /*############################################################################################################################ */
20306
20307                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20308                 /*Register : APERPERM_373 @ 0XFF9815D4</p>
20309
20310                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20311                 h.
20312                 PSU_LPD_XPPU_CFG_APERPERM_373_PERMISSION                                        0x12
20313
20314                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20315                 PSU_LPD_XPPU_CFG_APERPERM_373_TRUSTZONE                                         0x1
20316
20317                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20318                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20319                 PSU_LPD_XPPU_CFG_APERPERM_373_PARITY                                            0x0
20320
20321                 Entry 373 of the Aperture Permission List, for 32-byte IPI buffer 117 at BASE_32B + 0x00000EA0
20322                 (OFFSET, MASK, VALUE)      (0XFF9815D4, 0xF80FFFFFU ,0x08000012U)
20323                 RegMask = (LPD_XPPU_CFG_APERPERM_373_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_373_PARITY_MASK |  0 );
20324
20325                 RegVal = ((0x00000012U << LPD_XPPU_CFG_APERPERM_373_PERMISSION_SHIFT
20326                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_SHIFT
20327                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_373_PARITY_SHIFT
20328                         |  0 ) & RegMask); */
20329                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_373_OFFSET ,0xF80FFFFFU ,0x08000012U);
20330         /*############################################################################################################################ */
20331
20332                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20333                 /*Register : APERPERM_374 @ 0XFF9815D8</p>
20334
20335                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20336                 h.
20337                 PSU_LPD_XPPU_CFG_APERPERM_374_PERMISSION                                        0x20
20338
20339                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20340                 PSU_LPD_XPPU_CFG_APERPERM_374_TRUSTZONE                                         0x1
20341
20342                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20343                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20344                 PSU_LPD_XPPU_CFG_APERPERM_374_PARITY                                            0x0
20345
20346                 Entry 374 of the Aperture Permission List, for 32-byte IPI buffer 118 at BASE_32B + 0x00000EC0
20347                 (OFFSET, MASK, VALUE)      (0XFF9815D8, 0xF80FFFFFU ,0x08000020U)
20348                 RegMask = (LPD_XPPU_CFG_APERPERM_374_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_374_PARITY_MASK |  0 );
20349
20350                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_374_PERMISSION_SHIFT
20351                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_SHIFT
20352                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_374_PARITY_SHIFT
20353                         |  0 ) & RegMask); */
20354                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_374_OFFSET ,0xF80FFFFFU ,0x08000020U);
20355         /*############################################################################################################################ */
20356
20357                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20358                 /*Register : APERPERM_375 @ 0XFF9815DC</p>
20359
20360                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20361                 h.
20362                 PSU_LPD_XPPU_CFG_APERPERM_375_PERMISSION                                        0x2
20363
20364                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20365                 PSU_LPD_XPPU_CFG_APERPERM_375_TRUSTZONE                                         0x1
20366
20367                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20368                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20369                 PSU_LPD_XPPU_CFG_APERPERM_375_PARITY                                            0x0
20370
20371                 Entry 375 of the Aperture Permission List, for 32-byte IPI buffer 119 at BASE_32B + 0x00000EE0
20372                 (OFFSET, MASK, VALUE)      (0XFF9815DC, 0xF80FFFFFU ,0x08000002U)
20373                 RegMask = (LPD_XPPU_CFG_APERPERM_375_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_375_PARITY_MASK |  0 );
20374
20375                 RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_375_PERMISSION_SHIFT
20376                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_SHIFT
20377                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_375_PARITY_SHIFT
20378                         |  0 ) & RegMask); */
20379                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_375_OFFSET ,0xF80FFFFFU ,0x08000002U);
20380         /*############################################################################################################################ */
20381
20382                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20383                 /*Register : APERPERM_376 @ 0XFF9815E0</p>
20384
20385                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20386                 h.
20387                 PSU_LPD_XPPU_CFG_APERPERM_376_PERMISSION                                        0x20
20388
20389                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20390                 PSU_LPD_XPPU_CFG_APERPERM_376_TRUSTZONE                                         0x1
20391
20392                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20393                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20394                 PSU_LPD_XPPU_CFG_APERPERM_376_PARITY                                            0x0
20395
20396                 Entry 376 of the Aperture Permission List, for 32-byte IPI buffer 120 at BASE_32B + 0x00000F00
20397                 (OFFSET, MASK, VALUE)      (0XFF9815E0, 0xF80FFFFFU ,0x08000020U)
20398                 RegMask = (LPD_XPPU_CFG_APERPERM_376_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_376_PARITY_MASK |  0 );
20399
20400                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_376_PERMISSION_SHIFT
20401                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_SHIFT
20402                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_376_PARITY_SHIFT
20403                         |  0 ) & RegMask); */
20404                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_376_OFFSET ,0xF80FFFFFU ,0x08000020U);
20405         /*############################################################################################################################ */
20406
20407                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20408                 /*Register : APERPERM_377 @ 0XFF9815E4</p>
20409
20410                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20411                 h.
20412                 PSU_LPD_XPPU_CFG_APERPERM_377_PERMISSION                                        0x2
20413
20414                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20415                 PSU_LPD_XPPU_CFG_APERPERM_377_TRUSTZONE                                         0x1
20416
20417                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20418                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20419                 PSU_LPD_XPPU_CFG_APERPERM_377_PARITY                                            0x0
20420
20421                 Entry 377 of the Aperture Permission List, for 32-byte IPI buffer 121 at BASE_32B + 0x00000F20
20422                 (OFFSET, MASK, VALUE)      (0XFF9815E4, 0xF80FFFFFU ,0x08000002U)
20423                 RegMask = (LPD_XPPU_CFG_APERPERM_377_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_377_PARITY_MASK |  0 );
20424
20425                 RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_377_PERMISSION_SHIFT
20426                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_SHIFT
20427                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_377_PARITY_SHIFT
20428                         |  0 ) & RegMask); */
20429                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_377_OFFSET ,0xF80FFFFFU ,0x08000002U);
20430         /*############################################################################################################################ */
20431
20432                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20433                 /*Register : APERPERM_378 @ 0XFF9815E8</p>
20434
20435                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20436                 h.
20437                 PSU_LPD_XPPU_CFG_APERPERM_378_PERMISSION                                        0x20
20438
20439                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20440                 PSU_LPD_XPPU_CFG_APERPERM_378_TRUSTZONE                                         0x1
20441
20442                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20443                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20444                 PSU_LPD_XPPU_CFG_APERPERM_378_PARITY                                            0x0
20445
20446                 Entry 378 of the Aperture Permission List, for 32-byte IPI buffer 122 at BASE_32B + 0x00000F40
20447                 (OFFSET, MASK, VALUE)      (0XFF9815E8, 0xF80FFFFFU ,0x08000020U)
20448                 RegMask = (LPD_XPPU_CFG_APERPERM_378_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_378_PARITY_MASK |  0 );
20449
20450                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_378_PERMISSION_SHIFT
20451                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_SHIFT
20452                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_378_PARITY_SHIFT
20453                         |  0 ) & RegMask); */
20454                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_378_OFFSET ,0xF80FFFFFU ,0x08000020U);
20455         /*############################################################################################################################ */
20456
20457                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20458                 /*Register : APERPERM_379 @ 0XFF9815EC</p>
20459
20460                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20461                 h.
20462                 PSU_LPD_XPPU_CFG_APERPERM_379_PERMISSION                                        0x2
20463
20464                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20465                 PSU_LPD_XPPU_CFG_APERPERM_379_TRUSTZONE                                         0x1
20466
20467                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20468                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20469                 PSU_LPD_XPPU_CFG_APERPERM_379_PARITY                                            0x0
20470
20471                 Entry 379 of the Aperture Permission List, for 32-byte IPI buffer 123 at BASE_32B + 0x00000F60
20472                 (OFFSET, MASK, VALUE)      (0XFF9815EC, 0xF80FFFFFU ,0x08000002U)
20473                 RegMask = (LPD_XPPU_CFG_APERPERM_379_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_379_PARITY_MASK |  0 );
20474
20475                 RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_379_PERMISSION_SHIFT
20476                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_SHIFT
20477                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_379_PARITY_SHIFT
20478                         |  0 ) & RegMask); */
20479                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_379_OFFSET ,0xF80FFFFFU ,0x08000002U);
20480         /*############################################################################################################################ */
20481
20482                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20483                 /*Register : APERPERM_380 @ 0XFF9815F0</p>
20484
20485                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20486                 h.
20487                 PSU_LPD_XPPU_CFG_APERPERM_380_PERMISSION                                        0x20
20488
20489                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20490                 PSU_LPD_XPPU_CFG_APERPERM_380_TRUSTZONE                                         0x1
20491
20492                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20493                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20494                 PSU_LPD_XPPU_CFG_APERPERM_380_PARITY                                            0x0
20495
20496                 Entry 380 of the Aperture Permission List, for 32-byte IPI buffer 124 at BASE_32B + 0x00000F80
20497                 (OFFSET, MASK, VALUE)      (0XFF9815F0, 0xF80FFFFFU ,0x08000020U)
20498                 RegMask = (LPD_XPPU_CFG_APERPERM_380_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_380_PARITY_MASK |  0 );
20499
20500                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_380_PERMISSION_SHIFT
20501                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_SHIFT
20502                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_380_PARITY_SHIFT
20503                         |  0 ) & RegMask); */
20504                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_380_OFFSET ,0xF80FFFFFU ,0x08000020U);
20505         /*############################################################################################################################ */
20506
20507                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20508                 /*Register : APERPERM_381 @ 0XFF9815F4</p>
20509
20510                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20511                 h.
20512                 PSU_LPD_XPPU_CFG_APERPERM_381_PERMISSION                                        0x2
20513
20514                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20515                 PSU_LPD_XPPU_CFG_APERPERM_381_TRUSTZONE                                         0x1
20516
20517                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20518                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20519                 PSU_LPD_XPPU_CFG_APERPERM_381_PARITY                                            0x0
20520
20521                 Entry 381 of the Aperture Permission List, for 32-byte IPI buffer 125 at BASE_32B + 0x00000FA0
20522                 (OFFSET, MASK, VALUE)      (0XFF9815F4, 0xF80FFFFFU ,0x08000002U)
20523                 RegMask = (LPD_XPPU_CFG_APERPERM_381_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_381_PARITY_MASK |  0 );
20524
20525                 RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_381_PERMISSION_SHIFT
20526                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_SHIFT
20527                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_381_PARITY_SHIFT
20528                         |  0 ) & RegMask); */
20529                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_381_OFFSET ,0xF80FFFFFU ,0x08000002U);
20530         /*############################################################################################################################ */
20531
20532                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20533                 /*Register : APERPERM_382 @ 0XFF9815F8</p>
20534
20535                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20536                 h.
20537                 PSU_LPD_XPPU_CFG_APERPERM_382_PERMISSION                                        0x20
20538
20539                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20540                 PSU_LPD_XPPU_CFG_APERPERM_382_TRUSTZONE                                         0x1
20541
20542                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20543                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20544                 PSU_LPD_XPPU_CFG_APERPERM_382_PARITY                                            0x0
20545
20546                 Entry 382 of the Aperture Permission List, for 32-byte IPI buffer 126 at BASE_32B + 0x00000FC0
20547                 (OFFSET, MASK, VALUE)      (0XFF9815F8, 0xF80FFFFFU ,0x08000020U)
20548                 RegMask = (LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_382_PARITY_MASK |  0 );
20549
20550                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT
20551                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT
20552                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT
20553                         |  0 ) & RegMask); */
20554                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_382_OFFSET ,0xF80FFFFFU ,0x08000020U);
20555         /*############################################################################################################################ */
20556
20557                 // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
20558                 /*Register : APERPERM_383 @ 0XFF9815FC</p>
20559
20560                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20561                 h.
20562                 PSU_LPD_XPPU_CFG_APERPERM_383_PERMISSION                                        0x20
20563
20564                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20565                 PSU_LPD_XPPU_CFG_APERPERM_383_TRUSTZONE                                         0x1
20566
20567                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20568                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20569                 PSU_LPD_XPPU_CFG_APERPERM_383_PARITY                                            0x0
20570
20571                 Entry 383 of the Aperture Permission List, for 32-byte IPI buffer 127 at BASE_32B + 0x00000FE0
20572                 (OFFSET, MASK, VALUE)      (0XFF9815FC, 0xF80FFFFFU ,0x08000020U)
20573                 RegMask = (LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_383_PARITY_MASK |  0 );
20574
20575                 RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT
20576                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT
20577                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT
20578                         |  0 ) & RegMask); */
20579                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_383_OFFSET ,0xF80FFFFFU ,0x08000020U);
20580         /*############################################################################################################################ */
20581
20582                 // : APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF
20583                 // : APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF
20584                 // : APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFFFF
20585                 // : APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFFFF
20586                 // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
20587                 // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
20588                 // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
20589                 // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
20590                 // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
20591                 // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
20592                 // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
20593                 // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
20594                 // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
20595                 // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
20596                 // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
20597                 // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
20598                 // : APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS: DFFFFFFF
20599                 // : XPPU CONTROL
20600                 /*Register : err_ctrl @ 0XFF9CFFEC</p>
20601
20602                 Whether an APB access to the "hole" region and to an unimplemented register space causes PSLVERR
20603                 PSU_LPD_XPPU_SINK_ERR_CTRL_PSLVERR                                              1
20604
20605                 Error control register
20606                 (OFFSET, MASK, VALUE)      (0XFF9CFFEC, 0x00000001U ,0x00000001U)
20607                 RegMask = (LPD_XPPU_SINK_ERR_CTRL_PSLVERR_MASK |  0 );
20608
20609                 RegVal = ((0x00000001U << LPD_XPPU_SINK_ERR_CTRL_PSLVERR_SHIFT
20610                         |  0 ) & RegMask); */
20611                 PSU_Mask_Write (LPD_XPPU_SINK_ERR_CTRL_OFFSET ,0x00000001U ,0x00000001U);
20612         /*############################################################################################################################ */
20613
20614                 /*Register : CTRL @ 0XFF980000</p>
20615
20616                 0=Bypass XPPU (transparent) 1=Enable XPPU permission checking
20617                 PSU_LPD_XPPU_CFG_CTRL_ENABLE                                                    1
20618
20619                 XPPU Control Register
20620                 (OFFSET, MASK, VALUE)      (0XFF980000, 0x00000001U ,0x00000001U)
20621                 RegMask = (LPD_XPPU_CFG_CTRL_ENABLE_MASK |  0 );
20622
20623                 RegVal = ((0x00000001U << LPD_XPPU_CFG_CTRL_ENABLE_SHIFT
20624                         |  0 ) & RegMask); */
20625                 PSU_Mask_Write (LPD_XPPU_CFG_CTRL_OFFSET ,0x00000001U ,0x00000001U);
20626         /*############################################################################################################################ */
20627
20628                 // : XPPU INTERRUPT ENABLE
20629                 /*Register : IEN @ 0XFF980018</p>
20630
20631                 See Interuppt Status Register for details
20632                 PSU_LPD_XPPU_CFG_IEN_APER_PARITY                                                0X1
20633
20634                 See Interuppt Status Register for details
20635                 PSU_LPD_XPPU_CFG_IEN_APER_TZ                                                    0X1
20636
20637                 See Interuppt Status Register for details
20638                 PSU_LPD_XPPU_CFG_IEN_APER_PERM                                                  0X1
20639
20640                 See Interuppt Status Register for details
20641                 PSU_LPD_XPPU_CFG_IEN_MID_PARITY                                                 0X1
20642
20643                 See Interuppt Status Register for details
20644                 PSU_LPD_XPPU_CFG_IEN_MID_RO                                                     0X1
20645
20646                 See Interuppt Status Register for details
20647                 PSU_LPD_XPPU_CFG_IEN_MID_MISS                                                   0X1
20648
20649                 See Interuppt Status Register for details
20650                 PSU_LPD_XPPU_CFG_IEN_INV_APB                                                    0X1
20651
20652                 Interrupt Enable Register
20653                 (OFFSET, MASK, VALUE)      (0XFF980018, 0x000000EFU ,0x000000EFU)
20654                 RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK |  0 );
20655
20656                 RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
20657                         | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
20658                         | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
20659                         | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
20660                         | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT
20661                         | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
20662                         | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT
20663                         |  0 ) & RegMask); */
20664                 PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU);
20665         /*############################################################################################################################ */
20666
20667
20668   return 1;
20669 }
20670 unsigned long psu_ddr_xmpu0_data() {
20671                 // : DDR XMPU0
20672
20673   return 1;
20674 }
20675 unsigned long psu_ddr_xmpu1_data() {
20676                 // : DDR XMPU1
20677
20678   return 1;
20679 }
20680 unsigned long psu_ddr_xmpu2_data() {
20681                 // : DDR XMPU2
20682
20683   return 1;
20684 }
20685 unsigned long psu_ddr_xmpu3_data() {
20686                 // : DDR XMPU3
20687
20688   return 1;
20689 }
20690 unsigned long psu_ddr_xmpu4_data() {
20691                 // : DDR XMPU4
20692
20693   return 1;
20694 }
20695 unsigned long psu_ddr_xmpu5_data() {
20696                 // : DDR XMPU5
20697
20698   return 1;
20699 }
20700 unsigned long psu_ocm_xmpu_data() {
20701                 // : OCM XMPU
20702
20703   return 1;
20704 }
20705 unsigned long psu_fpd_xmpu_data() {
20706                 // : FPD XMPU
20707
20708   return 1;
20709 }
20710 unsigned long psu_protection_lock_data() {
20711                 // : LOCKING PROTECTION MODULE
20712                 // : XPPU LOCK
20713                 // : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
20714                 /*Register : APERPERM_152 @ 0XFF981260</p>
20715
20716                 This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
20717                 h.
20718                 PSU_LPD_XPPU_CFG_APERPERM_152_PERMISSION                                        0x0
20719
20720                 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
20721                 PSU_LPD_XPPU_CFG_APERPERM_152_TRUSTZONE                                         0x1
20722
20723                 SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
20724                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
20725                 PSU_LPD_XPPU_CFG_APERPERM_152_PARITY                                            0x0
20726
20727                 Entry 152 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00980000
20728                 (OFFSET, MASK, VALUE)      (0XFF981260, 0xF80FFFFFU ,0x08000000U)
20729                 RegMask = (LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_152_PARITY_MASK |  0 );
20730
20731                 RegVal = ((0x00000000U << LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT
20732                         | 0x00000001U << LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT
20733                         | 0x00000000U << LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT
20734                         |  0 ) & RegMask); */
20735                 PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_152_OFFSET ,0xF80FFFFFU ,0x08000000U);
20736         /*############################################################################################################################ */
20737
20738                 // : XMPU LOCK
20739
20740   return 1;
20741 }
20742 unsigned long psu_apply_master_tz() {
20743                 // : RPU
20744                 // : DP TZ
20745                 // : SATA TZ
20746                 // : PCIE TZ
20747                 // : USB TZ
20748                 // : SD TZ
20749                 // : GEM TZ
20750                 // : QSPI TZ
20751                 // : NAND TZ
20752
20753   return 1;
20754 }
20755 unsigned long psu_serdes_init_data() {
20756                 // : SERDES INITIALIZATION
20757                 // : GT REFERENCE CLOCK SOURCE SELECTION
20758                 /*Register : PLL_REF_SEL0 @ 0XFD410000</p>
20759
20760                 PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
20761                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
20762                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
20763                 PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0                                              0x9
20764
20765                 PLL0 Reference Selection Register
20766                 (OFFSET, MASK, VALUE)      (0XFD410000, 0x0000001FU ,0x00000009U)
20767                 RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK |  0 );
20768
20769                 RegVal = ((0x00000009U << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
20770                         |  0 ) & RegMask); */
20771                 PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x00000009U);
20772         /*############################################################################################################################ */
20773
20774                 /*Register : PLL_REF_SEL1 @ 0XFD410004</p>
20775
20776                 PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
20777                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
20778                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
20779                 PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1                                              0x9
20780
20781                 PLL1 Reference Selection Register
20782                 (OFFSET, MASK, VALUE)      (0XFD410004, 0x0000001FU ,0x00000009U)
20783                 RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK |  0 );
20784
20785                 RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
20786                         |  0 ) & RegMask); */
20787                 PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U);
20788         /*############################################################################################################################ */
20789
20790                 /*Register : PLL_REF_SEL2 @ 0XFD410008</p>
20791
20792                 PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
20793                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
20794                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
20795                 PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2                                              0x8
20796
20797                 PLL2 Reference Selection Register
20798                 (OFFSET, MASK, VALUE)      (0XFD410008, 0x0000001FU ,0x00000008U)
20799                 RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK |  0 );
20800
20801                 RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
20802                         |  0 ) & RegMask); */
20803                 PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U);
20804         /*############################################################################################################################ */
20805
20806                 /*Register : PLL_REF_SEL3 @ 0XFD41000C</p>
20807
20808                 PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
20809                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
20810                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
20811                 PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3                                              0xF
20812
20813                 PLL3 Reference Selection Register
20814                 (OFFSET, MASK, VALUE)      (0XFD41000C, 0x0000001FU ,0x0000000FU)
20815                 RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK |  0 );
20816
20817                 RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
20818                         |  0 ) & RegMask); */
20819                 PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU);
20820         /*############################################################################################################################ */
20821
20822                 // : GT REFERENCE CLOCK FREQUENCY SELECTION
20823                 /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860</p>
20824
20825                 Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
20826                 PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL                                 0x0
20827
20828                 Bit 3 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
20829                 PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3                                   0x1
20830
20831                 Lane0 Ref Clock Selection Register
20832                 (OFFSET, MASK, VALUE)      (0XFD402860, 0x00000088U ,0x00000008U)
20833                 RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK |  0 );
20834
20835                 RegVal = ((0x00000000U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
20836                         | 0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT
20837                         |  0 ) & RegMask); */
20838                 PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
20839         /*############################################################################################################################ */
20840
20841                 /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864</p>
20842
20843                 Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
20844                 PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL                                 0x0
20845
20846                 Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
20847                 PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3                                   0x1
20848
20849                 Lane1 Ref Clock Selection Register
20850                 (OFFSET, MASK, VALUE)      (0XFD402864, 0x00000088U ,0x00000008U)
20851                 RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK |  0 );
20852
20853                 RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
20854                         | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
20855                         |  0 ) & RegMask); */
20856                 PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
20857         /*############################################################################################################################ */
20858
20859                 /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868</p>
20860
20861                 Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
20862                 PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL                                 0x1
20863
20864                 Lane2 Ref Clock Selection Register
20865                 (OFFSET, MASK, VALUE)      (0XFD402868, 0x00000080U ,0x00000080U)
20866                 RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK |  0 );
20867
20868                 RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
20869                         |  0 ) & RegMask); */
20870                 PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
20871         /*############################################################################################################################ */
20872
20873                 /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C</p>
20874
20875                 Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
20876                 PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL                                 0x0
20877
20878                 Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
20879                 PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1                                   0x1
20880
20881                 Lane3 Ref Clock Selection Register
20882                 (OFFSET, MASK, VALUE)      (0XFD40286C, 0x00000082U ,0x00000002U)
20883                 RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK |  0 );
20884
20885                 RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
20886                         | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
20887                         |  0 ) & RegMask); */
20888                 PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U);
20889         /*############################################################################################################################ */
20890
20891                 // : ENABLE SPREAD SPECTRUM
20892                 /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094</p>
20893
20894                 Enable/Disable coarse code satureation limiting logic
20895                 PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION                         0x1
20896
20897                 Test mode register 37
20898                 (OFFSET, MASK, VALUE)      (0XFD40A094, 0x00000010U ,0x00000010U)
20899                 RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK |  0 );
20900
20901                 RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
20902                         |  0 ) & RegMask); */
20903                 PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U);
20904         /*############################################################################################################################ */
20905
20906                 /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368</p>
20907
20908                 Spread Spectrum No of Steps [7:0]
20909                 PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x38
20910
20911                 Spread Spectrum No of Steps bits 7:0
20912                 (OFFSET, MASK, VALUE)      (0XFD40A368, 0x000000FFU ,0x00000038U)
20913                 RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
20914
20915                 RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
20916                         |  0 ) & RegMask); */
20917                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U);
20918         /*############################################################################################################################ */
20919
20920                 /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C</p>
20921
20922                 Spread Spectrum No of Steps [10:8]
20923                 PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x03
20924
20925                 Spread Spectrum No of Steps bits 10:8
20926                 (OFFSET, MASK, VALUE)      (0XFD40A36C, 0x00000007U ,0x00000003U)
20927                 RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
20928
20929                 RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
20930                         |  0 ) & RegMask); */
20931                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
20932         /*############################################################################################################################ */
20933
20934                 /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368</p>
20935
20936                 Spread Spectrum No of Steps [7:0]
20937                 PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0xE0
20938
20939                 Spread Spectrum No of Steps bits 7:0
20940                 (OFFSET, MASK, VALUE)      (0XFD40E368, 0x000000FFU ,0x000000E0U)
20941                 RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
20942
20943                 RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
20944                         |  0 ) & RegMask); */
20945                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U);
20946         /*############################################################################################################################ */
20947
20948                 /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C</p>
20949
20950                 Spread Spectrum No of Steps [10:8]
20951                 PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x3
20952
20953                 Spread Spectrum No of Steps bits 10:8
20954                 (OFFSET, MASK, VALUE)      (0XFD40E36C, 0x00000007U ,0x00000003U)
20955                 RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
20956
20957                 RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
20958                         |  0 ) & RegMask); */
20959                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
20960         /*############################################################################################################################ */
20961
20962                 /*Register : L0_PLL_SS_STEPS_0_LSB @ 0XFD402368</p>
20963
20964                 Spread Spectrum No of Steps [7:0]
20965                 PSU_SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x58
20966
20967                 Spread Spectrum No of Steps bits 7:0
20968                 (OFFSET, MASK, VALUE)      (0XFD402368, 0x000000FFU ,0x00000058U)
20969                 RegMask = (SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
20970
20971                 RegVal = ((0x00000058U << SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
20972                         |  0 ) & RegMask); */
20973                 PSU_Mask_Write (SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U);
20974         /*############################################################################################################################ */
20975
20976                 /*Register : L0_PLL_SS_STEPS_1_MSB @ 0XFD40236C</p>
20977
20978                 Spread Spectrum No of Steps [10:8]
20979                 PSU_SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x3
20980
20981                 Spread Spectrum No of Steps bits 10:8
20982                 (OFFSET, MASK, VALUE)      (0XFD40236C, 0x00000007U ,0x00000003U)
20983                 RegMask = (SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
20984
20985                 RegVal = ((0x00000003U << SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
20986                         |  0 ) & RegMask); */
20987                 PSU_Mask_Write (SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
20988         /*############################################################################################################################ */
20989
20990                 /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368</p>
20991
20992                 Spread Spectrum No of Steps [7:0]
20993                 PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x58
20994
20995                 Spread Spectrum No of Steps bits 7:0
20996                 (OFFSET, MASK, VALUE)      (0XFD406368, 0x000000FFU ,0x00000058U)
20997                 RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
20998
20999                 RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
21000                         |  0 ) & RegMask); */
21001                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U);
21002         /*############################################################################################################################ */
21003
21004                 /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C</p>
21005
21006                 Spread Spectrum No of Steps [10:8]
21007                 PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x3
21008
21009                 Spread Spectrum No of Steps bits 10:8
21010                 (OFFSET, MASK, VALUE)      (0XFD40636C, 0x00000007U ,0x00000003U)
21011                 RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
21012
21013                 RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
21014                         |  0 ) & RegMask); */
21015                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
21016         /*############################################################################################################################ */
21017
21018                 /*Register : L0_PLL_SS_STEP_SIZE_0_LSB @ 0XFD402370</p>
21019
21020                 Step Size for Spread Spectrum [7:0]
21021                 PSU_SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x7C
21022
21023                 Step Size for Spread Spectrum LSB
21024                 (OFFSET, MASK, VALUE)      (0XFD402370, 0x000000FFU ,0x0000007CU)
21025                 RegMask = (SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
21026
21027                 RegVal = ((0x0000007CU << SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
21028                         |  0 ) & RegMask); */
21029                 PSU_Mask_Write (SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU);
21030         /*############################################################################################################################ */
21031
21032                 /*Register : L0_PLL_SS_STEP_SIZE_1 @ 0XFD402374</p>
21033
21034                 Step Size for Spread Spectrum [15:8]
21035                 PSU_SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x33
21036
21037                 Step Size for Spread Spectrum 1
21038                 (OFFSET, MASK, VALUE)      (0XFD402374, 0x000000FFU ,0x00000033U)
21039                 RegMask = (SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
21040
21041                 RegVal = ((0x00000033U << SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
21042                         |  0 ) & RegMask); */
21043                 PSU_Mask_Write (SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U);
21044         /*############################################################################################################################ */
21045
21046                 /*Register : L0_PLL_SS_STEP_SIZE_2 @ 0XFD402378</p>
21047
21048                 Step Size for Spread Spectrum [23:16]
21049                 PSU_SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
21050
21051                 Step Size for Spread Spectrum 2
21052                 (OFFSET, MASK, VALUE)      (0XFD402378, 0x000000FFU ,0x00000002U)
21053                 RegMask = (SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
21054
21055                 RegVal = ((0x00000002U << SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
21056                         |  0 ) & RegMask); */
21057                 PSU_Mask_Write (SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
21058         /*############################################################################################################################ */
21059
21060                 /*Register : L0_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40237C</p>
21061
21062                 Step Size for Spread Spectrum [25:24]
21063                 PSU_SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
21064
21065                 Enable/Disable test mode force on SS step size
21066                 PSU_SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
21067
21068                 Enable/Disable test mode force on SS no of steps
21069                 PSU_SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
21070
21071                 Enable force on enable Spread Spectrum
21072                 (OFFSET, MASK, VALUE)      (0XFD40237C, 0x00000033U ,0x00000030U)
21073                 RegMask = (SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
21074
21075                 RegVal = ((0x00000000U << SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
21076                         | 0x00000001U << SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
21077                         | 0x00000001U << SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
21078                         |  0 ) & RegMask); */
21079                 PSU_Mask_Write (SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
21080         /*############################################################################################################################ */
21081
21082                 /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370</p>
21083
21084                 Step Size for Spread Spectrum [7:0]
21085                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x7C
21086
21087                 Step Size for Spread Spectrum LSB
21088                 (OFFSET, MASK, VALUE)      (0XFD406370, 0x000000FFU ,0x0000007CU)
21089                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
21090
21091                 RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
21092                         |  0 ) & RegMask); */
21093                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU);
21094         /*############################################################################################################################ */
21095
21096                 /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374</p>
21097
21098                 Step Size for Spread Spectrum [15:8]
21099                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x33
21100
21101                 Step Size for Spread Spectrum 1
21102                 (OFFSET, MASK, VALUE)      (0XFD406374, 0x000000FFU ,0x00000033U)
21103                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
21104
21105                 RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
21106                         |  0 ) & RegMask); */
21107                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U);
21108         /*############################################################################################################################ */
21109
21110                 /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378</p>
21111
21112                 Step Size for Spread Spectrum [23:16]
21113                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
21114
21115                 Step Size for Spread Spectrum 2
21116                 (OFFSET, MASK, VALUE)      (0XFD406378, 0x000000FFU ,0x00000002U)
21117                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
21118
21119                 RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
21120                         |  0 ) & RegMask); */
21121                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
21122         /*############################################################################################################################ */
21123
21124                 /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C</p>
21125
21126                 Step Size for Spread Spectrum [25:24]
21127                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
21128
21129                 Enable/Disable test mode force on SS step size
21130                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
21131
21132                 Enable/Disable test mode force on SS no of steps
21133                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
21134
21135                 Enable force on enable Spread Spectrum
21136                 (OFFSET, MASK, VALUE)      (0XFD40637C, 0x00000033U ,0x00000030U)
21137                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
21138
21139                 RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
21140                         | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
21141                         | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
21142                         |  0 ) & RegMask); */
21143                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
21144         /*############################################################################################################################ */
21145
21146                 /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370</p>
21147
21148                 Step Size for Spread Spectrum [7:0]
21149                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0xF4
21150
21151                 Step Size for Spread Spectrum LSB
21152                 (OFFSET, MASK, VALUE)      (0XFD40A370, 0x000000FFU ,0x000000F4U)
21153                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
21154
21155                 RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
21156                         |  0 ) & RegMask); */
21157                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U);
21158         /*############################################################################################################################ */
21159
21160                 /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374</p>
21161
21162                 Step Size for Spread Spectrum [15:8]
21163                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x31
21164
21165                 Step Size for Spread Spectrum 1
21166                 (OFFSET, MASK, VALUE)      (0XFD40A374, 0x000000FFU ,0x00000031U)
21167                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
21168
21169                 RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
21170                         |  0 ) & RegMask); */
21171                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U);
21172         /*############################################################################################################################ */
21173
21174                 /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378</p>
21175
21176                 Step Size for Spread Spectrum [23:16]
21177                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
21178
21179                 Step Size for Spread Spectrum 2
21180                 (OFFSET, MASK, VALUE)      (0XFD40A378, 0x000000FFU ,0x00000002U)
21181                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
21182
21183                 RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
21184                         |  0 ) & RegMask); */
21185                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
21186         /*############################################################################################################################ */
21187
21188                 /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C</p>
21189
21190                 Step Size for Spread Spectrum [25:24]
21191                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
21192
21193                 Enable/Disable test mode force on SS step size
21194                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
21195
21196                 Enable/Disable test mode force on SS no of steps
21197                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
21198
21199                 Enable force on enable Spread Spectrum
21200                 (OFFSET, MASK, VALUE)      (0XFD40A37C, 0x00000033U ,0x00000030U)
21201                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
21202
21203                 RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
21204                         | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
21205                         | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
21206                         |  0 ) & RegMask); */
21207                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
21208         /*############################################################################################################################ */
21209
21210                 /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370</p>
21211
21212                 Step Size for Spread Spectrum [7:0]
21213                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0xC9
21214
21215                 Step Size for Spread Spectrum LSB
21216                 (OFFSET, MASK, VALUE)      (0XFD40E370, 0x000000FFU ,0x000000C9U)
21217                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
21218
21219                 RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
21220                         |  0 ) & RegMask); */
21221                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U);
21222         /*############################################################################################################################ */
21223
21224                 /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374</p>
21225
21226                 Step Size for Spread Spectrum [15:8]
21227                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0xD2
21228
21229                 Step Size for Spread Spectrum 1
21230                 (OFFSET, MASK, VALUE)      (0XFD40E374, 0x000000FFU ,0x000000D2U)
21231                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
21232
21233                 RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
21234                         |  0 ) & RegMask); */
21235                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U);
21236         /*############################################################################################################################ */
21237
21238                 /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378</p>
21239
21240                 Step Size for Spread Spectrum [23:16]
21241                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x1
21242
21243                 Step Size for Spread Spectrum 2
21244                 (OFFSET, MASK, VALUE)      (0XFD40E378, 0x000000FFU ,0x00000001U)
21245                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
21246
21247                 RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
21248                         |  0 ) & RegMask); */
21249                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U);
21250         /*############################################################################################################################ */
21251
21252                 /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C</p>
21253
21254                 Step Size for Spread Spectrum [25:24]
21255                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
21256
21257                 Enable/Disable test mode force on SS step size
21258                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
21259
21260                 Enable/Disable test mode force on SS no of steps
21261                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
21262
21263                 Enable test mode forcing on enable Spread Spectrum
21264                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS                             0x1
21265
21266                 Enable force on enable Spread Spectrum
21267                 (OFFSET, MASK, VALUE)      (0XFD40E37C, 0x000000B3U ,0x000000B0U)
21268                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK |  0 );
21269
21270                 RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
21271                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
21272                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
21273                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
21274                         |  0 ) & RegMask); */
21275                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U);
21276         /*############################################################################################################################ */
21277
21278                 /*Register : L2_TM_DIG_6 @ 0XFD40906C</p>
21279
21280                 Bypass Descrambler
21281                 PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM                                           0x1
21282
21283                 Enable Bypass for <1> TM_DIG_CTRL_6
21284                 PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
21285
21286                 Data path test modes in decoder and descram
21287                 (OFFSET, MASK, VALUE)      (0XFD40906C, 0x00000003U ,0x00000003U)
21288                 RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
21289
21290                 RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
21291                         | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
21292                         |  0 ) & RegMask); */
21293                 PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U);
21294         /*############################################################################################################################ */
21295
21296                 /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4</p>
21297
21298                 Bypass scrambler signal
21299                 PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
21300
21301                 Enable/disable scrambler bypass signal
21302                 PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
21303
21304                 MPHY PLL Gear and bypass scrambler
21305                 (OFFSET, MASK, VALUE)      (0XFD4080F4, 0x00000003U ,0x00000003U)
21306                 RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
21307
21308                 RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
21309                         | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
21310                         |  0 ) & RegMask); */
21311                 PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U);
21312         /*############################################################################################################################ */
21313
21314                 /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360</p>
21315
21316                 Enable test mode force on fractional mode enable
21317                 PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC                             0x1
21318
21319                 Fractional feedback division control and fractional value for feedback division bits 26:24
21320                 (OFFSET, MASK, VALUE)      (0XFD40E360, 0x00000040U ,0x00000040U)
21321                 RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK |  0 );
21322
21323                 RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
21324                         |  0 ) & RegMask); */
21325                 PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U);
21326         /*############################################################################################################################ */
21327
21328                 /*Register : L3_TM_DIG_6 @ 0XFD40D06C</p>
21329
21330                 Bypass 8b10b decoder
21331                 PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER                                           0x1
21332
21333                 Enable Bypass for <3> TM_DIG_CTRL_6
21334                 PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC                                         0x1
21335
21336                 Bypass Descrambler
21337                 PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM                                           0x1
21338
21339                 Enable Bypass for <1> TM_DIG_CTRL_6
21340                 PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
21341
21342                 Data path test modes in decoder and descram
21343                 (OFFSET, MASK, VALUE)      (0XFD40D06C, 0x0000000FU ,0x0000000FU)
21344                 RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
21345
21346                 RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
21347                         | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
21348                         | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
21349                         | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
21350                         |  0 ) & RegMask); */
21351                 PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU);
21352         /*############################################################################################################################ */
21353
21354                 /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4</p>
21355
21356                 Enable/disable encoder bypass signal
21357                 PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC                                           0x1
21358
21359                 Bypass scrambler signal
21360                 PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
21361
21362                 Enable/disable scrambler bypass signal
21363                 PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
21364
21365                 MPHY PLL Gear and bypass scrambler
21366                 (OFFSET, MASK, VALUE)      (0XFD40C0F4, 0x0000000BU ,0x0000000BU)
21367                 RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
21368
21369                 RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
21370                         | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
21371                         | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
21372                         |  0 ) & RegMask); */
21373                 PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU);
21374         /*############################################################################################################################ */
21375
21376                 /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00</p>
21377
21378                 PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
21379                 PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE                                            0x21
21380
21381                 Opmode Info
21382                 (OFFSET, MASK, VALUE)      (0XFD40CB00, 0x000000F0U ,0x000000F0U)
21383                 RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK |  0 );
21384
21385                 RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
21386                         |  0 ) & RegMask); */
21387                 PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
21388         /*############################################################################################################################ */
21389
21390                 // : ENABLE CHICKEN BIT FOR PCIE AND USB
21391                 /*Register : L2_TM_AUX_0 @ 0XFD4090CC</p>
21392
21393                 Spare- not used
21394                 PSU_SERDES_L2_TM_AUX_0_BIT_2                                                    1
21395
21396                 Spare registers
21397                 (OFFSET, MASK, VALUE)      (0XFD4090CC, 0x00000020U ,0x00000020U)
21398                 RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK |  0 );
21399
21400                 RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT
21401                         |  0 ) & RegMask); */
21402                 PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
21403         /*############################################################################################################################ */
21404
21405                 // : ENABLING EYE SURF
21406                 /*Register : L0_TM_DIG_8 @ 0XFD401074</p>
21407
21408                 Enable Eye Surf
21409                 PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE                                           0x1
21410
21411                 Test modes for Elastic buffer and enabling Eye Surf
21412                 (OFFSET, MASK, VALUE)      (0XFD401074, 0x00000010U ,0x00000010U)
21413                 RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK |  0 );
21414
21415                 RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
21416                         |  0 ) & RegMask); */
21417                 PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
21418         /*############################################################################################################################ */
21419
21420                 /*Register : L1_TM_DIG_8 @ 0XFD405074</p>
21421
21422                 Enable Eye Surf
21423                 PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE                                           0x1
21424
21425                 Test modes for Elastic buffer and enabling Eye Surf
21426                 (OFFSET, MASK, VALUE)      (0XFD405074, 0x00000010U ,0x00000010U)
21427                 RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK |  0 );
21428
21429                 RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
21430                         |  0 ) & RegMask); */
21431                 PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
21432         /*############################################################################################################################ */
21433
21434                 /*Register : L2_TM_DIG_8 @ 0XFD409074</p>
21435
21436                 Enable Eye Surf
21437                 PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE                                           0x1
21438
21439                 Test modes for Elastic buffer and enabling Eye Surf
21440                 (OFFSET, MASK, VALUE)      (0XFD409074, 0x00000010U ,0x00000010U)
21441                 RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK |  0 );
21442
21443                 RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
21444                         |  0 ) & RegMask); */
21445                 PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
21446         /*############################################################################################################################ */
21447
21448                 /*Register : L3_TM_DIG_8 @ 0XFD40D074</p>
21449
21450                 Enable Eye Surf
21451                 PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE                                           0x1
21452
21453                 Test modes for Elastic buffer and enabling Eye Surf
21454                 (OFFSET, MASK, VALUE)      (0XFD40D074, 0x00000010U ,0x00000010U)
21455                 RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK |  0 );
21456
21457                 RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
21458                         |  0 ) & RegMask); */
21459                 PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
21460         /*############################################################################################################################ */
21461
21462                 // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS
21463                 /*Register : L2_TM_MISC2 @ 0XFD40989C</p>
21464
21465                 ILL calib counts BYPASSED with calcode bits
21466                 PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS                                    0x1
21467
21468                 sampler cal
21469                 (OFFSET, MASK, VALUE)      (0XFD40989C, 0x00000080U ,0x00000080U)
21470                 RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK |  0 );
21471
21472                 RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
21473                         |  0 ) & RegMask); */
21474                 PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
21475         /*############################################################################################################################ */
21476
21477                 /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8</p>
21478
21479                 IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
21480                 PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0                               0x1A
21481
21482                 iqpi cal code
21483                 (OFFSET, MASK, VALUE)      (0XFD4098F8, 0x000000FFU ,0x0000001AU)
21484                 RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK |  0 );
21485
21486                 RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
21487                         |  0 ) & RegMask); */
21488                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU);
21489         /*############################################################################################################################ */
21490
21491                 /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC</p>
21492
21493                 IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
21494                 PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1                               0x1A
21495
21496                 iqpi cal code
21497                 (OFFSET, MASK, VALUE)      (0XFD4098FC, 0x000000FFU ,0x0000001AU)
21498                 RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK |  0 );
21499
21500                 RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
21501                         |  0 ) & RegMask); */
21502                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU);
21503         /*############################################################################################################################ */
21504
21505                 /*Register : L2_TM_ILL12 @ 0XFD409990</p>
21506
21507                 G1A pll ctr bypass value
21508                 PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL                                      0x10
21509
21510                 ill pll counter values
21511                 (OFFSET, MASK, VALUE)      (0XFD409990, 0x000000FFU ,0x00000010U)
21512                 RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK |  0 );
21513
21514                 RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
21515                         |  0 ) & RegMask); */
21516                 PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U);
21517         /*############################################################################################################################ */
21518
21519                 /*Register : L2_TM_E_ILL1 @ 0XFD409924</p>
21520
21521                 E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
21522                 PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0                                 0xFE
21523
21524                 epi cal code
21525                 (OFFSET, MASK, VALUE)      (0XFD409924, 0x000000FFU ,0x000000FEU)
21526                 RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK |  0 );
21527
21528                 RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
21529                         |  0 ) & RegMask); */
21530                 PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU);
21531         /*############################################################################################################################ */
21532
21533                 /*Register : L2_TM_E_ILL2 @ 0XFD409928</p>
21534
21535                 E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
21536                 PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1                                 0x0
21537
21538                 epi cal code
21539                 (OFFSET, MASK, VALUE)      (0XFD409928, 0x000000FFU ,0x00000000U)
21540                 RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK |  0 );
21541
21542                 RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
21543                         |  0 ) & RegMask); */
21544                 PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U);
21545         /*############################################################################################################################ */
21546
21547                 /*Register : L2_TM_IQ_ILL3 @ 0XFD409900</p>
21548
21549                 IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
21550                 PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2                               0x1A
21551
21552                 iqpi cal code
21553                 (OFFSET, MASK, VALUE)      (0XFD409900, 0x000000FFU ,0x0000001AU)
21554                 RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK |  0 );
21555
21556                 RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
21557                         |  0 ) & RegMask); */
21558                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU);
21559         /*############################################################################################################################ */
21560
21561                 /*Register : L2_TM_E_ILL3 @ 0XFD40992C</p>
21562
21563                 E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
21564                 PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2                                 0x0
21565
21566                 epi cal code
21567                 (OFFSET, MASK, VALUE)      (0XFD40992C, 0x000000FFU ,0x00000000U)
21568                 RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK |  0 );
21569
21570                 RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
21571                         |  0 ) & RegMask); */
21572                 PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
21573         /*############################################################################################################################ */
21574
21575                 /*Register : L2_TM_ILL8 @ 0XFD409980</p>
21576
21577                 ILL calibration code change wait time
21578                 PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT                                         0xFF
21579
21580                 ILL cal routine control
21581                 (OFFSET, MASK, VALUE)      (0XFD409980, 0x000000FFU ,0x000000FFU)
21582                 RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK |  0 );
21583
21584                 RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
21585                         |  0 ) & RegMask); */
21586                 PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
21587         /*############################################################################################################################ */
21588
21589                 /*Register : L2_TM_IQ_ILL8 @ 0XFD409914</p>
21590
21591                 IQ ILL polytrim bypass value
21592                 PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL                             0xF7
21593
21594                 iqpi polytrim
21595                 (OFFSET, MASK, VALUE)      (0XFD409914, 0x000000FFU ,0x000000F7U)
21596                 RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK |  0 );
21597
21598                 RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
21599                         |  0 ) & RegMask); */
21600                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
21601         /*############################################################################################################################ */
21602
21603                 /*Register : L2_TM_IQ_ILL9 @ 0XFD409918</p>
21604
21605                 bypass IQ polytrim
21606                 PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM                                  0x1
21607
21608                 enables for lf,constant gm trim and polytirm
21609                 (OFFSET, MASK, VALUE)      (0XFD409918, 0x00000001U ,0x00000001U)
21610                 RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK |  0 );
21611
21612                 RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
21613                         |  0 ) & RegMask); */
21614                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
21615         /*############################################################################################################################ */
21616
21617                 /*Register : L2_TM_E_ILL8 @ 0XFD409940</p>
21618
21619                 E ILL polytrim bypass value
21620                 PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL                               0xF7
21621
21622                 epi polytrim
21623                 (OFFSET, MASK, VALUE)      (0XFD409940, 0x000000FFU ,0x000000F7U)
21624                 RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK |  0 );
21625
21626                 RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
21627                         |  0 ) & RegMask); */
21628                 PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
21629         /*############################################################################################################################ */
21630
21631                 /*Register : L2_TM_E_ILL9 @ 0XFD409944</p>
21632
21633                 bypass E polytrim
21634                 PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM                                    0x1
21635
21636                 enables for lf,constant gm trim and polytirm
21637                 (OFFSET, MASK, VALUE)      (0XFD409944, 0x00000001U ,0x00000001U)
21638                 RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK |  0 );
21639
21640                 RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
21641                         |  0 ) & RegMask); */
21642                 PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
21643         /*############################################################################################################################ */
21644
21645                 /*Register : L3_TM_MISC2 @ 0XFD40D89C</p>
21646
21647                 ILL calib counts BYPASSED with calcode bits
21648                 PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS                                    0x1
21649
21650                 sampler cal
21651                 (OFFSET, MASK, VALUE)      (0XFD40D89C, 0x00000080U ,0x00000080U)
21652                 RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK |  0 );
21653
21654                 RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
21655                         |  0 ) & RegMask); */
21656                 PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
21657         /*############################################################################################################################ */
21658
21659                 /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8</p>
21660
21661                 IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
21662                 PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0                               0x7D
21663
21664                 iqpi cal code
21665                 (OFFSET, MASK, VALUE)      (0XFD40D8F8, 0x000000FFU ,0x0000007DU)
21666                 RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK |  0 );
21667
21668                 RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
21669                         |  0 ) & RegMask); */
21670                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU);
21671         /*############################################################################################################################ */
21672
21673                 /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC</p>
21674
21675                 IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
21676                 PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1                               0x7D
21677
21678                 iqpi cal code
21679                 (OFFSET, MASK, VALUE)      (0XFD40D8FC, 0x000000FFU ,0x0000007DU)
21680                 RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK |  0 );
21681
21682                 RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
21683                         |  0 ) & RegMask); */
21684                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU);
21685         /*############################################################################################################################ */
21686
21687                 /*Register : L3_TM_ILL12 @ 0XFD40D990</p>
21688
21689                 G1A pll ctr bypass value
21690                 PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL                                      0x1
21691
21692                 ill pll counter values
21693                 (OFFSET, MASK, VALUE)      (0XFD40D990, 0x000000FFU ,0x00000001U)
21694                 RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK |  0 );
21695
21696                 RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
21697                         |  0 ) & RegMask); */
21698                 PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U);
21699         /*############################################################################################################################ */
21700
21701                 /*Register : L3_TM_E_ILL1 @ 0XFD40D924</p>
21702
21703                 E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
21704                 PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0                                 0x9C
21705
21706                 epi cal code
21707                 (OFFSET, MASK, VALUE)      (0XFD40D924, 0x000000FFU ,0x0000009CU)
21708                 RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK |  0 );
21709
21710                 RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
21711                         |  0 ) & RegMask); */
21712                 PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU);
21713         /*############################################################################################################################ */
21714
21715                 /*Register : L3_TM_E_ILL2 @ 0XFD40D928</p>
21716
21717                 E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
21718                 PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1                                 0x39
21719
21720                 epi cal code
21721                 (OFFSET, MASK, VALUE)      (0XFD40D928, 0x000000FFU ,0x00000039U)
21722                 RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK |  0 );
21723
21724                 RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
21725                         |  0 ) & RegMask); */
21726                 PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U);
21727         /*############################################################################################################################ */
21728
21729                 /*Register : L3_TM_ILL11 @ 0XFD40D98C</p>
21730
21731                 G2A_PCIe1 PLL ctr bypass value
21732                 PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL                          0x2
21733
21734                 ill pll counter values
21735                 (OFFSET, MASK, VALUE)      (0XFD40D98C, 0x000000F0U ,0x00000020U)
21736                 RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK |  0 );
21737
21738                 RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
21739                         |  0 ) & RegMask); */
21740                 PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U);
21741         /*############################################################################################################################ */
21742
21743                 /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900</p>
21744
21745                 IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
21746                 PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2                               0x7D
21747
21748                 iqpi cal code
21749                 (OFFSET, MASK, VALUE)      (0XFD40D900, 0x000000FFU ,0x0000007DU)
21750                 RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK |  0 );
21751
21752                 RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
21753                         |  0 ) & RegMask); */
21754                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU);
21755         /*############################################################################################################################ */
21756
21757                 /*Register : L3_TM_E_ILL3 @ 0XFD40D92C</p>
21758
21759                 E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
21760                 PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2                                 0x64
21761
21762                 epi cal code
21763                 (OFFSET, MASK, VALUE)      (0XFD40D92C, 0x000000FFU ,0x00000064U)
21764                 RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK |  0 );
21765
21766                 RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
21767                         |  0 ) & RegMask); */
21768                 PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
21769         /*############################################################################################################################ */
21770
21771                 /*Register : L3_TM_ILL8 @ 0XFD40D980</p>
21772
21773                 ILL calibration code change wait time
21774                 PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT                                         0xFF
21775
21776                 ILL cal routine control
21777                 (OFFSET, MASK, VALUE)      (0XFD40D980, 0x000000FFU ,0x000000FFU)
21778                 RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK |  0 );
21779
21780                 RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
21781                         |  0 ) & RegMask); */
21782                 PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
21783         /*############################################################################################################################ */
21784
21785                 /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914</p>
21786
21787                 IQ ILL polytrim bypass value
21788                 PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL                             0xF7
21789
21790                 iqpi polytrim
21791                 (OFFSET, MASK, VALUE)      (0XFD40D914, 0x000000FFU ,0x000000F7U)
21792                 RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK |  0 );
21793
21794                 RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
21795                         |  0 ) & RegMask); */
21796                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
21797         /*############################################################################################################################ */
21798
21799                 /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918</p>
21800
21801                 bypass IQ polytrim
21802                 PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM                                  0x1
21803
21804                 enables for lf,constant gm trim and polytirm
21805                 (OFFSET, MASK, VALUE)      (0XFD40D918, 0x00000001U ,0x00000001U)
21806                 RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK |  0 );
21807
21808                 RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
21809                         |  0 ) & RegMask); */
21810                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
21811         /*############################################################################################################################ */
21812
21813                 /*Register : L3_TM_E_ILL8 @ 0XFD40D940</p>
21814
21815                 E ILL polytrim bypass value
21816                 PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL                               0xF7
21817
21818                 epi polytrim
21819                 (OFFSET, MASK, VALUE)      (0XFD40D940, 0x000000FFU ,0x000000F7U)
21820                 RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK |  0 );
21821
21822                 RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
21823                         |  0 ) & RegMask); */
21824                 PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
21825         /*############################################################################################################################ */
21826
21827                 /*Register : L3_TM_E_ILL9 @ 0XFD40D944</p>
21828
21829                 bypass E polytrim
21830                 PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM                                    0x1
21831
21832                 enables for lf,constant gm trim and polytirm
21833                 (OFFSET, MASK, VALUE)      (0XFD40D944, 0x00000001U ,0x00000001U)
21834                 RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK |  0 );
21835
21836                 RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
21837                         |  0 ) & RegMask); */
21838                 PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
21839         /*############################################################################################################################ */
21840
21841                 // : SYMBOL LOCK AND WAIT
21842                 // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
21843                 /*Register : L0_TM_RST_DLY @ 0XFD4019A4</p>
21844
21845                 Delay apb reset by specified amount
21846                 PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY                                            0xFF
21847
21848                 reset delay for apb reset w.r.t pso of hsrx
21849                 (OFFSET, MASK, VALUE)      (0XFD4019A4, 0x000000FFU ,0x000000FFU)
21850                 RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK |  0 );
21851
21852                 RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
21853                         |  0 ) & RegMask); */
21854                 PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
21855         /*############################################################################################################################ */
21856
21857                 /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038</p>
21858
21859                 Enable Bypass for <7> of TM_ANA_BYPS_15
21860                 PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE                       0x1
21861
21862                 Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
21863                 (OFFSET, MASK, VALUE)      (0XFD401038, 0x00000040U ,0x00000040U)
21864                 RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK |  0 );
21865
21866                 RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
21867                         |  0 ) & RegMask); */
21868                 PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
21869         /*############################################################################################################################ */
21870
21871                 /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C</p>
21872
21873                 Enable Bypass for <7> of TM_ANA_BYPS_12
21874                 PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG                              0x1
21875
21876                 Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
21877                 (OFFSET, MASK, VALUE)      (0XFD40102C, 0x00000040U ,0x00000040U)
21878                 RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK |  0 );
21879
21880                 RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
21881                         |  0 ) & RegMask); */
21882                 PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
21883         /*############################################################################################################################ */
21884
21885                 /*Register : L1_TM_RST_DLY @ 0XFD4059A4</p>
21886
21887                 Delay apb reset by specified amount
21888                 PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY                                            0xFF
21889
21890                 reset delay for apb reset w.r.t pso of hsrx
21891                 (OFFSET, MASK, VALUE)      (0XFD4059A4, 0x000000FFU ,0x000000FFU)
21892                 RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK |  0 );
21893
21894                 RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
21895                         |  0 ) & RegMask); */
21896                 PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
21897         /*############################################################################################################################ */
21898
21899                 /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038</p>
21900
21901                 Enable Bypass for <7> of TM_ANA_BYPS_15
21902                 PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE                       0x1
21903
21904                 Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
21905                 (OFFSET, MASK, VALUE)      (0XFD405038, 0x00000040U ,0x00000040U)
21906                 RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK |  0 );
21907
21908                 RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
21909                         |  0 ) & RegMask); */
21910                 PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
21911         /*############################################################################################################################ */
21912
21913                 /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C</p>
21914
21915                 Enable Bypass for <7> of TM_ANA_BYPS_12
21916                 PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG                              0x1
21917
21918                 Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
21919                 (OFFSET, MASK, VALUE)      (0XFD40502C, 0x00000040U ,0x00000040U)
21920                 RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK |  0 );
21921
21922                 RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
21923                         |  0 ) & RegMask); */
21924                 PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
21925         /*############################################################################################################################ */
21926
21927                 /*Register : L2_TM_RST_DLY @ 0XFD4099A4</p>
21928
21929                 Delay apb reset by specified amount
21930                 PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY                                            0xFF
21931
21932                 reset delay for apb reset w.r.t pso of hsrx
21933                 (OFFSET, MASK, VALUE)      (0XFD4099A4, 0x000000FFU ,0x000000FFU)
21934                 RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK |  0 );
21935
21936                 RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
21937                         |  0 ) & RegMask); */
21938                 PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
21939         /*############################################################################################################################ */
21940
21941                 /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038</p>
21942
21943                 Enable Bypass for <7> of TM_ANA_BYPS_15
21944                 PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE                       0x1
21945
21946                 Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
21947                 (OFFSET, MASK, VALUE)      (0XFD409038, 0x00000040U ,0x00000040U)
21948                 RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK |  0 );
21949
21950                 RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
21951                         |  0 ) & RegMask); */
21952                 PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
21953         /*############################################################################################################################ */
21954
21955                 /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C</p>
21956
21957                 Enable Bypass for <7> of TM_ANA_BYPS_12
21958                 PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG                              0x1
21959
21960                 Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
21961                 (OFFSET, MASK, VALUE)      (0XFD40902C, 0x00000040U ,0x00000040U)
21962                 RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK |  0 );
21963
21964                 RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
21965                         |  0 ) & RegMask); */
21966                 PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
21967         /*############################################################################################################################ */
21968
21969                 /*Register : L3_TM_RST_DLY @ 0XFD40D9A4</p>
21970
21971                 Delay apb reset by specified amount
21972                 PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY                                            0xFF
21973
21974                 reset delay for apb reset w.r.t pso of hsrx
21975                 (OFFSET, MASK, VALUE)      (0XFD40D9A4, 0x000000FFU ,0x000000FFU)
21976                 RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK |  0 );
21977
21978                 RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
21979                         |  0 ) & RegMask); */
21980                 PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
21981         /*############################################################################################################################ */
21982
21983                 /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038</p>
21984
21985                 Enable Bypass for <7> of TM_ANA_BYPS_15
21986                 PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE                       0x1
21987
21988                 Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
21989                 (OFFSET, MASK, VALUE)      (0XFD40D038, 0x00000040U ,0x00000040U)
21990                 RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK |  0 );
21991
21992                 RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
21993                         |  0 ) & RegMask); */
21994                 PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
21995         /*############################################################################################################################ */
21996
21997                 /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C</p>
21998
21999                 Enable Bypass for <7> of TM_ANA_BYPS_12
22000                 PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG                              0x1
22001
22002                 Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
22003                 (OFFSET, MASK, VALUE)      (0XFD40D02C, 0x00000040U ,0x00000040U)
22004                 RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK |  0 );
22005
22006                 RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
22007                         |  0 ) & RegMask); */
22008                 PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
22009         /*############################################################################################################################ */
22010
22011                 // : GT LANE SETTINGS
22012                 /*Register : ICM_CFG0 @ 0XFD410010</p>
22013
22014                 Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
22015                 , 7 - Unused
22016                 PSU_SERDES_ICM_CFG0_L0_ICM_CFG                                                  4
22017
22018                 Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
22019                  7 - Unused
22020                 PSU_SERDES_ICM_CFG0_L1_ICM_CFG                                                  4
22021
22022                 ICM Configuration Register 0
22023                 (OFFSET, MASK, VALUE)      (0XFD410010, 0x00000077U ,0x00000044U)
22024                 RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK |  0 );
22025
22026                 RegVal = ((0x00000004U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
22027                         | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
22028                         |  0 ) & RegMask); */
22029                 PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000044U);
22030         /*############################################################################################################################ */
22031
22032                 /*Register : ICM_CFG1 @ 0XFD410014</p>
22033
22034                 Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
22035                  7 - Unused
22036                 PSU_SERDES_ICM_CFG1_L2_ICM_CFG                                                  3
22037
22038                 Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
22039                  7 - Unused
22040                 PSU_SERDES_ICM_CFG1_L3_ICM_CFG                                                  2
22041
22042                 ICM Configuration Register 1
22043                 (OFFSET, MASK, VALUE)      (0XFD410014, 0x00000077U ,0x00000023U)
22044                 RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK |  0 );
22045
22046                 RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
22047                         | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
22048                         |  0 ) & RegMask); */
22049                 PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U);
22050         /*############################################################################################################################ */
22051
22052                 // : CHECKING PLL LOCK
22053                 // : ENABLE SERIAL DATA MUX DEEMPH
22054                 /*Register : L0_TXPMD_TM_45 @ 0XFD400CB4</p>
22055
22056                 Enable/disable DP post2 path
22057                 PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH                         0x1
22058
22059                 Override enable/disable of DP post2 path
22060                 PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH                    0x1
22061
22062                 Override enable/disable of DP post1 path
22063                 PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH                    0x1
22064
22065                 Enable/disable DP main path
22066                 PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH                          0x1
22067
22068                 Override enable/disable of DP main path
22069                 PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH                     0x1
22070
22071                 Post or pre or main DP path selection
22072                 (OFFSET, MASK, VALUE)      (0XFD400CB4, 0x00000037U ,0x00000037U)
22073                 RegMask = (SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK |  0 );
22074
22075                 RegVal = ((0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
22076                         | 0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
22077                         | 0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
22078                         | 0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
22079                         | 0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
22080                         |  0 ) & RegMask); */
22081                 PSU_Mask_Write (SERDES_L0_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
22082         /*############################################################################################################################ */
22083
22084                 /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4</p>
22085
22086                 Enable/disable DP post2 path
22087                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH                         0x1
22088
22089                 Override enable/disable of DP post2 path
22090                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH                    0x1
22091
22092                 Override enable/disable of DP post1 path
22093                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH                    0x1
22094
22095                 Enable/disable DP main path
22096                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH                          0x1
22097
22098                 Override enable/disable of DP main path
22099                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH                     0x1
22100
22101                 Post or pre or main DP path selection
22102                 (OFFSET, MASK, VALUE)      (0XFD404CB4, 0x00000037U ,0x00000037U)
22103                 RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK |  0 );
22104
22105                 RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
22106                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
22107                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
22108                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
22109                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
22110                         |  0 ) & RegMask); */
22111                 PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
22112         /*############################################################################################################################ */
22113
22114                 /*Register : L0_TX_ANA_TM_118 @ 0XFD4001D8</p>
22115
22116                 Test register force for enabling/disablign TX deemphasis bits <17:0>
22117                 PSU_SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
22118
22119                 Enable Override of TX deemphasis
22120                 (OFFSET, MASK, VALUE)      (0XFD4001D8, 0x00000001U ,0x00000001U)
22121                 RegMask = (SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK |  0 );
22122
22123                 RegVal = ((0x00000001U << SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
22124                         |  0 ) & RegMask); */
22125                 PSU_Mask_Write (SERDES_L0_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
22126         /*############################################################################################################################ */
22127
22128                 /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8</p>
22129
22130                 Test register force for enabling/disablign TX deemphasis bits <17:0>
22131                 PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
22132
22133                 Enable Override of TX deemphasis
22134                 (OFFSET, MASK, VALUE)      (0XFD4041D8, 0x00000001U ,0x00000001U)
22135                 RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK |  0 );
22136
22137                 RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
22138                         |  0 ) & RegMask); */
22139                 PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
22140         /*############################################################################################################################ */
22141
22142                 /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8</p>
22143
22144                 Test register force for enabling/disablign TX deemphasis bits <17:0>
22145                 PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
22146
22147                 Enable Override of TX deemphasis
22148                 (OFFSET, MASK, VALUE)      (0XFD40C1D8, 0x00000001U ,0x00000001U)
22149                 RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK |  0 );
22150
22151                 RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
22152                         |  0 ) & RegMask); */
22153                 PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
22154         /*############################################################################################################################ */
22155
22156                 // : CDR AND RX EQUALIZATION SETTINGS
22157                 /*Register : L3_TM_CDR5 @ 0XFD40DC14</p>
22158
22159                 FPHL FSM accumulate cycles
22160                 PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES                                       0x7
22161
22162                 FFL Phase0 int gain aka 2ol SD update rate
22163                 PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN                                          0x6
22164
22165                 Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control.
22166                 (OFFSET, MASK, VALUE)      (0XFD40DC14, 0x000000FFU ,0x000000E6U)
22167                 RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK |  0 );
22168
22169                 RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
22170                         | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
22171                         |  0 ) & RegMask); */
22172                 PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U);
22173         /*############################################################################################################################ */
22174
22175                 /*Register : L3_TM_CDR16 @ 0XFD40DC40</p>
22176
22177                 FFL Phase0 prop gain aka 1ol SD update rate
22178                 PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN                                        0xC
22179
22180                 Fast phase lock controls -- phase 0 prop gain
22181                 (OFFSET, MASK, VALUE)      (0XFD40DC40, 0x0000001FU ,0x0000000CU)
22182                 RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK |  0 );
22183
22184                 RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
22185                         |  0 ) & RegMask); */
22186                 PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU);
22187         /*############################################################################################################################ */
22188
22189                 /*Register : L3_TM_EQ0 @ 0XFD40D94C</p>
22190
22191                 EQ stg 2 controls BYPASSED
22192                 PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP                                           1
22193
22194                 eq stg1 and stg2 controls
22195                 (OFFSET, MASK, VALUE)      (0XFD40D94C, 0x00000020U ,0x00000020U)
22196                 RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK |  0 );
22197
22198                 RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
22199                         |  0 ) & RegMask); */
22200                 PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U);
22201         /*############################################################################################################################ */
22202
22203                 /*Register : L3_TM_EQ1 @ 0XFD40D950</p>
22204
22205                 EQ STG2 RL PROG
22206                 PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG                                            0x2
22207
22208                 EQ stg 2 preamp mode val
22209                 PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL                                    0x1
22210
22211                 eq stg1 and stg2 controls
22212                 (OFFSET, MASK, VALUE)      (0XFD40D950, 0x00000007U ,0x00000006U)
22213                 RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK |  0 );
22214
22215                 RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
22216                         | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
22217                         |  0 ) & RegMask); */
22218                 PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U);
22219         /*############################################################################################################################ */
22220
22221                 // : GEM SERDES SETTINGS
22222                 // : ENABLE PRE EMPHAIS AND VOLTAGE SWING
22223                 /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0</p>
22224
22225                 Margining factor value
22226                 PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR                         0
22227
22228                 Margining factor
22229                 (OFFSET, MASK, VALUE)      (0XFD404CC0, 0x0000001FU ,0x00000000U)
22230                 RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK |  0 );
22231
22232                 RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
22233                         |  0 ) & RegMask); */
22234                 PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
22235         /*############################################################################################################################ */
22236
22237                 /*Register : L0_TXPMD_TM_48 @ 0XFD400CC0</p>
22238
22239                 Margining factor value
22240                 PSU_SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR                         0
22241
22242                 Margining factor
22243                 (OFFSET, MASK, VALUE)      (0XFD400CC0, 0x0000001FU ,0x00000000U)
22244                 RegMask = (SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK |  0 );
22245
22246                 RegVal = ((0x00000000U << SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
22247                         |  0 ) & RegMask); */
22248                 PSU_Mask_Write (SERDES_L0_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
22249         /*############################################################################################################################ */
22250
22251                 /*Register : L1_TX_ANA_TM_18 @ 0XFD404048</p>
22252
22253                 pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
22254                 PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0
22255
22256                 Override for PIPE TX de-emphasis
22257                 (OFFSET, MASK, VALUE)      (0XFD404048, 0x000000FFU ,0x00000000U)
22258                 RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK |  0 );
22259
22260                 RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
22261                         |  0 ) & RegMask); */
22262                 PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
22263         /*############################################################################################################################ */
22264
22265                 /*Register : L0_TX_ANA_TM_18 @ 0XFD400048</p>
22266
22267                 pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
22268                 PSU_SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0
22269
22270                 Override for PIPE TX de-emphasis
22271                 (OFFSET, MASK, VALUE)      (0XFD400048, 0x000000FFU ,0x00000000U)
22272                 RegMask = (SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK |  0 );
22273
22274                 RegVal = ((0x00000000U << SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
22275                         |  0 ) & RegMask); */
22276                 PSU_Mask_Write (SERDES_L0_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
22277         /*############################################################################################################################ */
22278
22279                 /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048</p>
22280
22281                 pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
22282                 PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0x1
22283
22284                 Override for PIPE TX de-emphasis
22285                 (OFFSET, MASK, VALUE)      (0XFD40C048, 0x000000FFU ,0x00000001U)
22286                 RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK |  0 );
22287
22288                 RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
22289                         |  0 ) & RegMask); */
22290                 PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U);
22291         /*############################################################################################################################ */
22292
22293
22294   return 1;
22295 }
22296 unsigned long psu_resetout_init_data() {
22297                 // : TAKING SERDES PERIPHERAL OUT OF RESET RESET
22298                 // : PUTTING USB0 IN RESET
22299                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
22300
22301                 USB 0 reset for control registers
22302                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X0
22303
22304                 Software control register for the LPD block.
22305                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000400U ,0x00000000U)
22306                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK |  0 );
22307
22308                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
22309                         |  0 ) & RegMask); */
22310                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U);
22311         /*############################################################################################################################ */
22312
22313                 // : USB0 PIPE POWER PRESENT
22314                 /*Register : fpd_power_prsnt @ 0XFF9D0080</p>
22315
22316                 This bit is used to choose between PIPE power present and 1'b1
22317                 PSU_USB3_0_FPD_POWER_PRSNT_OPTION                                               0X1
22318
22319                 fpd_power_prsnt
22320                 (OFFSET, MASK, VALUE)      (0XFF9D0080, 0x00000001U ,0x00000001U)
22321                 RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK |  0 );
22322
22323                 RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
22324                         |  0 ) & RegMask); */
22325                 PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
22326         /*############################################################################################################################ */
22327
22328                 /*Register : fpd_pipe_clk @ 0XFF9D007C</p>
22329
22330                 This bit is used to choose between PIPE clock coming from SerDes and the suspend clk
22331                 PSU_USB3_0_FPD_PIPE_CLK_OPTION                                                  0x0
22332
22333                 fpd_pipe_clk
22334                 (OFFSET, MASK, VALUE)      (0XFF9D007C, 0x00000001U ,0x00000000U)
22335                 RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK |  0 );
22336
22337                 RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
22338                         |  0 ) & RegMask); */
22339                 PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U);
22340         /*############################################################################################################################ */
22341
22342                 // :
22343                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
22344
22345                 USB 0 sleep circuit reset
22346                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X0
22347
22348                 USB 0 reset
22349                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X0
22350
22351                 Software control register for the LPD block.
22352                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000140U ,0x00000000U)
22353                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
22354
22355                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
22356                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
22357                         |  0 ) & RegMask); */
22358                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U);
22359         /*############################################################################################################################ */
22360
22361                 // : PUTTING GEM0 IN RESET
22362                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
22363
22364                 GEM 3 reset
22365                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X0
22366
22367                 Software controlled reset for the GEMs
22368                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)
22369                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
22370
22371                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
22372                         |  0 ) & RegMask); */
22373                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
22374         /*############################################################################################################################ */
22375
22376                 // : PUTTING SATA IN RESET
22377                 /*Register : sata_misc_ctrl @ 0XFD3D0100</p>
22378
22379                 Sata PM clock control select
22380                 PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL                                         0x3
22381
22382                 Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
22383                 (OFFSET, MASK, VALUE)      (0XFD3D0100, 0x00000003U ,0x00000003U)
22384                 RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK |  0 );
22385
22386                 RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
22387                         |  0 ) & RegMask); */
22388                 PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U);
22389         /*############################################################################################################################ */
22390
22391                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
22392
22393                 Sata block level reset
22394                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X0
22395
22396                 FPD Block level software controlled reset
22397                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000000U)
22398                 RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
22399
22400                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
22401                         |  0 ) & RegMask); */
22402                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
22403         /*############################################################################################################################ */
22404
22405                 // : PUTTING DP IN RESET
22406                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
22407
22408                 Display Port block level reset (includes DPDMA)
22409                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X0
22410
22411                 FPD Block level software controlled reset
22412                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00000000U)
22413                 RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
22414
22415                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
22416                         |  0 ) & RegMask); */
22417                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U);
22418         /*############################################################################################################################ */
22419
22420                 /*Register : DP_PHY_RESET @ 0XFD4A0200</p>
22421
22422                 Set to '1' to hold the GT in reset. Clear to release.
22423                 PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X0
22424
22425                 Reset the transmitter PHY.
22426                 (OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000000U)
22427                 RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
22428
22429                 RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT
22430                         |  0 ) & RegMask); */
22431                 PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U);
22432         /*############################################################################################################################ */
22433
22434                 /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
22435
22436                 Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
22437                 ane0 Bits [3:2] - lane 1
22438                 PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0X0
22439
22440                 Control PHY Power down
22441                 (OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x00000000U)
22442                 RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
22443
22444                 RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
22445                         |  0 ) & RegMask); */
22446                 PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U);
22447         /*############################################################################################################################ */
22448
22449                 // : USB0 GFLADJ
22450                 /*Register : GUSB2PHYCFG @ 0XFE20C200</p>
22451
22452                 USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
22453                 he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
22454                 C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
22455                 . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
22456                 UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
22457                 alue. Note: This field is valid only in device mode.
22458                 PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM                                           0x9
22459
22460                 Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
22461                  of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
22462                 time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
22463                 ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
22464                 off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
22465                 ng hibernation. - This bit is valid only in device mode.
22466                 PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY                                             0x0
22467
22468                 Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
22469                 _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
22470                  to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
22471                 ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
22472                 n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
22473                 d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
22474                 d.
22475                 PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM                                            0x0
22476
22477                 USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
22478                 Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
22479                 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
22480                  in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
22481                  active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
22482                 PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL                                              0x0
22483
22484                 Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
22485                 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
22486                 ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
22487                 B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
22488                 PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF                                              0x0
22489
22490                 ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
22491                 e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
22492                 ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
22493                 lected through DWC_USB3_HSPHY_INTERFACE.
22494                 PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL                                       0x1
22495
22496                 PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
22497                  8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
22498                 lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
22499                  ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
22500                  any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
22501                 PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF                                               0x0
22502
22503                 HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
22504                 a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
22505                 dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
22506                 e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
22507                 The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
22508                 ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
22509                  clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
22510                 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
22511                 PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL                                             0x7
22512
22513                 Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
22514                 he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
22515                 ented.
22516                 (OFFSET, MASK, VALUE)      (0XFE20C200, 0x00003FBFU ,0x00002417U)
22517                 RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK |  0 );
22518
22519                 RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
22520                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
22521                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
22522                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
22523                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
22524                         | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
22525                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
22526                         | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
22527                         |  0 ) & RegMask); */
22528                 PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U);
22529         /*############################################################################################################################ */
22530
22531                 /*Register : GFLADJ @ 0XFE20C630</p>
22532
22533                 This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
22534                 alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
22535                 _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
22536                 TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
22537                 riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
22538                 cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
22539                 uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
22540                 ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
22541                 RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
22542                 PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ                                      0x0
22543
22544                 Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
22545                 ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
22546                  to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely
22547                 rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
22548                 (OFFSET, MASK, VALUE)      (0XFE20C630, 0x003FFF00U ,0x00000000U)
22549                 RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK |  0 );
22550
22551                 RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
22552                         |  0 ) & RegMask); */
22553                 PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
22554         /*############################################################################################################################ */
22555
22556                 // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
22557                 /*Register : ATTR_25 @ 0XFD480064</p>
22558
22559                 If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
22560                 ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
22561                 PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED                      0X1
22562
22563                 ATTR_25
22564                 (OFFSET, MASK, VALUE)      (0XFD480064, 0x00000200U ,0x00000200U)
22565                 RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK |  0 );
22566
22567                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
22568                         |  0 ) & RegMask); */
22569                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U);
22570         /*############################################################################################################################ */
22571
22572                 // : CHECK PLL LOCK FOR LANE1
22573                 /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4</p>
22574
22575                 Status Read value of PLL Lock
22576                 PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
22577                 (OFFSET, MASK, VALUE)      (0XFD4063E4, 0x00000010U ,0x00000010U)  */
22578                 mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
22579
22580         /*############################################################################################################################ */
22581
22582                 // : CHECK PLL LOCK FOR LANE2
22583                 /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4</p>
22584
22585                 Status Read value of PLL Lock
22586                 PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
22587                 (OFFSET, MASK, VALUE)      (0XFD40A3E4, 0x00000010U ,0x00000010U)  */
22588                 mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
22589
22590         /*############################################################################################################################ */
22591
22592                 // : CHECK PLL LOCK FOR LANE3
22593                 /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4</p>
22594
22595                 Status Read value of PLL Lock
22596                 PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
22597                 (OFFSET, MASK, VALUE)      (0XFD40E3E4, 0x00000010U ,0x00000010U)  */
22598                 mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
22599
22600         /*############################################################################################################################ */
22601
22602                 // : SATA AHCI VENDOR SETTING
22603                 /*Register : PP2C @ 0XFD0C00AC</p>
22604
22605                 CIBGMN: COMINIT Burst Gap Minimum.
22606                 PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN                                                0x18
22607
22608                 CIBGMX: COMINIT Burst Gap Maximum.
22609                 PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX                                                0x40
22610
22611                 CIBGN: COMINIT Burst Gap Nominal.
22612                 PSU_SATA_AHCI_VENDOR_PP2C_CIBGN                                                 0x18
22613
22614                 CINMP: COMINIT Negate Minimum Period.
22615                 PSU_SATA_AHCI_VENDOR_PP2C_CINMP                                                 0x28
22616
22617                 PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete
22618                 s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
22619                 (OFFSET, MASK, VALUE)      (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U)
22620                 RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK |  0 );
22621
22622                 RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
22623                         | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
22624                         | 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
22625                         | 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
22626                         |  0 ) & RegMask); */
22627                 PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U);
22628         /*############################################################################################################################ */
22629
22630                 /*Register : PP3C @ 0XFD0C00B0</p>
22631
22632                 CWBGMN: COMWAKE Burst Gap Minimum.
22633                 PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN                                                0x06
22634
22635                 CWBGMX: COMWAKE Burst Gap Maximum.
22636                 PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX                                                0x14
22637
22638                 CWBGN: COMWAKE Burst Gap Nominal.
22639                 PSU_SATA_AHCI_VENDOR_PP3C_CWBGN                                                 0x08
22640
22641                 CWNMP: COMWAKE Negate Minimum Period.
22642                 PSU_SATA_AHCI_VENDOR_PP3C_CWNMP                                                 0x0E
22643
22644                 PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter
22645                  for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
22646                 (OFFSET, MASK, VALUE)      (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U)
22647                 RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK |  0 );
22648
22649                 RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
22650                         | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
22651                         | 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
22652                         | 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
22653                         |  0 ) & RegMask); */
22654                 PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U);
22655         /*############################################################################################################################ */
22656
22657                 /*Register : PP4C @ 0XFD0C00B4</p>
22658
22659                 BMX: COM Burst Maximum.
22660                 PSU_SATA_AHCI_VENDOR_PP4C_BMX                                                   0x13
22661
22662                 BNM: COM Burst Nominal.
22663                 PSU_SATA_AHCI_VENDOR_PP4C_BNM                                                   0x08
22664
22665                 SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
22666                 rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
22667                  Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
22668                 500ns based on a 150MHz PMCLK.
22669                 PSU_SATA_AHCI_VENDOR_PP4C_SFD                                                   0x4A
22670
22671                 PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
22672                  value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128
22673                 PSU_SATA_AHCI_VENDOR_PP4C_PTST                                                  0x06
22674
22675                 PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters
22676                 for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
22677                 (OFFSET, MASK, VALUE)      (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U)
22678                 RegMask = (SATA_AHCI_VENDOR_PP4C_BMX_MASK | SATA_AHCI_VENDOR_PP4C_BNM_MASK | SATA_AHCI_VENDOR_PP4C_SFD_MASK | SATA_AHCI_VENDOR_PP4C_PTST_MASK |  0 );
22679
22680                 RegVal = ((0x00000013U << SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
22681                         | 0x00000008U << SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
22682                         | 0x0000004AU << SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
22683                         | 0x00000006U << SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
22684                         |  0 ) & RegMask); */
22685                 PSU_Mask_Write (SATA_AHCI_VENDOR_PP4C_OFFSET ,0xFFFFFFFFU ,0x064A0813U);
22686         /*############################################################################################################################ */
22687
22688                 /*Register : PP5C @ 0XFD0C00B8</p>
22689
22690                 RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.
22691                 PSU_SATA_AHCI_VENDOR_PP5C_RIT                                                   0xC96A4
22692
22693                 RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
22694                  completed, for a fast SERDES it is suggested that this value be 54.2us / 4
22695                 PSU_SATA_AHCI_VENDOR_PP5C_RCT                                                   0x3FF
22696
22697                 PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po
22698                 t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
22699                 (OFFSET, MASK, VALUE)      (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U)
22700                 RegMask = (SATA_AHCI_VENDOR_PP5C_RIT_MASK | SATA_AHCI_VENDOR_PP5C_RCT_MASK |  0 );
22701
22702                 RegVal = ((0x000C96A4U << SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
22703                         | 0x000003FFU << SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
22704                         |  0 ) & RegMask); */
22705                 PSU_Mask_Write (SATA_AHCI_VENDOR_PP5C_OFFSET ,0xFFFFFFFFU ,0x3FFC96A4U);
22706         /*############################################################################################################################ */
22707
22708
22709   return 1;
22710 }
22711 unsigned long psu_resetin_init_data() {
22712                 // : PUTTING SERDES PERIPHERAL IN RESET
22713                 // : PUTTING USB0 IN RESET
22714                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
22715
22716                 USB 0 reset for control registers
22717                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X1
22718
22719                 USB 0 sleep circuit reset
22720                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X1
22721
22722                 USB 0 reset
22723                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X1
22724
22725                 Software control register for the LPD block.
22726                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000540U)
22727                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
22728
22729                 RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
22730                         | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
22731                         | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
22732                         |  0 ) & RegMask); */
22733                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U);
22734         /*############################################################################################################################ */
22735
22736                 // : PUTTING GEM0 IN RESET
22737                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
22738
22739                 GEM 3 reset
22740                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X1
22741
22742                 Software controlled reset for the GEMs
22743                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000008U)
22744                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
22745
22746                 RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
22747                         |  0 ) & RegMask); */
22748                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U);
22749         /*############################################################################################################################ */
22750
22751                 // : PUTTING SATA IN RESET
22752                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
22753
22754                 Sata block level reset
22755                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X1
22756
22757                 FPD Block level software controlled reset
22758                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000002U)
22759                 RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
22760
22761                 RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
22762                         |  0 ) & RegMask); */
22763                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U);
22764         /*############################################################################################################################ */
22765
22766                 // : PUTTING DP IN RESET
22767                 /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
22768
22769                 Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
22770                 ane0 Bits [3:2] - lane 1
22771                 PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0XA
22772
22773                 Control PHY Power down
22774                 (OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x0000000AU)
22775                 RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
22776
22777                 RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
22778                         |  0 ) & RegMask); */
22779                 PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU);
22780         /*############################################################################################################################ */
22781
22782                 /*Register : DP_PHY_RESET @ 0XFD4A0200</p>
22783
22784                 Set to '1' to hold the GT in reset. Clear to release.
22785                 PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X1
22786
22787                 Reset the transmitter PHY.
22788                 (OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000002U)
22789                 RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
22790
22791                 RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT
22792                         |  0 ) & RegMask); */
22793                 PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U);
22794         /*############################################################################################################################ */
22795
22796                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
22797
22798                 Display Port block level reset (includes DPDMA)
22799                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X1
22800
22801                 FPD Block level software controlled reset
22802                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00010000U)
22803                 RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
22804
22805                 RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
22806                         |  0 ) & RegMask); */
22807                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U);
22808         /*############################################################################################################################ */
22809
22810
22811   return 1;
22812 }
22813 unsigned long psu_ps_pl_isolation_removal_data() {
22814                 // : AFI RESET
22815                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
22816
22817                 AF_FM0 block level reset
22818                 PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET                                           0
22819
22820                 AF_FM1 block level reset
22821                 PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET                                           0
22822
22823                 AF_FM2 block level reset
22824                 PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET                                           0
22825
22826                 AF_FM3 block level reset
22827                 PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET                                           0
22828
22829                 AF_FM4 block level reset
22830                 PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET                                           0
22831
22832                 AF_FM5 block level reset
22833                 PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET                                           0
22834
22835                 FPD Block level software controlled reset
22836                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00001F80U ,0x00000000U)
22837                 RegMask = (CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK |  0 );
22838
22839                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT
22840                         | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT
22841                         | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT
22842                         | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT
22843                         | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT
22844                         | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT
22845                         |  0 ) & RegMask); */
22846                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00001F80U ,0x00000000U);
22847         /*############################################################################################################################ */
22848
22849                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
22850
22851                 AFI FM 6
22852                 PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET                                           0
22853
22854                 Software control register for the LPD block.
22855                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00080000U ,0x00000000U)
22856                 RegMask = (CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK |  0 );
22857
22858                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT
22859                         |  0 ) & RegMask); */
22860                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00080000U ,0x00000000U);
22861         /*############################################################################################################################ */
22862
22863                 // : AFIFM INTERFACE WIDTH
22864                 /*Register : afi_fs @ 0XFD615000</p>
22865
22866                 Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
22867                 : 128-bit AXI data width 11: reserved
22868                 PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL                                                  0x2
22869
22870                 Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
22871                 : 128-bit AXI data width 11: reserved
22872                 PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL                                                  0x2
22873
22874                 afi fs SLCR control register. This register is static and should not be modified during operation.
22875                 (OFFSET, MASK, VALUE)      (0XFD615000, 0x00000F00U ,0x00000A00U)
22876                 RegMask = (FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK | FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK |  0 );
22877
22878                 RegVal = ((0x00000002U << FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT
22879                         | 0x00000002U << FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT
22880                         |  0 ) & RegMask); */
22881                 PSU_Mask_Write (FPD_SLCR_AFI_FS_OFFSET ,0x00000F00U ,0x00000A00U);
22882         /*############################################################################################################################ */
22883
22884                 /*Register : afi_fs @ 0XFF419000</p>
22885
22886                 Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
22887                 : 128-bit AXI data width 11: reserved
22888                 PSU_LPD_SLCR_AFI_FS_DW_SS2_SEL                                                  0x2
22889
22890                 afi fs SLCR control register. Do not change the bits durin
22891                 (OFFSET, MASK, VALUE)      (0XFF419000, 0x00000300U ,0x00000200U)
22892                 RegMask = (LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK |  0 );
22893
22894                 RegVal = ((0x00000002U << LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT
22895                         |  0 ) & RegMask); */
22896                 PSU_Mask_Write (LPD_SLCR_AFI_FS_OFFSET ,0x00000300U ,0x00000200U);
22897         /*############################################################################################################################ */
22898
22899                 /*Register : AFIFM_RDCTRL @ 0XFD360000</p>
22900
22901                 Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
22902                 bit enabled
22903                 PSU_AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH                                            0x0
22904
22905                 Read Channel Control Register
22906                 (OFFSET, MASK, VALUE)      (0XFD360000, 0x00000003U ,0x00000000U)
22907                 RegMask = (AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_MASK |  0 );
22908
22909                 RegVal = ((0x00000000U << AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
22910                         |  0 ) & RegMask); */
22911                 PSU_Mask_Write (AFIFM0_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
22912         /*############################################################################################################################ */
22913
22914                 /*Register : AFIFM_RDCTRL @ 0XFD370000</p>
22915
22916                 Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
22917                 bit enabled
22918                 PSU_AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH                                            0x0
22919
22920                 Read Channel Control Register
22921                 (OFFSET, MASK, VALUE)      (0XFD370000, 0x00000003U ,0x00000000U)
22922                 RegMask = (AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_MASK |  0 );
22923
22924                 RegVal = ((0x00000000U << AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
22925                         |  0 ) & RegMask); */
22926                 PSU_Mask_Write (AFIFM1_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
22927         /*############################################################################################################################ */
22928
22929                 /*Register : AFIFM_RDCTRL @ 0XFD380000</p>
22930
22931                 Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
22932                 bit enabled
22933                 PSU_AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH                                            0x0
22934
22935                 Read Channel Control Register
22936                 (OFFSET, MASK, VALUE)      (0XFD380000, 0x00000003U ,0x00000000U)
22937                 RegMask = (AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK |  0 );
22938
22939                 RegVal = ((0x00000000U << AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
22940                         |  0 ) & RegMask); */
22941                 PSU_Mask_Write (AFIFM2_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
22942         /*############################################################################################################################ */
22943
22944                 /*Register : AFIFM_RDCTRL @ 0XFD390000</p>
22945
22946                 Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
22947                 bit enabled
22948                 PSU_AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH                                            0x0
22949
22950                 Read Channel Control Register
22951                 (OFFSET, MASK, VALUE)      (0XFD390000, 0x00000003U ,0x00000000U)
22952                 RegMask = (AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_MASK |  0 );
22953
22954                 RegVal = ((0x00000000U << AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
22955                         |  0 ) & RegMask); */
22956                 PSU_Mask_Write (AFIFM3_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
22957         /*############################################################################################################################ */
22958
22959                 /*Register : AFIFM_RDCTRL @ 0XFD3A0000</p>
22960
22961                 Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
22962                 bit enabled
22963                 PSU_AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH                                            0x0
22964
22965                 Read Channel Control Register
22966                 (OFFSET, MASK, VALUE)      (0XFD3A0000, 0x00000003U ,0x00000000U)
22967                 RegMask = (AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_MASK |  0 );
22968
22969                 RegVal = ((0x00000000U << AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
22970                         |  0 ) & RegMask); */
22971                 PSU_Mask_Write (AFIFM4_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
22972         /*############################################################################################################################ */
22973
22974                 /*Register : AFIFM_RDCTRL @ 0XFD3B0000</p>
22975
22976                 Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
22977                 bit enabled
22978                 PSU_AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH                                            0x0
22979
22980                 Read Channel Control Register
22981                 (OFFSET, MASK, VALUE)      (0XFD3B0000, 0x00000003U ,0x00000000U)
22982                 RegMask = (AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_MASK |  0 );
22983
22984                 RegVal = ((0x00000000U << AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
22985                         |  0 ) & RegMask); */
22986                 PSU_Mask_Write (AFIFM5_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
22987         /*############################################################################################################################ */
22988
22989                 /*Register : AFIFM_RDCTRL @ 0XFF9B0000</p>
22990
22991                 Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
22992                 bit enabled
22993                 PSU_AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH                                            0x0
22994
22995                 Read Channel Control Register
22996                 (OFFSET, MASK, VALUE)      (0XFF9B0000, 0x00000003U ,0x00000000U)
22997                 RegMask = (AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_MASK |  0 );
22998
22999                 RegVal = ((0x00000000U << AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
23000                         |  0 ) & RegMask); */
23001                 PSU_Mask_Write (AFIFM6_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
23002         /*############################################################################################################################ */
23003
23004                 /*Register : AFIFM_WRCTRL @ 0XFD360014</p>
23005
23006                 Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
23007                 -bit enabled
23008                 PSU_AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH                                            0x0
23009
23010                 Write Channel Control Register
23011                 (OFFSET, MASK, VALUE)      (0XFD360014, 0x00000003U ,0x00000000U)
23012                 RegMask = (AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_MASK |  0 );
23013
23014                 RegVal = ((0x00000000U << AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
23015                         |  0 ) & RegMask); */
23016                 PSU_Mask_Write (AFIFM0_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
23017         /*############################################################################################################################ */
23018
23019                 /*Register : AFIFM_WRCTRL @ 0XFD370014</p>
23020
23021                 Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
23022                 -bit enabled
23023                 PSU_AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH                                            0x0
23024
23025                 Write Channel Control Register
23026                 (OFFSET, MASK, VALUE)      (0XFD370014, 0x00000003U ,0x00000000U)
23027                 RegMask = (AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_MASK |  0 );
23028
23029                 RegVal = ((0x00000000U << AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
23030                         |  0 ) & RegMask); */
23031                 PSU_Mask_Write (AFIFM1_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
23032         /*############################################################################################################################ */
23033
23034                 /*Register : AFIFM_WRCTRL @ 0XFD380014</p>
23035
23036                 Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
23037                 -bit enabled
23038                 PSU_AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH                                            0x0
23039
23040                 Write Channel Control Register
23041                 (OFFSET, MASK, VALUE)      (0XFD380014, 0x00000003U ,0x00000000U)
23042                 RegMask = (AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK |  0 );
23043
23044                 RegVal = ((0x00000000U << AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
23045                         |  0 ) & RegMask); */
23046                 PSU_Mask_Write (AFIFM2_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
23047         /*############################################################################################################################ */
23048
23049                 /*Register : AFIFM_WRCTRL @ 0XFD390014</p>
23050
23051                 Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
23052                 -bit enabled
23053                 PSU_AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH                                            0x0
23054
23055                 Write Channel Control Register
23056                 (OFFSET, MASK, VALUE)      (0XFD390014, 0x00000003U ,0x00000000U)
23057                 RegMask = (AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_MASK |  0 );
23058
23059                 RegVal = ((0x00000000U << AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
23060                         |  0 ) & RegMask); */
23061                 PSU_Mask_Write (AFIFM3_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
23062         /*############################################################################################################################ */
23063
23064                 /*Register : AFIFM_WRCTRL @ 0XFD3A0014</p>
23065
23066                 Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
23067                 -bit enabled
23068                 PSU_AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH                                            0x0
23069
23070                 Write Channel Control Register
23071                 (OFFSET, MASK, VALUE)      (0XFD3A0014, 0x00000003U ,0x00000000U)
23072                 RegMask = (AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_MASK |  0 );
23073
23074                 RegVal = ((0x00000000U << AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
23075                         |  0 ) & RegMask); */
23076                 PSU_Mask_Write (AFIFM4_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
23077         /*############################################################################################################################ */
23078
23079                 /*Register : AFIFM_WRCTRL @ 0XFD3B0014</p>
23080
23081                 Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
23082                 -bit enabled
23083                 PSU_AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH                                            0x0
23084
23085                 Write Channel Control Register
23086                 (OFFSET, MASK, VALUE)      (0XFD3B0014, 0x00000003U ,0x00000000U)
23087                 RegMask = (AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_MASK |  0 );
23088
23089                 RegVal = ((0x00000000U << AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
23090                         |  0 ) & RegMask); */
23091                 PSU_Mask_Write (AFIFM5_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
23092         /*############################################################################################################################ */
23093
23094                 /*Register : AFIFM_WRCTRL @ 0XFF9B0014</p>
23095
23096                 Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
23097                 -bit enabled
23098                 PSU_AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH                                            0x0
23099
23100                 Write Channel Control Register
23101                 (OFFSET, MASK, VALUE)      (0XFF9B0014, 0x00000003U ,0x00000000U)
23102                 RegMask = (AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_MASK |  0 );
23103
23104                 RegVal = ((0x00000000U << AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
23105                         |  0 ) & RegMask); */
23106                 PSU_Mask_Write (AFIFM6_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
23107         /*############################################################################################################################ */
23108
23109                 // : PS-PL POWER UP REQUEST
23110                 /*Register : REQ_PWRUP_INT_EN @ 0XFFD80118</p>
23111
23112                 Power-up Request Interrupt Enable for PL
23113                 PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL                                              1
23114
23115                 Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt.
23116                 (OFFSET, MASK, VALUE)      (0XFFD80118, 0x00800000U ,0x00800000U)
23117                 RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK |  0 );
23118
23119                 RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
23120                         |  0 ) & RegMask); */
23121                 PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U);
23122         /*############################################################################################################################ */
23123
23124                 /*Register : REQ_PWRUP_TRIG @ 0XFFD80120</p>
23125
23126                 Power-up Request Trigger for PL
23127                 PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL                                                1
23128
23129                 Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU.
23130                 (OFFSET, MASK, VALUE)      (0XFFD80120, 0x00800000U ,0x00800000U)
23131                 RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK |  0 );
23132
23133                 RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
23134                         |  0 ) & RegMask); */
23135                 PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U);
23136         /*############################################################################################################################ */
23137
23138                 // : POLL ON PL POWER STATUS
23139                 /*Register : REQ_PWRUP_STATUS @ 0XFFD80110</p>
23140
23141                 Power-up Request Status for PL
23142                 PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL                                              1
23143                 (OFFSET, MASK, VALUE)      (0XFFD80110, 0x00800000U ,0x00000000U)  */
23144                 mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U);
23145
23146         /*############################################################################################################################ */
23147
23148
23149   return 1;
23150 }
23151 unsigned long psu_ps_pl_reset_config_data() {
23152                 // : PS PL RESET SEQUENCE
23153                 // : FABRIC RESET USING EMIO
23154                 /*Register : MASK_DATA_5_MSW @ 0XFF0A002C</p>
23155
23156                 Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
23157                 PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW                                             0x8000
23158
23159                 Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
23160                 (OFFSET, MASK, VALUE)      (0XFF0A002C, 0xFFFF0000U ,0x80000000U)
23161                 RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK |  0 );
23162
23163                 RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
23164                         |  0 ) & RegMask); */
23165                 PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U);
23166         /*############################################################################################################################ */
23167
23168                 /*Register : DIRM_5 @ 0XFF0A0344</p>
23169
23170                 Operation is the same as DIRM_0[DIRECTION_0]
23171                 PSU_GPIO_DIRM_5_DIRECTION_5                                                     0x80000000
23172
23173                 Direction mode (GPIO Bank5, EMIO)
23174                 (OFFSET, MASK, VALUE)      (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U)
23175                 RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK |  0 );
23176
23177                 RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT
23178                         |  0 ) & RegMask); */
23179                 PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
23180         /*############################################################################################################################ */
23181
23182                 /*Register : OEN_5 @ 0XFF0A0348</p>
23183
23184                 Operation is the same as OEN_0[OP_ENABLE_0]
23185                 PSU_GPIO_OEN_5_OP_ENABLE_5                                                      0x80000000
23186
23187                 Output enable (GPIO Bank5, EMIO)
23188                 (OFFSET, MASK, VALUE)      (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U)
23189                 RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK |  0 );
23190
23191                 RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT
23192                         |  0 ) & RegMask); */
23193                 PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
23194         /*############################################################################################################################ */
23195
23196                 /*Register : DATA_5 @ 0XFF0A0054</p>
23197
23198                 Output Data
23199                 PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
23200
23201                 Output Data (GPIO Bank5, EMIO)
23202                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
23203                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
23204
23205                 RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
23206                         |  0 ) & RegMask); */
23207                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
23208         /*############################################################################################################################ */
23209
23210                 mask_delay(1);
23211
23212         /*############################################################################################################################ */
23213
23214                 // : FABRIC RESET USING DATA_5 TOGGLE
23215                 /*Register : DATA_5 @ 0XFF0A0054</p>
23216
23217                 Output Data
23218                 PSU_GPIO_DATA_5_DATA_5                                                          0X00000000
23219
23220                 Output Data (GPIO Bank5, EMIO)
23221                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U)
23222                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
23223
23224                 RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT
23225                         |  0 ) & RegMask); */
23226                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U);
23227         /*############################################################################################################################ */
23228
23229                 mask_delay(1);
23230
23231         /*############################################################################################################################ */
23232
23233                 // : FABRIC RESET USING DATA_5 TOGGLE
23234                 /*Register : DATA_5 @ 0XFF0A0054</p>
23235
23236                 Output Data
23237                 PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
23238
23239                 Output Data (GPIO Bank5, EMIO)
23240                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
23241                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
23242
23243                 RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
23244                         |  0 ) & RegMask); */
23245                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
23246         /*############################################################################################################################ */
23247
23248
23249   return 1;
23250 }
23251
23252 unsigned long psu_ddr_phybringup_data() {
23253
23254
23255                 unsigned int regval = 0;
23256         int dpll_divisor;
23257         dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U;
23258         prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U);
23259         prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
23260         Xil_Out32(0xFD080004U, 0x00040003U);
23261         while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
23262         prog_reg (0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U);
23263         prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U);
23264         prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U);
23265         prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U);
23266         prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor);
23267         Xil_Out32(0xFD080004U, 0x40040071U);
23268         while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
23269         Xil_Out32(0xFD080004U, 0x40040001U);
23270         while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
23271         // PHY BRINGUP SEQ
23272         while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU);
23273         prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
23274         //poll for PHY initialization to complete
23275         while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU);
23276
23277         Xil_Out32(0xFD0701B0U, 0x00000001U);
23278         Xil_Out32(0xFD070320U, 0x00000001U);
23279         while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U);
23280         prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
23281          Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR
23282           regval = Xil_In32(0xFD080030); //PUB_PGSR0
23283           while(regval != 0x80000FFF){
23284              regval = Xil_In32(0xFD080030); //PUB_PGSR0
23285           }
23286
23287
23288  // Run Vref training in static read mode
23289         Xil_Out32(0xFD080200U, 0x100091C7U);
23290         Xil_Out32(0xFD080018U, 0x00F01EF2U);
23291         Xil_Out32(0xFD08001CU, 0x55AA5498U);
23292         Xil_Out32(0xFD08142CU, 0x00041830U);
23293         Xil_Out32(0xFD08146CU, 0x00041830U);
23294         Xil_Out32(0xFD0814ACU, 0x00041830U);
23295         Xil_Out32(0xFD0814ECU, 0x00041830U);
23296         Xil_Out32(0xFD08152CU, 0x00041830U);
23297
23298
23299          Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR
23300           regval = Xil_In32(0xFD080030); //PUB_PGSR0
23301           while((regval & 0x80004001) != 0x80004001){
23302              regval = Xil_In32(0xFD080030); //PUB_PGSR0
23303           }
23304
23305          // Vref training is complete, disabling static read mode
23306         Xil_Out32(0xFD080200U, 0x800091C7U);
23307         Xil_Out32(0xFD080018U, 0x00F12302U);
23308         Xil_Out32(0xFD08001CU, 0x55AA5480U);
23309         Xil_Out32(0xFD08142CU, 0x00041800U);
23310         Xil_Out32(0xFD08146CU, 0x00041800U);
23311         Xil_Out32(0xFD0814ACU, 0x00041800U);
23312         Xil_Out32(0xFD0814ECU, 0x00041800U);
23313         Xil_Out32(0xFD08152CU, 0x00041800U);
23314
23315
23316          Xil_Out32(0xFD080004, 0x0000C001); //PUB_PIR
23317           regval = Xil_In32(0xFD080030); //PUB_PGSR0
23318           while((regval & 0x80000C01) != 0x80000C01){
23319              regval = Xil_In32(0xFD080030); //PUB_PGSR0
23320           }
23321
23322         Xil_Out32(0xFD070180U, 0x01000040U);
23323         Xil_Out32(0xFD070060U, 0x00000000U);
23324         prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
23325
23326 return 1;
23327 }
23328
23329 /**
23330  * CRL_APB Base Address
23331  */
23332 #define CRL_APB_BASEADDR      0XFF5E0000U
23333 #define CRL_APB_RST_LPD_IOU0    ( ( CRL_APB_BASEADDR ) + 0X00000230U )
23334 #define CRL_APB_RST_LPD_IOU1    ( ( CRL_APB_BASEADDR ) + 0X00000234U )
23335 #define CRL_APB_RST_LPD_IOU2    ( ( CRL_APB_BASEADDR ) + 0X00000238U )
23336 #define CRL_APB_RST_LPD_TOP    ( ( CRL_APB_BASEADDR ) + 0X0000023CU )
23337 #define CRL_APB_IOU_SWITCH_CTRL    ( ( CRL_APB_BASEADDR ) + 0X0000009CU )
23338
23339 /**
23340  * CRF_APB Base Address
23341  */
23342 #define CRF_APB_BASEADDR      0XFD1A0000U
23343
23344 #define CRF_APB_RST_FPD_TOP    ( ( CRF_APB_BASEADDR ) + 0X00000100U )
23345 #define CRF_APB_GPU_REF_CTRL    ( ( CRF_APB_BASEADDR ) + 0X00000084U )
23346 #define CRF_APB_RST_DDR_SS    ( ( CRF_APB_BASEADDR ) + 0X00000108U )
23347 #define PSU_MASK_POLL_TIME 1100000
23348
23349
23350 int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
23351         volatile u32 *addr = (volatile u32*)(unsigned long) add;
23352         int i = 0;
23353         while ((*addr & mask)!= value) {
23354                 if (i == PSU_MASK_POLL_TIME) {
23355                         return 0;
23356                 }
23357                 i++;
23358         }
23359         return 1;
23360         //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
23361 }
23362
23363 int mask_poll(u32 add , u32 mask) {
23364         volatile u32 *addr = (volatile u32*)(unsigned long) add;
23365         int i = 0;
23366         while (!(*addr & mask)) {
23367                 if (i == PSU_MASK_POLL_TIME) {
23368                         return 0;
23369                 }
23370                 i++;
23371         }
23372         return 1;
23373         //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
23374 }
23375
23376 void mask_delay(u32 delay) {
23377     usleep (delay);
23378 }
23379
23380 u32 mask_read(u32 add , u32 mask ) {
23381         volatile u32 *addr = (volatile u32*)(unsigned long) add;
23382         u32 val = (*addr & mask);
23383         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
23384         return val;
23385 }
23386
23387
23388 //Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES.
23389 //These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are
23390 //required for current silicon version and are likely to undergo further changes with subsequent silicon versions.
23391
23392
23393
23394 int serdes_fixcal_code() {
23395         int MaskStatus = 1;
23396
23397    // L3_TM_CALIB_DIG19
23398    Xil_Out32(0xFD40EC4C,0x00000020);
23399    //ICM_CFG0
23400    Xil_Out32(0xFD410010,0x00000001);
23401
23402    //is calibration done, polling on L3_CALIB_DONE_STATUS
23403    MaskStatus = mask_poll(0xFD40EF14, 0x2);
23404
23405    if (MaskStatus == 0)
23406    {
23407         xil_printf("SERDES initialization timed out\n\r");
23408    }
23409
23410    unsigned int tmp_0_1;
23411    tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
23412
23413    unsigned int tmp_0_2 = tmp_0_1 & (0x7);
23414    unsigned int tmp_0_3 = tmp_0_1 & (0x38);
23415    //Configure ICM for de-asserting CMN_Resetn
23416    Xil_Out32(0xFD410010,0x00000000);
23417    Xil_Out32(0xFD410014,0x00000000);
23418
23419    unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1);
23420    tmp_0_2_mod = (tmp_0_2_mod <<4);
23421
23422    tmp_0_3 = tmp_0_3 >>3;
23423    Xil_Out32(0xFD40EC4C,tmp_0_3);
23424
23425    //L3_TM_CALIB_DIG18
23426    Xil_Out32(0xFD40EC48,tmp_0_2_mod);
23427    return MaskStatus;
23428
23429
23430 }
23431
23432 int serdes_enb_coarse_saturation() {
23433   //Enable PLL Coarse Code saturation Logic
23434    Xil_Out32(0xFD402094,0x00000010);
23435    Xil_Out32(0xFD406094,0x00000010);
23436    Xil_Out32(0xFD40A094,0x00000010);
23437    Xil_Out32(0xFD40E094,0x00000010);
23438    return 1;
23439 }
23440
23441 int init_serdes() {
23442         int status = 1;
23443         status &=  psu_resetin_init_data();
23444
23445         status &= serdes_fixcal_code();
23446         status &= serdes_enb_coarse_saturation();
23447
23448     status &=  psu_serdes_init_data();
23449         status &=  psu_resetout_init_data();
23450
23451         return status;
23452 }
23453
23454
23455
23456
23457
23458
23459 void init_peripheral()
23460 {
23461         unsigned int RegValue;
23462
23463         /* Turn on IOU Clock */
23464         //Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500);
23465
23466         /* Release all resets in the IOU */
23467         Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000);
23468         Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000);
23469         Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000);
23470
23471         /* Activate GPU clocks */
23472         //Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500);
23473
23474         /* Take LPD out of reset except R5 */
23475         RegValue = Xil_In32(CRL_APB_RST_LPD_TOP);
23476         RegValue &= 0x7;
23477         Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue);
23478
23479         /* Take most of FPD out of reset */
23480         Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000);
23481
23482         /* Making DPDMA as secure */
23483   unsigned int tmp_regval;
23484   tmp_regval = Xil_In32(0xFD690040);
23485   tmp_regval &= ~0x00000001;
23486   Xil_Out32(0xFD690040, tmp_regval);
23487
23488         /* Making PCIe as secure */
23489   tmp_regval = Xil_In32(0xFD690030);
23490   tmp_regval &= ~0x00000001;
23491   Xil_Out32(0xFD690030, tmp_regval);
23492 }
23493
23494 int psu_init_xppu_aper_ram() {
23495         unsigned long APER_OFFSET = 0xFF981000;
23496         int i = 0;
23497         for (; i <= 400; i++) {
23498                 PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U);
23499                 APER_OFFSET = APER_OFFSET + 0x4;
23500         }
23501
23502         return 0;
23503 }
23504
23505 int psu_lpd_protection() {
23506    psu_init_xppu_aper_ram();
23507    psu_lpd_xppu_data();
23508    return 0;
23509 }
23510
23511 int psu_ddr_protection() {
23512    psu_ddr_xmpu0_data();
23513    psu_ddr_xmpu1_data();
23514    psu_ddr_xmpu2_data();
23515    psu_ddr_xmpu3_data();
23516    psu_ddr_xmpu4_data();
23517    psu_ddr_xmpu5_data();
23518    return 0;
23519 }
23520 int psu_ocm_protection() {
23521    psu_ocm_xmpu_data();
23522    return 0;
23523 }
23524
23525 int psu_fpd_protection() {
23526    psu_fpd_xmpu_data();
23527    return 0;
23528 }
23529
23530 int psu_protection_lock() {
23531   psu_protection_lock_data();
23532   return 0;
23533 }
23534
23535 int psu_protection() {
23536   psu_ddr_protection();
23537   psu_ocm_protection();
23538   psu_fpd_protection();
23539   psu_lpd_protection();
23540   return 0;
23541 }
23542
23543
23544
23545 int
23546 psu_init()
23547 {
23548         int status = 1;
23549         status &= psu_mio_init_data ();
23550         status &=   psu_pll_init_data ();
23551         status &=   psu_clock_init_data ();
23552
23553         status &=  psu_ddr_init_data ();
23554         status &=  psu_ddr_phybringup_data ();
23555         status &=  psu_peripherals_init_data ();
23556
23557         status &=  init_serdes();
23558         init_peripheral ();
23559
23560         status &=  psu_peripherals_powerdwn_data ();
23561
23562         if (status == 0) {
23563                 return 1;
23564         }
23565         return 0;
23566 }