git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.h

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 *  This program is free software; you can redistribute it and/or modify
   6 *  it under the terms of the GNU General Public License as published by
   7 *  the Free Software Foundation; either version 2 of the License, or
   8 *  (at your option) any later version.
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 *  You should have received a copy of the GNU General Public License along
  16 *  with this program; if not, see <http://www.gnu.org/licenses/>
  17 *
  18 *
  19 ******************************************************************************/
  20 /****************************************************************************/
  21 /**
  22 *
  23 * @file psu_init_gpl.h
  24 *
  25 * This file is automatically generated
  26 *
  27 *****************************************************************************/
  28
  29
  30 #undef CRL_APB_RPLL_CFG_OFFSET
  31 #define CRL_APB_RPLL_CFG_OFFSET                                                    0XFF5E0034
  32 #undef CRL_APB_RPLL_CTRL_OFFSET
  33 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  34 #undef CRL_APB_RPLL_CTRL_OFFSET
  35 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  36 #undef CRL_APB_RPLL_CTRL_OFFSET
  37 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  38 #undef CRL_APB_RPLL_CTRL_OFFSET
  39 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  40 #undef CRL_APB_RPLL_CTRL_OFFSET
  41 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  42 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET
  43 #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
  44 #undef CRL_APB_RPLL_FRAC_CFG_OFFSET
  45 #define CRL_APB_RPLL_FRAC_CFG_OFFSET                                               0XFF5E0038
  46 #undef CRL_APB_IOPLL_CFG_OFFSET
  47 #define CRL_APB_IOPLL_CFG_OFFSET                                                   0XFF5E0024
  48 #undef CRL_APB_IOPLL_CTRL_OFFSET
  49 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  50 #undef CRL_APB_IOPLL_CTRL_OFFSET
  51 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  52 #undef CRL_APB_IOPLL_CTRL_OFFSET
  53 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  54 #undef CRL_APB_IOPLL_CTRL_OFFSET
  55 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  56 #undef CRL_APB_IOPLL_CTRL_OFFSET
  57 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  58 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET
  59 #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
  60 #undef CRL_APB_IOPLL_FRAC_CFG_OFFSET
  61 #define CRL_APB_IOPLL_FRAC_CFG_OFFSET                                              0XFF5E0028
  62 #undef CRF_APB_APLL_CFG_OFFSET
  63 #define CRF_APB_APLL_CFG_OFFSET                                                    0XFD1A0024
  64 #undef CRF_APB_APLL_CTRL_OFFSET
  65 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  66 #undef CRF_APB_APLL_CTRL_OFFSET
  67 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  68 #undef CRF_APB_APLL_CTRL_OFFSET
  69 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  70 #undef CRF_APB_APLL_CTRL_OFFSET
  71 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  72 #undef CRF_APB_APLL_CTRL_OFFSET
  73 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  74 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET
  75 #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
  76 #undef CRF_APB_APLL_FRAC_CFG_OFFSET
  77 #define CRF_APB_APLL_FRAC_CFG_OFFSET                                               0XFD1A0028
  78 #undef CRF_APB_DPLL_CFG_OFFSET
  79 #define CRF_APB_DPLL_CFG_OFFSET                                                    0XFD1A0030
  80 #undef CRF_APB_DPLL_CTRL_OFFSET
  81 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
  82 #undef CRF_APB_DPLL_CTRL_OFFSET
  83 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
  84 #undef CRF_APB_DPLL_CTRL_OFFSET
  85 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
  86 #undef CRF_APB_DPLL_CTRL_OFFSET
  87 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
  88 #undef CRF_APB_DPLL_CTRL_OFFSET
  89 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
  90 #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET
  91 #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
  92 #undef CRF_APB_DPLL_FRAC_CFG_OFFSET
  93 #define CRF_APB_DPLL_FRAC_CFG_OFFSET                                               0XFD1A0034
  94 #undef CRF_APB_VPLL_CFG_OFFSET
  95 #define CRF_APB_VPLL_CFG_OFFSET                                                    0XFD1A003C
  96 #undef CRF_APB_VPLL_CTRL_OFFSET
  97 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
  98 #undef CRF_APB_VPLL_CTRL_OFFSET
  99 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 100 #undef CRF_APB_VPLL_CTRL_OFFSET
 101 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 102 #undef CRF_APB_VPLL_CTRL_OFFSET
 103 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 104 #undef CRF_APB_VPLL_CTRL_OFFSET
 105 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 106 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET
 107 #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050
 108 #undef CRF_APB_VPLL_FRAC_CFG_OFFSET
 109 #define CRF_APB_VPLL_FRAC_CFG_OFFSET                                               0XFD1A0040
 110
 111 /*PLL loop filter resistor control*/
 112 #undef CRL_APB_RPLL_CFG_RES_DEFVAL
 113 #undef CRL_APB_RPLL_CFG_RES_SHIFT
 114 #undef CRL_APB_RPLL_CFG_RES_MASK
 115 #define CRL_APB_RPLL_CFG_RES_DEFVAL                                                0x00000000
 116 #define CRL_APB_RPLL_CFG_RES_SHIFT                                                 0
 117 #define CRL_APB_RPLL_CFG_RES_MASK                                                  0x0000000FU
 118
 119 /*PLL charge pump control*/
 120 #undef CRL_APB_RPLL_CFG_CP_DEFVAL
 121 #undef CRL_APB_RPLL_CFG_CP_SHIFT
 122 #undef CRL_APB_RPLL_CFG_CP_MASK
 123 #define CRL_APB_RPLL_CFG_CP_DEFVAL                                                 0x00000000
 124 #define CRL_APB_RPLL_CFG_CP_SHIFT                                                  5
 125 #define CRL_APB_RPLL_CFG_CP_MASK                                                   0x000001E0U
 126
 127 /*PLL loop filter high frequency capacitor control*/
 128 #undef CRL_APB_RPLL_CFG_LFHF_DEFVAL
 129 #undef CRL_APB_RPLL_CFG_LFHF_SHIFT
 130 #undef CRL_APB_RPLL_CFG_LFHF_MASK
 131 #define CRL_APB_RPLL_CFG_LFHF_DEFVAL                                               0x00000000
 132 #define CRL_APB_RPLL_CFG_LFHF_SHIFT                                                10
 133 #define CRL_APB_RPLL_CFG_LFHF_MASK                                                 0x00000C00U
 134
 135 /*Lock circuit counter setting*/
 136 #undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL
 137 #undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
 138 #undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK
 139 #define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
 140 #define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT                                            13
 141 #define CRL_APB_RPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
 142
 143 /*Lock circuit configuration settings for lock windowsize*/
 144 #undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL
 145 #undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
 146 #undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK
 147 #define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
 148 #define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT                                            25
 149 #define CRL_APB_RPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
 150
 151 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 152                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 153 #undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL
 154 #undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
 155 #undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK
 156 #define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL                                           0x00012C09
 157 #define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT                                            20
 158 #define CRL_APB_RPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
 159
 160 /*The integer portion of the feedback divider to the PLL*/
 161 #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL
 162 #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT
 163 #undef CRL_APB_RPLL_CTRL_FBDIV_MASK
 164 #define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
 165 #define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                                              8
 166 #define CRL_APB_RPLL_CTRL_FBDIV_MASK                                               0x00007F00U
 167
 168 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 169 #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL
 170 #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT
 171 #undef CRL_APB_RPLL_CTRL_DIV2_MASK
 172 #define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                                              0x00012C09
 173 #define CRL_APB_RPLL_CTRL_DIV2_SHIFT                                               16
 174 #define CRL_APB_RPLL_CTRL_DIV2_MASK                                                0x00010000U
 175
 176 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 177                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 178 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
 179 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 180 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
 181 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
 182 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
 183 #define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
 184
 185 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 186 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
 187 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
 188 #undef CRL_APB_RPLL_CTRL_RESET_MASK
 189 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
 190 #define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
 191 #define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
 192
 193 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 194 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
 195 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
 196 #undef CRL_APB_RPLL_CTRL_RESET_MASK
 197 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
 198 #define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
 199 #define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
 200
 201 /*RPLL is locked*/
 202 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL
 203 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT
 204 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK
 205 #define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                                        0x00000018
 206 #define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                                         1
 207 #define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                                          0x00000002U
 208 #define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
 209
 210 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 211                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 212 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
 213 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 214 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
 215 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
 216 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
 217 #define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
 218
 219 /*Divisor value for this clock.*/
 220 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
 221 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 222 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK
 223 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
 224 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                    8
 225 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
 226
 227 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 228                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 229 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL
 230 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
 231 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK
 232 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
 233 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT                                        31
 234 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
 235
 236 /*Fractional value for the Feedback value.*/
 237 #undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL
 238 #undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
 239 #undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK
 240 #define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
 241 #define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT                                           0
 242 #define CRL_APB_RPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
 243
 244 /*PLL loop filter resistor control*/
 245 #undef CRL_APB_IOPLL_CFG_RES_DEFVAL
 246 #undef CRL_APB_IOPLL_CFG_RES_SHIFT
 247 #undef CRL_APB_IOPLL_CFG_RES_MASK
 248 #define CRL_APB_IOPLL_CFG_RES_DEFVAL                                               0x00000000
 249 #define CRL_APB_IOPLL_CFG_RES_SHIFT                                                0
 250 #define CRL_APB_IOPLL_CFG_RES_MASK                                                 0x0000000FU
 251
 252 /*PLL charge pump control*/
 253 #undef CRL_APB_IOPLL_CFG_CP_DEFVAL
 254 #undef CRL_APB_IOPLL_CFG_CP_SHIFT
 255 #undef CRL_APB_IOPLL_CFG_CP_MASK
 256 #define CRL_APB_IOPLL_CFG_CP_DEFVAL                                                0x00000000
 257 #define CRL_APB_IOPLL_CFG_CP_SHIFT                                                 5
 258 #define CRL_APB_IOPLL_CFG_CP_MASK                                                  0x000001E0U
 259
 260 /*PLL loop filter high frequency capacitor control*/
 261 #undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL
 262 #undef CRL_APB_IOPLL_CFG_LFHF_SHIFT
 263 #undef CRL_APB_IOPLL_CFG_LFHF_MASK
 264 #define CRL_APB_IOPLL_CFG_LFHF_DEFVAL                                              0x00000000
 265 #define CRL_APB_IOPLL_CFG_LFHF_SHIFT                                               10
 266 #define CRL_APB_IOPLL_CFG_LFHF_MASK                                                0x00000C00U
 267
 268 /*Lock circuit counter setting*/
 269 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL
 270 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
 271 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK
 272 #define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL                                          0x00000000
 273 #define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT                                           13
 274 #define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK                                            0x007FE000U
 275
 276 /*Lock circuit configuration settings for lock windowsize*/
 277 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL
 278 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
 279 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK
 280 #define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL                                          0x00000000
 281 #define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT                                           25
 282 #define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK                                            0xFE000000U
 283
 284 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 285                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 286 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL
 287 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
 288 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK
 289 #define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL                                          0x00012C09
 290 #define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT                                           20
 291 #define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK                                            0x00700000U
 292
 293 /*The integer portion of the feedback divider to the PLL*/
 294 #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL
 295 #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
 296 #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK
 297 #define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                                            0x00012C09
 298 #define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                                             8
 299 #define CRL_APB_IOPLL_CTRL_FBDIV_MASK                                              0x00007F00U
 300
 301 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 302 #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL
 303 #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT
 304 #undef CRL_APB_IOPLL_CTRL_DIV2_MASK
 305 #define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                                             0x00012C09
 306 #define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                                              16
 307 #define CRL_APB_IOPLL_CTRL_DIV2_MASK                                               0x00010000U
 308
 309 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 310                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 311 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
 312 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 313 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
 314 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
 315 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
 316 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
 317
 318 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 319 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
 320 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
 321 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
 322 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
 323 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
 324 #define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
 325
 326 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 327 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
 328 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
 329 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
 330 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
 331 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
 332 #define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
 333
 334 /*IOPLL is locked*/
 335 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL
 336 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT
 337 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK
 338 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                                       0x00000018
 339 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                                        0
 340 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                                         0x00000001U
 341 #define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
 342
 343 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 344                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 345 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
 346 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 347 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
 348 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
 349 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
 350 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
 351
 352 /*Divisor value for this clock.*/
 353 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
 354 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 355 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK
 356 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                  0x00000400
 357 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                   8
 358 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                                    0x00003F00U
 359
 360 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 361                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 362 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL
 363 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
 364 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK
 365 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL                                      0x00000000
 366 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT                                       31
 367 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK                                        0x80000000U
 368
 369 /*Fractional value for the Feedback value.*/
 370 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL
 371 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
 372 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK
 373 #define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL                                         0x00000000
 374 #define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT                                          0
 375 #define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK                                           0x0000FFFFU
 376
 377 /*PLL loop filter resistor control*/
 378 #undef CRF_APB_APLL_CFG_RES_DEFVAL
 379 #undef CRF_APB_APLL_CFG_RES_SHIFT
 380 #undef CRF_APB_APLL_CFG_RES_MASK
 381 #define CRF_APB_APLL_CFG_RES_DEFVAL                                                0x00000000
 382 #define CRF_APB_APLL_CFG_RES_SHIFT                                                 0
 383 #define CRF_APB_APLL_CFG_RES_MASK                                                  0x0000000FU
 384
 385 /*PLL charge pump control*/
 386 #undef CRF_APB_APLL_CFG_CP_DEFVAL
 387 #undef CRF_APB_APLL_CFG_CP_SHIFT
 388 #undef CRF_APB_APLL_CFG_CP_MASK
 389 #define CRF_APB_APLL_CFG_CP_DEFVAL                                                 0x00000000
 390 #define CRF_APB_APLL_CFG_CP_SHIFT                                                  5
 391 #define CRF_APB_APLL_CFG_CP_MASK                                                   0x000001E0U
 392
 393 /*PLL loop filter high frequency capacitor control*/
 394 #undef CRF_APB_APLL_CFG_LFHF_DEFVAL
 395 #undef CRF_APB_APLL_CFG_LFHF_SHIFT
 396 #undef CRF_APB_APLL_CFG_LFHF_MASK
 397 #define CRF_APB_APLL_CFG_LFHF_DEFVAL                                               0x00000000
 398 #define CRF_APB_APLL_CFG_LFHF_SHIFT                                                10
 399 #define CRF_APB_APLL_CFG_LFHF_MASK                                                 0x00000C00U
 400
 401 /*Lock circuit counter setting*/
 402 #undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL
 403 #undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
 404 #undef CRF_APB_APLL_CFG_LOCK_CNT_MASK
 405 #define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
 406 #define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT                                            13
 407 #define CRF_APB_APLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
 408
 409 /*Lock circuit configuration settings for lock windowsize*/
 410 #undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL
 411 #undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
 412 #undef CRF_APB_APLL_CFG_LOCK_DLY_MASK
 413 #define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
 414 #define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT                                            25
 415 #define CRF_APB_APLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
 416
 417 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 418                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 419 #undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL
 420 #undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
 421 #undef CRF_APB_APLL_CTRL_PRE_SRC_MASK
 422 #define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL                                           0x00012C09
 423 #define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT                                            20
 424 #define CRF_APB_APLL_CTRL_PRE_SRC_MASK                                             0x00700000U
 425
 426 /*The integer portion of the feedback divider to the PLL*/
 427 #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL
 428 #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT
 429 #undef CRF_APB_APLL_CTRL_FBDIV_MASK
 430 #define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
 431 #define CRF_APB_APLL_CTRL_FBDIV_SHIFT                                              8
 432 #define CRF_APB_APLL_CTRL_FBDIV_MASK                                               0x00007F00U
 433
 434 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 435 #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL
 436 #undef CRF_APB_APLL_CTRL_DIV2_SHIFT
 437 #undef CRF_APB_APLL_CTRL_DIV2_MASK
 438 #define CRF_APB_APLL_CTRL_DIV2_DEFVAL                                              0x00012C09
 439 #define CRF_APB_APLL_CTRL_DIV2_SHIFT                                               16
 440 #define CRF_APB_APLL_CTRL_DIV2_MASK                                                0x00010000U
 441
 442 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 443                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 444 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
 445 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
 446 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
 447 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
 448 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
 449 #define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
 450
 451 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 452 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
 453 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
 454 #undef CRF_APB_APLL_CTRL_RESET_MASK
 455 #define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
 456 #define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
 457 #define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
 458
 459 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 460 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
 461 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
 462 #undef CRF_APB_APLL_CTRL_RESET_MASK
 463 #define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
 464 #define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
 465 #define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
 466
 467 /*APLL is locked*/
 468 #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL
 469 #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT
 470 #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK
 471 #define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                                        0x00000038
 472 #define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                                         0
 473 #define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                                          0x00000001U
 474 #define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
 475
 476 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 477                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 478 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
 479 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
 480 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
 481 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
 482 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
 483 #define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
 484
 485 /*Divisor value for this clock.*/
 486 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
 487 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 488 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK
 489 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
 490 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
 491 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
 492
 493 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 494                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 495 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL
 496 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
 497 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK
 498 #define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
 499 #define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT                                        31
 500 #define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
 501
 502 /*Fractional value for the Feedback value.*/
 503 #undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL
 504 #undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
 505 #undef CRF_APB_APLL_FRAC_CFG_DATA_MASK
 506 #define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
 507 #define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT                                           0
 508 #define CRF_APB_APLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
 509
 510 /*PLL loop filter resistor control*/
 511 #undef CRF_APB_DPLL_CFG_RES_DEFVAL
 512 #undef CRF_APB_DPLL_CFG_RES_SHIFT
 513 #undef CRF_APB_DPLL_CFG_RES_MASK
 514 #define CRF_APB_DPLL_CFG_RES_DEFVAL                                                0x00000000
 515 #define CRF_APB_DPLL_CFG_RES_SHIFT                                                 0
 516 #define CRF_APB_DPLL_CFG_RES_MASK                                                  0x0000000FU
 517
 518 /*PLL charge pump control*/
 519 #undef CRF_APB_DPLL_CFG_CP_DEFVAL
 520 #undef CRF_APB_DPLL_CFG_CP_SHIFT
 521 #undef CRF_APB_DPLL_CFG_CP_MASK
 522 #define CRF_APB_DPLL_CFG_CP_DEFVAL                                                 0x00000000
 523 #define CRF_APB_DPLL_CFG_CP_SHIFT                                                  5
 524 #define CRF_APB_DPLL_CFG_CP_MASK                                                   0x000001E0U
 525
 526 /*PLL loop filter high frequency capacitor control*/
 527 #undef CRF_APB_DPLL_CFG_LFHF_DEFVAL
 528 #undef CRF_APB_DPLL_CFG_LFHF_SHIFT
 529 #undef CRF_APB_DPLL_CFG_LFHF_MASK
 530 #define CRF_APB_DPLL_CFG_LFHF_DEFVAL                                               0x00000000
 531 #define CRF_APB_DPLL_CFG_LFHF_SHIFT                                                10
 532 #define CRF_APB_DPLL_CFG_LFHF_MASK                                                 0x00000C00U
 533
 534 /*Lock circuit counter setting*/
 535 #undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL
 536 #undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
 537 #undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK
 538 #define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
 539 #define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT                                            13
 540 #define CRF_APB_DPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
 541
 542 /*Lock circuit configuration settings for lock windowsize*/
 543 #undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL
 544 #undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
 545 #undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK
 546 #define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
 547 #define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT                                            25
 548 #define CRF_APB_DPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
 549
 550 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 551                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 552 #undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL
 553 #undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
 554 #undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK
 555 #define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL                                           0x00002C09
 556 #define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT                                            20
 557 #define CRF_APB_DPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
 558
 559 /*The integer portion of the feedback divider to the PLL*/
 560 #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL
 561 #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT
 562 #undef CRF_APB_DPLL_CTRL_FBDIV_MASK
 563 #define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                                             0x00002C09
 564 #define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                                              8
 565 #define CRF_APB_DPLL_CTRL_FBDIV_MASK                                               0x00007F00U
 566
 567 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 568 #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL
 569 #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT
 570 #undef CRF_APB_DPLL_CTRL_DIV2_MASK
 571 #define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                                              0x00002C09
 572 #define CRF_APB_DPLL_CTRL_DIV2_SHIFT                                               16
 573 #define CRF_APB_DPLL_CTRL_DIV2_MASK                                                0x00010000U
 574
 575 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 576                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 577 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
 578 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 579 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
 580 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
 581 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
 582 #define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
 583
 584 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 585 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
 586 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
 587 #undef CRF_APB_DPLL_CTRL_RESET_MASK
 588 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
 589 #define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
 590 #define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
 591
 592 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 593 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
 594 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
 595 #undef CRF_APB_DPLL_CTRL_RESET_MASK
 596 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
 597 #define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
 598 #define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
 599
 600 /*DPLL is locked*/
 601 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL
 602 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT
 603 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK
 604 #define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                                        0x00000038
 605 #define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                                         1
 606 #define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                                          0x00000002U
 607 #define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
 608
 609 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 610                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 611 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
 612 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 613 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
 614 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
 615 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
 616 #define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
 617
 618 /*Divisor value for this clock.*/
 619 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
 620 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 621 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK
 622 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
 623 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
 624 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
 625
 626 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 627                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 628 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL
 629 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
 630 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK
 631 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
 632 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT                                        31
 633 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
 634
 635 /*Fractional value for the Feedback value.*/
 636 #undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL
 637 #undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
 638 #undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK
 639 #define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
 640 #define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT                                           0
 641 #define CRF_APB_DPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
 642
 643 /*PLL loop filter resistor control*/
 644 #undef CRF_APB_VPLL_CFG_RES_DEFVAL
 645 #undef CRF_APB_VPLL_CFG_RES_SHIFT
 646 #undef CRF_APB_VPLL_CFG_RES_MASK
 647 #define CRF_APB_VPLL_CFG_RES_DEFVAL                                                0x00000000
 648 #define CRF_APB_VPLL_CFG_RES_SHIFT                                                 0
 649 #define CRF_APB_VPLL_CFG_RES_MASK                                                  0x0000000FU
 650
 651 /*PLL charge pump control*/
 652 #undef CRF_APB_VPLL_CFG_CP_DEFVAL
 653 #undef CRF_APB_VPLL_CFG_CP_SHIFT
 654 #undef CRF_APB_VPLL_CFG_CP_MASK
 655 #define CRF_APB_VPLL_CFG_CP_DEFVAL                                                 0x00000000
 656 #define CRF_APB_VPLL_CFG_CP_SHIFT                                                  5
 657 #define CRF_APB_VPLL_CFG_CP_MASK                                                   0x000001E0U
 658
 659 /*PLL loop filter high frequency capacitor control*/
 660 #undef CRF_APB_VPLL_CFG_LFHF_DEFVAL
 661 #undef CRF_APB_VPLL_CFG_LFHF_SHIFT
 662 #undef CRF_APB_VPLL_CFG_LFHF_MASK
 663 #define CRF_APB_VPLL_CFG_LFHF_DEFVAL                                               0x00000000
 664 #define CRF_APB_VPLL_CFG_LFHF_SHIFT                                                10
 665 #define CRF_APB_VPLL_CFG_LFHF_MASK                                                 0x00000C00U
 666
 667 /*Lock circuit counter setting*/
 668 #undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL
 669 #undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
 670 #undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK
 671 #define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
 672 #define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT                                            13
 673 #define CRF_APB_VPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
 674
 675 /*Lock circuit configuration settings for lock windowsize*/
 676 #undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL
 677 #undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
 678 #undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK
 679 #define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
 680 #define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT                                            25
 681 #define CRF_APB_VPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
 682
 683 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 684                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 685 #undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL
 686 #undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
 687 #undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK
 688 #define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL                                           0x00012809
 689 #define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT                                            20
 690 #define CRF_APB_VPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
 691
 692 /*The integer portion of the feedback divider to the PLL*/
 693 #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL
 694 #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT
 695 #undef CRF_APB_VPLL_CTRL_FBDIV_MASK
 696 #define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                                             0x00012809
 697 #define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                                              8
 698 #define CRF_APB_VPLL_CTRL_FBDIV_MASK                                               0x00007F00U
 699
 700 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 701 #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL
 702 #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT
 703 #undef CRF_APB_VPLL_CTRL_DIV2_MASK
 704 #define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                                              0x00012809
 705 #define CRF_APB_VPLL_CTRL_DIV2_SHIFT                                               16
 706 #define CRF_APB_VPLL_CTRL_DIV2_MASK                                                0x00010000U
 707
 708 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 709                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 710 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
 711 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 712 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
 713 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
 714 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
 715 #define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
 716
 717 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 718 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
 719 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
 720 #undef CRF_APB_VPLL_CTRL_RESET_MASK
 721 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
 722 #define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
 723 #define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
 724
 725 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 726 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
 727 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
 728 #undef CRF_APB_VPLL_CTRL_RESET_MASK
 729 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
 730 #define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
 731 #define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
 732
 733 /*VPLL is locked*/
 734 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL
 735 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT
 736 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK
 737 #define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                                        0x00000038
 738 #define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                                         2
 739 #define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                                          0x00000004U
 740 #define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
 741
 742 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 743                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 744 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
 745 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 746 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
 747 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
 748 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
 749 #define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
 750
 751 /*Divisor value for this clock.*/
 752 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
 753 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 754 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK
 755 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
 756 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
 757 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
 758
 759 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 760                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 761 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL
 762 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
 763 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK
 764 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
 765 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT                                        31
 766 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
 767
 768 /*Fractional value for the Feedback value.*/
 769 #undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL
 770 #undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
 771 #undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK
 772 #define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
 773 #define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT                                           0
 774 #define CRF_APB_VPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
 775 #undef CRL_APB_GEM3_REF_CTRL_OFFSET
 776 #define CRL_APB_GEM3_REF_CTRL_OFFSET                                               0XFF5E005C
 777 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
 778 #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
 779 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
 780 #define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
 781 #undef CRL_APB_QSPI_REF_CTRL_OFFSET
 782 #define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
 783 #undef CRL_APB_SDIO1_REF_CTRL_OFFSET
 784 #define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
 785 #undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET
 786 #define IOU_SLCR_SDIO_CLK_CTRL_OFFSET                                              0XFF18030C
 787 #undef CRL_APB_UART0_REF_CTRL_OFFSET
 788 #define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
 789 #undef CRL_APB_UART1_REF_CTRL_OFFSET
 790 #define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
 791 #undef CRL_APB_I2C0_REF_CTRL_OFFSET
 792 #define CRL_APB_I2C0_REF_CTRL_OFFSET                                               0XFF5E0120
 793 #undef CRL_APB_I2C1_REF_CTRL_OFFSET
 794 #define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
 795 #undef CRL_APB_CAN1_REF_CTRL_OFFSET
 796 #define CRL_APB_CAN1_REF_CTRL_OFFSET                                               0XFF5E0088
 797 #undef CRL_APB_CPU_R5_CTRL_OFFSET
 798 #define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
 799 #undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
 800 #define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
 801 #undef CRL_APB_PCAP_CTRL_OFFSET
 802 #define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
 803 #undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
 804 #define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
 805 #undef CRL_APB_LPD_LSBUS_CTRL_OFFSET
 806 #define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
 807 #undef CRL_APB_DBG_LPD_CTRL_OFFSET
 808 #define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
 809 #undef CRL_APB_ADMA_REF_CTRL_OFFSET
 810 #define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
 811 #undef CRL_APB_PL0_REF_CTRL_OFFSET
 812 #define CRL_APB_PL0_REF_CTRL_OFFSET                                                0XFF5E00C0
 813 #undef CRL_APB_PL1_REF_CTRL_OFFSET
 814 #define CRL_APB_PL1_REF_CTRL_OFFSET                                                0XFF5E00C4
 815 #undef CRL_APB_PL2_REF_CTRL_OFFSET
 816 #define CRL_APB_PL2_REF_CTRL_OFFSET                                                0XFF5E00C8
 817 #undef CRL_APB_PL3_REF_CTRL_OFFSET
 818 #define CRL_APB_PL3_REF_CTRL_OFFSET                                                0XFF5E00CC
 819 #undef CRL_APB_AMS_REF_CTRL_OFFSET
 820 #define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
 821 #undef CRL_APB_DLL_REF_CTRL_OFFSET
 822 #define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
 823 #undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET
 824 #define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
 825 #undef CRF_APB_SATA_REF_CTRL_OFFSET
 826 #define CRF_APB_SATA_REF_CTRL_OFFSET                                               0XFD1A00A0
 827 #undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET
 828 #define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
 829 #undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET
 830 #define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
 831 #undef CRF_APB_DP_STC_REF_CTRL_OFFSET
 832 #define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
 833 #undef CRF_APB_ACPU_CTRL_OFFSET
 834 #define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
 835 #undef CRF_APB_DBG_TRACE_CTRL_OFFSET
 836 #define CRF_APB_DBG_TRACE_CTRL_OFFSET                                              0XFD1A0064
 837 #undef CRF_APB_DBG_FPD_CTRL_OFFSET
 838 #define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
 839 #undef CRF_APB_DDR_CTRL_OFFSET
 840 #define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
 841 #undef CRF_APB_GPU_REF_CTRL_OFFSET
 842 #define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
 843 #undef CRF_APB_GDMA_REF_CTRL_OFFSET
 844 #define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
 845 #undef CRF_APB_DPDMA_REF_CTRL_OFFSET
 846 #define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
 847 #undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET
 848 #define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
 849 #undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
 850 #define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
 851 #undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
 852 #define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
 853 #undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET
 854 #define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET                                            0XFF180380
 855 #undef FPD_SLCR_WDT_CLK_SEL_OFFSET
 856 #define FPD_SLCR_WDT_CLK_SEL_OFFSET                                                0XFD610100
 857 #undef IOU_SLCR_WDT_CLK_SEL_OFFSET
 858 #define IOU_SLCR_WDT_CLK_SEL_OFFSET                                                0XFF180300
 859 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET
 860 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET                                         0XFF410050
 861
 862 /*Clock active for the RX channel*/
 863 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
 864 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
 865 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK
 866 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
 867 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT                                      26
 868 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
 869
 870 /*Clock active signal. Switch to 0 to disable the clock*/
 871 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL
 872 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
 873 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK
 874 #define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
 875 #define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT                                         25
 876 #define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK                                          0x02000000U
 877
 878 /*6 bit divider*/
 879 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL
 880 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
 881 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK
 882 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
 883 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT                                       16
 884 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
 885
 886 /*6 bit divider*/
 887 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL
 888 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
 889 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK
 890 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
 891 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT                                       8
 892 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
 893
 894 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 895                 clock. This is not usually an issue, but designers must be aware.)*/
 896 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL
 897 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
 898 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK
 899 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
 900 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT                                         0
 901 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK                                          0x00000007U
 902
 903 /*Clock active signal. Switch to 0 to disable the clock*/
 904 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
 905 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
 906 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK
 907 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
 908 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                                     25
 909 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
 910
 911 /*6 bit divider*/
 912 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL
 913 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
 914 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK
 915 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
 916 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
 917 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
 918
 919 /*6 bit divider*/
 920 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL
 921 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
 922 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK
 923 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
 924 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
 925 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
 926
 927 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 928                 clock. This is not usually an issue, but designers must be aware.)*/
 929 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL
 930 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
 931 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK
 932 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
 933 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
 934 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
 935
 936 /*Clock active signal. Switch to 0 to disable the clock*/
 937 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
 938 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
 939 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK
 940 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL                                   0x00052000
 941 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                                    25
 942 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                                     0x02000000U
 943
 944 /*6 bit divider*/
 945 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL
 946 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
 947 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK
 948 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL                                 0x00052000
 949 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT                                  16
 950 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK                                   0x003F0000U
 951
 952 /*6 bit divider*/
 953 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL
 954 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
 955 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK
 956 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL                                 0x00052000
 957 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT                                  8
 958 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
 959
 960 /*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 961                 clock. This is not usually an issue, but designers must be aware.)*/
 962 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL
 963 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
 964 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK
 965 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL                                   0x00052000
 966 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                                    0
 967 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                                     0x00000007U
 968
 969 /*Clock active signal. Switch to 0 to disable the clock*/
 970 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL
 971 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
 972 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK
 973 #define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                                        0x01000800
 974 #define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                                         24
 975 #define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                                          0x01000000U
 976
 977 /*6 bit divider*/
 978 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL
 979 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
 980 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK
 981 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000800
 982 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                                       16
 983 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
 984
 985 /*6 bit divider*/
 986 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL
 987 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
 988 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK
 989 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000800
 990 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                                       8
 991 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
 992
 993 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 994                 clock. This is not usually an issue, but designers must be aware.)*/
 995 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL
 996 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
 997 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK
 998 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                                        0x01000800
 999 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                                         0
1000 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1001
1002 /*Clock active signal. Switch to 0 to disable the clock*/
1003 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
1004 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
1005 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK
1006 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
1007 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                                        24
1008 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                                         0x01000000U
1009
1010 /*6 bit divider*/
1011 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL
1012 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
1013 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK
1014 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
1015 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                                      16
1016 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
1017
1018 /*6 bit divider*/
1019 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL
1020 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
1021 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK
1022 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
1023 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                                      8
1024 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
1025
1026 /*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1027                 clock. This is not usually an issue, but designers must be aware.)*/
1028 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL
1029 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
1030 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK
1031 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
1032 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                                        0
1033 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
1034
1035 /*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/
1036 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL
1037 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
1038 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK
1039 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL                             0x00000000
1040 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT                              17
1041 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK                               0x00020000U
1042
1043 /*Clock active signal. Switch to 0 to disable the clock*/
1044 #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL
1045 #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
1046 #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK
1047 #define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
1048 #define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                                        24
1049 #define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                                         0x01000000U
1050
1051 /*6 bit divider*/
1052 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL
1053 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
1054 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK
1055 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
1056 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                                      16
1057 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
1058
1059 /*6 bit divider*/
1060 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL
1061 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
1062 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK
1063 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
1064 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                                      8
1065 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
1066
1067 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1068                 clock. This is not usually an issue, but designers must be aware.)*/
1069 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL
1070 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
1071 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK
1072 #define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
1073 #define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                                        0
1074 #define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
1075
1076 /*Clock active signal. Switch to 0 to disable the clock*/
1077 #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL
1078 #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
1079 #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK
1080 #define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
1081 #define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                                        24
1082 #define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                                         0x01000000U
1083
1084 /*6 bit divider*/
1085 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL
1086 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
1087 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK
1088 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
1089 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                                      16
1090 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
1091
1092 /*6 bit divider*/
1093 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL
1094 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
1095 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK
1096 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
1097 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                                      8
1098 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
1099
1100 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1101                 clock. This is not usually an issue, but designers must be aware.)*/
1102 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL
1103 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
1104 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK
1105 #define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
1106 #define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                                        0
1107 #define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
1108
1109 /*Clock active signal. Switch to 0 to disable the clock*/
1110 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL
1111 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
1112 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK
1113 #define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
1114 #define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT                                         24
1115 #define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK                                          0x01000000U
1116
1117 /*6 bit divider*/
1118 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL
1119 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
1120 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK
1121 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
1122 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT                                       16
1123 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1124
1125 /*6 bit divider*/
1126 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL
1127 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
1128 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK
1129 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
1130 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT                                       8
1131 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1132
1133 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1134                 clock. This is not usually an issue, but designers must be aware.)*/
1135 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL
1136 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
1137 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK
1138 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
1139 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT                                         0
1140 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1141
1142 /*Clock active signal. Switch to 0 to disable the clock*/
1143 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL
1144 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
1145 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK
1146 #define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
1147 #define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                                         24
1148 #define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                                          0x01000000U
1149
1150 /*6 bit divider*/
1151 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL
1152 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
1153 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK
1154 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
1155 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                                       16
1156 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1157
1158 /*6 bit divider*/
1159 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL
1160 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
1161 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK
1162 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
1163 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                                       8
1164 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1165
1166 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1167                 clock. This is not usually an issue, but designers must be aware.)*/
1168 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL
1169 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
1170 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK
1171 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
1172 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                                         0
1173 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1174
1175 /*Clock active signal. Switch to 0 to disable the clock*/
1176 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
1177 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
1178 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK
1179 #define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
1180 #define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT                                         24
1181 #define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK                                          0x01000000U
1182
1183 /*6 bit divider*/
1184 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL
1185 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
1186 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK
1187 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
1188 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT                                       16
1189 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1190
1191 /*6 bit divider*/
1192 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL
1193 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
1194 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK
1195 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
1196 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT                                       8
1197 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1198
1199 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1200                 clock. This is not usually an issue, but designers must be aware.)*/
1201 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL
1202 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
1203 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK
1204 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
1205 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT                                         0
1206 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1207
1208 /*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
1209                 d lead to system hang*/
1210 #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL
1211 #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
1212 #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK
1213 #define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                                          0x03000600
1214 #define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                                           24
1215 #define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                                            0x01000000U
1216
1217 /*6 bit divider*/
1218 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL
1219 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
1220 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK
1221 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                                        0x03000600
1222 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                                         8
1223 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                                          0x00003F00U
1224
1225 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1226                 clock. This is not usually an issue, but designers must be aware.)*/
1227 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL
1228 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
1229 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK
1230 #define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                                          0x03000600
1231 #define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                                           0
1232 #define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                                            0x00000007U
1233
1234 /*Clock active signal. Switch to 0 to disable the clock*/
1235 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL
1236 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
1237 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK
1238 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                                      0x00001500
1239 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                                       24
1240 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
1241
1242 /*6 bit divider*/
1243 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL
1244 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
1245 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK
1246 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x00001500
1247 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
1248 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
1249
1250 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1251                 clock. This is not usually an issue, but designers must be aware.)*/
1252 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL
1253 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
1254 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK
1255 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x00001500
1256 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                                       0
1257 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
1258
1259 /*Clock active signal. Switch to 0 to disable the clock*/
1260 #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
1261 #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
1262 #undef CRL_APB_PCAP_CTRL_CLKACT_MASK
1263 #define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                                            0x00001500
1264 #define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                                             24
1265 #define CRL_APB_PCAP_CTRL_CLKACT_MASK                                              0x01000000U
1266
1267 /*6 bit divider*/
1268 #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL
1269 #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
1270 #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK
1271 #define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                                          0x00001500
1272 #define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                                           8
1273 #define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                                            0x00003F00U
1274
1275 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1276                 clock. This is not usually an issue, but designers must be aware.)*/
1277 #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL
1278 #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
1279 #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK
1280 #define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                                            0x00001500
1281 #define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                                             0
1282 #define CRL_APB_PCAP_CTRL_SRCSEL_MASK                                              0x00000007U
1283
1284 /*Clock active signal. Switch to 0 to disable the clock*/
1285 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL
1286 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
1287 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK
1288 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                                      0x01000500
1289 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                                       24
1290 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
1291
1292 /*6 bit divider*/
1293 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL
1294 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
1295 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK
1296 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x01000500
1297 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
1298 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
1299
1300 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1301                 clock. This is not usually an issue, but designers must be aware.)*/
1302 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL
1303 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
1304 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK
1305 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x01000500
1306 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                                       0
1307 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
1308
1309 /*Clock active signal. Switch to 0 to disable the clock*/
1310 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL
1311 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
1312 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK
1313 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                                       0x01001800
1314 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                                        24
1315 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                                         0x01000000U
1316
1317 /*6 bit divider*/
1318 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL
1319 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
1320 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK
1321 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                                     0x01001800
1322 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                                      8
1323 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                                       0x00003F00U
1324
1325 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1326                 clock. This is not usually an issue, but designers must be aware.)*/
1327 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL
1328 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
1329 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK
1330 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                                       0x01001800
1331 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                                        0
1332 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                                         0x00000007U
1333
1334 /*Clock active signal. Switch to 0 to disable the clock*/
1335 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL
1336 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
1337 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK
1338 #define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                                         0x01002000
1339 #define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                                          24
1340 #define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                                           0x01000000U
1341
1342 /*6 bit divider*/
1343 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL
1344 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
1345 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK
1346 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                                       0x01002000
1347 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                                        8
1348 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
1349
1350 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1351                 clock. This is not usually an issue, but designers must be aware.)*/
1352 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL
1353 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
1354 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK
1355 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                                         0x01002000
1356 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                                          0
1357 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                                           0x00000007U
1358
1359 /*Clock active signal. Switch to 0 to disable the clock*/
1360 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
1361 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
1362 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK
1363 #define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                                        0x00002000
1364 #define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                                         24
1365 #define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
1366
1367 /*6 bit divider*/
1368 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL
1369 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
1370 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK
1371 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002000
1372 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                                       8
1373 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1374
1375 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1376                 clock. This is not usually an issue, but designers must be aware.)*/
1377 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL
1378 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
1379 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK
1380 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                                        0x00002000
1381 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                                         0
1382 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1383
1384 /*Clock active signal. Switch to 0 to disable the clock*/
1385 #undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL
1386 #undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
1387 #undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK
1388 #define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
1389 #define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT                                          24
1390 #define CRL_APB_PL0_REF_CTRL_CLKACT_MASK                                           0x01000000U
1391
1392 /*6 bit divider*/
1393 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL
1394 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
1395 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK
1396 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
1397 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT                                        16
1398 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1399
1400 /*6 bit divider*/
1401 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL
1402 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
1403 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK
1404 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
1405 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT                                        8
1406 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1407
1408 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1409                 clock. This is not usually an issue, but designers must be aware.)*/
1410 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL
1411 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
1412 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK
1413 #define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
1414 #define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT                                          0
1415 #define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1416
1417 /*Clock active signal. Switch to 0 to disable the clock*/
1418 #undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL
1419 #undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
1420 #undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK
1421 #define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
1422 #define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT                                          24
1423 #define CRL_APB_PL1_REF_CTRL_CLKACT_MASK                                           0x01000000U
1424
1425 /*6 bit divider*/
1426 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL
1427 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
1428 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK
1429 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
1430 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT                                        16
1431 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1432
1433 /*6 bit divider*/
1434 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL
1435 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
1436 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK
1437 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
1438 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT                                        8
1439 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1440
1441 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1442                 clock. This is not usually an issue, but designers must be aware.)*/
1443 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL
1444 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
1445 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK
1446 #define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
1447 #define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT                                          0
1448 #define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1449
1450 /*Clock active signal. Switch to 0 to disable the clock*/
1451 #undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL
1452 #undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
1453 #undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK
1454 #define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
1455 #define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT                                          24
1456 #define CRL_APB_PL2_REF_CTRL_CLKACT_MASK                                           0x01000000U
1457
1458 /*6 bit divider*/
1459 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL
1460 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
1461 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK
1462 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
1463 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT                                        16
1464 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1465
1466 /*6 bit divider*/
1467 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL
1468 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
1469 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK
1470 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
1471 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT                                        8
1472 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1473
1474 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1475                 clock. This is not usually an issue, but designers must be aware.)*/
1476 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL
1477 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
1478 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK
1479 #define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
1480 #define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT                                          0
1481 #define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1482
1483 /*Clock active signal. Switch to 0 to disable the clock*/
1484 #undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL
1485 #undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
1486 #undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK
1487 #define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
1488 #define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT                                          24
1489 #define CRL_APB_PL3_REF_CTRL_CLKACT_MASK                                           0x01000000U
1490
1491 /*6 bit divider*/
1492 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL
1493 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
1494 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK
1495 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
1496 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT                                        16
1497 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1498
1499 /*6 bit divider*/
1500 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL
1501 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
1502 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK
1503 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
1504 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT                                        8
1505 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1506
1507 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1508                 clock. This is not usually an issue, but designers must be aware.)*/
1509 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL
1510 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
1511 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK
1512 #define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
1513 #define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT                                          0
1514 #define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1515
1516 /*6 bit divider*/
1517 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL
1518 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
1519 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK
1520 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                                       0x01001800
1521 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                                        16
1522 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1523
1524 /*6 bit divider*/
1525 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL
1526 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
1527 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK
1528 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                                       0x01001800
1529 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                                        8
1530 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1531
1532 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1533                 clock. This is not usually an issue, but designers must be aware.)*/
1534 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL
1535 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
1536 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK
1537 #define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                                         0x01001800
1538 #define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                                          0
1539 #define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1540
1541 /*Clock active signal. Switch to 0 to disable the clock*/
1542 #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL
1543 #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
1544 #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK
1545 #define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                                         0x01001800
1546 #define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                                          24
1547 #define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                                           0x01000000U
1548
1549 /*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1550                 is not usually an issue, but designers must be aware.)*/
1551 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL
1552 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
1553 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK
1554 #define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                                         0x00000000
1555 #define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                                          0
1556 #define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1557
1558 /*6 bit divider*/
1559 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL
1560 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
1561 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK
1562 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL                                 0x00001800
1563 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT                                  8
1564 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
1565
1566 /*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and
1567                  cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
1568 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL
1569 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
1570 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK
1571 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL                                   0x00001800
1572 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                                    0
1573 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                                     0x00000007U
1574
1575 /*Clock active signal. Switch to 0 to disable the clock*/
1576 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL
1577 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
1578 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK
1579 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL                                   0x00001800
1580 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                                    24
1581 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                                     0x01000000U
1582
1583 /*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1584                 he new clock. This is not usually an issue, but designers must be aware.)*/
1585 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL
1586 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
1587 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK
1588 #define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL                                        0x01001600
1589 #define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT                                         0
1590 #define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1591
1592 /*Clock active signal. Switch to 0 to disable the clock*/
1593 #undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL
1594 #undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
1595 #undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK
1596 #define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL                                        0x01001600
1597 #define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT                                         24
1598 #define CRF_APB_SATA_REF_CTRL_CLKACT_MASK                                          0x01000000U
1599
1600 /*6 bit divider*/
1601 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL
1602 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
1603 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK
1604 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001600
1605 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT                                       8
1606 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1607
1608 /*6 bit divider*/
1609 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL
1610 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
1611 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK
1612 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01002300
1613 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT                                   16
1614 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
1615
1616 /*6 bit divider*/
1617 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL
1618 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
1619 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK
1620 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01002300
1621 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT                                   8
1622 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
1623
1624 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1625                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
1626 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL
1627 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
1628 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK
1629 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                                    0x01002300
1630 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                                     0
1631 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
1632
1633 /*Clock active signal. Switch to 0 to disable the clock*/
1634 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL
1635 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
1636 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK
1637 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                                    0x01002300
1638 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                                     24
1639 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                                      0x01000000U
1640
1641 /*6 bit divider*/
1642 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL
1643 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
1644 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK
1645 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01032300
1646 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT                                   16
1647 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
1648
1649 /*6 bit divider*/
1650 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL
1651 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
1652 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK
1653 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01032300
1654 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT                                   8
1655 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
1656
1657 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1658                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
1659 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL
1660 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
1661 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK
1662 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                                    0x01032300
1663 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                                     0
1664 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
1665
1666 /*Clock active signal. Switch to 0 to disable the clock*/
1667 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL
1668 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
1669 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK
1670 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                                    0x01032300
1671 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                                     24
1672 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                                      0x01000000U
1673
1674 /*6 bit divider*/
1675 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL
1676 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
1677 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK
1678 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                                    0x01203200
1679 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                                     16
1680 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                                      0x003F0000U
1681
1682 /*6 bit divider*/
1683 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL
1684 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
1685 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK
1686 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                                    0x01203200
1687 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                                     8
1688 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                                      0x00003F00U
1689
1690 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
1691                 e new clock. This is not usually an issue, but designers must be aware.)*/
1692 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL
1693 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
1694 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK
1695 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                                      0x01203200
1696 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                                       0
1697 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                                        0x00000007U
1698
1699 /*Clock active signal. Switch to 0 to disable the clock*/
1700 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL
1701 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
1702 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK
1703 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                                      0x01203200
1704 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                                       24
1705 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                                        0x01000000U
1706
1707 /*6 bit divider*/
1708 #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL
1709 #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
1710 #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK
1711 #define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                                          0x03000400
1712 #define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                                           8
1713 #define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                                            0x00003F00U
1714
1715 /*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1716                 lock. This is not usually an issue, but designers must be aware.)*/
1717 #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL
1718 #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
1719 #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK
1720 #define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                                            0x03000400
1721 #define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                                             0
1722 #define CRF_APB_ACPU_CTRL_SRCSEL_MASK                                              0x00000007U
1723
1724 /*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/
1725 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL
1726 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
1727 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK
1728 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                                       0x03000400
1729 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                                        25
1730 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                                         0x02000000U
1731
1732 /*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
1733                  to the entire APU*/
1734 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL
1735 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
1736 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK
1737 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                                       0x03000400
1738 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                                        24
1739 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                                         0x01000000U
1740
1741 /*6 bit divider*/
1742 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL
1743 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
1744 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK
1745 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL                                     0x00002500
1746 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT                                      8
1747 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK                                       0x00003F00U
1748
1749 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1750                 he new clock. This is not usually an issue, but designers must be aware.)*/
1751 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL
1752 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
1753 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK
1754 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL                                       0x00002500
1755 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT                                        0
1756 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK                                         0x00000007U
1757
1758 /*Clock active signal. Switch to 0 to disable the clock*/
1759 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL
1760 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
1761 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK
1762 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL                                       0x00002500
1763 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT                                        24
1764 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK                                         0x01000000U
1765
1766 /*6 bit divider*/
1767 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL
1768 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
1769 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK
1770 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                                       0x01002500
1771 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                                        8
1772 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
1773
1774 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1775                 he new clock. This is not usually an issue, but designers must be aware.)*/
1776 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL
1777 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
1778 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK
1779 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                                         0x01002500
1780 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                                          0
1781 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                                           0x00000007U
1782
1783 /*Clock active signal. Switch to 0 to disable the clock*/
1784 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL
1785 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
1786 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK
1787 #define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                                         0x01002500
1788 #define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                                          24
1789 #define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                                           0x01000000U
1790
1791 /*6 bit divider*/
1792 #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL
1793 #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
1794 #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK
1795 #define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                                           0x01000500
1796 #define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                                            8
1797 #define CRF_APB_DDR_CTRL_DIVISOR0_MASK                                             0x00003F00U
1798
1799 /*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1800                 s not usually an issue, but designers must be aware.)*/
1801 #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL
1802 #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT
1803 #undef CRF_APB_DDR_CTRL_SRCSEL_MASK
1804 #define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                                             0x01000500
1805 #define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                                              0
1806 #define CRF_APB_DDR_CTRL_SRCSEL_MASK                                               0x00000007U
1807
1808 /*6 bit divider*/
1809 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL
1810 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
1811 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK
1812 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                                       0x00001500
1813 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                                        8
1814 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1815
1816 /*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1817                 he new clock. This is not usually an issue, but designers must be aware.)*/
1818 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL
1819 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
1820 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK
1821 #define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                                         0x00001500
1822 #define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                                          0
1823 #define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1824
1825 /*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/
1826 #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL
1827 #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
1828 #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK
1829 #define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                                         0x00001500
1830 #define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                                          24
1831 #define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                                           0x01000000U
1832
1833 /*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
1834 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL
1835 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
1836 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK
1837 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                                     0x00001500
1838 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                                      25
1839 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                                       0x02000000U
1840
1841 /*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
1842 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL
1843 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
1844 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK
1845 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                                     0x00001500
1846 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                                      26
1847 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                                       0x04000000U
1848
1849 /*6 bit divider*/
1850 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL
1851 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
1852 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK
1853 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
1854 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                                       8
1855 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1856
1857 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1858                 lock. This is not usually an issue, but designers must be aware.)*/
1859 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL
1860 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
1861 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK
1862 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
1863 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                                         0
1864 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1865
1866 /*Clock active signal. Switch to 0 to disable the clock*/
1867 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL
1868 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
1869 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK
1870 #define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
1871 #define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                                         24
1872 #define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
1873
1874 /*6 bit divider*/
1875 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL
1876 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
1877 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK
1878 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000500
1879 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                                      8
1880 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
1881
1882 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1883                 lock. This is not usually an issue, but designers must be aware.)*/
1884 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL
1885 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
1886 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK
1887 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                                       0x01000500
1888 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                                        0
1889 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                                         0x00000007U
1890
1891 /*Clock active signal. Switch to 0 to disable the clock*/
1892 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL
1893 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
1894 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK
1895 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                                       0x01000500
1896 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                                        24
1897 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                                         0x01000000U
1898
1899 /*6 bit divider*/
1900 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL
1901 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
1902 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK
1903 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                                    0x01000400
1904 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                                     8
1905 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                                      0x00003F00U
1906
1907 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1908                 lock. This is not usually an issue, but designers must be aware.)*/
1909 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL
1910 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
1911 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK
1912 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                                      0x01000400
1913 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                                       0
1914 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                                        0x00000007U
1915
1916 /*Clock active signal. Switch to 0 to disable the clock*/
1917 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL
1918 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
1919 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK
1920 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                                      0x01000400
1921 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                                       24
1922 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                                        0x01000000U
1923
1924 /*6 bit divider*/
1925 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL
1926 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
1927 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK
1928 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL                                   0x01000800
1929 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                                    8
1930 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                                     0x00003F00U
1931
1932 /*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1933                 he new clock. This is not usually an issue, but designers must be aware.)*/
1934 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL
1935 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
1936 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK
1937 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                                     0x01000800
1938 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                                      0
1939 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                                       0x00000007U
1940
1941 /*Clock active signal. Switch to 0 to disable the clock*/
1942 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL
1943 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
1944 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK
1945 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                                     0x01000800
1946 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                                      24
1947 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                                       0x01000000U
1948
1949 /*6 bit divider*/
1950 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
1951 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
1952 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK
1953 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                                     0x00000A00
1954 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                                      8
1955 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                                       0x00003F00U
1956
1957 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1958                 he new clock. This is not usually an issue, but designers must be aware.)*/
1959 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL
1960 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
1961 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK
1962 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                                       0x00000A00
1963 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                                        0
1964 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                                         0x00000007U
1965
1966 /*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
1967                 0" = Select the R5 clock for the APB interface of TTC0*/
1968 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL
1969 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
1970 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK
1971 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL                                   0x00000000
1972 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT                                    0
1973 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK                                     0x00000003U
1974
1975 /*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
1976                 0" = Select the R5 clock for the APB interface of TTC1*/
1977 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL
1978 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
1979 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK
1980 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL                                   0x00000000
1981 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT                                    2
1982 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK                                     0x0000000CU
1983
1984 /*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
1985                 0" = Select the R5 clock for the APB interface of TTC2*/
1986 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL
1987 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
1988 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK
1989 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL                                   0x00000000
1990 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT                                    4
1991 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK                                     0x00000030U
1992
1993 /*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
1994                 0" = Select the R5 clock for the APB interface of TTC3*/
1995 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL
1996 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
1997 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK
1998 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL                                   0x00000000
1999 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT                                    6
2000 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK                                     0x000000C0U
2001
2002 /*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/
2003 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
2004 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2005 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK
2006 #define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                                         0x00000000
2007 #define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT                                          0
2008 #define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK                                           0x00000001U
2009
2010 /*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout
2011                 ia MIO*/
2012 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
2013 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2014 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK
2015 #define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                                         0x00000000
2016 #define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT                                          0
2017 #define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK                                           0x00000001U
2018
2019 /*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/
2020 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL
2021 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
2022 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK
2023 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL                                  0x00000000
2024 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT                                   0
2025 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK                                    0x00000001U
2026 #undef CRF_APB_RST_DDR_SS_OFFSET
2027 #define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
2028 #undef DDRC_MSTR_OFFSET
2029 #define DDRC_MSTR_OFFSET                                                           0XFD070000
2030 #undef DDRC_MRCTRL0_OFFSET
2031 #define DDRC_MRCTRL0_OFFSET                                                        0XFD070010
2032 #undef DDRC_DERATEEN_OFFSET
2033 #define DDRC_DERATEEN_OFFSET                                                       0XFD070020
2034 #undef DDRC_DERATEINT_OFFSET
2035 #define DDRC_DERATEINT_OFFSET                                                      0XFD070024
2036 #undef DDRC_PWRCTL_OFFSET
2037 #define DDRC_PWRCTL_OFFSET                                                         0XFD070030
2038 #undef DDRC_PWRTMG_OFFSET
2039 #define DDRC_PWRTMG_OFFSET                                                         0XFD070034
2040 #undef DDRC_RFSHCTL0_OFFSET
2041 #define DDRC_RFSHCTL0_OFFSET                                                       0XFD070050
2042 #undef DDRC_RFSHCTL3_OFFSET
2043 #define DDRC_RFSHCTL3_OFFSET                                                       0XFD070060
2044 #undef DDRC_RFSHTMG_OFFSET
2045 #define DDRC_RFSHTMG_OFFSET                                                        0XFD070064
2046 #undef DDRC_ECCCFG0_OFFSET
2047 #define DDRC_ECCCFG0_OFFSET                                                        0XFD070070
2048 #undef DDRC_ECCCFG1_OFFSET
2049 #define DDRC_ECCCFG1_OFFSET                                                        0XFD070074
2050 #undef DDRC_CRCPARCTL1_OFFSET
2051 #define DDRC_CRCPARCTL1_OFFSET                                                     0XFD0700C4
2052 #undef DDRC_CRCPARCTL2_OFFSET
2053 #define DDRC_CRCPARCTL2_OFFSET                                                     0XFD0700C8
2054 #undef DDRC_INIT0_OFFSET
2055 #define DDRC_INIT0_OFFSET                                                          0XFD0700D0
2056 #undef DDRC_INIT1_OFFSET
2057 #define DDRC_INIT1_OFFSET                                                          0XFD0700D4
2058 #undef DDRC_INIT2_OFFSET
2059 #define DDRC_INIT2_OFFSET                                                          0XFD0700D8
2060 #undef DDRC_INIT3_OFFSET
2061 #define DDRC_INIT3_OFFSET                                                          0XFD0700DC
2062 #undef DDRC_INIT4_OFFSET
2063 #define DDRC_INIT4_OFFSET                                                          0XFD0700E0
2064 #undef DDRC_INIT5_OFFSET
2065 #define DDRC_INIT5_OFFSET                                                          0XFD0700E4
2066 #undef DDRC_INIT6_OFFSET
2067 #define DDRC_INIT6_OFFSET                                                          0XFD0700E8
2068 #undef DDRC_INIT7_OFFSET
2069 #define DDRC_INIT7_OFFSET                                                          0XFD0700EC
2070 #undef DDRC_DIMMCTL_OFFSET
2071 #define DDRC_DIMMCTL_OFFSET                                                        0XFD0700F0
2072 #undef DDRC_RANKCTL_OFFSET
2073 #define DDRC_RANKCTL_OFFSET                                                        0XFD0700F4
2074 #undef DDRC_DRAMTMG0_OFFSET
2075 #define DDRC_DRAMTMG0_OFFSET                                                       0XFD070100
2076 #undef DDRC_DRAMTMG1_OFFSET
2077 #define DDRC_DRAMTMG1_OFFSET                                                       0XFD070104
2078 #undef DDRC_DRAMTMG2_OFFSET
2079 #define DDRC_DRAMTMG2_OFFSET                                                       0XFD070108
2080 #undef DDRC_DRAMTMG3_OFFSET
2081 #define DDRC_DRAMTMG3_OFFSET                                                       0XFD07010C
2082 #undef DDRC_DRAMTMG4_OFFSET
2083 #define DDRC_DRAMTMG4_OFFSET                                                       0XFD070110
2084 #undef DDRC_DRAMTMG5_OFFSET
2085 #define DDRC_DRAMTMG5_OFFSET                                                       0XFD070114
2086 #undef DDRC_DRAMTMG6_OFFSET
2087 #define DDRC_DRAMTMG6_OFFSET                                                       0XFD070118
2088 #undef DDRC_DRAMTMG7_OFFSET
2089 #define DDRC_DRAMTMG7_OFFSET                                                       0XFD07011C
2090 #undef DDRC_DRAMTMG8_OFFSET
2091 #define DDRC_DRAMTMG8_OFFSET                                                       0XFD070120
2092 #undef DDRC_DRAMTMG9_OFFSET
2093 #define DDRC_DRAMTMG9_OFFSET                                                       0XFD070124
2094 #undef DDRC_DRAMTMG11_OFFSET
2095 #define DDRC_DRAMTMG11_OFFSET                                                      0XFD07012C
2096 #undef DDRC_DRAMTMG12_OFFSET
2097 #define DDRC_DRAMTMG12_OFFSET                                                      0XFD070130
2098 #undef DDRC_ZQCTL0_OFFSET
2099 #define DDRC_ZQCTL0_OFFSET                                                         0XFD070180
2100 #undef DDRC_ZQCTL1_OFFSET
2101 #define DDRC_ZQCTL1_OFFSET                                                         0XFD070184
2102 #undef DDRC_DFITMG0_OFFSET
2103 #define DDRC_DFITMG0_OFFSET                                                        0XFD070190
2104 #undef DDRC_DFITMG1_OFFSET
2105 #define DDRC_DFITMG1_OFFSET                                                        0XFD070194
2106 #undef DDRC_DFILPCFG0_OFFSET
2107 #define DDRC_DFILPCFG0_OFFSET                                                      0XFD070198
2108 #undef DDRC_DFILPCFG1_OFFSET
2109 #define DDRC_DFILPCFG1_OFFSET                                                      0XFD07019C
2110 #undef DDRC_DFIUPD1_OFFSET
2111 #define DDRC_DFIUPD1_OFFSET                                                        0XFD0701A4
2112 #undef DDRC_DFIMISC_OFFSET
2113 #define DDRC_DFIMISC_OFFSET                                                        0XFD0701B0
2114 #undef DDRC_DFITMG2_OFFSET
2115 #define DDRC_DFITMG2_OFFSET                                                        0XFD0701B4
2116 #undef DDRC_DBICTL_OFFSET
2117 #define DDRC_DBICTL_OFFSET                                                         0XFD0701C0
2118 #undef DDRC_ADDRMAP0_OFFSET
2119 #define DDRC_ADDRMAP0_OFFSET                                                       0XFD070200
2120 #undef DDRC_ADDRMAP1_OFFSET
2121 #define DDRC_ADDRMAP1_OFFSET                                                       0XFD070204
2122 #undef DDRC_ADDRMAP2_OFFSET
2123 #define DDRC_ADDRMAP2_OFFSET                                                       0XFD070208
2124 #undef DDRC_ADDRMAP3_OFFSET
2125 #define DDRC_ADDRMAP3_OFFSET                                                       0XFD07020C
2126 #undef DDRC_ADDRMAP4_OFFSET
2127 #define DDRC_ADDRMAP4_OFFSET                                                       0XFD070210
2128 #undef DDRC_ADDRMAP5_OFFSET
2129 #define DDRC_ADDRMAP5_OFFSET                                                       0XFD070214
2130 #undef DDRC_ADDRMAP6_OFFSET
2131 #define DDRC_ADDRMAP6_OFFSET                                                       0XFD070218
2132 #undef DDRC_ADDRMAP7_OFFSET
2133 #define DDRC_ADDRMAP7_OFFSET                                                       0XFD07021C
2134 #undef DDRC_ADDRMAP8_OFFSET
2135 #define DDRC_ADDRMAP8_OFFSET                                                       0XFD070220
2136 #undef DDRC_ADDRMAP9_OFFSET
2137 #define DDRC_ADDRMAP9_OFFSET                                                       0XFD070224
2138 #undef DDRC_ADDRMAP10_OFFSET
2139 #define DDRC_ADDRMAP10_OFFSET                                                      0XFD070228
2140 #undef DDRC_ADDRMAP11_OFFSET
2141 #define DDRC_ADDRMAP11_OFFSET                                                      0XFD07022C
2142 #undef DDRC_ODTCFG_OFFSET
2143 #define DDRC_ODTCFG_OFFSET                                                         0XFD070240
2144 #undef DDRC_ODTMAP_OFFSET
2145 #define DDRC_ODTMAP_OFFSET                                                         0XFD070244
2146 #undef DDRC_SCHED_OFFSET
2147 #define DDRC_SCHED_OFFSET                                                          0XFD070250
2148 #undef DDRC_PERFLPR1_OFFSET
2149 #define DDRC_PERFLPR1_OFFSET                                                       0XFD070264
2150 #undef DDRC_PERFWR1_OFFSET
2151 #define DDRC_PERFWR1_OFFSET                                                        0XFD07026C
2152 #undef DDRC_DQMAP5_OFFSET
2153 #define DDRC_DQMAP5_OFFSET                                                         0XFD070294
2154 #undef DDRC_DBG0_OFFSET
2155 #define DDRC_DBG0_OFFSET                                                           0XFD070300
2156 #undef DDRC_DBGCMD_OFFSET
2157 #define DDRC_DBGCMD_OFFSET                                                         0XFD07030C
2158 #undef DDRC_SWCTL_OFFSET
2159 #define DDRC_SWCTL_OFFSET                                                          0XFD070320
2160 #undef DDRC_PCCFG_OFFSET
2161 #define DDRC_PCCFG_OFFSET                                                          0XFD070400
2162 #undef DDRC_PCFGR_0_OFFSET
2163 #define DDRC_PCFGR_0_OFFSET                                                        0XFD070404
2164 #undef DDRC_PCFGW_0_OFFSET
2165 #define DDRC_PCFGW_0_OFFSET                                                        0XFD070408
2166 #undef DDRC_PCTRL_0_OFFSET
2167 #define DDRC_PCTRL_0_OFFSET                                                        0XFD070490
2168 #undef DDRC_PCFGQOS0_0_OFFSET
2169 #define DDRC_PCFGQOS0_0_OFFSET                                                     0XFD070494
2170 #undef DDRC_PCFGQOS1_0_OFFSET
2171 #define DDRC_PCFGQOS1_0_OFFSET                                                     0XFD070498
2172 #undef DDRC_PCFGR_1_OFFSET
2173 #define DDRC_PCFGR_1_OFFSET                                                        0XFD0704B4
2174 #undef DDRC_PCFGW_1_OFFSET
2175 #define DDRC_PCFGW_1_OFFSET                                                        0XFD0704B8
2176 #undef DDRC_PCTRL_1_OFFSET
2177 #define DDRC_PCTRL_1_OFFSET                                                        0XFD070540
2178 #undef DDRC_PCFGQOS0_1_OFFSET
2179 #define DDRC_PCFGQOS0_1_OFFSET                                                     0XFD070544
2180 #undef DDRC_PCFGQOS1_1_OFFSET
2181 #define DDRC_PCFGQOS1_1_OFFSET                                                     0XFD070548
2182 #undef DDRC_PCFGR_2_OFFSET
2183 #define DDRC_PCFGR_2_OFFSET                                                        0XFD070564
2184 #undef DDRC_PCFGW_2_OFFSET
2185 #define DDRC_PCFGW_2_OFFSET                                                        0XFD070568
2186 #undef DDRC_PCTRL_2_OFFSET
2187 #define DDRC_PCTRL_2_OFFSET                                                        0XFD0705F0
2188 #undef DDRC_PCFGQOS0_2_OFFSET
2189 #define DDRC_PCFGQOS0_2_OFFSET                                                     0XFD0705F4
2190 #undef DDRC_PCFGQOS1_2_OFFSET
2191 #define DDRC_PCFGQOS1_2_OFFSET                                                     0XFD0705F8
2192 #undef DDRC_PCFGR_3_OFFSET
2193 #define DDRC_PCFGR_3_OFFSET                                                        0XFD070614
2194 #undef DDRC_PCFGW_3_OFFSET
2195 #define DDRC_PCFGW_3_OFFSET                                                        0XFD070618
2196 #undef DDRC_PCTRL_3_OFFSET
2197 #define DDRC_PCTRL_3_OFFSET                                                        0XFD0706A0
2198 #undef DDRC_PCFGQOS0_3_OFFSET
2199 #define DDRC_PCFGQOS0_3_OFFSET                                                     0XFD0706A4
2200 #undef DDRC_PCFGQOS1_3_OFFSET
2201 #define DDRC_PCFGQOS1_3_OFFSET                                                     0XFD0706A8
2202 #undef DDRC_PCFGWQOS0_3_OFFSET
2203 #define DDRC_PCFGWQOS0_3_OFFSET                                                    0XFD0706AC
2204 #undef DDRC_PCFGWQOS1_3_OFFSET
2205 #define DDRC_PCFGWQOS1_3_OFFSET                                                    0XFD0706B0
2206 #undef DDRC_PCFGR_4_OFFSET
2207 #define DDRC_PCFGR_4_OFFSET                                                        0XFD0706C4
2208 #undef DDRC_PCFGW_4_OFFSET
2209 #define DDRC_PCFGW_4_OFFSET                                                        0XFD0706C8
2210 #undef DDRC_PCTRL_4_OFFSET
2211 #define DDRC_PCTRL_4_OFFSET                                                        0XFD070750
2212 #undef DDRC_PCFGQOS0_4_OFFSET
2213 #define DDRC_PCFGQOS0_4_OFFSET                                                     0XFD070754
2214 #undef DDRC_PCFGQOS1_4_OFFSET
2215 #define DDRC_PCFGQOS1_4_OFFSET                                                     0XFD070758
2216 #undef DDRC_PCFGWQOS0_4_OFFSET
2217 #define DDRC_PCFGWQOS0_4_OFFSET                                                    0XFD07075C
2218 #undef DDRC_PCFGWQOS1_4_OFFSET
2219 #define DDRC_PCFGWQOS1_4_OFFSET                                                    0XFD070760
2220 #undef DDRC_PCFGR_5_OFFSET
2221 #define DDRC_PCFGR_5_OFFSET                                                        0XFD070774
2222 #undef DDRC_PCFGW_5_OFFSET
2223 #define DDRC_PCFGW_5_OFFSET                                                        0XFD070778
2224 #undef DDRC_PCTRL_5_OFFSET
2225 #define DDRC_PCTRL_5_OFFSET                                                        0XFD070800
2226 #undef DDRC_PCFGQOS0_5_OFFSET
2227 #define DDRC_PCFGQOS0_5_OFFSET                                                     0XFD070804
2228 #undef DDRC_PCFGQOS1_5_OFFSET
2229 #define DDRC_PCFGQOS1_5_OFFSET                                                     0XFD070808
2230 #undef DDRC_PCFGWQOS0_5_OFFSET
2231 #define DDRC_PCFGWQOS0_5_OFFSET                                                    0XFD07080C
2232 #undef DDRC_PCFGWQOS1_5_OFFSET
2233 #define DDRC_PCFGWQOS1_5_OFFSET                                                    0XFD070810
2234 #undef DDRC_SARBASE0_OFFSET
2235 #define DDRC_SARBASE0_OFFSET                                                       0XFD070F04
2236 #undef DDRC_SARSIZE0_OFFSET
2237 #define DDRC_SARSIZE0_OFFSET                                                       0XFD070F08
2238 #undef DDRC_SARBASE1_OFFSET
2239 #define DDRC_SARBASE1_OFFSET                                                       0XFD070F0C
2240 #undef DDRC_SARSIZE1_OFFSET
2241 #define DDRC_SARSIZE1_OFFSET                                                       0XFD070F10
2242 #undef DDRC_DFITMG0_SHADOW_OFFSET
2243 #define DDRC_DFITMG0_SHADOW_OFFSET                                                 0XFD072190
2244 #undef CRF_APB_RST_DDR_SS_OFFSET
2245 #define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
2246 #undef DDR_PHY_PGCR0_OFFSET
2247 #define DDR_PHY_PGCR0_OFFSET                                                       0XFD080010
2248 #undef DDR_PHY_PGCR2_OFFSET
2249 #define DDR_PHY_PGCR2_OFFSET                                                       0XFD080018
2250 #undef DDR_PHY_PGCR3_OFFSET
2251 #define DDR_PHY_PGCR3_OFFSET                                                       0XFD08001C
2252 #undef DDR_PHY_PGCR5_OFFSET
2253 #define DDR_PHY_PGCR5_OFFSET                                                       0XFD080024
2254 #undef DDR_PHY_PTR0_OFFSET
2255 #define DDR_PHY_PTR0_OFFSET                                                        0XFD080040
2256 #undef DDR_PHY_PTR1_OFFSET
2257 #define DDR_PHY_PTR1_OFFSET                                                        0XFD080044
2258 #undef DDR_PHY_DSGCR_OFFSET
2259 #define DDR_PHY_DSGCR_OFFSET                                                       0XFD080090
2260 #undef DDR_PHY_DCR_OFFSET
2261 #define DDR_PHY_DCR_OFFSET                                                         0XFD080100
2262 #undef DDR_PHY_DTPR0_OFFSET
2263 #define DDR_PHY_DTPR0_OFFSET                                                       0XFD080110
2264 #undef DDR_PHY_DTPR1_OFFSET
2265 #define DDR_PHY_DTPR1_OFFSET                                                       0XFD080114
2266 #undef DDR_PHY_DTPR2_OFFSET
2267 #define DDR_PHY_DTPR2_OFFSET                                                       0XFD080118
2268 #undef DDR_PHY_DTPR3_OFFSET
2269 #define DDR_PHY_DTPR3_OFFSET                                                       0XFD08011C
2270 #undef DDR_PHY_DTPR4_OFFSET
2271 #define DDR_PHY_DTPR4_OFFSET                                                       0XFD080120
2272 #undef DDR_PHY_DTPR5_OFFSET
2273 #define DDR_PHY_DTPR5_OFFSET                                                       0XFD080124
2274 #undef DDR_PHY_DTPR6_OFFSET
2275 #define DDR_PHY_DTPR6_OFFSET                                                       0XFD080128
2276 #undef DDR_PHY_RDIMMGCR0_OFFSET
2277 #define DDR_PHY_RDIMMGCR0_OFFSET                                                   0XFD080140
2278 #undef DDR_PHY_RDIMMGCR1_OFFSET
2279 #define DDR_PHY_RDIMMGCR1_OFFSET                                                   0XFD080144
2280 #undef DDR_PHY_RDIMMCR0_OFFSET
2281 #define DDR_PHY_RDIMMCR0_OFFSET                                                    0XFD080150
2282 #undef DDR_PHY_RDIMMCR1_OFFSET
2283 #define DDR_PHY_RDIMMCR1_OFFSET                                                    0XFD080154
2284 #undef DDR_PHY_MR0_OFFSET
2285 #define DDR_PHY_MR0_OFFSET                                                         0XFD080180
2286 #undef DDR_PHY_MR1_OFFSET
2287 #define DDR_PHY_MR1_OFFSET                                                         0XFD080184
2288 #undef DDR_PHY_MR2_OFFSET
2289 #define DDR_PHY_MR2_OFFSET                                                         0XFD080188
2290 #undef DDR_PHY_MR3_OFFSET
2291 #define DDR_PHY_MR3_OFFSET                                                         0XFD08018C
2292 #undef DDR_PHY_MR4_OFFSET
2293 #define DDR_PHY_MR4_OFFSET                                                         0XFD080190
2294 #undef DDR_PHY_MR5_OFFSET
2295 #define DDR_PHY_MR5_OFFSET                                                         0XFD080194
2296 #undef DDR_PHY_MR6_OFFSET
2297 #define DDR_PHY_MR6_OFFSET                                                         0XFD080198
2298 #undef DDR_PHY_MR11_OFFSET
2299 #define DDR_PHY_MR11_OFFSET                                                        0XFD0801AC
2300 #undef DDR_PHY_MR12_OFFSET
2301 #define DDR_PHY_MR12_OFFSET                                                        0XFD0801B0
2302 #undef DDR_PHY_MR13_OFFSET
2303 #define DDR_PHY_MR13_OFFSET                                                        0XFD0801B4
2304 #undef DDR_PHY_MR14_OFFSET
2305 #define DDR_PHY_MR14_OFFSET                                                        0XFD0801B8
2306 #undef DDR_PHY_MR22_OFFSET
2307 #define DDR_PHY_MR22_OFFSET                                                        0XFD0801D8
2308 #undef DDR_PHY_DTCR0_OFFSET
2309 #define DDR_PHY_DTCR0_OFFSET                                                       0XFD080200
2310 #undef DDR_PHY_DTCR1_OFFSET
2311 #define DDR_PHY_DTCR1_OFFSET                                                       0XFD080204
2312 #undef DDR_PHY_CATR0_OFFSET
2313 #define DDR_PHY_CATR0_OFFSET                                                       0XFD080240
2314 #undef DDR_PHY_BISTLSR_OFFSET
2315 #define DDR_PHY_BISTLSR_OFFSET                                                     0XFD080414
2316 #undef DDR_PHY_RIOCR5_OFFSET
2317 #define DDR_PHY_RIOCR5_OFFSET                                                      0XFD0804F4
2318 #undef DDR_PHY_ACIOCR0_OFFSET
2319 #define DDR_PHY_ACIOCR0_OFFSET                                                     0XFD080500
2320 #undef DDR_PHY_ACIOCR2_OFFSET
2321 #define DDR_PHY_ACIOCR2_OFFSET                                                     0XFD080508
2322 #undef DDR_PHY_ACIOCR3_OFFSET
2323 #define DDR_PHY_ACIOCR3_OFFSET                                                     0XFD08050C
2324 #undef DDR_PHY_ACIOCR4_OFFSET
2325 #define DDR_PHY_ACIOCR4_OFFSET                                                     0XFD080510
2326 #undef DDR_PHY_IOVCR0_OFFSET
2327 #define DDR_PHY_IOVCR0_OFFSET                                                      0XFD080520
2328 #undef DDR_PHY_VTCR0_OFFSET
2329 #define DDR_PHY_VTCR0_OFFSET                                                       0XFD080528
2330 #undef DDR_PHY_VTCR1_OFFSET
2331 #define DDR_PHY_VTCR1_OFFSET                                                       0XFD08052C
2332 #undef DDR_PHY_ACBDLR1_OFFSET
2333 #define DDR_PHY_ACBDLR1_OFFSET                                                     0XFD080544
2334 #undef DDR_PHY_ACBDLR2_OFFSET
2335 #define DDR_PHY_ACBDLR2_OFFSET                                                     0XFD080548
2336 #undef DDR_PHY_ACBDLR6_OFFSET
2337 #define DDR_PHY_ACBDLR6_OFFSET                                                     0XFD080558
2338 #undef DDR_PHY_ACBDLR7_OFFSET
2339 #define DDR_PHY_ACBDLR7_OFFSET                                                     0XFD08055C
2340 #undef DDR_PHY_ACBDLR8_OFFSET
2341 #define DDR_PHY_ACBDLR8_OFFSET                                                     0XFD080560
2342 #undef DDR_PHY_ACBDLR9_OFFSET
2343 #define DDR_PHY_ACBDLR9_OFFSET                                                     0XFD080564
2344 #undef DDR_PHY_ZQCR_OFFSET
2345 #define DDR_PHY_ZQCR_OFFSET                                                        0XFD080680
2346 #undef DDR_PHY_ZQ0PR0_OFFSET
2347 #define DDR_PHY_ZQ0PR0_OFFSET                                                      0XFD080684
2348 #undef DDR_PHY_ZQ0OR0_OFFSET
2349 #define DDR_PHY_ZQ0OR0_OFFSET                                                      0XFD080694
2350 #undef DDR_PHY_ZQ0OR1_OFFSET
2351 #define DDR_PHY_ZQ0OR1_OFFSET                                                      0XFD080698
2352 #undef DDR_PHY_ZQ1PR0_OFFSET
2353 #define DDR_PHY_ZQ1PR0_OFFSET                                                      0XFD0806A4
2354 #undef DDR_PHY_DX0GCR0_OFFSET
2355 #define DDR_PHY_DX0GCR0_OFFSET                                                     0XFD080700
2356 #undef DDR_PHY_DX0GCR4_OFFSET
2357 #define DDR_PHY_DX0GCR4_OFFSET                                                     0XFD080710
2358 #undef DDR_PHY_DX0GCR5_OFFSET
2359 #define DDR_PHY_DX0GCR5_OFFSET                                                     0XFD080714
2360 #undef DDR_PHY_DX0GCR6_OFFSET
2361 #define DDR_PHY_DX0GCR6_OFFSET                                                     0XFD080718
2362 #undef DDR_PHY_DX0LCDLR2_OFFSET
2363 #define DDR_PHY_DX0LCDLR2_OFFSET                                                   0XFD080788
2364 #undef DDR_PHY_DX0GTR0_OFFSET
2365 #define DDR_PHY_DX0GTR0_OFFSET                                                     0XFD0807C0
2366 #undef DDR_PHY_DX1GCR0_OFFSET
2367 #define DDR_PHY_DX1GCR0_OFFSET                                                     0XFD080800
2368 #undef DDR_PHY_DX1GCR4_OFFSET
2369 #define DDR_PHY_DX1GCR4_OFFSET                                                     0XFD080810
2370 #undef DDR_PHY_DX1GCR5_OFFSET
2371 #define DDR_PHY_DX1GCR5_OFFSET                                                     0XFD080814
2372 #undef DDR_PHY_DX1GCR6_OFFSET
2373 #define DDR_PHY_DX1GCR6_OFFSET                                                     0XFD080818
2374 #undef DDR_PHY_DX1LCDLR2_OFFSET
2375 #define DDR_PHY_DX1LCDLR2_OFFSET                                                   0XFD080888
2376 #undef DDR_PHY_DX1GTR0_OFFSET
2377 #define DDR_PHY_DX1GTR0_OFFSET                                                     0XFD0808C0
2378 #undef DDR_PHY_DX2GCR0_OFFSET
2379 #define DDR_PHY_DX2GCR0_OFFSET                                                     0XFD080900
2380 #undef DDR_PHY_DX2GCR1_OFFSET
2381 #define DDR_PHY_DX2GCR1_OFFSET                                                     0XFD080904
2382 #undef DDR_PHY_DX2GCR4_OFFSET
2383 #define DDR_PHY_DX2GCR4_OFFSET                                                     0XFD080910
2384 #undef DDR_PHY_DX2GCR5_OFFSET
2385 #define DDR_PHY_DX2GCR5_OFFSET                                                     0XFD080914
2386 #undef DDR_PHY_DX2GCR6_OFFSET
2387 #define DDR_PHY_DX2GCR6_OFFSET                                                     0XFD080918
2388 #undef DDR_PHY_DX2LCDLR2_OFFSET
2389 #define DDR_PHY_DX2LCDLR2_OFFSET                                                   0XFD080988
2390 #undef DDR_PHY_DX2GTR0_OFFSET
2391 #define DDR_PHY_DX2GTR0_OFFSET                                                     0XFD0809C0
2392 #undef DDR_PHY_DX3GCR0_OFFSET
2393 #define DDR_PHY_DX3GCR0_OFFSET                                                     0XFD080A00
2394 #undef DDR_PHY_DX3GCR1_OFFSET
2395 #define DDR_PHY_DX3GCR1_OFFSET                                                     0XFD080A04
2396 #undef DDR_PHY_DX3GCR4_OFFSET
2397 #define DDR_PHY_DX3GCR4_OFFSET                                                     0XFD080A10
2398 #undef DDR_PHY_DX3GCR5_OFFSET
2399 #define DDR_PHY_DX3GCR5_OFFSET                                                     0XFD080A14
2400 #undef DDR_PHY_DX3GCR6_OFFSET
2401 #define DDR_PHY_DX3GCR6_OFFSET                                                     0XFD080A18
2402 #undef DDR_PHY_DX3LCDLR2_OFFSET
2403 #define DDR_PHY_DX3LCDLR2_OFFSET                                                   0XFD080A88
2404 #undef DDR_PHY_DX3GTR0_OFFSET
2405 #define DDR_PHY_DX3GTR0_OFFSET                                                     0XFD080AC0
2406 #undef DDR_PHY_DX4GCR0_OFFSET
2407 #define DDR_PHY_DX4GCR0_OFFSET                                                     0XFD080B00
2408 #undef DDR_PHY_DX4GCR1_OFFSET
2409 #define DDR_PHY_DX4GCR1_OFFSET                                                     0XFD080B04
2410 #undef DDR_PHY_DX4GCR4_OFFSET
2411 #define DDR_PHY_DX4GCR4_OFFSET                                                     0XFD080B10
2412 #undef DDR_PHY_DX4GCR5_OFFSET
2413 #define DDR_PHY_DX4GCR5_OFFSET                                                     0XFD080B14
2414 #undef DDR_PHY_DX4GCR6_OFFSET
2415 #define DDR_PHY_DX4GCR6_OFFSET                                                     0XFD080B18
2416 #undef DDR_PHY_DX4LCDLR2_OFFSET
2417 #define DDR_PHY_DX4LCDLR2_OFFSET                                                   0XFD080B88
2418 #undef DDR_PHY_DX4GTR0_OFFSET
2419 #define DDR_PHY_DX4GTR0_OFFSET                                                     0XFD080BC0
2420 #undef DDR_PHY_DX5GCR0_OFFSET
2421 #define DDR_PHY_DX5GCR0_OFFSET                                                     0XFD080C00
2422 #undef DDR_PHY_DX5GCR1_OFFSET
2423 #define DDR_PHY_DX5GCR1_OFFSET                                                     0XFD080C04
2424 #undef DDR_PHY_DX5GCR4_OFFSET
2425 #define DDR_PHY_DX5GCR4_OFFSET                                                     0XFD080C10
2426 #undef DDR_PHY_DX5GCR5_OFFSET
2427 #define DDR_PHY_DX5GCR5_OFFSET                                                     0XFD080C14
2428 #undef DDR_PHY_DX5GCR6_OFFSET
2429 #define DDR_PHY_DX5GCR6_OFFSET                                                     0XFD080C18
2430 #undef DDR_PHY_DX5LCDLR2_OFFSET
2431 #define DDR_PHY_DX5LCDLR2_OFFSET                                                   0XFD080C88
2432 #undef DDR_PHY_DX5GTR0_OFFSET
2433 #define DDR_PHY_DX5GTR0_OFFSET                                                     0XFD080CC0
2434 #undef DDR_PHY_DX6GCR0_OFFSET
2435 #define DDR_PHY_DX6GCR0_OFFSET                                                     0XFD080D00
2436 #undef DDR_PHY_DX6GCR1_OFFSET
2437 #define DDR_PHY_DX6GCR1_OFFSET                                                     0XFD080D04
2438 #undef DDR_PHY_DX6GCR4_OFFSET
2439 #define DDR_PHY_DX6GCR4_OFFSET                                                     0XFD080D10
2440 #undef DDR_PHY_DX6GCR5_OFFSET
2441 #define DDR_PHY_DX6GCR5_OFFSET                                                     0XFD080D14
2442 #undef DDR_PHY_DX6GCR6_OFFSET
2443 #define DDR_PHY_DX6GCR6_OFFSET                                                     0XFD080D18
2444 #undef DDR_PHY_DX6LCDLR2_OFFSET
2445 #define DDR_PHY_DX6LCDLR2_OFFSET                                                   0XFD080D88
2446 #undef DDR_PHY_DX6GTR0_OFFSET
2447 #define DDR_PHY_DX6GTR0_OFFSET                                                     0XFD080DC0
2448 #undef DDR_PHY_DX7GCR0_OFFSET
2449 #define DDR_PHY_DX7GCR0_OFFSET                                                     0XFD080E00
2450 #undef DDR_PHY_DX7GCR1_OFFSET
2451 #define DDR_PHY_DX7GCR1_OFFSET                                                     0XFD080E04
2452 #undef DDR_PHY_DX7GCR4_OFFSET
2453 #define DDR_PHY_DX7GCR4_OFFSET                                                     0XFD080E10
2454 #undef DDR_PHY_DX7GCR5_OFFSET
2455 #define DDR_PHY_DX7GCR5_OFFSET                                                     0XFD080E14
2456 #undef DDR_PHY_DX7GCR6_OFFSET
2457 #define DDR_PHY_DX7GCR6_OFFSET                                                     0XFD080E18
2458 #undef DDR_PHY_DX7LCDLR2_OFFSET
2459 #define DDR_PHY_DX7LCDLR2_OFFSET                                                   0XFD080E88
2460 #undef DDR_PHY_DX7GTR0_OFFSET
2461 #define DDR_PHY_DX7GTR0_OFFSET                                                     0XFD080EC0
2462 #undef DDR_PHY_DX8GCR0_OFFSET
2463 #define DDR_PHY_DX8GCR0_OFFSET                                                     0XFD080F00
2464 #undef DDR_PHY_DX8GCR1_OFFSET
2465 #define DDR_PHY_DX8GCR1_OFFSET                                                     0XFD080F04
2466 #undef DDR_PHY_DX8GCR4_OFFSET
2467 #define DDR_PHY_DX8GCR4_OFFSET                                                     0XFD080F10
2468 #undef DDR_PHY_DX8GCR5_OFFSET
2469 #define DDR_PHY_DX8GCR5_OFFSET                                                     0XFD080F14
2470 #undef DDR_PHY_DX8GCR6_OFFSET
2471 #define DDR_PHY_DX8GCR6_OFFSET                                                     0XFD080F18
2472 #undef DDR_PHY_DX8LCDLR2_OFFSET
2473 #define DDR_PHY_DX8LCDLR2_OFFSET                                                   0XFD080F88
2474 #undef DDR_PHY_DX8GTR0_OFFSET
2475 #define DDR_PHY_DX8GTR0_OFFSET                                                     0XFD080FC0
2476 #undef DDR_PHY_DX8SL0OSC_OFFSET
2477 #define DDR_PHY_DX8SL0OSC_OFFSET                                                   0XFD081400
2478 #undef DDR_PHY_DX8SL0DQSCTL_OFFSET
2479 #define DDR_PHY_DX8SL0DQSCTL_OFFSET                                                0XFD08141C
2480 #undef DDR_PHY_DX8SL0DXCTL2_OFFSET
2481 #define DDR_PHY_DX8SL0DXCTL2_OFFSET                                                0XFD08142C
2482 #undef DDR_PHY_DX8SL0IOCR_OFFSET
2483 #define DDR_PHY_DX8SL0IOCR_OFFSET                                                  0XFD081430
2484 #undef DDR_PHY_DX8SL1OSC_OFFSET
2485 #define DDR_PHY_DX8SL1OSC_OFFSET                                                   0XFD081440
2486 #undef DDR_PHY_DX8SL1DQSCTL_OFFSET
2487 #define DDR_PHY_DX8SL1DQSCTL_OFFSET                                                0XFD08145C
2488 #undef DDR_PHY_DX8SL1DXCTL2_OFFSET
2489 #define DDR_PHY_DX8SL1DXCTL2_OFFSET                                                0XFD08146C
2490 #undef DDR_PHY_DX8SL1IOCR_OFFSET
2491 #define DDR_PHY_DX8SL1IOCR_OFFSET                                                  0XFD081470
2492 #undef DDR_PHY_DX8SL2OSC_OFFSET
2493 #define DDR_PHY_DX8SL2OSC_OFFSET                                                   0XFD081480
2494 #undef DDR_PHY_DX8SL2DQSCTL_OFFSET
2495 #define DDR_PHY_DX8SL2DQSCTL_OFFSET                                                0XFD08149C
2496 #undef DDR_PHY_DX8SL2DXCTL2_OFFSET
2497 #define DDR_PHY_DX8SL2DXCTL2_OFFSET                                                0XFD0814AC
2498 #undef DDR_PHY_DX8SL2IOCR_OFFSET
2499 #define DDR_PHY_DX8SL2IOCR_OFFSET                                                  0XFD0814B0
2500 #undef DDR_PHY_DX8SL3OSC_OFFSET
2501 #define DDR_PHY_DX8SL3OSC_OFFSET                                                   0XFD0814C0
2502 #undef DDR_PHY_DX8SL3DQSCTL_OFFSET
2503 #define DDR_PHY_DX8SL3DQSCTL_OFFSET                                                0XFD0814DC
2504 #undef DDR_PHY_DX8SL3DXCTL2_OFFSET
2505 #define DDR_PHY_DX8SL3DXCTL2_OFFSET                                                0XFD0814EC
2506 #undef DDR_PHY_DX8SL3IOCR_OFFSET
2507 #define DDR_PHY_DX8SL3IOCR_OFFSET                                                  0XFD0814F0
2508 #undef DDR_PHY_DX8SL4OSC_OFFSET
2509 #define DDR_PHY_DX8SL4OSC_OFFSET                                                   0XFD081500
2510 #undef DDR_PHY_DX8SL4DQSCTL_OFFSET
2511 #define DDR_PHY_DX8SL4DQSCTL_OFFSET                                                0XFD08151C
2512 #undef DDR_PHY_DX8SL4DXCTL2_OFFSET
2513 #define DDR_PHY_DX8SL4DXCTL2_OFFSET                                                0XFD08152C
2514 #undef DDR_PHY_DX8SL4IOCR_OFFSET
2515 #define DDR_PHY_DX8SL4IOCR_OFFSET                                                  0XFD081530
2516 #undef DDR_PHY_DX8SLBDQSCTL_OFFSET
2517 #define DDR_PHY_DX8SLBDQSCTL_OFFSET                                                0XFD0817DC
2518 #undef DDR_PHY_PIR_OFFSET
2519 #define DDR_PHY_PIR_OFFSET                                                         0XFD080004
2520
2521 /*DDR block level reset inside of the DDR Sub System*/
2522 #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
2523 #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
2524 #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
2525 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                                        0x0000000F
2526 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                                         3
2527 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                                          0x00000008U
2528
2529 /*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32
2530                 evice*/
2531 #undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL
2532 #undef DDRC_MSTR_DEVICE_CONFIG_SHIFT
2533 #undef DDRC_MSTR_DEVICE_CONFIG_MASK
2534 #define DDRC_MSTR_DEVICE_CONFIG_DEFVAL                                             0x03040001
2535 #define DDRC_MSTR_DEVICE_CONFIG_SHIFT                                              30
2536 #define DDRC_MSTR_DEVICE_CONFIG_MASK                                               0xC0000000U
2537
2538 /*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/
2539 #undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL
2540 #undef DDRC_MSTR_FREQUENCY_MODE_SHIFT
2541 #undef DDRC_MSTR_FREQUENCY_MODE_MASK
2542 #define DDRC_MSTR_FREQUENCY_MODE_DEFVAL                                            0x03040001
2543 #define DDRC_MSTR_FREQUENCY_MODE_SHIFT                                             29
2544 #define DDRC_MSTR_FREQUENCY_MODE_MASK                                              0x20000000U
2545
2546 /*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
2547                 esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 -
2548                 ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
2549                 ks - 1111 - Four ranks*/
2550 #undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL
2551 #undef DDRC_MSTR_ACTIVE_RANKS_SHIFT
2552 #undef DDRC_MSTR_ACTIVE_RANKS_MASK
2553 #define DDRC_MSTR_ACTIVE_RANKS_DEFVAL                                              0x03040001
2554 #define DDRC_MSTR_ACTIVE_RANKS_SHIFT                                               24
2555 #define DDRC_MSTR_ACTIVE_RANKS_MASK                                                0x03000000U
2556
2557 /*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
2558                  of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls
2559                 he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
2560                 -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
2561                  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/
2562 #undef DDRC_MSTR_BURST_RDWR_DEFVAL
2563 #undef DDRC_MSTR_BURST_RDWR_SHIFT
2564 #undef DDRC_MSTR_BURST_RDWR_MASK
2565 #define DDRC_MSTR_BURST_RDWR_DEFVAL                                                0x03040001
2566 #define DDRC_MSTR_BURST_RDWR_SHIFT                                                 16
2567 #define DDRC_MSTR_BURST_RDWR_MASK                                                  0x000F0000U
2568
2569 /*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM
2570                 n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
2571                 l_off_mode is not supported, and this bit must be set to '0'.*/
2572 #undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL
2573 #undef DDRC_MSTR_DLL_OFF_MODE_SHIFT
2574 #undef DDRC_MSTR_DLL_OFF_MODE_MASK
2575 #define DDRC_MSTR_DLL_OFF_MODE_DEFVAL                                              0x03040001
2576 #define DDRC_MSTR_DLL_OFF_MODE_SHIFT                                               15
2577 #define DDRC_MSTR_DLL_OFF_MODE_MASK                                                0x00008000U
2578
2579 /*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
2580                 AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
2581                 dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
2582                 figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/
2583 #undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL
2584 #undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
2585 #undef DDRC_MSTR_DATA_BUS_WIDTH_MASK
2586 #define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL                                            0x03040001
2587 #define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT                                             12
2588 #define DDRC_MSTR_DATA_BUS_WIDTH_MASK                                              0x00003000U
2589
2590 /*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
2591                  only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode
2592                 s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/
2593 #undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL
2594 #undef DDRC_MSTR_GEARDOWN_MODE_SHIFT
2595 #undef DDRC_MSTR_GEARDOWN_MODE_MASK
2596 #define DDRC_MSTR_GEARDOWN_MODE_DEFVAL                                             0x03040001
2597 #define DDRC_MSTR_GEARDOWN_MODE_SHIFT                                              11
2598 #define DDRC_MSTR_GEARDOWN_MODE_MASK                                               0x00000800U
2599
2600 /*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held
2601                 or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in
2602                 PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
2603                 ing is not supported in DDR4 geardown mode.*/
2604 #undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL
2605 #undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
2606 #undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK
2607 #define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL                                         0x03040001
2608 #define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT                                          10
2609 #define DDRC_MSTR_EN_2T_TIMING_MODE_MASK                                           0x00000400U
2610
2611 /*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
2612                 t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
2613                  (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
2614                 _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/
2615 #undef DDRC_MSTR_BURSTCHOP_DEFVAL
2616 #undef DDRC_MSTR_BURSTCHOP_SHIFT
2617 #undef DDRC_MSTR_BURSTCHOP_MASK
2618 #define DDRC_MSTR_BURSTCHOP_DEFVAL                                                 0x03040001
2619 #define DDRC_MSTR_BURSTCHOP_SHIFT                                                  9
2620 #define DDRC_MSTR_BURSTCHOP_MASK                                                   0x00000200U
2621
2622 /*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
2623                 port LPDDR4.*/
2624 #undef DDRC_MSTR_LPDDR4_DEFVAL
2625 #undef DDRC_MSTR_LPDDR4_SHIFT
2626 #undef DDRC_MSTR_LPDDR4_MASK
2627 #define DDRC_MSTR_LPDDR4_DEFVAL                                                    0x03040001
2628 #define DDRC_MSTR_LPDDR4_SHIFT                                                     5
2629 #define DDRC_MSTR_LPDDR4_MASK                                                      0x00000020U
2630
2631 /*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support
2632                 DR4.*/
2633 #undef DDRC_MSTR_DDR4_DEFVAL
2634 #undef DDRC_MSTR_DDR4_SHIFT
2635 #undef DDRC_MSTR_DDR4_MASK
2636 #define DDRC_MSTR_DDR4_DEFVAL                                                      0x03040001
2637 #define DDRC_MSTR_DDR4_SHIFT                                                       4
2638 #define DDRC_MSTR_DDR4_MASK                                                        0x00000010U
2639
2640 /*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
2641                 port LPDDR3.*/
2642 #undef DDRC_MSTR_LPDDR3_DEFVAL
2643 #undef DDRC_MSTR_LPDDR3_SHIFT
2644 #undef DDRC_MSTR_LPDDR3_MASK
2645 #define DDRC_MSTR_LPDDR3_DEFVAL                                                    0x03040001
2646 #define DDRC_MSTR_LPDDR3_SHIFT                                                     3
2647 #define DDRC_MSTR_LPDDR3_MASK                                                      0x00000008U
2648
2649 /*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
2650                 port LPDDR2.*/
2651 #undef DDRC_MSTR_LPDDR2_DEFVAL
2652 #undef DDRC_MSTR_LPDDR2_SHIFT
2653 #undef DDRC_MSTR_LPDDR2_MASK
2654 #define DDRC_MSTR_LPDDR2_DEFVAL                                                    0x03040001
2655 #define DDRC_MSTR_LPDDR2_SHIFT                                                     2
2656 #define DDRC_MSTR_LPDDR2_MASK                                                      0x00000004U
2657
2658 /*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
2659                 */
2660 #undef DDRC_MSTR_DDR3_DEFVAL
2661 #undef DDRC_MSTR_DDR3_SHIFT
2662 #undef DDRC_MSTR_DDR3_MASK
2663 #define DDRC_MSTR_DDR3_DEFVAL                                                      0x03040001
2664 #define DDRC_MSTR_DDR3_SHIFT                                                       0
2665 #define DDRC_MSTR_DDR3_MASK                                                        0x00000001U
2666
2667 /*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
2668                  automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
2669                 re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/
2670 #undef DDRC_MRCTRL0_MR_WR_DEFVAL
2671 #undef DDRC_MRCTRL0_MR_WR_SHIFT
2672 #undef DDRC_MRCTRL0_MR_WR_MASK
2673 #define DDRC_MRCTRL0_MR_WR_DEFVAL                                                  0x00000030
2674 #define DDRC_MRCTRL0_MR_WR_SHIFT                                                   31
2675 #define DDRC_MRCTRL0_MR_WR_MASK                                                    0x80000000U
2676
2677 /*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
2678                  - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
2679                 R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
2680                 dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well
2681                 s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
2682                 put Inversion of RDIMMs.*/
2683 #undef DDRC_MRCTRL0_MR_ADDR_DEFVAL
2684 #undef DDRC_MRCTRL0_MR_ADDR_SHIFT
2685 #undef DDRC_MRCTRL0_MR_ADDR_MASK
2686 #define DDRC_MRCTRL0_MR_ADDR_DEFVAL                                                0x00000030
2687 #define DDRC_MRCTRL0_MR_ADDR_SHIFT                                                 12
2688 #define DDRC_MRCTRL0_MR_ADDR_MASK                                                  0x0000F000U
2689
2690 /*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
2691                  However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
2692                 amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks
2693                  and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/
2694 #undef DDRC_MRCTRL0_MR_RANK_DEFVAL
2695 #undef DDRC_MRCTRL0_MR_RANK_SHIFT
2696 #undef DDRC_MRCTRL0_MR_RANK_MASK
2697 #define DDRC_MRCTRL0_MR_RANK_DEFVAL                                                0x00000030
2698 #define DDRC_MRCTRL0_MR_RANK_SHIFT                                                 4
2699 #define DDRC_MRCTRL0_MR_RANK_MASK                                                  0x00000030U
2700
2701 /*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not.
2702                 or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
2703                  be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared
2704                 o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
2705                 n is not allowed - 1 - Software intervention is allowed*/
2706 #undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL
2707 #undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT
2708 #undef DDRC_MRCTRL0_SW_INIT_INT_MASK
2709 #define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL                                            0x00000030
2710 #define DDRC_MRCTRL0_SW_INIT_INT_SHIFT                                             3
2711 #define DDRC_MRCTRL0_SW_INIT_INT_MASK                                              0x00000008U
2712
2713 /*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/
2714 #undef DDRC_MRCTRL0_PDA_EN_DEFVAL
2715 #undef DDRC_MRCTRL0_PDA_EN_SHIFT
2716 #undef DDRC_MRCTRL0_PDA_EN_MASK
2717 #define DDRC_MRCTRL0_PDA_EN_DEFVAL                                                 0x00000030
2718 #define DDRC_MRCTRL0_PDA_EN_SHIFT                                                  2
2719 #define DDRC_MRCTRL0_PDA_EN_MASK                                                   0x00000004U
2720
2721 /*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/
2722 #undef DDRC_MRCTRL0_MPR_EN_DEFVAL
2723 #undef DDRC_MRCTRL0_MPR_EN_SHIFT
2724 #undef DDRC_MRCTRL0_MPR_EN_MASK
2725 #define DDRC_MRCTRL0_MPR_EN_DEFVAL                                                 0x00000030
2726 #define DDRC_MRCTRL0_MPR_EN_SHIFT                                                  1
2727 #define DDRC_MRCTRL0_MPR_EN_MASK                                                   0x00000002U
2728
2729 /*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
2730                 d*/
2731 #undef DDRC_MRCTRL0_MR_TYPE_DEFVAL
2732 #undef DDRC_MRCTRL0_MR_TYPE_SHIFT
2733 #undef DDRC_MRCTRL0_MR_TYPE_MASK
2734 #define DDRC_MRCTRL0_MR_TYPE_DEFVAL                                                0x00000030
2735 #define DDRC_MRCTRL0_MR_TYPE_SHIFT                                                 0
2736 #define DDRC_MRCTRL0_MR_TYPE_MASK                                                  0x00000001U
2737
2738 /*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
2739                  Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
2740                 g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/
2741 #undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL
2742 #undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
2743 #undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK
2744 #define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL                                       0x00000000
2745 #define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT                                        8
2746 #define DDRC_DERATEEN_RC_DERATE_VALUE_MASK                                         0x00000300U
2747
2748 /*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
2749                 r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/
2750 #undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL
2751 #undef DDRC_DERATEEN_DERATE_BYTE_SHIFT
2752 #undef DDRC_DERATEEN_DERATE_BYTE_MASK
2753 #define DDRC_DERATEEN_DERATE_BYTE_DEFVAL                                           0x00000000
2754 #define DDRC_DERATEEN_DERATE_BYTE_SHIFT                                            4
2755 #define DDRC_DERATEEN_DERATE_BYTE_MASK                                             0x000000F0U
2756
2757 /*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
2758                 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
2759                 for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/
2760 #undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL
2761 #undef DDRC_DERATEEN_DERATE_VALUE_SHIFT
2762 #undef DDRC_DERATEEN_DERATE_VALUE_MASK
2763 #define DDRC_DERATEEN_DERATE_VALUE_DEFVAL                                          0x00000000
2764 #define DDRC_DERATEEN_DERATE_VALUE_SHIFT                                           1
2765 #define DDRC_DERATEEN_DERATE_VALUE_MASK                                            0x00000002U
2766
2767 /*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
2768                 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
2769                 mode.*/
2770 #undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL
2771 #undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT
2772 #undef DDRC_DERATEEN_DERATE_ENABLE_MASK
2773 #define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL                                         0x00000000
2774 #define DDRC_DERATEEN_DERATE_ENABLE_SHIFT                                          0
2775 #define DDRC_DERATEEN_DERATE_ENABLE_MASK                                           0x00000001U
2776
2777 /*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
2778                 DR3/LPDDR4. This register must not be set to zero*/
2779 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
2780 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
2781 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK
2782 #define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
2783 #define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT                                     0
2784 #define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK                                      0xFFFFFFFFU
2785
2786 /*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
2787                 r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state -
2788                  - Allow transition from Self refresh state*/
2789 #undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL
2790 #undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
2791 #undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK
2792 #define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL                                         0x00000000
2793 #define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT                                          6
2794 #define DDRC_PWRCTL_STAY_IN_SELFREF_MASK                                           0x00000040U
2795
2796 /*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
2797                 M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
2798                 are Exit from Self Refresh*/
2799 #undef DDRC_PWRCTL_SELFREF_SW_DEFVAL
2800 #undef DDRC_PWRCTL_SELFREF_SW_SHIFT
2801 #undef DDRC_PWRCTL_SELFREF_SW_MASK
2802 #define DDRC_PWRCTL_SELFREF_SW_DEFVAL                                              0x00000000
2803 #define DDRC_PWRCTL_SELFREF_SW_SHIFT                                               5
2804 #define DDRC_PWRCTL_SELFREF_SW_MASK                                                0x00000020U
2805
2806 /*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
2807                 st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For
2808                 on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
2809                 DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/
2810 #undef DDRC_PWRCTL_MPSM_EN_DEFVAL
2811 #undef DDRC_PWRCTL_MPSM_EN_SHIFT
2812 #undef DDRC_PWRCTL_MPSM_EN_MASK
2813 #define DDRC_PWRCTL_MPSM_EN_DEFVAL                                                 0x00000000
2814 #define DDRC_PWRCTL_MPSM_EN_SHIFT                                                  4
2815 #define DDRC_PWRCTL_MPSM_EN_MASK                                                   0x00000010U
2816
2817 /*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
2818                 is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
2819                 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in
2820                 ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
2821                 rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/
2822 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL
2823 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
2824 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK
2825 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL                                 0x00000000
2826 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT                                  3
2827 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK                                   0x00000008U
2828
2829 /*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
2830                 et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down
2831                 xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
2832                  should not be set to 1. FOR PERFORMANCE ONLY.*/
2833 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL
2834 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
2835 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK
2836 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL                                        0x00000000
2837 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT                                         2
2838 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK                                          0x00000004U
2839
2840 /*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
2841                 RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/
2842 #undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL
2843 #undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT
2844 #undef DDRC_PWRCTL_POWERDOWN_EN_MASK
2845 #define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL                                            0x00000000
2846 #define DDRC_PWRCTL_POWERDOWN_EN_SHIFT                                             1
2847 #define DDRC_PWRCTL_POWERDOWN_EN_MASK                                              0x00000002U
2848
2849 /*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
2850                 f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/
2851 #undef DDRC_PWRCTL_SELFREF_EN_DEFVAL
2852 #undef DDRC_PWRCTL_SELFREF_EN_SHIFT
2853 #undef DDRC_PWRCTL_SELFREF_EN_MASK
2854 #define DDRC_PWRCTL_SELFREF_EN_DEFVAL                                              0x00000000
2855 #define DDRC_PWRCTL_SELFREF_EN_SHIFT                                               0
2856 #define DDRC_PWRCTL_SELFREF_EN_MASK                                                0x00000001U
2857
2858 /*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in
2859                 he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/
2860 #undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL
2861 #undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
2862 #undef DDRC_PWRTMG_SELFREF_TO_X32_MASK
2863 #define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL                                          0x00402010
2864 #define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT                                           16
2865 #define DDRC_PWRTMG_SELFREF_TO_X32_MASK                                            0x00FF0000U
2866
2867 /*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
2868                 ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
2869                 iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/
2870 #undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL
2871 #undef DDRC_PWRTMG_T_DPD_X4096_SHIFT
2872 #undef DDRC_PWRTMG_T_DPD_X4096_MASK
2873 #define DDRC_PWRTMG_T_DPD_X4096_DEFVAL                                             0x00402010
2874 #define DDRC_PWRTMG_T_DPD_X4096_SHIFT                                              8
2875 #define DDRC_PWRTMG_T_DPD_X4096_MASK                                               0x0000FF00U
2876
2877 /*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
2878                  PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/
2879 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL
2880 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
2881 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK
2882 #define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL                                        0x00402010
2883 #define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT                                         0
2884 #define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK                                          0x0000001FU
2885
2886 /*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
2887                 d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
2888                  It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
2889                 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
2890                 om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/
2891 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL
2892 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
2893 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK
2894 #define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL                                        0x00210000
2895 #define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT                                         20
2896 #define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK                                          0x00F00000U
2897
2898 /*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
2899                 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
2900                  would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
2901                 HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
2902                 formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
2903                 ued to the uMCTL2. FOR PERFORMANCE ONLY.*/
2904 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL
2905 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
2906 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK
2907 #define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL                                        0x00210000
2908 #define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT                                         12
2909 #define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK                                          0x0001F000U
2910
2911 /*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
2912                 reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
2913                 reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
2914                 RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
2915                 . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
2916                 tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
2917                 fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
2918                 ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
2919                 tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
2920                 d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
2921                 initiated update is complete.*/
2922 #undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL
2923 #undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
2924 #undef DDRC_RFSHCTL0_REFRESH_BURST_MASK
2925 #define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL                                         0x00210000
2926 #define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT                                          4
2927 #define DDRC_RFSHCTL0_REFRESH_BURST_MASK                                           0x000001F0U
2928
2929 /*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
2930                 t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
2931                 support LPDDR2/LPDDR3/LPDDR4*/
2932 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL
2933 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
2934 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK
2935 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL                                      0x00210000
2936 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT                                       2
2937 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK                                        0x00000004U
2938
2939 /*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
2940                 ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
2941                 orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
2942                 self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in
2943                 uture version of the uMCTL2.*/
2944 #undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL
2945 #undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
2946 #undef DDRC_RFSHCTL3_REFRESH_MODE_MASK
2947 #define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL                                          0x00000000
2948 #define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT                                           4
2949 #define DDRC_RFSHCTL3_REFRESH_MODE_MASK                                            0x00000070U
2950
2951 /*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value
2952                 s automatically updated when exiting reset, so it does not need to be toggled initially.*/
2953 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL
2954 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
2955 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK
2956 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL                                  0x00000000
2957 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT                                   1
2958 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK                                    0x00000002U
2959
2960 /*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
2961                 ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
2962                 auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
2963                 is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'.
2964                 his register field is changeable on the fly.*/
2965 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL
2966 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
2967 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK
2968 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL                                      0x00000000
2969 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT                                       0
2970 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK                                        0x00000001U
2971
2972 /*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
2973                  for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
2974                 , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should
2975                 e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
2976                 ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
2977                 programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
2978                 TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/
2979 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL
2980 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
2981 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK
2982 #define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL                                          0x0062008C
2983 #define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT                                           16
2984 #define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK                                            0x0FFF0000U
2985
2986 /*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the
2987                 REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
2988                  - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/
2989 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL
2990 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
2991 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK
2992 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL                                       0x0062008C
2993 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT                                        15
2994 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK                                         0x00008000U
2995
2996 /*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
2997                  RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
2998                 DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
2999                  per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
3000                 equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
3001                 opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/
3002 #undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL
3003 #undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT
3004 #undef DDRC_RFSHTMG_T_RFC_MIN_MASK
3005 #define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL                                              0x0062008C
3006 #define DDRC_RFSHTMG_T_RFC_MIN_SHIFT                                               0
3007 #define DDRC_RFSHTMG_T_RFC_MIN_MASK                                                0x000003FFU
3008
3009 /*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/
3010 #undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL
3011 #undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT
3012 #undef DDRC_ECCCFG0_DIS_SCRUB_MASK
3013 #define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL                                              0x00000000
3014 #define DDRC_ECCCFG0_DIS_SCRUB_SHIFT                                               4
3015 #define DDRC_ECCCFG0_DIS_SCRUB_MASK                                                0x00000010U
3016
3017 /*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
3018                  use*/
3019 #undef DDRC_ECCCFG0_ECC_MODE_DEFVAL
3020 #undef DDRC_ECCCFG0_ECC_MODE_SHIFT
3021 #undef DDRC_ECCCFG0_ECC_MODE_MASK
3022 #define DDRC_ECCCFG0_ECC_MODE_DEFVAL                                               0x00000000
3023 #define DDRC_ECCCFG0_ECC_MODE_SHIFT                                                0
3024 #define DDRC_ECCCFG0_ECC_MODE_MASK                                                 0x00000007U
3025
3026 /*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
3027                 ng, if ECCCFG1.data_poison_en=1*/
3028 #undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL
3029 #undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
3030 #undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK
3031 #define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL                                        0x00000000
3032 #define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT                                         1
3033 #define DDRC_ECCCFG1_DATA_POISON_BIT_MASK                                          0x00000002U
3034
3035 /*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/
3036 #undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL
3037 #undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
3038 #undef DDRC_ECCCFG1_DATA_POISON_EN_MASK
3039 #define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL                                         0x00000000
3040 #define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT                                          0
3041 #define DDRC_ECCCFG1_DATA_POISON_EN_MASK                                           0x00000001U
3042
3043 /*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
3044                 the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY
3045                 pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
3046                 L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
3047                 dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
3048                 e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/
3049 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL
3050 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
3051 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK
3052 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL                                     0x10000200
3053 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT                                      24
3054 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK                                       0x3F000000U
3055
3056 /*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
3057                 M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
3058                 the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
3059                 the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
3060                 RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
3061                  handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
3062                 rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
3063                 ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in
3064                 he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is
3065                 one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in
3066                 PR Page 1 should be treated as 'Don't care'.*/
3067 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL
3068 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
3069 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK
3070 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL                                   0x10000200
3071 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT                                    9
3072 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK                                     0x00000200U
3073
3074 /*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
3075                  CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
3076                  disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/
3077 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL
3078 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
3079 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK
3080 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL                             0x10000200
3081 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT                              8
3082 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK                               0x00000100U
3083
3084 /*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
3085                 d to support DDR4.*/
3086 #undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL
3087 #undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
3088 #undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK
3089 #define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL                                          0x10000200
3090 #define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT                                           7
3091 #define DDRC_CRCPARCTL1_CRC_INC_DM_MASK                                            0x00000080U
3092
3093 /*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
3094                  CRC mode register setting in the DRAM.*/
3095 #undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL
3096 #undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
3097 #undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK
3098 #define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL                                          0x10000200
3099 #define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT                                           4
3100 #define DDRC_CRCPARCTL1_CRC_ENABLE_MASK                                            0x00000010U
3101
3102 /*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of
3103                 /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
3104                 is register should be 1.*/
3105 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL
3106 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
3107 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK
3108 #define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL                                       0x10000200
3109 #define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT                                        0
3110 #define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK                                         0x00000001U
3111
3112 /*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
3113                  - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
3114                 er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/
3115 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL
3116 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
3117 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK
3118 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL                                  0x0030050C
3119 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT                                   16
3120 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK                                    0x01FF0000U
3121
3122 /*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
3123                 tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
3124                 value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/
3125 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL
3126 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
3127 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK
3128 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL                                  0x0030050C
3129 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT                                   8
3130 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK                                    0x00001F00U
3131
3132 /*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
3133                 ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
3134                 er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
3135                 les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
3136                 or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
3137                 ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
3138                 max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
3139                 bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
3140                 + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
3141                 ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The
3142                 ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
3143                 to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
3144                  Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
3145                 PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
3146                 _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
3147                 C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
3148                 e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
3149                  bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
3150                 H-6 Values of 0, 1 and 2 are illegal.*/
3151 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL
3152 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
3153 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK
3154 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL                        0x0030050C
3155 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT                         0
3156 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK                          0x0000003FU
3157
3158 /*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
3159                  in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
3160                 ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
3161                 r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported
3162                 or LPDDR4 in this version of the uMCTL2.*/
3163 #undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL
3164 #undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
3165 #undef DDRC_INIT0_SKIP_DRAM_INIT_MASK
3166 #define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL                                           0x0002004E
3167 #define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT                                            30
3168 #define DDRC_INIT0_SKIP_DRAM_INIT_MASK                                             0xC0000000U
3169
3170 /*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires
3171                  400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
3172                 grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
3173                 MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/
3174 #undef DDRC_INIT0_POST_CKE_X1024_DEFVAL
3175 #undef DDRC_INIT0_POST_CKE_X1024_SHIFT
3176 #undef DDRC_INIT0_POST_CKE_X1024_MASK
3177 #define DDRC_INIT0_POST_CKE_X1024_DEFVAL                                           0x0002004E
3178 #define DDRC_INIT0_POST_CKE_X1024_SHIFT                                            16
3179 #define DDRC_INIT0_POST_CKE_X1024_MASK                                             0x03FF0000U
3180
3181 /*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2
3182                 pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
3183                 tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
3184                  to next integer value.*/
3185 #undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL
3186 #undef DDRC_INIT0_PRE_CKE_X1024_SHIFT
3187 #undef DDRC_INIT0_PRE_CKE_X1024_MASK
3188 #define DDRC_INIT0_PRE_CKE_X1024_DEFVAL                                            0x0002004E
3189 #define DDRC_INIT0_PRE_CKE_X1024_SHIFT                                             0
3190 #define DDRC_INIT0_PRE_CKE_X1024_MASK                                              0x00000FFFU
3191
3192 /*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
3193                 LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/
3194 #undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL
3195 #undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
3196 #undef DDRC_INIT1_DRAM_RSTN_X1024_MASK
3197 #define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL                                          0x00000000
3198 #define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT                                           16
3199 #define DDRC_INIT1_DRAM_RSTN_X1024_MASK                                            0x01FF0000U
3200
3201 /*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
3202                 bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/
3203 #undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL
3204 #undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT
3205 #undef DDRC_INIT1_FINAL_WAIT_X32_MASK
3206 #define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL                                           0x00000000
3207 #define DDRC_INIT1_FINAL_WAIT_X32_SHIFT                                            8
3208 #define DDRC_INIT1_FINAL_WAIT_X32_MASK                                             0x00007F00U
3209
3210 /*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
3211                 . There is no known specific requirement for this; it may be set to zero.*/
3212 #undef DDRC_INIT1_PRE_OCD_X32_DEFVAL
3213 #undef DDRC_INIT1_PRE_OCD_X32_SHIFT
3214 #undef DDRC_INIT1_PRE_OCD_X32_MASK
3215 #define DDRC_INIT1_PRE_OCD_X32_DEFVAL                                              0x00000000
3216 #define DDRC_INIT1_PRE_OCD_X32_SHIFT                                               0
3217 #define DDRC_INIT1_PRE_OCD_X32_MASK                                                0x0000000FU
3218
3219 /*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/
3220 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL
3221 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
3222 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK
3223 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL                                     0x00000D05
3224 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT                                      8
3225 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK                                       0x0000FF00U
3226
3227 /*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
3228                 e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/
3229 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL
3230 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
3231 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK
3232 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL                                      0x00000D05
3233 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT                                       0
3234 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK                                        0x0000000FU
3235
3236 /*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
3237                  DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
3238                 register*/
3239 #undef DDRC_INIT3_MR_DEFVAL
3240 #undef DDRC_INIT3_MR_SHIFT
3241 #undef DDRC_INIT3_MR_MASK
3242 #define DDRC_INIT3_MR_DEFVAL                                                       0x00000510
3243 #define DDRC_INIT3_MR_SHIFT                                                        16
3244 #define DDRC_INIT3_MR_MASK                                                         0xFFFF0000U
3245
3246 /*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
3247                 bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
3248                  bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
3249                 lue to write to MR2 register*/
3250 #undef DDRC_INIT3_EMR_DEFVAL
3251 #undef DDRC_INIT3_EMR_SHIFT
3252 #undef DDRC_INIT3_EMR_MASK
3253 #define DDRC_INIT3_EMR_DEFVAL                                                      0x00000510
3254 #define DDRC_INIT3_EMR_SHIFT                                                       0
3255 #define DDRC_INIT3_EMR_MASK                                                        0x0000FFFFU
3256
3257 /*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3
3258                 egister mDDR: Unused*/
3259 #undef DDRC_INIT4_EMR2_DEFVAL
3260 #undef DDRC_INIT4_EMR2_SHIFT
3261 #undef DDRC_INIT4_EMR2_MASK
3262 #define DDRC_INIT4_EMR2_DEFVAL                                                     0x00000000
3263 #define DDRC_INIT4_EMR2_SHIFT                                                      16
3264 #define DDRC_INIT4_EMR2_MASK                                                       0xFFFF0000U
3265
3266 /*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to
3267                 rite to MR13 register*/
3268 #undef DDRC_INIT4_EMR3_DEFVAL
3269 #undef DDRC_INIT4_EMR3_SHIFT
3270 #undef DDRC_INIT4_EMR3_MASK
3271 #define DDRC_INIT4_EMR3_DEFVAL                                                     0x00000000
3272 #define DDRC_INIT4_EMR3_SHIFT                                                      0
3273 #define DDRC_INIT4_EMR3_MASK                                                       0x0000FFFFU
3274
3275 /*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock
3276                 ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/
3277 #undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL
3278 #undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
3279 #undef DDRC_INIT5_DEV_ZQINIT_X32_MASK
3280 #define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL                                           0x00100004
3281 #define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT                                            16
3282 #define DDRC_INIT5_DEV_ZQINIT_X32_MASK                                             0x00FF0000U
3283
3284 /*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
3285                 3 typically requires 10 us.*/
3286 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL
3287 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
3288 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK
3289 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL                                      0x00100004
3290 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT                                       0
3291 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK                                        0x000003FFU
3292
3293 /*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/
3294 #undef DDRC_INIT6_MR4_DEFVAL
3295 #undef DDRC_INIT6_MR4_SHIFT
3296 #undef DDRC_INIT6_MR4_MASK
3297 #define DDRC_INIT6_MR4_DEFVAL                                                      0x00000000
3298 #define DDRC_INIT6_MR4_SHIFT                                                       16
3299 #define DDRC_INIT6_MR4_MASK                                                        0xFFFF0000U
3300
3301 /*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/
3302 #undef DDRC_INIT6_MR5_DEFVAL
3303 #undef DDRC_INIT6_MR5_SHIFT
3304 #undef DDRC_INIT6_MR5_MASK
3305 #define DDRC_INIT6_MR5_DEFVAL                                                      0x00000000
3306 #define DDRC_INIT6_MR5_SHIFT                                                       0
3307 #define DDRC_INIT6_MR5_MASK                                                        0x0000FFFFU
3308
3309 /*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/
3310 #undef DDRC_INIT7_MR6_DEFVAL
3311 #undef DDRC_INIT7_MR6_SHIFT
3312 #undef DDRC_INIT7_MR6_MASK
3313 #define DDRC_INIT7_MR6_DEFVAL
3314 #define DDRC_INIT7_MR6_SHIFT                                                       16
3315 #define DDRC_INIT7_MR6_MASK                                                        0xFFFF0000U
3316
3317 /*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
3318                 ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
3319                  address mirroring is enabled.*/
3320 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL
3321 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
3322 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK
3323 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL                                  0x00000000
3324 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT                                   5
3325 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK                                    0x00000020U
3326
3327 /*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
3328                  be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output
3329                 nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
3330                 effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
3331                 led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/
3332 #undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL
3333 #undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
3334 #undef DDRC_DIMMCTL_MRS_BG1_EN_MASK
3335 #define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL                                             0x00000000
3336 #define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT                                              4
3337 #define DDRC_DIMMCTL_MRS_BG1_EN_MASK                                               0x00000010U
3338
3339 /*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
3340                  be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled,
3341                 his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address
3342                 f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/
3343 #undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL
3344 #undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT
3345 #undef DDRC_DIMMCTL_MRS_A17_EN_MASK
3346 #define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL                                             0x00000000
3347 #define DDRC_DIMMCTL_MRS_A17_EN_SHIFT                                              3
3348 #define DDRC_DIMMCTL_MRS_A17_EN_MASK                                               0x00000008U
3349
3350 /*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
3351                 which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17,
3352                 A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
3353                 lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated.
3354                 or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
3355                  has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
3356                 ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/
3357 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL
3358 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
3359 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK
3360 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL                                     0x00000000
3361 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT                                      2
3362 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK                                       0x00000004U
3363
3364 /*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
3365                 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits
3366                 re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
3367                 at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
3368                 sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
3369                  swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
3370                 ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
3371                 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
3372                 hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
3373                 ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
3374                 not implement address mirroring*/
3375 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL
3376 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
3377 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK
3378 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL                                      0x00000000
3379 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT                                       1
3380 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK                                        0x00000002U
3381
3382 /*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
3383                 R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
3384                 CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
3385                  each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/
3386 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL
3387 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
3388 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK
3389 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL                                     0x00000000
3390 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT                                      0
3391 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK                                       0x00000001U
3392
3393 /*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
3394                 e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
3395                 nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
3396                 ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
3397                 ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed
3398                 n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
3399                 ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
3400                 or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
3401                  to the next integer.*/
3402 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL
3403 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
3404 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK
3405 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL                                       0x0000066F
3406 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT                                        8
3407 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK                                         0x00000F00U
3408
3409 /*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
3410                 e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
3411                 sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
3412                 p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
3413                 ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
3414                 requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
3415                 quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and
3416                 ound it up to the next integer.*/
3417 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL
3418 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
3419 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK
3420 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL                                       0x0000066F
3421 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT                                        4
3422 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK                                         0x000000F0U
3423
3424 /*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
3425                 nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
3426                 on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
3427                 -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
3428                 _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
3429                 om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
3430                 ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to
3431                 llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
3432                 ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as
3433                 ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
3434                 . FOR PERFORMANCE ONLY.*/
3435 #undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL
3436 #undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT
3437 #undef DDRC_RANKCTL_MAX_RANK_RD_MASK
3438 #define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL                                            0x0000066F
3439 #define DDRC_RANKCTL_MAX_RANK_RD_SHIFT                                             0
3440 #define DDRC_RANKCTL_MAX_RANK_RD_MASK                                              0x0000000FU
3441
3442 /*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles
3443                  15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
3444                  value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
3445                 Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this
3446                 arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
3447                 with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/
3448 #undef DDRC_DRAMTMG0_WR2PRE_DEFVAL
3449 #undef DDRC_DRAMTMG0_WR2PRE_SHIFT
3450 #undef DDRC_DRAMTMG0_WR2PRE_MASK
3451 #define DDRC_DRAMTMG0_WR2PRE_DEFVAL                                                0x0F101B0F
3452 #define DDRC_DRAMTMG0_WR2PRE_SHIFT                                                 24
3453 #define DDRC_DRAMTMG0_WR2PRE_MASK                                                  0x7F000000U
3454
3455 /*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
3456                 in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next
3457                 nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/
3458 #undef DDRC_DRAMTMG0_T_FAW_DEFVAL
3459 #undef DDRC_DRAMTMG0_T_FAW_SHIFT
3460 #undef DDRC_DRAMTMG0_T_FAW_MASK
3461 #define DDRC_DRAMTMG0_T_FAW_DEFVAL                                                 0x0F101B0F
3462 #define DDRC_DRAMTMG0_T_FAW_SHIFT                                                  16
3463 #define DDRC_DRAMTMG0_T_FAW_MASK                                                   0x003F0000U
3464
3465 /*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
3466                 imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
3467                  No rounding up. Unit: Multiples of 1024 clocks.*/
3468 #undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL
3469 #undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
3470 #undef DDRC_DRAMTMG0_T_RAS_MAX_MASK
3471 #define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL                                             0x0F101B0F
3472 #define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT                                              8
3473 #define DDRC_DRAMTMG0_T_RAS_MAX_MASK                                               0x00007F00U
3474
3475 /*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode,
3476                 rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
3477                  (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/
3478 #undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL
3479 #undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
3480 #undef DDRC_DRAMTMG0_T_RAS_MIN_MASK
3481 #define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL                                             0x0F101B0F
3482 #define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT                                              0
3483 #define DDRC_DRAMTMG0_T_RAS_MIN_MASK                                               0x0000003FU
3484
3485 /*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
3486                  is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2,
3487                 rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/
3488 #undef DDRC_DRAMTMG1_T_XP_DEFVAL
3489 #undef DDRC_DRAMTMG1_T_XP_SHIFT
3490 #undef DDRC_DRAMTMG1_T_XP_MASK
3491 #define DDRC_DRAMTMG1_T_XP_DEFVAL                                                  0x00080414
3492 #define DDRC_DRAMTMG1_T_XP_SHIFT                                                   16
3493 #define DDRC_DRAMTMG1_T_XP_MASK                                                    0x001F0000U
3494
3495 /*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
3496                 R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
3497                 S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
3498                 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
3499                 gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
3500                 e. Unit: Clocks.*/
3501 #undef DDRC_DRAMTMG1_RD2PRE_DEFVAL
3502 #undef DDRC_DRAMTMG1_RD2PRE_SHIFT
3503 #undef DDRC_DRAMTMG1_RD2PRE_MASK
3504 #define DDRC_DRAMTMG1_RD2PRE_DEFVAL                                                0x00080414
3505 #define DDRC_DRAMTMG1_RD2PRE_SHIFT                                                 8
3506 #define DDRC_DRAMTMG1_RD2PRE_MASK                                                  0x00001F00U
3507
3508 /*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
3509                  up to next integer value. Unit: Clocks.*/
3510 #undef DDRC_DRAMTMG1_T_RC_DEFVAL
3511 #undef DDRC_DRAMTMG1_T_RC_SHIFT
3512 #undef DDRC_DRAMTMG1_T_RC_MASK
3513 #define DDRC_DRAMTMG1_T_RC_DEFVAL                                                  0x00080414
3514 #define DDRC_DRAMTMG1_T_RC_SHIFT                                                   0
3515 #define DDRC_DRAMTMG1_T_RC_MASK                                                    0x0000007FU
3516
3517 /*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
3518                 t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
3519                 tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
3520                 equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
3521                  is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
3522 #undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL
3523 #undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
3524 #undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK
3525 #define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL                                         0x0305060D
3526 #define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT                                          24
3527 #define DDRC_DRAMTMG2_WRITE_LATENCY_MASK                                           0x3F000000U
3528
3529 /*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
3530                 using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For
3531                 onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
3532                 er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
3533                 s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
3534 #undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL
3535 #undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT
3536 #undef DDRC_DRAMTMG2_READ_LATENCY_MASK
3537 #define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL                                          0x0305060D
3538 #define DDRC_DRAMTMG2_READ_LATENCY_SHIFT                                           16
3539 #define DDRC_DRAMTMG2_READ_LATENCY_MASK                                            0x003F0000U
3540
3541 /*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
3542                 PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
3543                 /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
3544                 time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL =
3545                 urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
3546                 tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
3547                 DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
3548                 gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
3549 #undef DDRC_DRAMTMG2_RD2WR_DEFVAL
3550 #undef DDRC_DRAMTMG2_RD2WR_SHIFT
3551 #undef DDRC_DRAMTMG2_RD2WR_MASK
3552 #define DDRC_DRAMTMG2_RD2WR_DEFVAL                                                 0x0305060D
3553 #define DDRC_DRAMTMG2_RD2WR_SHIFT                                                  8
3554 #define DDRC_DRAMTMG2_RD2WR_MASK                                                   0x00003F00U
3555
3556 /*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
3557                 k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
3558                  per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
3559                  length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
3560                 d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
3561                  delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
3562                 ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
3563 #undef DDRC_DRAMTMG2_WR2RD_DEFVAL
3564 #undef DDRC_DRAMTMG2_WR2RD_SHIFT
3565 #undef DDRC_DRAMTMG2_WR2RD_MASK
3566 #define DDRC_DRAMTMG2_WR2RD_DEFVAL                                                 0x0305060D
3567 #define DDRC_DRAMTMG2_WR2RD_SHIFT                                                  0
3568 #define DDRC_DRAMTMG2_WR2RD_MASK                                                   0x0000003FU
3569
3570 /*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
3571                  LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW
3572                 nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
3573                  used for the time from a MRW/MRR to a MRW/MRR.*/
3574 #undef DDRC_DRAMTMG3_T_MRW_DEFVAL
3575 #undef DDRC_DRAMTMG3_T_MRW_SHIFT
3576 #undef DDRC_DRAMTMG3_T_MRW_MASK
3577 #define DDRC_DRAMTMG3_T_MRW_DEFVAL                                                 0x0050400C
3578 #define DDRC_DRAMTMG3_T_MRW_SHIFT                                                  20
3579 #define DDRC_DRAMTMG3_T_MRW_MASK                                                   0x3FF00000U
3580
3581 /*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time
3582                 rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
3583                 nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
3584                 4 is used, set to tMRD_PAR(tMOD+PL) instead.*/
3585 #undef DDRC_DRAMTMG3_T_MRD_DEFVAL
3586 #undef DDRC_DRAMTMG3_T_MRD_SHIFT
3587 #undef DDRC_DRAMTMG3_T_MRD_MASK
3588 #define DDRC_DRAMTMG3_T_MRD_DEFVAL                                                 0x0050400C
3589 #define DDRC_DRAMTMG3_T_MRD_SHIFT                                                  12
3590 #define DDRC_DRAMTMG3_T_MRD_MASK                                                   0x0003F000U
3591
3592 /*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
3593                 y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
3594                  if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
3595                  + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/
3596 #undef DDRC_DRAMTMG3_T_MOD_DEFVAL
3597 #undef DDRC_DRAMTMG3_T_MOD_SHIFT
3598 #undef DDRC_DRAMTMG3_T_MOD_MASK
3599 #define DDRC_DRAMTMG3_T_MOD_DEFVAL                                                 0x0050400C
3600 #define DDRC_DRAMTMG3_T_MOD_SHIFT                                                  0
3601 #define DDRC_DRAMTMG3_T_MOD_MASK                                                   0x000003FFU
3602
3603 /*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
3604                 am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
3605                 lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/
3606 #undef DDRC_DRAMTMG4_T_RCD_DEFVAL
3607 #undef DDRC_DRAMTMG4_T_RCD_SHIFT
3608 #undef DDRC_DRAMTMG4_T_RCD_MASK
3609 #define DDRC_DRAMTMG4_T_RCD_DEFVAL                                                 0x05040405
3610 #define DDRC_DRAMTMG4_T_RCD_SHIFT                                                  24
3611 #define DDRC_DRAMTMG4_T_RCD_MASK                                                   0x1F000000U
3612
3613 /*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
3614                 time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
3615                 d it up to the next integer value. Unit: clocks.*/
3616 #undef DDRC_DRAMTMG4_T_CCD_DEFVAL
3617 #undef DDRC_DRAMTMG4_T_CCD_SHIFT
3618 #undef DDRC_DRAMTMG4_T_CCD_MASK
3619 #define DDRC_DRAMTMG4_T_CCD_DEFVAL                                                 0x05040405
3620 #define DDRC_DRAMTMG4_T_CCD_SHIFT                                                  16
3621 #define DDRC_DRAMTMG4_T_CCD_MASK                                                   0x000F0000U
3622
3623 /*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
3624                  activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
3625                 it up to the next integer value. Unit: Clocks.*/
3626 #undef DDRC_DRAMTMG4_T_RRD_DEFVAL
3627 #undef DDRC_DRAMTMG4_T_RRD_SHIFT
3628 #undef DDRC_DRAMTMG4_T_RRD_MASK
3629 #define DDRC_DRAMTMG4_T_RRD_DEFVAL                                                 0x05040405
3630 #define DDRC_DRAMTMG4_T_RRD_SHIFT                                                  8
3631 #define DDRC_DRAMTMG4_T_RRD_MASK                                                   0x00000F00U
3632
3633 /*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
3634                 (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
3635                 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/
3636 #undef DDRC_DRAMTMG4_T_RP_DEFVAL
3637 #undef DDRC_DRAMTMG4_T_RP_SHIFT
3638 #undef DDRC_DRAMTMG4_T_RP_MASK
3639 #define DDRC_DRAMTMG4_T_RP_DEFVAL                                                  0x05040405
3640 #define DDRC_DRAMTMG4_T_RP_SHIFT                                                   0
3641 #define DDRC_DRAMTMG4_T_RP_MASK                                                    0x0000001FU
3642
3643 /*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
3644                 e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
3645                 tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
3646                 eger.*/
3647 #undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL
3648 #undef DDRC_DRAMTMG5_T_CKSRX_SHIFT
3649 #undef DDRC_DRAMTMG5_T_CKSRX_MASK
3650 #define DDRC_DRAMTMG5_T_CKSRX_DEFVAL                                               0x05050403
3651 #define DDRC_DRAMTMG5_T_CKSRX_SHIFT                                                24
3652 #define DDRC_DRAMTMG5_T_CKSRX_MASK                                                 0x0F000000U
3653
3654 /*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
3655                  SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4:
3656                 ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
3657                 to next integer.*/
3658 #undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL
3659 #undef DDRC_DRAMTMG5_T_CKSRE_SHIFT
3660 #undef DDRC_DRAMTMG5_T_CKSRE_MASK
3661 #define DDRC_DRAMTMG5_T_CKSRE_DEFVAL                                               0x05050403
3662 #define DDRC_DRAMTMG5_T_CKSRE_SHIFT                                                16
3663 #define DDRC_DRAMTMG5_T_CKSRE_MASK                                                 0x000F0000U
3664
3665 /*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
3666                 tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE
3667                  1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
3668                 .*/
3669 #undef DDRC_DRAMTMG5_T_CKESR_DEFVAL
3670 #undef DDRC_DRAMTMG5_T_CKESR_SHIFT
3671 #undef DDRC_DRAMTMG5_T_CKESR_MASK
3672 #define DDRC_DRAMTMG5_T_CKESR_DEFVAL                                               0x05050403
3673 #define DDRC_DRAMTMG5_T_CKESR_SHIFT                                                8
3674 #define DDRC_DRAMTMG5_T_CKESR_MASK                                                 0x00003F00U
3675
3676 /*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of
3677                 CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set
3678                 his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
3679                  next integer value. Unit: Clocks.*/
3680 #undef DDRC_DRAMTMG5_T_CKE_DEFVAL
3681 #undef DDRC_DRAMTMG5_T_CKE_SHIFT
3682 #undef DDRC_DRAMTMG5_T_CKE_MASK
3683 #define DDRC_DRAMTMG5_T_CKE_DEFVAL                                                 0x05050403
3684 #define DDRC_DRAMTMG5_T_CKE_SHIFT                                                  0
3685 #define DDRC_DRAMTMG5_T_CKE_MASK                                                   0x0000001FU
3686
3687 /*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after
3688                 PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
3689                 ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
3690                 devices.*/
3691 #undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL
3692 #undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT
3693 #undef DDRC_DRAMTMG6_T_CKDPDE_MASK
3694 #define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL                                              0x02020005
3695 #define DDRC_DRAMTMG6_T_CKDPDE_SHIFT                                               24
3696 #define DDRC_DRAMTMG6_T_CKDPDE_MASK                                                0x0F000000U
3697
3698 /*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock
3699                 table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
3700                 gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
3701                 R or LPDDR2 devices.*/
3702 #undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL
3703 #undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT
3704 #undef DDRC_DRAMTMG6_T_CKDPDX_MASK
3705 #define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL                                              0x02020005
3706 #define DDRC_DRAMTMG6_T_CKDPDX_SHIFT                                               16
3707 #define DDRC_DRAMTMG6_T_CKDPDX_MASK                                                0x000F0000U
3708
3709 /*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the
3710                 lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
3711                 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it
3712                 p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
3713 #undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL
3714 #undef DDRC_DRAMTMG6_T_CKCSX_SHIFT
3715 #undef DDRC_DRAMTMG6_T_CKCSX_MASK
3716 #define DDRC_DRAMTMG6_T_CKCSX_DEFVAL                                               0x02020005
3717 #define DDRC_DRAMTMG6_T_CKCSX_SHIFT                                                0
3718 #define DDRC_DRAMTMG6_T_CKCSX_MASK                                                 0x0000000FU
3719
3720 /*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE.
3721                 ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
3722                 is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
3723                 DDR2/LPDDR3/LPDDR4 devices.*/
3724 #undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL
3725 #undef DDRC_DRAMTMG7_T_CKPDE_SHIFT
3726 #undef DDRC_DRAMTMG7_T_CKPDE_MASK
3727 #define DDRC_DRAMTMG7_T_CKPDE_DEFVAL                                               0x00000202
3728 #define DDRC_DRAMTMG7_T_CKPDE_SHIFT                                                8
3729 #define DDRC_DRAMTMG7_T_CKPDE_MASK                                                 0x00000F00U
3730
3731 /*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
3732                 time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
3733                 , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
3734                 g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
3735 #undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL
3736 #undef DDRC_DRAMTMG7_T_CKPDX_SHIFT
3737 #undef DDRC_DRAMTMG7_T_CKPDX_MASK
3738 #define DDRC_DRAMTMG7_T_CKPDX_DEFVAL                                               0x00000202
3739 #define DDRC_DRAMTMG7_T_CKPDX_SHIFT                                                0
3740 #define DDRC_DRAMTMG7_T_CKPDX_MASK                                                 0x0000000FU
3741
3742 /*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
3743                 O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
3744                  is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/
3745 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL
3746 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
3747 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK
3748 #define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL                                         0x03034405
3749 #define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT                                          24
3750 #define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK                                           0x7F000000U
3751
3752 /*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
3753                 ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
3754                 nsure this is less than or equal to t_xs_x32.*/
3755 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL
3756 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
3757 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK
3758 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL                                        0x03034405
3759 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT                                         16
3760 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK                                          0x007F0000U
3761
3762 /*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3763                 bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3764                 DR4 SDRAMs.*/
3765 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL
3766 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
3767 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK
3768 #define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL                                          0x03034405
3769 #define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT                                           8
3770 #define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK                                            0x00007F00U
3771
3772 /*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3773                 above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3774                 DDR4 SDRAMs.*/
3775 #undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL
3776 #undef DDRC_DRAMTMG8_T_XS_X32_SHIFT
3777 #undef DDRC_DRAMTMG8_T_XS_X32_MASK
3778 #define DDRC_DRAMTMG8_T_XS_X32_DEFVAL                                              0x03034405
3779 #define DDRC_DRAMTMG8_T_XS_X32_SHIFT                                               0
3780 #define DDRC_DRAMTMG8_T_XS_X32_MASK                                                0x0000007FU
3781
3782 /*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/
3783 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL
3784 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
3785 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK
3786 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL                                      0x0004040D
3787 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT                                       30
3788 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK                                        0x40000000U
3789
3790 /*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a'
3791                 o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
3792                 nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/
3793 #undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL
3794 #undef DDRC_DRAMTMG9_T_CCD_S_SHIFT
3795 #undef DDRC_DRAMTMG9_T_CCD_S_MASK
3796 #define DDRC_DRAMTMG9_T_CCD_S_DEFVAL                                               0x0004040D
3797 #define DDRC_DRAMTMG9_T_CCD_S_SHIFT                                                16
3798 #define DDRC_DRAMTMG9_T_CCD_S_MASK                                                 0x00070000U
3799
3800 /*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
3801                 ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
3802                 R4. Unit: Clocks.*/
3803 #undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL
3804 #undef DDRC_DRAMTMG9_T_RRD_S_SHIFT
3805 #undef DDRC_DRAMTMG9_T_RRD_S_MASK
3806 #define DDRC_DRAMTMG9_T_RRD_S_DEFVAL                                               0x0004040D
3807 #define DDRC_DRAMTMG9_T_RRD_S_SHIFT                                                8
3808 #define DDRC_DRAMTMG9_T_RRD_S_MASK                                                 0x00000F00U
3809
3810 /*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
3811                 round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
3812                  Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
3813                 d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
3814                 is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using
3815                 he above equation by 2, and round it up to next integer.*/
3816 #undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL
3817 #undef DDRC_DRAMTMG9_WR2RD_S_SHIFT
3818 #undef DDRC_DRAMTMG9_WR2RD_S_MASK
3819 #define DDRC_DRAMTMG9_WR2RD_S_DEFVAL                                               0x0004040D
3820 #define DDRC_DRAMTMG9_WR2RD_S_SHIFT                                                0
3821 #define DDRC_DRAMTMG9_WR2RD_S_MASK                                                 0x0000003FU
3822
3823 /*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
3824                 this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
3825                 ples of 32 clocks.*/
3826 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL
3827 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
3828 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK
3829 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL                                    0x440C021C
3830 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT                                     24
3831 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK                                      0x7F000000U
3832
3833 /*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
3834                  RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/
3835 #undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL
3836 #undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT
3837 #undef DDRC_DRAMTMG11_T_MPX_LH_MASK
3838 #define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL                                             0x440C021C
3839 #define DDRC_DRAMTMG11_T_MPX_LH_SHIFT                                              16
3840 #define DDRC_DRAMTMG11_T_MPX_LH_MASK                                               0x001F0000U
3841
3842 /*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
3843                 up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/
3844 #undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL
3845 #undef DDRC_DRAMTMG11_T_MPX_S_SHIFT
3846 #undef DDRC_DRAMTMG11_T_MPX_S_MASK
3847 #define DDRC_DRAMTMG11_T_MPX_S_DEFVAL                                              0x440C021C
3848 #define DDRC_DRAMTMG11_T_MPX_S_SHIFT                                               8
3849 #define DDRC_DRAMTMG11_T_MPX_S_MASK                                                0x00000300U
3850
3851 /*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
3852                 r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
3853                 teger.*/
3854 #undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL
3855 #undef DDRC_DRAMTMG11_T_CKMPE_SHIFT
3856 #undef DDRC_DRAMTMG11_T_CKMPE_MASK
3857 #define DDRC_DRAMTMG11_T_CKMPE_DEFVAL                                              0x440C021C
3858 #define DDRC_DRAMTMG11_T_CKMPE_SHIFT                                               0
3859 #define DDRC_DRAMTMG11_T_CKMPE_MASK                                                0x0000001FU
3860
3861 /*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
3862                 REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/
3863 #undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL
3864 #undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT
3865 #undef DDRC_DRAMTMG12_T_CMDCKE_MASK
3866 #define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL                                             0x00020610
3867 #define DDRC_DRAMTMG12_T_CMDCKE_SHIFT                                              16
3868 #define DDRC_DRAMTMG12_T_CMDCKE_MASK                                               0x00030000U
3869
3870 /*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
3871                 /2) and round it up to next integer value.*/
3872 #undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL
3873 #undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
3874 #undef DDRC_DRAMTMG12_T_CKEHCMD_MASK
3875 #define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL                                            0x00020610
3876 #define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT                                             8
3877 #define DDRC_DRAMTMG12_T_CKEHCMD_MASK                                              0x00000F00U
3878
3879 /*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
3880                 s to (tMRD_PDA/2) and round it up to next integer value.*/
3881 #undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL
3882 #undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
3883 #undef DDRC_DRAMTMG12_T_MRD_PDA_MASK
3884 #define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL                                            0x00020610
3885 #define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT                                             0
3886 #define DDRC_DRAMTMG12_T_MRD_PDA_MASK                                              0x0000001FU
3887
3888 /*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
3889                 ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
3890                 ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3891 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL
3892 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
3893 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK
3894 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL                                             0x02000040
3895 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT                                              31
3896 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK                                               0x80000000U
3897
3898 /*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
3899                 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
3900                 own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
3901                 ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3902 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL
3903 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
3904 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK
3905 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL                                            0x02000040
3906 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT                                             30
3907 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK                                              0x40000000U
3908
3909 /*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
3910                 nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
3911                 rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3912 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL
3913 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
3914 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK
3915 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL                                      0x02000040
3916 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT                                       29
3917 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK                                        0x20000000U
3918
3919 /*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable
3920                 ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
3921                 gns supporting DDR4 devices.*/
3922 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL
3923 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
3924 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK
3925 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL                                          0x02000040
3926 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT                                           28
3927 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK                                            0x10000000U
3928
3929 /*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
3930                 on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
3931                 er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
3932                 ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for
3933                 esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3934 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL
3935 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
3936 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK
3937 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL                                           0x02000040
3938 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT                                            16
3939 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK                                             0x07FF0000U
3940
3941 /*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
3942                 ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
3943                 e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
3944                 s.*/
3945 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL
3946 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
3947 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK
3948 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL                                          0x02000040
3949 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT                                           0
3950 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK                                            0x000003FFU
3951
3952 /*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
3953                 ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is
3954                 nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/
3955 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL
3956 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
3957 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK
3958 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL                                          0x02000100
3959 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT                                           20
3960 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK                                            0x3FF00000U
3961
3962 /*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
3963                 PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs
3964                 upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3965 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL
3966 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
3967 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK
3968 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL                               0x02000100
3969 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT                                0
3970 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK                                 0x000FFFFFU
3971
3972 /*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
3973                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
3974                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
3975                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
3976 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL
3977 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
3978 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK
3979 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL                                       0x07020002
3980 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT                                        24
3981 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK                                         0x1F000000U
3982
3983 /*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
3984                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
3985                 fer to PHY specification for correct value.*/
3986 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL
3987 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
3988 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK
3989 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL                                     0x07020002
3990 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT                                      23
3991 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK                                       0x00800000U
3992
3993 /*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
3994                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
3995                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
3996                  latency through the RDIMM. Unit: Clocks*/
3997 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL
3998 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
3999 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK
4000 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL                                        0x07020002
4001 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT                                         16
4002 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK                                          0x003F0000U
4003
4004 /*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
4005                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
4006                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
4007                 e.*/
4008 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL
4009 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
4010 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK
4011 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL                                     0x07020002
4012 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT                                      15
4013 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK                                       0x00008000U
4014
4015 /*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
4016                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
4017                 te, max supported value is 8. Unit: Clocks*/
4018 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL
4019 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
4020 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK
4021 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL                                        0x07020002
4022 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT                                         8
4023 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK                                          0x00003F00U
4024
4025 /*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
4026                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
4027                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
4028                 rough the RDIMM.*/
4029 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL
4030 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
4031 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK
4032 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL                                         0x07020002
4033 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT                                          0
4034 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK                                           0x0000003FU
4035
4036 /*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven.
4037                 his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
4038                 the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/
4039 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL
4040 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
4041 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK
4042 #define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL                                          0x00000404
4043 #define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT                                           28
4044 #define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK                                            0xF0000000U
4045
4046 /*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
4047                  is driven.*/
4048 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL
4049 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
4050 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK
4051 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL                                        0x00000404
4052 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT                                         24
4053 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK                                          0x03000000U
4054
4055 /*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
4056                 nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
4057                  correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to
4058                 phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
4059                 RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
4060                 : Clocks*/
4061 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL
4062 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
4063 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK
4064 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL                                     0x00000404
4065 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT                                      16
4066 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK                                       0x001F0000U
4067
4068 /*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to
4069                 he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase
4070                 ligned, this timing parameter should be rounded up to the next integer value.*/
4071 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL
4072 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
4073 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK
4074 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL                                 0x00000404
4075 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT                                  8
4076 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK                                   0x00000F00U
4077
4078 /*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first
4079                 alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
4080                 not phase aligned, this timing parameter should be rounded up to the next integer value.*/
4081 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL
4082 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
4083 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK
4084 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL                                  0x00000404
4085 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT                                   0
4086 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK                                    0x0000000FU
4087
4088 /*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
4089                 g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/
4090 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL
4091 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
4092 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK
4093 #define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL                                         0x07000000
4094 #define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT                                          24
4095 #define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK                                           0x0F000000U
4096
4097 /*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
4098                 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
4099                 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD -
4100                 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
4101                 .*/
4102 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL
4103 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
4104 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK
4105 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL                                    0x07000000
4106 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT                                     20
4107 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK                                      0x00F00000U
4108
4109 /*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
4110                 nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/
4111 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL
4112 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
4113 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK
4114 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL                                        0x07000000
4115 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT                                         16
4116 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK                                          0x00010000U
4117
4118 /*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
4119                 les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 -
4120                 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
4121                 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
4122 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL
4123 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
4124 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK
4125 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL                                     0x07000000
4126 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT                                      12
4127 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK                                       0x0000F000U
4128
4129 /*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/
4130 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL
4131 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
4132 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK
4133 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL                                         0x07000000
4134 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT                                          8
4135 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK                                           0x00000100U
4136
4137 /*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
4138                 s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
4139                 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
4140                  cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
4141 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL
4142 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
4143 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK
4144 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL                                     0x07000000
4145 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT                                      4
4146 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK                                       0x000000F0U
4147
4148 /*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/
4149 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL
4150 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
4151 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK
4152 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL                                         0x07000000
4153 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT                                          0
4154 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK                                           0x00000001U
4155
4156 /*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
4157                 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles
4158                  0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
4159                 D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/
4160 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL
4161 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
4162 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK
4163 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL                                   0x00000000
4164 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT                                    4
4165 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK                                     0x000000F0U
4166
4167 /*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
4168                 only present for designs supporting DDR4 devices.*/
4169 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL
4170 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
4171 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK
4172 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL                                       0x00000000
4173 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT                                        0
4174 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK                                         0x00000001U
4175
4176 /*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
4177                 ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
4178                 t read request when the uMCTL2 is idle. Unit: 1024 clocks*/
4179 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL
4180 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
4181 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK
4182 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL                       0x00000000
4183 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT                        16
4184 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK                         0x00FF0000U
4185
4186 /*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request;
4187                 hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
4188                 idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
4189                 e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
4190                 Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
4191                 024. Unit: 1024 clocks*/
4192 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL
4193 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
4194 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK
4195 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL                       0x00000000
4196 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT                        0
4197 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK                         0x000000FFU
4198
4199 /*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/
4200 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL
4201 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
4202 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK
4203 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL                                   0x00000001
4204 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT                                    2
4205 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK                                     0x00000004U
4206
4207 /*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
4208                 in designs configured to support DDR4 and LPDDR4.*/
4209 #undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL
4210 #undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
4211 #undef DDRC_DFIMISC_PHY_DBI_MODE_MASK
4212 #define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL                                           0x00000001
4213 #define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT                                            1
4214 #define DDRC_DFIMISC_PHY_DBI_MODE_MASK                                             0x00000002U
4215
4216 /*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
4217                 ion*/
4218 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL
4219 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
4220 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK
4221 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL                                   0x00000001
4222 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT                                    0
4223 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK                                     0x00000001U
4224
4225 /*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
4226                 l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/
4227 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL
4228 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
4229 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK
4230 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL                                       0x00000202
4231 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT                                        8
4232 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK                                         0x00003F00U
4233
4234 /*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
4235                 l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/
4236 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL
4237 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
4238 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK
4239 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL                                       0x00000202
4240 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT                                        0
4241 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK                                         0x0000003FU
4242
4243 /*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
4244                 as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/
4245 #undef DDRC_DBICTL_RD_DBI_EN_DEFVAL
4246 #undef DDRC_DBICTL_RD_DBI_EN_SHIFT
4247 #undef DDRC_DBICTL_RD_DBI_EN_MASK
4248 #define DDRC_DBICTL_RD_DBI_EN_DEFVAL                                               0x00000001
4249 #define DDRC_DBICTL_RD_DBI_EN_SHIFT                                                2
4250 #define DDRC_DBICTL_RD_DBI_EN_MASK                                                 0x00000004U
4251
4252 /*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
4253                 ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/
4254 #undef DDRC_DBICTL_WR_DBI_EN_DEFVAL
4255 #undef DDRC_DBICTL_WR_DBI_EN_SHIFT
4256 #undef DDRC_DBICTL_WR_DBI_EN_MASK
4257 #define DDRC_DBICTL_WR_DBI_EN_DEFVAL                                               0x00000001
4258 #define DDRC_DBICTL_WR_DBI_EN_SHIFT                                                1
4259 #define DDRC_DBICTL_WR_DBI_EN_MASK                                                 0x00000002U
4260
4261 /*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
4262                 mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
4263                 : Set this to inverted value of MR13[5] which is opposite polarity from this signal*/
4264 #undef DDRC_DBICTL_DM_EN_DEFVAL
4265 #undef DDRC_DBICTL_DM_EN_SHIFT
4266 #undef DDRC_DBICTL_DM_EN_MASK
4267 #define DDRC_DBICTL_DM_EN_DEFVAL                                                   0x00000001
4268 #define DDRC_DBICTL_DM_EN_SHIFT                                                    0
4269 #define DDRC_DBICTL_DM_EN_MASK                                                     0x00000001U
4270
4271 /*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
4272                  bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/
4273 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
4274 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
4275 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK
4276 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
4277 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT                                        0
4278 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK                                         0x0000001FU
4279
4280 /*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
4281                 bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/
4282 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL
4283 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
4284 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK
4285 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL                                       0x00000000
4286 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT                                        16
4287 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK                                         0x001F0000U
4288
4289 /*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
4290                 r each of the bank address bits is determined by adding the internal base to the value of this field.*/
4291 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL
4292 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
4293 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK
4294 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL                                       0x00000000
4295 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT                                        8
4296 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK                                         0x00001F00U
4297
4298 /*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
4299                 r each of the bank address bits is determined by adding the internal base to the value of this field.*/
4300 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL
4301 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
4302 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK
4303 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL                                       0x00000000
4304 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT                                        0
4305 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK                                         0x0000001FU
4306
4307 /*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
4308                 s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
4309                  Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
4310                  this field. If set to 15, this column address bit is set to 0.*/
4311 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL
4312 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
4313 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK
4314 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL                                        0x00000000
4315 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT                                         24
4316 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK                                          0x0F000000U
4317
4318 /*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
4319                 s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
4320                 Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
4321                 this field. If set to 15, this column address bit is set to 0.*/
4322 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL
4323 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
4324 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK
4325 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL                                        0x00000000
4326 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT                                         16
4327 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK                                          0x000F0000U
4328
4329 /*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
4330                 s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
4331                 Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
4332                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
4333                  this case.*/
4334 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL
4335 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
4336 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK
4337 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL                                        0x00000000
4338 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT                                         8
4339 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK                                          0x00000F00U
4340
4341 /*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
4342                 s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
4343                 Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
4344                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/
4345 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL
4346 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
4347 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK
4348 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL                                        0x00000000
4349 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT                                         0
4350 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK                                          0x0000000FU
4351
4352 /*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
4353                 s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
4354                 column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
4355                  determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note:
4356                 er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
4357                 ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
4358                  hence column bit 10 is used.*/
4359 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL
4360 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
4361 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK
4362 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL                                        0x00000000
4363 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT                                         24
4364 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK                                          0x0F000000U
4365
4366 /*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
4367                 s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
4368                  LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
4369                 ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
4370                 cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
4371                 mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
4372                 .*/
4373 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL
4374 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
4375 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK
4376 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL                                        0x00000000
4377 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT                                         16
4378 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK                                          0x000F0000U
4379
4380 /*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
4381                 s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
4382                 Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
4383                 this field. If set to 15, this column address bit is set to 0.*/
4384 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL
4385 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
4386 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK
4387 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL                                        0x00000000
4388 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT                                         8
4389 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK                                          0x00000F00U
4390
4391 /*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
4392                 s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
4393                 Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
4394                 this field. If set to 15, this column address bit is set to 0.*/
4395 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL
4396 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
4397 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK
4398 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL                                        0x00000000
4399 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT                                         0
4400 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK                                          0x0000000FU
4401
4402 /*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
4403                 mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must
4404                 e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
4405                 l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
4406                 n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
4407                 dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/
4408 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL
4409 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
4410 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK
4411 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL                                       0x00000000
4412 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT                                        8
4413 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK                                         0x00000F00U
4414
4415 /*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
4416                 mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
4417                 To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
4418                 termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
4419                 JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
4420                 bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
4421                 nce column bit 10 is used.*/
4422 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL
4423 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
4424 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK
4425 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL                                       0x00000000
4426 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT                                        0
4427 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK                                         0x0000000FU
4428
4429 /*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
4430                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/
4431 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL
4432 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
4433 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK
4434 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL                                       0x00000000
4435 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT                                        24
4436 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK                                         0x0F000000U
4437
4438 /*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
4439                 bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF
4440                 ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value
4441                 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/
4442 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL
4443 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
4444 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK
4445 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL                                     0x00000000
4446 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT                                      16
4447 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK                                       0x000F0000U
4448
4449 /*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
4450                  each of the row address bits is determined by adding the internal base to the value of this field.*/
4451 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL
4452 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
4453 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK
4454 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL                                        0x00000000
4455 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT                                         8
4456 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK                                          0x00000F00U
4457
4458 /*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
4459                  each of the row address bits is determined by adding the internal base to the value of this field.*/
4460 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL
4461 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
4462 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK
4463 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL                                        0x00000000
4464 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT                                         0
4465 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK                                          0x0000000FU
4466
4467 /*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
4468                 having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
4469                 y in designs configured to support LPDDR3.*/
4470 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL
4471 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
4472 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK
4473 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL                                       0x00000000
4474 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT                                        31
4475 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK                                         0x80000000U
4476
4477 /*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
4478                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/
4479 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL
4480 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
4481 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK
4482 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL                                       0x00000000
4483 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT                                        24
4484 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK                                         0x0F000000U
4485
4486 /*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
4487                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/
4488 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL
4489 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
4490 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK
4491 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL                                       0x00000000
4492 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT                                        16
4493 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK                                         0x000F0000U
4494
4495 /*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
4496                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/
4497 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL
4498 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
4499 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK
4500 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL                                       0x00000000
4501 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT                                        8
4502 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK                                         0x00000F00U
4503
4504 /*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
4505                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/
4506 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL
4507 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
4508 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK
4509 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL                                       0x00000000
4510 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT                                        0
4511 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK                                         0x0000000FU
4512
4513 /*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
4514                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/
4515 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL
4516 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
4517 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK
4518 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL                                       0x00000000
4519 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT                                        8
4520 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK                                         0x00000F00U
4521
4522 /*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
4523                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/
4524 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL
4525 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
4526 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK
4527 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL                                       0x00000000
4528 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT                                        0
4529 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK                                         0x0000000FU
4530
4531 /*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
4532                 address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If
4533                 et to 31, bank group address bit 1 is set to 0.*/
4534 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL
4535 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
4536 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK
4537 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL                                         0x00000000
4538 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT                                          8
4539 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK                                           0x00001F00U
4540
4541 /*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
4542                 bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/
4543 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL
4544 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
4545 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK
4546 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL                                         0x00000000
4547 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT                                          0
4548 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK                                           0x0000001FU
4549
4550 /*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
4551                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4552                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4553 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL
4554 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
4555 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK
4556 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL                                        0x00000000
4557 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT                                         24
4558 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK                                          0x0F000000U
4559
4560 /*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
4561                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4562                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4563 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL
4564 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
4565 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK
4566 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL                                        0x00000000
4567 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT                                         16
4568 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK                                          0x000F0000U
4569
4570 /*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
4571                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
4572                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4573 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL
4574 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
4575 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK
4576 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL                                        0x00000000
4577 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT                                         8
4578 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK                                          0x00000F00U
4579
4580 /*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
4581                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
4582                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4583 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL
4584 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
4585 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK
4586 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL                                        0x00000000
4587 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT                                         0
4588 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK                                          0x0000000FU
4589
4590 /*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
4591                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4592                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4593 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL
4594 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
4595 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK
4596 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL                                       0x00000000
4597 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT                                        24
4598 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK                                         0x0F000000U
4599
4600 /*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
4601                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4602                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4603 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL
4604 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
4605 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK
4606 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL                                       0x00000000
4607 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT                                        16
4608 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK                                         0x000F0000U
4609
4610 /*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
4611                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4612                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4613 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL
4614 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
4615 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK
4616 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL                                       0x00000000
4617 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT                                        8
4618 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK                                         0x00000F00U
4619
4620 /*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
4621                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4622                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4623 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL
4624 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
4625 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK
4626 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL                                       0x00000000
4627 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT                                        0
4628 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK                                         0x0000000FU
4629
4630 /*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit
4631                 or each of the row address bits is determined by adding the internal base to the value of this field. This register field is
4632                 sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4633 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
4634 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
4635 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK
4636 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
4637 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT                                       0
4638 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK                                        0x0000000FU
4639
4640 /*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
4641                 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: -
4642                 L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1
4643                 CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/
4644 #undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL
4645 #undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
4646 #undef DDRC_ODTCFG_WR_ODT_HOLD_MASK
4647 #define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL                                             0x04000400
4648 #define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT                                              24
4649 #define DDRC_ODTCFG_WR_ODT_HOLD_MASK                                               0x0F000000U
4650
4651 /*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
4652                 remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
4653                 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
4654                  DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/
4655 #undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL
4656 #undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
4657 #undef DDRC_ODTCFG_WR_ODT_DELAY_MASK
4658 #define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL                                            0x04000400
4659 #define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT                                             16
4660 #define DDRC_ODTCFG_WR_ODT_DELAY_MASK                                              0x001F0000U
4661
4662 /*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
4663                  0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
4664                 tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
4665                 )*/
4666 #undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL
4667 #undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
4668 #undef DDRC_ODTCFG_RD_ODT_HOLD_MASK
4669 #define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL                                             0x04000400
4670 #define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT                                              8
4671 #define DDRC_ODTCFG_RD_ODT_HOLD_MASK                                               0x00000F00U
4672
4673 /*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must
4674                 emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
4675                 CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
4676                 L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
4677                 write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
4678                 uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/
4679 #undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL
4680 #undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
4681 #undef DDRC_ODTCFG_RD_ODT_DELAY_MASK
4682 #define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL                                            0x04000400
4683 #define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT                                             2
4684 #define DDRC_ODTCFG_RD_ODT_DELAY_MASK                                              0x0000007CU
4685
4686 /*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can
4687                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
4688                  etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
4689 #undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL
4690 #undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
4691 #undef DDRC_ODTMAP_RANK1_RD_ODT_MASK
4692 #define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL                                            0x00002211
4693 #define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT                                             12
4694 #define DDRC_ODTMAP_RANK1_RD_ODT_MASK                                              0x00003000U
4695
4696 /*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
4697                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
4698                 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
4699 #undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL
4700 #undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
4701 #undef DDRC_ODTMAP_RANK1_WR_ODT_MASK
4702 #define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL                                            0x00002211
4703 #define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT                                             8
4704 #define DDRC_ODTMAP_RANK1_WR_ODT_MASK                                              0x00000300U
4705
4706 /*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can
4707                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
4708                  etc. For each rank, set its bit to 1 to enable its ODT.*/
4709 #undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL
4710 #undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
4711 #undef DDRC_ODTMAP_RANK0_RD_ODT_MASK
4712 #define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL                                            0x00002211
4713 #define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT                                             4
4714 #define DDRC_ODTMAP_RANK0_RD_ODT_MASK                                              0x00000030U
4715
4716 /*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
4717                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
4718                 etc. For each rank, set its bit to 1 to enable its ODT.*/
4719 #undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL
4720 #undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
4721 #undef DDRC_ODTMAP_RANK0_WR_ODT_MASK
4722 #define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL                                            0x00002211
4723 #define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT                                             0
4724 #define DDRC_ODTMAP_RANK0_WR_ODT_MASK                                              0x00000003U
4725
4726 /*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
4727                 non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
4728                 ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this
4729                 egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
4730                 OR PERFORMANCE ONLY*/
4731 #undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL
4732 #undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
4733 #undef DDRC_SCHED_RDWR_IDLE_GAP_MASK
4734 #define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL                                            0x00002005
4735 #define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT                                             24
4736 #define DDRC_SCHED_RDWR_IDLE_GAP_MASK                                              0x7F000000U
4737
4738 /*UNUSED*/
4739 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL
4740 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
4741 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK
4742 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL                                   0x00002005
4743 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT                                    16
4744 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK                                     0x00FF0000U
4745
4746 /*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
4747                  the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
4748                 to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
4749                 priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
4750                  than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
4751                 sing out of single bit error correction RMW operation.*/
4752 #undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL
4753 #undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
4754 #undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK
4755 #define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL                                          0x00002005
4756 #define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT                                           8
4757 #define DDRC_SCHED_LPR_NUM_ENTRIES_MASK                                            0x00003F00U
4758
4759 /*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
4760                 e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this
4761                 egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
4762                 es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed
4763                 s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
4764                 ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open
4765                 age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
4766                 ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/
4767 #undef DDRC_SCHED_PAGECLOSE_DEFVAL
4768 #undef DDRC_SCHED_PAGECLOSE_SHIFT
4769 #undef DDRC_SCHED_PAGECLOSE_MASK
4770 #define DDRC_SCHED_PAGECLOSE_DEFVAL                                                0x00002005
4771 #define DDRC_SCHED_PAGECLOSE_SHIFT                                                 2
4772 #define DDRC_SCHED_PAGECLOSE_MASK                                                  0x00000004U
4773
4774 /*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/
4775 #undef DDRC_SCHED_PREFER_WRITE_DEFVAL
4776 #undef DDRC_SCHED_PREFER_WRITE_SHIFT
4777 #undef DDRC_SCHED_PREFER_WRITE_MASK
4778 #define DDRC_SCHED_PREFER_WRITE_DEFVAL                                             0x00002005
4779 #define DDRC_SCHED_PREFER_WRITE_SHIFT                                              1
4780 #define DDRC_SCHED_PREFER_WRITE_MASK                                               0x00000002U
4781
4782 /*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
4783                 ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
4784                 e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
4785                 ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/
4786 #undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL
4787 #undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
4788 #undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK
4789 #define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL                                          0x00002005
4790 #define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT                                           0
4791 #define DDRC_SCHED_FORCE_LOW_PRI_N_MASK                                            0x00000001U
4792
4793 /*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
4794                  transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
4795 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL
4796 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
4797 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK
4798 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL                                   0x0F00007F
4799 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT                                    24
4800 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK                                     0xFF000000U
4801
4802 /*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
4803                 er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
4804                 be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
4805 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL
4806 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
4807 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK
4808 #define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL                                        0x0F00007F
4809 #define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT                                         0
4810 #define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK                                          0x0000FFFFU
4811
4812 /*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
4813                 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
4814 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL
4815 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
4816 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK
4817 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL                                      0x0F00007F
4818 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT                                       24
4819 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK                                        0xFF000000U
4820
4821 /*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
4822                 r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
4823                 e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
4824 #undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL
4825 #undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT
4826 #undef DDRC_PERFWR1_W_MAX_STARVE_MASK
4827 #define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL                                           0x0F00007F
4828 #define DDRC_PERFWR1_W_MAX_STARVE_SHIFT                                            0
4829 #define DDRC_PERFWR1_W_MAX_STARVE_MASK                                             0x0000FFFFU
4830
4831 /*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
4832                 all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and
4833                 wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
4834                 port DDR4.*/
4835 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
4836 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
4837 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK
4838 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
4839 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT                                         0
4840 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK                                          0x00000001U
4841
4842 /*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
4843                 lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
4844                 s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/
4845 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL
4846 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
4847 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK
4848 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL                                    0x00000000
4849 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT                                     4
4850 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK                                      0x00000010U
4851
4852 /*When 1, disable write combine. FOR DEBUG ONLY*/
4853 #undef DDRC_DBG0_DIS_WC_DEFVAL
4854 #undef DDRC_DBG0_DIS_WC_SHIFT
4855 #undef DDRC_DBG0_DIS_WC_MASK
4856 #define DDRC_DBG0_DIS_WC_DEFVAL                                                    0x00000000
4857 #define DDRC_DBG0_DIS_WC_SHIFT                                                     0
4858 #define DDRC_DBG0_DIS_WC_MASK                                                      0x00000001U
4859
4860 /*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
4861                 the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
4862                 register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
4863                 _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
4864                  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/
4865 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL
4866 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
4867 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK
4868 #define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL                                            0x00000000
4869 #define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT                                             31
4870 #define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK                                              0x80000000U
4871
4872 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in
4873                 he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/
4874 #undef DDRC_DBGCMD_CTRLUPD_DEFVAL
4875 #undef DDRC_DBGCMD_CTRLUPD_SHIFT
4876 #undef DDRC_DBGCMD_CTRLUPD_MASK
4877 #define DDRC_DBGCMD_CTRLUPD_DEFVAL                                                 0x00000000
4878 #define DDRC_DBGCMD_CTRLUPD_SHIFT                                                  5
4879 #define DDRC_DBGCMD_CTRLUPD_MASK                                                   0x00000020U
4880
4881 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to
4882                 he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
4883                 en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
4884                 d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
4885                 de.*/
4886 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL
4887 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
4888 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK
4889 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL                                          0x00000000
4890 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT                                           4
4891 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK                                            0x00000010U
4892
4893 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
4894                 refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4895                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4896                 wn operating modes or Maximum Power Saving Mode.*/
4897 #undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL
4898 #undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT
4899 #undef DDRC_DBGCMD_RANK1_REFRESH_MASK
4900 #define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL                                           0x00000000
4901 #define DDRC_DBGCMD_RANK1_REFRESH_SHIFT                                            1
4902 #define DDRC_DBGCMD_RANK1_REFRESH_MASK                                             0x00000002U
4903
4904 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
4905                 refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4906                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4907                 wn operating modes or Maximum Power Saving Mode.*/
4908 #undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL
4909 #undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT
4910 #undef DDRC_DBGCMD_RANK0_REFRESH_MASK
4911 #define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL                                           0x00000000
4912 #define DDRC_DBGCMD_RANK0_REFRESH_SHIFT                                            0
4913 #define DDRC_DBGCMD_RANK0_REFRESH_MASK                                             0x00000001U
4914
4915 /*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back
4916                 egister to 1 once programming is done.*/
4917 #undef DDRC_SWCTL_SW_DONE_DEFVAL
4918 #undef DDRC_SWCTL_SW_DONE_SHIFT
4919 #undef DDRC_SWCTL_SW_DONE_MASK
4920 #define DDRC_SWCTL_SW_DONE_DEFVAL
4921 #define DDRC_SWCTL_SW_DONE_SHIFT                                                   0
4922 #define DDRC_SWCTL_SW_DONE_MASK                                                    0x00000001U
4923
4924 /*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
4925                 e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
4926                 h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
4927                 ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
4928                 _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
4929                 ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
4930                 DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
4931                 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
4932                 -AC is enabled*/
4933 #undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL
4934 #undef DDRC_PCCFG_BL_EXP_MODE_SHIFT
4935 #undef DDRC_PCCFG_BL_EXP_MODE_MASK
4936 #define DDRC_PCCFG_BL_EXP_MODE_DEFVAL                                              0x00000000
4937 #define DDRC_PCCFG_BL_EXP_MODE_SHIFT                                               8
4938 #define DDRC_PCCFG_BL_EXP_MODE_MASK                                                0x00000100U
4939
4940 /*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
4941                 rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
4942                 ge DDRC transactions.*/
4943 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL
4944 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
4945 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK
4946 #define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL                                          0x00000000
4947 #define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT                                           4
4948 #define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK                                            0x00000010U
4949
4950 /*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based
4951                 n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
4952                 _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/
4953 #undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL
4954 #undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
4955 #undef DDRC_PCCFG_GO2CRITICAL_EN_MASK
4956 #define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL                                           0x00000000
4957 #define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT                                            0
4958 #define DDRC_PCCFG_GO2CRITICAL_EN_MASK                                             0x00000001U
4959
4960 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4961                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4962                 imit register.*/
4963 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL
4964 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
4965 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK
4966 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
4967 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
4968 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
4969
4970 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4971                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4972                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4973                 ess handshaking (it is not associated with any particular command).*/
4974 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL
4975 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
4976 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK
4977 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
4978 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT                                       13
4979 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK                                        0x00002000U
4980
4981 /*If set to 1, enables aging function for the read channel of the port.*/
4982 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL
4983 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
4984 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK
4985 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
4986 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT                                        12
4987 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK                                         0x00001000U
4988
4989 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4990                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4991                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4992                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4993                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4994                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4995                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4996                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4997                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4998                 he two LSBs of this register field are tied internally to 2'b00.*/
4999 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL
5000 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
5001 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK
5002 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5003 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT                                        0
5004 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5005
5006 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5007                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5008                 imit register.*/
5009 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL
5010 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
5011 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK
5012 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5013 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5014 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5015
5016 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5017                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5018                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5019                 not associated with any particular command).*/
5020 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL
5021 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
5022 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK
5023 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5024 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT                                       13
5025 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5026
5027 /*If set to 1, enables aging function for the write channel of the port.*/
5028 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL
5029 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
5030 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK
5031 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5032 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT                                        12
5033 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK                                         0x00001000U
5034
5035 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5036                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5037                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5038                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5039                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5040                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5041                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5042                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5043 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL
5044 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
5045 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK
5046 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5047 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT                                        0
5048 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5049
5050 /*Enables port n.*/
5051 #undef DDRC_PCTRL_0_PORT_EN_DEFVAL
5052 #undef DDRC_PCTRL_0_PORT_EN_SHIFT
5053 #undef DDRC_PCTRL_0_PORT_EN_MASK
5054 #define DDRC_PCTRL_0_PORT_EN_DEFVAL
5055 #define DDRC_PCTRL_0_PORT_EN_SHIFT                                                 0
5056 #define DDRC_PCTRL_0_PORT_EN_MASK                                                  0x00000001U
5057
5058 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5059                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5060                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5061 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL
5062 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
5063 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK
5064 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
5065 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT                                     20
5066 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK                                      0x00300000U
5067
5068 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5069                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5070                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5071 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL
5072 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
5073 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK
5074 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
5075 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT                                     16
5076 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK                                      0x00030000U
5077
5078 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5079                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5080                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5081                  values.*/
5082 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL
5083 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
5084 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK
5085 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
5086 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT                                      0
5087 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5088
5089 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5090 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL
5091 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
5092 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK
5093 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5094 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5095 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5096
5097 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5098 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL
5099 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
5100 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK
5101 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5102 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5103 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5104
5105 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5106                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5107                 imit register.*/
5108 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL
5109 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
5110 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK
5111 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5112 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5113 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5114
5115 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5116                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5117                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5118                 ess handshaking (it is not associated with any particular command).*/
5119 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL
5120 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
5121 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK
5122 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5123 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT                                       13
5124 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5125
5126 /*If set to 1, enables aging function for the read channel of the port.*/
5127 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL
5128 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
5129 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK
5130 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5131 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT                                        12
5132 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK                                         0x00001000U
5133
5134 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5135                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5136                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5137                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5138                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5139                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5140                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5141                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5142                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5143                 he two LSBs of this register field are tied internally to 2'b00.*/
5144 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL
5145 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
5146 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK
5147 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5148 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT                                        0
5149 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5150
5151 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5152                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5153                 imit register.*/
5154 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL
5155 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
5156 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK
5157 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5158 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5159 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5160
5161 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5162                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5163                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5164                 not associated with any particular command).*/
5165 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL
5166 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
5167 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK
5168 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5169 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT                                       13
5170 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5171
5172 /*If set to 1, enables aging function for the write channel of the port.*/
5173 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL
5174 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
5175 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK
5176 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5177 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT                                        12
5178 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK                                         0x00001000U
5179
5180 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5181                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5182                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5183                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5184                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5185                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5186                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5187                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5188 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL
5189 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
5190 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK
5191 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5192 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT                                        0
5193 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5194
5195 /*Enables port n.*/
5196 #undef DDRC_PCTRL_1_PORT_EN_DEFVAL
5197 #undef DDRC_PCTRL_1_PORT_EN_SHIFT
5198 #undef DDRC_PCTRL_1_PORT_EN_MASK
5199 #define DDRC_PCTRL_1_PORT_EN_DEFVAL
5200 #define DDRC_PCTRL_1_PORT_EN_SHIFT                                                 0
5201 #define DDRC_PCTRL_1_PORT_EN_MASK                                                  0x00000001U
5202
5203 /*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
5204                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
5205                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5206 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL
5207 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
5208 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK
5209 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL                                    0x02000E00
5210 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT                                     24
5211 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK                                      0x03000000U
5212
5213 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5214                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5215                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5216 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL
5217 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
5218 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK
5219 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL                                    0x02000E00
5220 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT                                     20
5221 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK                                      0x00300000U
5222
5223 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5224                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5225                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5226 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL
5227 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
5228 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK
5229 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL                                    0x02000E00
5230 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT                                     16
5231 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK                                      0x00030000U
5232
5233 /*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
5234                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
5235                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
5236                 ust be set to distinct values.*/
5237 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL
5238 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
5239 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK
5240 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL                                     0x02000E00
5241 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT                                      8
5242 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK                                       0x00000F00U
5243
5244 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5245                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5246                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5247                  values.*/
5248 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL
5249 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
5250 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK
5251 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL                                     0x02000E00
5252 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT                                      0
5253 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5254
5255 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5256 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL
5257 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
5258 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK
5259 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5260 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5261 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5262
5263 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5264 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL
5265 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
5266 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK
5267 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5268 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5269 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5270
5271 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5272                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5273                 imit register.*/
5274 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL
5275 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
5276 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK
5277 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5278 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5279 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5280
5281 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5282                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5283                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5284                 ess handshaking (it is not associated with any particular command).*/
5285 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL
5286 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
5287 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK
5288 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5289 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT                                       13
5290 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5291
5292 /*If set to 1, enables aging function for the read channel of the port.*/
5293 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL
5294 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
5295 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK
5296 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5297 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT                                        12
5298 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK                                         0x00001000U
5299
5300 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5301                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5302                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5303                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5304                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5305                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5306                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5307                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5308                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5309                 he two LSBs of this register field are tied internally to 2'b00.*/
5310 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL
5311 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
5312 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK
5313 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5314 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT                                        0
5315 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5316
5317 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5318                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5319                 imit register.*/
5320 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL
5321 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
5322 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK
5323 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5324 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5325 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5326
5327 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5328                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5329                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5330                 not associated with any particular command).*/
5331 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL
5332 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
5333 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK
5334 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5335 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT                                       13
5336 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5337
5338 /*If set to 1, enables aging function for the write channel of the port.*/
5339 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL
5340 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
5341 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK
5342 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5343 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT                                        12
5344 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK                                         0x00001000U
5345
5346 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5347                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5348                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5349                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5350                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5351                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5352                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5353                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5354 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL
5355 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
5356 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK
5357 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5358 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT                                        0
5359 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5360
5361 /*Enables port n.*/
5362 #undef DDRC_PCTRL_2_PORT_EN_DEFVAL
5363 #undef DDRC_PCTRL_2_PORT_EN_SHIFT
5364 #undef DDRC_PCTRL_2_PORT_EN_MASK
5365 #define DDRC_PCTRL_2_PORT_EN_DEFVAL
5366 #define DDRC_PCTRL_2_PORT_EN_SHIFT                                                 0
5367 #define DDRC_PCTRL_2_PORT_EN_MASK                                                  0x00000001U
5368
5369 /*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
5370                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
5371                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5372 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL
5373 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
5374 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK
5375 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL                                    0x02000E00
5376 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT                                     24
5377 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK                                      0x03000000U
5378
5379 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5380                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5381                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5382 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL
5383 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
5384 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK
5385 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL                                    0x02000E00
5386 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT                                     20
5387 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK                                      0x00300000U
5388
5389 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5390                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5391                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5392 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL
5393 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
5394 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK
5395 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL                                    0x02000E00
5396 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT                                     16
5397 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK                                      0x00030000U
5398
5399 /*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
5400                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
5401                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
5402                 ust be set to distinct values.*/
5403 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL
5404 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
5405 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK
5406 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL                                     0x02000E00
5407 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT                                      8
5408 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK                                       0x00000F00U
5409
5410 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5411                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5412                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5413                  values.*/
5414 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL
5415 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
5416 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK
5417 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL                                     0x02000E00
5418 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT                                      0
5419 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5420
5421 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5422 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL
5423 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
5424 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK
5425 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5426 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5427 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5428
5429 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5430 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL
5431 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
5432 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK
5433 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5434 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5435 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5436
5437 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5438                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5439                 imit register.*/
5440 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL
5441 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
5442 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK
5443 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5444 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5445 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5446
5447 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5448                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5449                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5450                 ess handshaking (it is not associated with any particular command).*/
5451 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL
5452 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
5453 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK
5454 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5455 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT                                       13
5456 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5457
5458 /*If set to 1, enables aging function for the read channel of the port.*/
5459 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL
5460 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
5461 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK
5462 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5463 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT                                        12
5464 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK                                         0x00001000U
5465
5466 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5467                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5468                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5469                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5470                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5471                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5472                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5473                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5474                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5475                 he two LSBs of this register field are tied internally to 2'b00.*/
5476 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL
5477 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
5478 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK
5479 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5480 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT                                        0
5481 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5482
5483 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5484                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5485                 imit register.*/
5486 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL
5487 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
5488 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK
5489 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5490 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5491 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5492
5493 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5494                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5495                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5496                 not associated with any particular command).*/
5497 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL
5498 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
5499 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK
5500 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5501 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT                                       13
5502 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5503
5504 /*If set to 1, enables aging function for the write channel of the port.*/
5505 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL
5506 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
5507 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK
5508 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5509 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT                                        12
5510 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK                                         0x00001000U
5511
5512 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5513                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5514                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5515                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5516                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5517                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5518                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5519                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5520 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL
5521 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
5522 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK
5523 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5524 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT                                        0
5525 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5526
5527 /*Enables port n.*/
5528 #undef DDRC_PCTRL_3_PORT_EN_DEFVAL
5529 #undef DDRC_PCTRL_3_PORT_EN_SHIFT
5530 #undef DDRC_PCTRL_3_PORT_EN_MASK
5531 #define DDRC_PCTRL_3_PORT_EN_DEFVAL
5532 #define DDRC_PCTRL_3_PORT_EN_SHIFT                                                 0
5533 #define DDRC_PCTRL_3_PORT_EN_MASK                                                  0x00000001U
5534
5535 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5536                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5537                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5538 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL
5539 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
5540 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK
5541 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
5542 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT                                     20
5543 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK                                      0x00300000U
5544
5545 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5546                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5547                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5548 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL
5549 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
5550 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK
5551 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
5552 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT                                     16
5553 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK                                      0x00030000U
5554
5555 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5556                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5557                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5558                  values.*/
5559 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL
5560 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
5561 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK
5562 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
5563 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT                                      0
5564 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5565
5566 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5567 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL
5568 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
5569 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK
5570 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5571 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5572 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5573
5574 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5575 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL
5576 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
5577 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK
5578 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5579 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5580 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5581
5582 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5583                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
5584 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL
5585 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
5586 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK
5587 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
5588 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT                                    20
5589 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK                                     0x00300000U
5590
5591 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5592                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
5593 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL
5594 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
5595 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK
5596 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
5597 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT                                    16
5598 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK                                     0x00030000U
5599
5600 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5601                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5602                 s to higher port priority.*/
5603 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL
5604 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
5605 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK
5606 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
5607 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT                                      0
5608 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
5609
5610 /*Specifies the timeout value for write transactions.*/
5611 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
5612 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
5613 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK
5614 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
5615 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT                                    0
5616 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
5617
5618 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5619                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5620                 imit register.*/
5621 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL
5622 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
5623 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK
5624 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5625 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5626 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5627
5628 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5629                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5630                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5631                 ess handshaking (it is not associated with any particular command).*/
5632 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL
5633 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
5634 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK
5635 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5636 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT                                       13
5637 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5638
5639 /*If set to 1, enables aging function for the read channel of the port.*/
5640 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL
5641 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
5642 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK
5643 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5644 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT                                        12
5645 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK                                         0x00001000U
5646
5647 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5648                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5649                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5650                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5651                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5652                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5653                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5654                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5655                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5656                 he two LSBs of this register field are tied internally to 2'b00.*/
5657 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL
5658 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
5659 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK
5660 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5661 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT                                        0
5662 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5663
5664 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5665                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5666                 imit register.*/
5667 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL
5668 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
5669 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK
5670 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5671 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5672 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5673
5674 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5675                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5676                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5677                 not associated with any particular command).*/
5678 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL
5679 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
5680 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK
5681 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5682 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT                                       13
5683 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5684
5685 /*If set to 1, enables aging function for the write channel of the port.*/
5686 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL
5687 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
5688 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK
5689 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5690 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT                                        12
5691 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK                                         0x00001000U
5692
5693 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5694                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5695                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5696                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5697                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5698                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5699                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5700                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5701 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL
5702 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
5703 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK
5704 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5705 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT                                        0
5706 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5707
5708 /*Enables port n.*/
5709 #undef DDRC_PCTRL_4_PORT_EN_DEFVAL
5710 #undef DDRC_PCTRL_4_PORT_EN_SHIFT
5711 #undef DDRC_PCTRL_4_PORT_EN_MASK
5712 #define DDRC_PCTRL_4_PORT_EN_DEFVAL
5713 #define DDRC_PCTRL_4_PORT_EN_SHIFT                                                 0
5714 #define DDRC_PCTRL_4_PORT_EN_MASK                                                  0x00000001U
5715
5716 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5717                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5718                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5719 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL
5720 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
5721 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK
5722 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
5723 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT                                     20
5724 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK                                      0x00300000U
5725
5726 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5727                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5728                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5729 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL
5730 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
5731 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK
5732 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
5733 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT                                     16
5734 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK                                      0x00030000U
5735
5736 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5737                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5738                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5739                  values.*/
5740 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL
5741 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
5742 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK
5743 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
5744 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT                                      0
5745 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5746
5747 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5748 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL
5749 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
5750 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK
5751 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5752 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5753 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5754
5755 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5756 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL
5757 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
5758 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK
5759 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5760 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5761 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5762
5763 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5764                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
5765 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL
5766 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
5767 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK
5768 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
5769 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT                                    20
5770 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK                                     0x00300000U
5771
5772 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5773                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
5774 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL
5775 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
5776 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK
5777 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
5778 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT                                    16
5779 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK                                     0x00030000U
5780
5781 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5782                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5783                 s to higher port priority.*/
5784 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL
5785 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
5786 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK
5787 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
5788 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT                                      0
5789 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
5790
5791 /*Specifies the timeout value for write transactions.*/
5792 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
5793 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
5794 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK
5795 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
5796 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT                                    0
5797 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
5798
5799 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5800                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5801                 imit register.*/
5802 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL
5803 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
5804 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK
5805 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5806 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5807 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5808
5809 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5810                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5811                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5812                 ess handshaking (it is not associated with any particular command).*/
5813 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL
5814 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
5815 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK
5816 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5817 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT                                       13
5818 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5819
5820 /*If set to 1, enables aging function for the read channel of the port.*/
5821 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL
5822 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
5823 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK
5824 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5825 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT                                        12
5826 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK                                         0x00001000U
5827
5828 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5829                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5830                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5831                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5832                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5833                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5834                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5835                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5836                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5837                 he two LSBs of this register field are tied internally to 2'b00.*/
5838 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL
5839 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
5840 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK
5841 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5842 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT                                        0
5843 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5844
5845 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5846                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5847                 imit register.*/
5848 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL
5849 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
5850 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK
5851 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5852 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5853 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5854
5855 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5856                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5857                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5858                 not associated with any particular command).*/
5859 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL
5860 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
5861 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK
5862 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5863 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT                                       13
5864 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5865
5866 /*If set to 1, enables aging function for the write channel of the port.*/
5867 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL
5868 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
5869 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK
5870 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5871 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT                                        12
5872 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK                                         0x00001000U
5873
5874 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5875                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5876                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5877                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5878                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5879                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5880                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5881                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5882 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL
5883 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
5884 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK
5885 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5886 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT                                        0
5887 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5888
5889 /*Enables port n.*/
5890 #undef DDRC_PCTRL_5_PORT_EN_DEFVAL
5891 #undef DDRC_PCTRL_5_PORT_EN_SHIFT
5892 #undef DDRC_PCTRL_5_PORT_EN_MASK
5893 #define DDRC_PCTRL_5_PORT_EN_DEFVAL
5894 #define DDRC_PCTRL_5_PORT_EN_SHIFT                                                 0
5895 #define DDRC_PCTRL_5_PORT_EN_MASK                                                  0x00000001U
5896
5897 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5898                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5899                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5900 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL
5901 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
5902 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK
5903 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
5904 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT                                     20
5905 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK                                      0x00300000U
5906
5907 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5908                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5909                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5910 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL
5911 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
5912 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK
5913 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
5914 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT                                     16
5915 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK                                      0x00030000U
5916
5917 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5918                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5919                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5920                  values.*/
5921 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL
5922 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
5923 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK
5924 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
5925 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT                                      0
5926 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5927
5928 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5929 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL
5930 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
5931 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK
5932 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5933 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5934 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5935
5936 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5937 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL
5938 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
5939 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK
5940 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5941 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5942 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5943
5944 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5945                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
5946 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL
5947 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
5948 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK
5949 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
5950 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT                                    20
5951 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK                                     0x00300000U
5952
5953 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5954                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
5955 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL
5956 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
5957 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK
5958 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
5959 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT                                    16
5960 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK                                     0x00030000U
5961
5962 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5963                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5964                 s to higher port priority.*/
5965 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL
5966 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
5967 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK
5968 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
5969 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT                                      0
5970 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
5971
5972 /*Specifies the timeout value for write transactions.*/
5973 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
5974 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
5975 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK
5976 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
5977 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT                                    0
5978 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
5979
5980 /*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
5981                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
5982 #undef DDRC_SARBASE0_BASE_ADDR_DEFVAL
5983 #undef DDRC_SARBASE0_BASE_ADDR_SHIFT
5984 #undef DDRC_SARBASE0_BASE_ADDR_MASK
5985 #define DDRC_SARBASE0_BASE_ADDR_DEFVAL
5986 #define DDRC_SARBASE0_BASE_ADDR_SHIFT                                              0
5987 #define DDRC_SARBASE0_BASE_ADDR_MASK                                               0x000001FFU
5988
5989 /*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
5990                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
5991                 or example, if register is programmed to 0, region will have 1 block.*/
5992 #undef DDRC_SARSIZE0_NBLOCKS_DEFVAL
5993 #undef DDRC_SARSIZE0_NBLOCKS_SHIFT
5994 #undef DDRC_SARSIZE0_NBLOCKS_MASK
5995 #define DDRC_SARSIZE0_NBLOCKS_DEFVAL
5996 #define DDRC_SARSIZE0_NBLOCKS_SHIFT                                                0
5997 #define DDRC_SARSIZE0_NBLOCKS_MASK                                                 0x000000FFU
5998
5999 /*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
6000                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
6001 #undef DDRC_SARBASE1_BASE_ADDR_DEFVAL
6002 #undef DDRC_SARBASE1_BASE_ADDR_SHIFT
6003 #undef DDRC_SARBASE1_BASE_ADDR_MASK
6004 #define DDRC_SARBASE1_BASE_ADDR_DEFVAL
6005 #define DDRC_SARBASE1_BASE_ADDR_SHIFT                                              0
6006 #define DDRC_SARBASE1_BASE_ADDR_MASK                                               0x000001FFU
6007
6008 /*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
6009                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
6010                 or example, if register is programmed to 0, region will have 1 block.*/
6011 #undef DDRC_SARSIZE1_NBLOCKS_DEFVAL
6012 #undef DDRC_SARSIZE1_NBLOCKS_SHIFT
6013 #undef DDRC_SARSIZE1_NBLOCKS_MASK
6014 #define DDRC_SARSIZE1_NBLOCKS_DEFVAL
6015 #define DDRC_SARSIZE1_NBLOCKS_SHIFT                                                0
6016 #define DDRC_SARSIZE1_NBLOCKS_MASK                                                 0x000000FFU
6017
6018 /*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
6019                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
6020                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
6021                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
6022 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL
6023 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
6024 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK
6025 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL                                0x07020002
6026 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT                                 24
6027 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK                                  0x1F000000U
6028
6029 /*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
6030                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
6031                 fer to PHY specification for correct value.*/
6032 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL
6033 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
6034 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK
6035 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL                              0x07020002
6036 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT                               23
6037 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK                                0x00800000U
6038
6039 /*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
6040                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
6041                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
6042                  latency through the RDIMM. Unit: Clocks*/
6043 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL
6044 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
6045 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK
6046 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL                                 0x07020002
6047 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT                                  16
6048 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK                                   0x003F0000U
6049
6050 /*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
6051                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
6052                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
6053                 e.*/
6054 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL
6055 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
6056 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK
6057 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL                              0x07020002
6058 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT                               15
6059 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK                                0x00008000U
6060
6061 /*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
6062                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
6063                 te, max supported value is 8. Unit: Clocks*/
6064 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL
6065 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
6066 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK
6067 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL                                 0x07020002
6068 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT                                  8
6069 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK                                   0x00003F00U
6070
6071 /*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
6072                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
6073                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
6074                 rough the RDIMM.*/
6075 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL
6076 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
6077 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK
6078 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL                                  0x07020002
6079 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT                                   0
6080 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK                                    0x0000003FU
6081
6082 /*DDR block level reset inside of the DDR Sub System*/
6083 #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
6084 #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
6085 #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
6086 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                                        0x0000000F
6087 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                                         3
6088 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                                          0x00000008U
6089
6090 /*Address Copy*/
6091 #undef DDR_PHY_PGCR0_ADCP_DEFVAL
6092 #undef DDR_PHY_PGCR0_ADCP_SHIFT
6093 #undef DDR_PHY_PGCR0_ADCP_MASK
6094 #define DDR_PHY_PGCR0_ADCP_DEFVAL                                                  0x07001E00
6095 #define DDR_PHY_PGCR0_ADCP_SHIFT                                                   31
6096 #define DDR_PHY_PGCR0_ADCP_MASK                                                    0x80000000U
6097
6098 /*Reserved. Returns zeroes on reads.*/
6099 #undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL
6100 #undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
6101 #undef DDR_PHY_PGCR0_RESERVED_30_27_MASK
6102 #define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL                                        0x07001E00
6103 #define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT                                         27
6104 #define DDR_PHY_PGCR0_RESERVED_30_27_MASK                                          0x78000000U
6105
6106 /*PHY FIFO Reset*/
6107 #undef DDR_PHY_PGCR0_PHYFRST_DEFVAL
6108 #undef DDR_PHY_PGCR0_PHYFRST_SHIFT
6109 #undef DDR_PHY_PGCR0_PHYFRST_MASK
6110 #define DDR_PHY_PGCR0_PHYFRST_DEFVAL                                               0x07001E00
6111 #define DDR_PHY_PGCR0_PHYFRST_SHIFT                                                26
6112 #define DDR_PHY_PGCR0_PHYFRST_MASK                                                 0x04000000U
6113
6114 /*Oscillator Mode Address/Command Delay Line Select*/
6115 #undef DDR_PHY_PGCR0_OSCACDL_DEFVAL
6116 #undef DDR_PHY_PGCR0_OSCACDL_SHIFT
6117 #undef DDR_PHY_PGCR0_OSCACDL_MASK
6118 #define DDR_PHY_PGCR0_OSCACDL_DEFVAL                                               0x07001E00
6119 #define DDR_PHY_PGCR0_OSCACDL_SHIFT                                                24
6120 #define DDR_PHY_PGCR0_OSCACDL_MASK                                                 0x03000000U
6121
6122 /*Reserved. Returns zeroes on reads.*/
6123 #undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL
6124 #undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
6125 #undef DDR_PHY_PGCR0_RESERVED_23_19_MASK
6126 #define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL                                        0x07001E00
6127 #define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT                                         19
6128 #define DDR_PHY_PGCR0_RESERVED_23_19_MASK                                          0x00F80000U
6129
6130 /*Digital Test Output Select*/
6131 #undef DDR_PHY_PGCR0_DTOSEL_DEFVAL
6132 #undef DDR_PHY_PGCR0_DTOSEL_SHIFT
6133 #undef DDR_PHY_PGCR0_DTOSEL_MASK
6134 #define DDR_PHY_PGCR0_DTOSEL_DEFVAL                                                0x07001E00
6135 #define DDR_PHY_PGCR0_DTOSEL_SHIFT                                                 14
6136 #define DDR_PHY_PGCR0_DTOSEL_MASK                                                  0x0007C000U
6137
6138 /*Reserved. Returns zeroes on reads.*/
6139 #undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL
6140 #undef DDR_PHY_PGCR0_RESERVED_13_SHIFT
6141 #undef DDR_PHY_PGCR0_RESERVED_13_MASK
6142 #define DDR_PHY_PGCR0_RESERVED_13_DEFVAL                                           0x07001E00
6143 #define DDR_PHY_PGCR0_RESERVED_13_SHIFT                                            13
6144 #define DDR_PHY_PGCR0_RESERVED_13_MASK                                             0x00002000U
6145
6146 /*Oscillator Mode Division*/
6147 #undef DDR_PHY_PGCR0_OSCDIV_DEFVAL
6148 #undef DDR_PHY_PGCR0_OSCDIV_SHIFT
6149 #undef DDR_PHY_PGCR0_OSCDIV_MASK
6150 #define DDR_PHY_PGCR0_OSCDIV_DEFVAL                                                0x07001E00
6151 #define DDR_PHY_PGCR0_OSCDIV_SHIFT                                                 9
6152 #define DDR_PHY_PGCR0_OSCDIV_MASK                                                  0x00001E00U
6153
6154 /*Oscillator Enable*/
6155 #undef DDR_PHY_PGCR0_OSCEN_DEFVAL
6156 #undef DDR_PHY_PGCR0_OSCEN_SHIFT
6157 #undef DDR_PHY_PGCR0_OSCEN_MASK
6158 #define DDR_PHY_PGCR0_OSCEN_DEFVAL                                                 0x07001E00
6159 #define DDR_PHY_PGCR0_OSCEN_SHIFT                                                  8
6160 #define DDR_PHY_PGCR0_OSCEN_MASK                                                   0x00000100U
6161
6162 /*Reserved. Returns zeroes on reads.*/
6163 #undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL
6164 #undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
6165 #undef DDR_PHY_PGCR0_RESERVED_7_0_MASK
6166 #define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL                                          0x07001E00
6167 #define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT                                           0
6168 #define DDR_PHY_PGCR0_RESERVED_7_0_MASK                                            0x000000FFU
6169
6170 /*Clear Training Status Registers*/
6171 #undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL
6172 #undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT
6173 #undef DDR_PHY_PGCR2_CLRTSTAT_MASK
6174 #define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL                                              0x00F12480
6175 #define DDR_PHY_PGCR2_CLRTSTAT_SHIFT                                               31
6176 #define DDR_PHY_PGCR2_CLRTSTAT_MASK                                                0x80000000U
6177
6178 /*Clear Impedance Calibration*/
6179 #undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL
6180 #undef DDR_PHY_PGCR2_CLRZCAL_SHIFT
6181 #undef DDR_PHY_PGCR2_CLRZCAL_MASK
6182 #define DDR_PHY_PGCR2_CLRZCAL_DEFVAL                                               0x00F12480
6183 #define DDR_PHY_PGCR2_CLRZCAL_SHIFT                                                30
6184 #define DDR_PHY_PGCR2_CLRZCAL_MASK                                                 0x40000000U
6185
6186 /*Clear Parity Error*/
6187 #undef DDR_PHY_PGCR2_CLRPERR_DEFVAL
6188 #undef DDR_PHY_PGCR2_CLRPERR_SHIFT
6189 #undef DDR_PHY_PGCR2_CLRPERR_MASK
6190 #define DDR_PHY_PGCR2_CLRPERR_DEFVAL                                               0x00F12480
6191 #define DDR_PHY_PGCR2_CLRPERR_SHIFT                                                29
6192 #define DDR_PHY_PGCR2_CLRPERR_MASK                                                 0x20000000U
6193
6194 /*Initialization Complete Pin Configuration*/
6195 #undef DDR_PHY_PGCR2_ICPC_DEFVAL
6196 #undef DDR_PHY_PGCR2_ICPC_SHIFT
6197 #undef DDR_PHY_PGCR2_ICPC_MASK
6198 #define DDR_PHY_PGCR2_ICPC_DEFVAL                                                  0x00F12480
6199 #define DDR_PHY_PGCR2_ICPC_SHIFT                                                   28
6200 #define DDR_PHY_PGCR2_ICPC_MASK                                                    0x10000000U
6201
6202 /*Data Training PUB Mode Exit Timer*/
6203 #undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL
6204 #undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT
6205 #undef DDR_PHY_PGCR2_DTPMXTMR_MASK
6206 #define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL                                              0x00F12480
6207 #define DDR_PHY_PGCR2_DTPMXTMR_SHIFT                                               20
6208 #define DDR_PHY_PGCR2_DTPMXTMR_MASK                                                0x0FF00000U
6209
6210 /*Initialization Bypass*/
6211 #undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL
6212 #undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT
6213 #undef DDR_PHY_PGCR2_INITFSMBYP_MASK
6214 #define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL                                            0x00F12480
6215 #define DDR_PHY_PGCR2_INITFSMBYP_SHIFT                                             19
6216 #define DDR_PHY_PGCR2_INITFSMBYP_MASK                                              0x00080000U
6217
6218 /*PLL FSM Bypass*/
6219 #undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL
6220 #undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
6221 #undef DDR_PHY_PGCR2_PLLFSMBYP_MASK
6222 #define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL                                             0x00F12480
6223 #define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT                                              18
6224 #define DDR_PHY_PGCR2_PLLFSMBYP_MASK                                               0x00040000U
6225
6226 /*Refresh Period*/
6227 #undef DDR_PHY_PGCR2_TREFPRD_DEFVAL
6228 #undef DDR_PHY_PGCR2_TREFPRD_SHIFT
6229 #undef DDR_PHY_PGCR2_TREFPRD_MASK
6230 #define DDR_PHY_PGCR2_TREFPRD_DEFVAL                                               0x00F12480
6231 #define DDR_PHY_PGCR2_TREFPRD_SHIFT                                                0
6232 #define DDR_PHY_PGCR2_TREFPRD_MASK                                                 0x0003FFFFU
6233
6234 /*CKN Enable*/
6235 #undef DDR_PHY_PGCR3_CKNEN_DEFVAL
6236 #undef DDR_PHY_PGCR3_CKNEN_SHIFT
6237 #undef DDR_PHY_PGCR3_CKNEN_MASK
6238 #define DDR_PHY_PGCR3_CKNEN_DEFVAL                                                 0x55AA0080
6239 #define DDR_PHY_PGCR3_CKNEN_SHIFT                                                  24
6240 #define DDR_PHY_PGCR3_CKNEN_MASK                                                   0xFF000000U
6241
6242 /*CK Enable*/
6243 #undef DDR_PHY_PGCR3_CKEN_DEFVAL
6244 #undef DDR_PHY_PGCR3_CKEN_SHIFT
6245 #undef DDR_PHY_PGCR3_CKEN_MASK
6246 #define DDR_PHY_PGCR3_CKEN_DEFVAL                                                  0x55AA0080
6247 #define DDR_PHY_PGCR3_CKEN_SHIFT                                                   16
6248 #define DDR_PHY_PGCR3_CKEN_MASK                                                    0x00FF0000U
6249
6250 /*Reserved. Return zeroes on reads.*/
6251 #undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL
6252 #undef DDR_PHY_PGCR3_RESERVED_15_SHIFT
6253 #undef DDR_PHY_PGCR3_RESERVED_15_MASK
6254 #define DDR_PHY_PGCR3_RESERVED_15_DEFVAL                                           0x55AA0080
6255 #define DDR_PHY_PGCR3_RESERVED_15_SHIFT                                            15
6256 #define DDR_PHY_PGCR3_RESERVED_15_MASK                                             0x00008000U
6257
6258 /*Enable Clock Gating for AC [0] ctl_rd_clk*/
6259 #undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL
6260 #undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
6261 #undef DDR_PHY_PGCR3_GATEACRDCLK_MASK
6262 #define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL                                           0x55AA0080
6263 #define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT                                            13
6264 #define DDR_PHY_PGCR3_GATEACRDCLK_MASK                                             0x00006000U
6265
6266 /*Enable Clock Gating for AC [0] ddr_clk*/
6267 #undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL
6268 #undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
6269 #undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK
6270 #define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL                                          0x55AA0080
6271 #define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT                                           11
6272 #define DDR_PHY_PGCR3_GATEACDDRCLK_MASK                                            0x00001800U
6273
6274 /*Enable Clock Gating for AC [0] ctl_clk*/
6275 #undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL
6276 #undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
6277 #undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK
6278 #define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL                                          0x55AA0080
6279 #define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT                                           9
6280 #define DDR_PHY_PGCR3_GATEACCTLCLK_MASK                                            0x00000600U
6281
6282 /*Reserved. Return zeroes on reads.*/
6283 #undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL
6284 #undef DDR_PHY_PGCR3_RESERVED_8_SHIFT
6285 #undef DDR_PHY_PGCR3_RESERVED_8_MASK
6286 #define DDR_PHY_PGCR3_RESERVED_8_DEFVAL                                            0x55AA0080
6287 #define DDR_PHY_PGCR3_RESERVED_8_SHIFT                                             8
6288 #define DDR_PHY_PGCR3_RESERVED_8_MASK                                              0x00000100U
6289
6290 /*Controls DDL Bypass Modes*/
6291 #undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL
6292 #undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
6293 #undef DDR_PHY_PGCR3_DDLBYPMODE_MASK
6294 #define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL                                            0x55AA0080
6295 #define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT                                             6
6296 #define DDR_PHY_PGCR3_DDLBYPMODE_MASK                                              0x000000C0U
6297
6298 /*IO Loop-Back Select*/
6299 #undef DDR_PHY_PGCR3_IOLB_DEFVAL
6300 #undef DDR_PHY_PGCR3_IOLB_SHIFT
6301 #undef DDR_PHY_PGCR3_IOLB_MASK
6302 #define DDR_PHY_PGCR3_IOLB_DEFVAL                                                  0x55AA0080
6303 #define DDR_PHY_PGCR3_IOLB_SHIFT                                                   5
6304 #define DDR_PHY_PGCR3_IOLB_MASK                                                    0x00000020U
6305
6306 /*AC Receive FIFO Read Mode*/
6307 #undef DDR_PHY_PGCR3_RDMODE_DEFVAL
6308 #undef DDR_PHY_PGCR3_RDMODE_SHIFT
6309 #undef DDR_PHY_PGCR3_RDMODE_MASK
6310 #define DDR_PHY_PGCR3_RDMODE_DEFVAL                                                0x55AA0080
6311 #define DDR_PHY_PGCR3_RDMODE_SHIFT                                                 3
6312 #define DDR_PHY_PGCR3_RDMODE_MASK                                                  0x00000018U
6313
6314 /*Read FIFO Reset Disable*/
6315 #undef DDR_PHY_PGCR3_DISRST_DEFVAL
6316 #undef DDR_PHY_PGCR3_DISRST_SHIFT
6317 #undef DDR_PHY_PGCR3_DISRST_MASK
6318 #define DDR_PHY_PGCR3_DISRST_DEFVAL                                                0x55AA0080
6319 #define DDR_PHY_PGCR3_DISRST_SHIFT                                                 2
6320 #define DDR_PHY_PGCR3_DISRST_MASK                                                  0x00000004U
6321
6322 /*Clock Level when Clock Gating*/
6323 #undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL
6324 #undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT
6325 #undef DDR_PHY_PGCR3_CLKLEVEL_MASK
6326 #define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL                                              0x55AA0080
6327 #define DDR_PHY_PGCR3_CLKLEVEL_SHIFT                                               0
6328 #define DDR_PHY_PGCR3_CLKLEVEL_MASK                                                0x00000003U
6329
6330 /*Frequency B Ratio Term*/
6331 #undef DDR_PHY_PGCR5_FRQBT_DEFVAL
6332 #undef DDR_PHY_PGCR5_FRQBT_SHIFT
6333 #undef DDR_PHY_PGCR5_FRQBT_MASK
6334 #define DDR_PHY_PGCR5_FRQBT_DEFVAL                                                 0x01010000
6335 #define DDR_PHY_PGCR5_FRQBT_SHIFT                                                  24
6336 #define DDR_PHY_PGCR5_FRQBT_MASK                                                   0xFF000000U
6337
6338 /*Frequency A Ratio Term*/
6339 #undef DDR_PHY_PGCR5_FRQAT_DEFVAL
6340 #undef DDR_PHY_PGCR5_FRQAT_SHIFT
6341 #undef DDR_PHY_PGCR5_FRQAT_MASK
6342 #define DDR_PHY_PGCR5_FRQAT_DEFVAL                                                 0x01010000
6343 #define DDR_PHY_PGCR5_FRQAT_SHIFT                                                  16
6344 #define DDR_PHY_PGCR5_FRQAT_MASK                                                   0x00FF0000U
6345
6346 /*DFI Disconnect Time Period*/
6347 #undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL
6348 #undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
6349 #undef DDR_PHY_PGCR5_DISCNPERIOD_MASK
6350 #define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL                                           0x01010000
6351 #define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT                                            8
6352 #define DDR_PHY_PGCR5_DISCNPERIOD_MASK                                             0x0000FF00U
6353
6354 /*Receiver bias core side control*/
6355 #undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL
6356 #undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
6357 #undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK
6358 #define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL                                           0x01010000
6359 #define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT                                            4
6360 #define DDR_PHY_PGCR5_VREF_RBCTRL_MASK                                             0x000000F0U
6361
6362 /*Reserved. Return zeroes on reads.*/
6363 #undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL
6364 #undef DDR_PHY_PGCR5_RESERVED_3_SHIFT
6365 #undef DDR_PHY_PGCR5_RESERVED_3_MASK
6366 #define DDR_PHY_PGCR5_RESERVED_3_DEFVAL                                            0x01010000
6367 #define DDR_PHY_PGCR5_RESERVED_3_SHIFT                                             3
6368 #define DDR_PHY_PGCR5_RESERVED_3_MASK                                              0x00000008U
6369
6370 /*Internal VREF generator REFSEL ragne select*/
6371 #undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL
6372 #undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
6373 #undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK
6374 #define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL                                        0x01010000
6375 #define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT                                         2
6376 #define DDR_PHY_PGCR5_DXREFISELRANGE_MASK                                          0x00000004U
6377
6378 /*DDL Page Read Write select*/
6379 #undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL
6380 #undef DDR_PHY_PGCR5_DDLPGACT_SHIFT
6381 #undef DDR_PHY_PGCR5_DDLPGACT_MASK
6382 #define DDR_PHY_PGCR5_DDLPGACT_DEFVAL                                              0x01010000
6383 #define DDR_PHY_PGCR5_DDLPGACT_SHIFT                                               1
6384 #define DDR_PHY_PGCR5_DDLPGACT_MASK                                                0x00000002U
6385
6386 /*DDL Page Read Write select*/
6387 #undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL
6388 #undef DDR_PHY_PGCR5_DDLPGRW_SHIFT
6389 #undef DDR_PHY_PGCR5_DDLPGRW_MASK
6390 #define DDR_PHY_PGCR5_DDLPGRW_DEFVAL                                               0x01010000
6391 #define DDR_PHY_PGCR5_DDLPGRW_SHIFT                                                0
6392 #define DDR_PHY_PGCR5_DDLPGRW_MASK                                                 0x00000001U
6393
6394 /*PLL Power-Down Time*/
6395 #undef DDR_PHY_PTR0_TPLLPD_DEFVAL
6396 #undef DDR_PHY_PTR0_TPLLPD_SHIFT
6397 #undef DDR_PHY_PTR0_TPLLPD_MASK
6398 #define DDR_PHY_PTR0_TPLLPD_DEFVAL                                                 0x42C21590
6399 #define DDR_PHY_PTR0_TPLLPD_SHIFT                                                  21
6400 #define DDR_PHY_PTR0_TPLLPD_MASK                                                   0xFFE00000U
6401
6402 /*PLL Gear Shift Time*/
6403 #undef DDR_PHY_PTR0_TPLLGS_DEFVAL
6404 #undef DDR_PHY_PTR0_TPLLGS_SHIFT
6405 #undef DDR_PHY_PTR0_TPLLGS_MASK
6406 #define DDR_PHY_PTR0_TPLLGS_DEFVAL                                                 0x42C21590
6407 #define DDR_PHY_PTR0_TPLLGS_SHIFT                                                  6
6408 #define DDR_PHY_PTR0_TPLLGS_MASK                                                   0x001FFFC0U
6409
6410 /*PHY Reset Time*/
6411 #undef DDR_PHY_PTR0_TPHYRST_DEFVAL
6412 #undef DDR_PHY_PTR0_TPHYRST_SHIFT
6413 #undef DDR_PHY_PTR0_TPHYRST_MASK
6414 #define DDR_PHY_PTR0_TPHYRST_DEFVAL                                                0x42C21590
6415 #define DDR_PHY_PTR0_TPHYRST_SHIFT                                                 0
6416 #define DDR_PHY_PTR0_TPHYRST_MASK                                                  0x0000003FU
6417
6418 /*PLL Lock Time*/
6419 #undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL
6420 #undef DDR_PHY_PTR1_TPLLLOCK_SHIFT
6421 #undef DDR_PHY_PTR1_TPLLLOCK_MASK
6422 #define DDR_PHY_PTR1_TPLLLOCK_DEFVAL                                               0xD05612C0
6423 #define DDR_PHY_PTR1_TPLLLOCK_SHIFT                                                16
6424 #define DDR_PHY_PTR1_TPLLLOCK_MASK                                                 0xFFFF0000U
6425
6426 /*Reserved. Returns zeroes on reads.*/
6427 #undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL
6428 #undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT
6429 #undef DDR_PHY_PTR1_RESERVED_15_13_MASK
6430 #define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL                                         0xD05612C0
6431 #define DDR_PHY_PTR1_RESERVED_15_13_SHIFT                                          13
6432 #define DDR_PHY_PTR1_RESERVED_15_13_MASK                                           0x0000E000U
6433
6434 /*PLL Reset Time*/
6435 #undef DDR_PHY_PTR1_TPLLRST_DEFVAL
6436 #undef DDR_PHY_PTR1_TPLLRST_SHIFT
6437 #undef DDR_PHY_PTR1_TPLLRST_MASK
6438 #define DDR_PHY_PTR1_TPLLRST_DEFVAL                                                0xD05612C0
6439 #define DDR_PHY_PTR1_TPLLRST_SHIFT                                                 0
6440 #define DDR_PHY_PTR1_TPLLRST_MASK                                                  0x00001FFFU
6441
6442 /*Reserved. Return zeroes on reads.*/
6443 #undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL
6444 #undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
6445 #undef DDR_PHY_DSGCR_RESERVED_31_28_MASK
6446 #define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL                                        0x02A04101
6447 #define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT                                         28
6448 #define DDR_PHY_DSGCR_RESERVED_31_28_MASK                                          0xF0000000U
6449
6450 /*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
6451                 fault calculation.*/
6452 #undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL
6453 #undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT
6454 #undef DDR_PHY_DSGCR_RDBICLSEL_MASK
6455 #define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL                                             0x02A04101
6456 #define DDR_PHY_DSGCR_RDBICLSEL_SHIFT                                              27
6457 #define DDR_PHY_DSGCR_RDBICLSEL_MASK                                               0x08000000U
6458
6459 /*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/
6460 #undef DDR_PHY_DSGCR_RDBICL_DEFVAL
6461 #undef DDR_PHY_DSGCR_RDBICL_SHIFT
6462 #undef DDR_PHY_DSGCR_RDBICL_MASK
6463 #define DDR_PHY_DSGCR_RDBICL_DEFVAL                                                0x02A04101
6464 #define DDR_PHY_DSGCR_RDBICL_SHIFT                                                 24
6465 #define DDR_PHY_DSGCR_RDBICL_MASK                                                  0x07000000U
6466
6467 /*PHY Impedance Update Enable*/
6468 #undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL
6469 #undef DDR_PHY_DSGCR_PHYZUEN_SHIFT
6470 #undef DDR_PHY_DSGCR_PHYZUEN_MASK
6471 #define DDR_PHY_DSGCR_PHYZUEN_DEFVAL                                               0x02A04101
6472 #define DDR_PHY_DSGCR_PHYZUEN_SHIFT                                                23
6473 #define DDR_PHY_DSGCR_PHYZUEN_MASK                                                 0x00800000U
6474
6475 /*Reserved. Return zeroes on reads.*/
6476 #undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL
6477 #undef DDR_PHY_DSGCR_RESERVED_22_SHIFT
6478 #undef DDR_PHY_DSGCR_RESERVED_22_MASK
6479 #define DDR_PHY_DSGCR_RESERVED_22_DEFVAL                                           0x02A04101
6480 #define DDR_PHY_DSGCR_RESERVED_22_SHIFT                                            22
6481 #define DDR_PHY_DSGCR_RESERVED_22_MASK                                             0x00400000U
6482
6483 /*SDRAM Reset Output Enable*/
6484 #undef DDR_PHY_DSGCR_RSTOE_DEFVAL
6485 #undef DDR_PHY_DSGCR_RSTOE_SHIFT
6486 #undef DDR_PHY_DSGCR_RSTOE_MASK
6487 #define DDR_PHY_DSGCR_RSTOE_DEFVAL                                                 0x02A04101
6488 #define DDR_PHY_DSGCR_RSTOE_SHIFT                                                  21
6489 #define DDR_PHY_DSGCR_RSTOE_MASK                                                   0x00200000U
6490
6491 /*Single Data Rate Mode*/
6492 #undef DDR_PHY_DSGCR_SDRMODE_DEFVAL
6493 #undef DDR_PHY_DSGCR_SDRMODE_SHIFT
6494 #undef DDR_PHY_DSGCR_SDRMODE_MASK
6495 #define DDR_PHY_DSGCR_SDRMODE_DEFVAL                                               0x02A04101
6496 #define DDR_PHY_DSGCR_SDRMODE_SHIFT                                                19
6497 #define DDR_PHY_DSGCR_SDRMODE_MASK                                                 0x00180000U
6498
6499 /*Reserved. Return zeroes on reads.*/
6500 #undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL
6501 #undef DDR_PHY_DSGCR_RESERVED_18_SHIFT
6502 #undef DDR_PHY_DSGCR_RESERVED_18_MASK
6503 #define DDR_PHY_DSGCR_RESERVED_18_DEFVAL                                           0x02A04101
6504 #define DDR_PHY_DSGCR_RESERVED_18_SHIFT                                            18
6505 #define DDR_PHY_DSGCR_RESERVED_18_MASK                                             0x00040000U
6506
6507 /*ATO Analog Test Enable*/
6508 #undef DDR_PHY_DSGCR_ATOAE_DEFVAL
6509 #undef DDR_PHY_DSGCR_ATOAE_SHIFT
6510 #undef DDR_PHY_DSGCR_ATOAE_MASK
6511 #define DDR_PHY_DSGCR_ATOAE_DEFVAL                                                 0x02A04101
6512 #define DDR_PHY_DSGCR_ATOAE_SHIFT                                                  17
6513 #define DDR_PHY_DSGCR_ATOAE_MASK                                                   0x00020000U
6514
6515 /*DTO Output Enable*/
6516 #undef DDR_PHY_DSGCR_DTOOE_DEFVAL
6517 #undef DDR_PHY_DSGCR_DTOOE_SHIFT
6518 #undef DDR_PHY_DSGCR_DTOOE_MASK
6519 #define DDR_PHY_DSGCR_DTOOE_DEFVAL                                                 0x02A04101
6520 #define DDR_PHY_DSGCR_DTOOE_SHIFT                                                  16
6521 #define DDR_PHY_DSGCR_DTOOE_MASK                                                   0x00010000U
6522
6523 /*DTO I/O Mode*/
6524 #undef DDR_PHY_DSGCR_DTOIOM_DEFVAL
6525 #undef DDR_PHY_DSGCR_DTOIOM_SHIFT
6526 #undef DDR_PHY_DSGCR_DTOIOM_MASK
6527 #define DDR_PHY_DSGCR_DTOIOM_DEFVAL                                                0x02A04101
6528 #define DDR_PHY_DSGCR_DTOIOM_SHIFT                                                 15
6529 #define DDR_PHY_DSGCR_DTOIOM_MASK                                                  0x00008000U
6530
6531 /*DTO Power Down Receiver*/
6532 #undef DDR_PHY_DSGCR_DTOPDR_DEFVAL
6533 #undef DDR_PHY_DSGCR_DTOPDR_SHIFT
6534 #undef DDR_PHY_DSGCR_DTOPDR_MASK
6535 #define DDR_PHY_DSGCR_DTOPDR_DEFVAL                                                0x02A04101
6536 #define DDR_PHY_DSGCR_DTOPDR_SHIFT                                                 14
6537 #define DDR_PHY_DSGCR_DTOPDR_MASK                                                  0x00004000U
6538
6539 /*Reserved. Return zeroes on reads*/
6540 #undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL
6541 #undef DDR_PHY_DSGCR_RESERVED_13_SHIFT
6542 #undef DDR_PHY_DSGCR_RESERVED_13_MASK
6543 #define DDR_PHY_DSGCR_RESERVED_13_DEFVAL                                           0x02A04101
6544 #define DDR_PHY_DSGCR_RESERVED_13_SHIFT                                            13
6545 #define DDR_PHY_DSGCR_RESERVED_13_MASK                                             0x00002000U
6546
6547 /*DTO On-Die Termination*/
6548 #undef DDR_PHY_DSGCR_DTOODT_DEFVAL
6549 #undef DDR_PHY_DSGCR_DTOODT_SHIFT
6550 #undef DDR_PHY_DSGCR_DTOODT_MASK
6551 #define DDR_PHY_DSGCR_DTOODT_DEFVAL                                                0x02A04101
6552 #define DDR_PHY_DSGCR_DTOODT_SHIFT                                                 12
6553 #define DDR_PHY_DSGCR_DTOODT_MASK                                                  0x00001000U
6554
6555 /*PHY Update Acknowledge Delay*/
6556 #undef DDR_PHY_DSGCR_PUAD_DEFVAL
6557 #undef DDR_PHY_DSGCR_PUAD_SHIFT
6558 #undef DDR_PHY_DSGCR_PUAD_MASK
6559 #define DDR_PHY_DSGCR_PUAD_DEFVAL                                                  0x02A04101
6560 #define DDR_PHY_DSGCR_PUAD_SHIFT                                                   6
6561 #define DDR_PHY_DSGCR_PUAD_MASK                                                    0x00000FC0U
6562
6563 /*Controller Update Acknowledge Enable*/
6564 #undef DDR_PHY_DSGCR_CUAEN_DEFVAL
6565 #undef DDR_PHY_DSGCR_CUAEN_SHIFT
6566 #undef DDR_PHY_DSGCR_CUAEN_MASK
6567 #define DDR_PHY_DSGCR_CUAEN_DEFVAL                                                 0x02A04101
6568 #define DDR_PHY_DSGCR_CUAEN_SHIFT                                                  5
6569 #define DDR_PHY_DSGCR_CUAEN_MASK                                                   0x00000020U
6570
6571 /*Reserved. Return zeroes on reads*/
6572 #undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL
6573 #undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
6574 #undef DDR_PHY_DSGCR_RESERVED_4_3_MASK
6575 #define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL                                          0x02A04101
6576 #define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT                                           3
6577 #define DDR_PHY_DSGCR_RESERVED_4_3_MASK                                            0x00000018U
6578
6579 /*Controller Impedance Update Enable*/
6580 #undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL
6581 #undef DDR_PHY_DSGCR_CTLZUEN_SHIFT
6582 #undef DDR_PHY_DSGCR_CTLZUEN_MASK
6583 #define DDR_PHY_DSGCR_CTLZUEN_DEFVAL                                               0x02A04101
6584 #define DDR_PHY_DSGCR_CTLZUEN_SHIFT                                                2
6585 #define DDR_PHY_DSGCR_CTLZUEN_MASK                                                 0x00000004U
6586
6587 /*Reserved. Return zeroes on reads*/
6588 #undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL
6589 #undef DDR_PHY_DSGCR_RESERVED_1_SHIFT
6590 #undef DDR_PHY_DSGCR_RESERVED_1_MASK
6591 #define DDR_PHY_DSGCR_RESERVED_1_DEFVAL                                            0x02A04101
6592 #define DDR_PHY_DSGCR_RESERVED_1_SHIFT                                             1
6593 #define DDR_PHY_DSGCR_RESERVED_1_MASK                                              0x00000002U
6594
6595 /*PHY Update Request Enable*/
6596 #undef DDR_PHY_DSGCR_PUREN_DEFVAL
6597 #undef DDR_PHY_DSGCR_PUREN_SHIFT
6598 #undef DDR_PHY_DSGCR_PUREN_MASK
6599 #define DDR_PHY_DSGCR_PUREN_DEFVAL                                                 0x02A04101
6600 #define DDR_PHY_DSGCR_PUREN_SHIFT                                                  0
6601 #define DDR_PHY_DSGCR_PUREN_MASK                                                   0x00000001U
6602
6603 /*DDR4 Gear Down Timing.*/
6604 #undef DDR_PHY_DCR_GEARDN_DEFVAL
6605 #undef DDR_PHY_DCR_GEARDN_SHIFT
6606 #undef DDR_PHY_DCR_GEARDN_MASK
6607 #define DDR_PHY_DCR_GEARDN_DEFVAL                                                  0x0000040D
6608 #define DDR_PHY_DCR_GEARDN_SHIFT                                                   31
6609 #define DDR_PHY_DCR_GEARDN_MASK                                                    0x80000000U
6610
6611 /*Un-used Bank Group*/
6612 #undef DDR_PHY_DCR_UBG_DEFVAL
6613 #undef DDR_PHY_DCR_UBG_SHIFT
6614 #undef DDR_PHY_DCR_UBG_MASK
6615 #define DDR_PHY_DCR_UBG_DEFVAL                                                     0x0000040D
6616 #define DDR_PHY_DCR_UBG_SHIFT                                                      30
6617 #define DDR_PHY_DCR_UBG_MASK                                                       0x40000000U
6618
6619 /*Un-buffered DIMM Address Mirroring*/
6620 #undef DDR_PHY_DCR_UDIMM_DEFVAL
6621 #undef DDR_PHY_DCR_UDIMM_SHIFT
6622 #undef DDR_PHY_DCR_UDIMM_MASK
6623 #define DDR_PHY_DCR_UDIMM_DEFVAL                                                   0x0000040D
6624 #define DDR_PHY_DCR_UDIMM_SHIFT                                                    29
6625 #define DDR_PHY_DCR_UDIMM_MASK                                                     0x20000000U
6626
6627 /*DDR 2T Timing*/
6628 #undef DDR_PHY_DCR_DDR2T_DEFVAL
6629 #undef DDR_PHY_DCR_DDR2T_SHIFT
6630 #undef DDR_PHY_DCR_DDR2T_MASK
6631 #define DDR_PHY_DCR_DDR2T_DEFVAL                                                   0x0000040D
6632 #define DDR_PHY_DCR_DDR2T_SHIFT                                                    28
6633 #define DDR_PHY_DCR_DDR2T_MASK                                                     0x10000000U
6634
6635 /*No Simultaneous Rank Access*/
6636 #undef DDR_PHY_DCR_NOSRA_DEFVAL
6637 #undef DDR_PHY_DCR_NOSRA_SHIFT
6638 #undef DDR_PHY_DCR_NOSRA_MASK
6639 #define DDR_PHY_DCR_NOSRA_DEFVAL                                                   0x0000040D
6640 #define DDR_PHY_DCR_NOSRA_SHIFT                                                    27
6641 #define DDR_PHY_DCR_NOSRA_MASK                                                     0x08000000U
6642
6643 /*Reserved. Return zeroes on reads.*/
6644 #undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL
6645 #undef DDR_PHY_DCR_RESERVED_26_18_SHIFT
6646 #undef DDR_PHY_DCR_RESERVED_26_18_MASK
6647 #define DDR_PHY_DCR_RESERVED_26_18_DEFVAL                                          0x0000040D
6648 #define DDR_PHY_DCR_RESERVED_26_18_SHIFT                                           18
6649 #define DDR_PHY_DCR_RESERVED_26_18_MASK                                            0x07FC0000U
6650
6651 /*Byte Mask*/
6652 #undef DDR_PHY_DCR_BYTEMASK_DEFVAL
6653 #undef DDR_PHY_DCR_BYTEMASK_SHIFT
6654 #undef DDR_PHY_DCR_BYTEMASK_MASK
6655 #define DDR_PHY_DCR_BYTEMASK_DEFVAL                                                0x0000040D
6656 #define DDR_PHY_DCR_BYTEMASK_SHIFT                                                 10
6657 #define DDR_PHY_DCR_BYTEMASK_MASK                                                  0x0003FC00U
6658
6659 /*DDR Type*/
6660 #undef DDR_PHY_DCR_DDRTYPE_DEFVAL
6661 #undef DDR_PHY_DCR_DDRTYPE_SHIFT
6662 #undef DDR_PHY_DCR_DDRTYPE_MASK
6663 #define DDR_PHY_DCR_DDRTYPE_DEFVAL                                                 0x0000040D
6664 #define DDR_PHY_DCR_DDRTYPE_SHIFT                                                  8
6665 #define DDR_PHY_DCR_DDRTYPE_MASK                                                   0x00000300U
6666
6667 /*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/
6668 #undef DDR_PHY_DCR_MPRDQ_DEFVAL
6669 #undef DDR_PHY_DCR_MPRDQ_SHIFT
6670 #undef DDR_PHY_DCR_MPRDQ_MASK
6671 #define DDR_PHY_DCR_MPRDQ_DEFVAL                                                   0x0000040D
6672 #define DDR_PHY_DCR_MPRDQ_SHIFT                                                    7
6673 #define DDR_PHY_DCR_MPRDQ_MASK                                                     0x00000080U
6674
6675 /*Primary DQ (DDR3 Only)*/
6676 #undef DDR_PHY_DCR_PDQ_DEFVAL
6677 #undef DDR_PHY_DCR_PDQ_SHIFT
6678 #undef DDR_PHY_DCR_PDQ_MASK
6679 #define DDR_PHY_DCR_PDQ_DEFVAL                                                     0x0000040D
6680 #define DDR_PHY_DCR_PDQ_SHIFT                                                      4
6681 #define DDR_PHY_DCR_PDQ_MASK                                                       0x00000070U
6682
6683 /*DDR 8-Bank*/
6684 #undef DDR_PHY_DCR_DDR8BNK_DEFVAL
6685 #undef DDR_PHY_DCR_DDR8BNK_SHIFT
6686 #undef DDR_PHY_DCR_DDR8BNK_MASK
6687 #define DDR_PHY_DCR_DDR8BNK_DEFVAL                                                 0x0000040D
6688 #define DDR_PHY_DCR_DDR8BNK_SHIFT                                                  3
6689 #define DDR_PHY_DCR_DDR8BNK_MASK                                                   0x00000008U
6690
6691 /*DDR Mode*/
6692 #undef DDR_PHY_DCR_DDRMD_DEFVAL
6693 #undef DDR_PHY_DCR_DDRMD_SHIFT
6694 #undef DDR_PHY_DCR_DDRMD_MASK
6695 #define DDR_PHY_DCR_DDRMD_DEFVAL                                                   0x0000040D
6696 #define DDR_PHY_DCR_DDRMD_SHIFT                                                    0
6697 #define DDR_PHY_DCR_DDRMD_MASK                                                     0x00000007U
6698
6699 /*Reserved. Return zeroes on reads.*/
6700 #undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL
6701 #undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
6702 #undef DDR_PHY_DTPR0_RESERVED_31_29_MASK
6703 #define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL                                        0x105A2D08
6704 #define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT                                         29
6705 #define DDR_PHY_DTPR0_RESERVED_31_29_MASK                                          0xE0000000U
6706
6707 /*Activate to activate command delay (different banks)*/
6708 #undef DDR_PHY_DTPR0_TRRD_DEFVAL
6709 #undef DDR_PHY_DTPR0_TRRD_SHIFT
6710 #undef DDR_PHY_DTPR0_TRRD_MASK
6711 #define DDR_PHY_DTPR0_TRRD_DEFVAL                                                  0x105A2D08
6712 #define DDR_PHY_DTPR0_TRRD_SHIFT                                                   24
6713 #define DDR_PHY_DTPR0_TRRD_MASK                                                    0x1F000000U
6714
6715 /*Reserved. Return zeroes on reads.*/
6716 #undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL
6717 #undef DDR_PHY_DTPR0_RESERVED_23_SHIFT
6718 #undef DDR_PHY_DTPR0_RESERVED_23_MASK
6719 #define DDR_PHY_DTPR0_RESERVED_23_DEFVAL                                           0x105A2D08
6720 #define DDR_PHY_DTPR0_RESERVED_23_SHIFT                                            23
6721 #define DDR_PHY_DTPR0_RESERVED_23_MASK                                             0x00800000U
6722
6723 /*Activate to precharge command delay*/
6724 #undef DDR_PHY_DTPR0_TRAS_DEFVAL
6725 #undef DDR_PHY_DTPR0_TRAS_SHIFT
6726 #undef DDR_PHY_DTPR0_TRAS_MASK
6727 #define DDR_PHY_DTPR0_TRAS_DEFVAL                                                  0x105A2D08
6728 #define DDR_PHY_DTPR0_TRAS_SHIFT                                                   16
6729 #define DDR_PHY_DTPR0_TRAS_MASK                                                    0x007F0000U
6730
6731 /*Reserved. Return zeroes on reads.*/
6732 #undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL
6733 #undef DDR_PHY_DTPR0_RESERVED_15_SHIFT
6734 #undef DDR_PHY_DTPR0_RESERVED_15_MASK
6735 #define DDR_PHY_DTPR0_RESERVED_15_DEFVAL                                           0x105A2D08
6736 #define DDR_PHY_DTPR0_RESERVED_15_SHIFT                                            15
6737 #define DDR_PHY_DTPR0_RESERVED_15_MASK                                             0x00008000U
6738
6739 /*Precharge command period*/
6740 #undef DDR_PHY_DTPR0_TRP_DEFVAL
6741 #undef DDR_PHY_DTPR0_TRP_SHIFT
6742 #undef DDR_PHY_DTPR0_TRP_MASK
6743 #define DDR_PHY_DTPR0_TRP_DEFVAL                                                   0x105A2D08
6744 #define DDR_PHY_DTPR0_TRP_SHIFT                                                    8
6745 #define DDR_PHY_DTPR0_TRP_MASK                                                     0x00007F00U
6746
6747 /*Reserved. Return zeroes on reads.*/
6748 #undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL
6749 #undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
6750 #undef DDR_PHY_DTPR0_RESERVED_7_5_MASK
6751 #define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL                                          0x105A2D08
6752 #define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT                                           5
6753 #define DDR_PHY_DTPR0_RESERVED_7_5_MASK                                            0x000000E0U
6754
6755 /*Internal read to precharge command delay*/
6756 #undef DDR_PHY_DTPR0_TRTP_DEFVAL
6757 #undef DDR_PHY_DTPR0_TRTP_SHIFT
6758 #undef DDR_PHY_DTPR0_TRTP_MASK
6759 #define DDR_PHY_DTPR0_TRTP_DEFVAL                                                  0x105A2D08
6760 #define DDR_PHY_DTPR0_TRTP_SHIFT                                                   0
6761 #define DDR_PHY_DTPR0_TRTP_MASK                                                    0x0000001FU
6762
6763 /*Reserved. Return zeroes on reads.*/
6764 #undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL
6765 #undef DDR_PHY_DTPR1_RESERVED_31_SHIFT
6766 #undef DDR_PHY_DTPR1_RESERVED_31_MASK
6767 #define DDR_PHY_DTPR1_RESERVED_31_DEFVAL                                           0x5656041E
6768 #define DDR_PHY_DTPR1_RESERVED_31_SHIFT                                            31
6769 #define DDR_PHY_DTPR1_RESERVED_31_MASK                                             0x80000000U
6770
6771 /*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/
6772 #undef DDR_PHY_DTPR1_TWLMRD_DEFVAL
6773 #undef DDR_PHY_DTPR1_TWLMRD_SHIFT
6774 #undef DDR_PHY_DTPR1_TWLMRD_MASK
6775 #define DDR_PHY_DTPR1_TWLMRD_DEFVAL                                                0x5656041E
6776 #define DDR_PHY_DTPR1_TWLMRD_SHIFT                                                 24
6777 #define DDR_PHY_DTPR1_TWLMRD_MASK                                                  0x7F000000U
6778
6779 /*Reserved. Return zeroes on reads.*/
6780 #undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL
6781 #undef DDR_PHY_DTPR1_RESERVED_23_SHIFT
6782 #undef DDR_PHY_DTPR1_RESERVED_23_MASK
6783 #define DDR_PHY_DTPR1_RESERVED_23_DEFVAL                                           0x5656041E
6784 #define DDR_PHY_DTPR1_RESERVED_23_SHIFT                                            23
6785 #define DDR_PHY_DTPR1_RESERVED_23_MASK                                             0x00800000U
6786
6787 /*4-bank activate period*/
6788 #undef DDR_PHY_DTPR1_TFAW_DEFVAL
6789 #undef DDR_PHY_DTPR1_TFAW_SHIFT
6790 #undef DDR_PHY_DTPR1_TFAW_MASK
6791 #define DDR_PHY_DTPR1_TFAW_DEFVAL                                                  0x5656041E
6792 #define DDR_PHY_DTPR1_TFAW_SHIFT                                                   16
6793 #define DDR_PHY_DTPR1_TFAW_MASK                                                    0x007F0000U
6794
6795 /*Reserved. Return zeroes on reads.*/
6796 #undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL
6797 #undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
6798 #undef DDR_PHY_DTPR1_RESERVED_15_11_MASK
6799 #define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL                                        0x5656041E
6800 #define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT                                         11
6801 #define DDR_PHY_DTPR1_RESERVED_15_11_MASK                                          0x0000F800U
6802
6803 /*Load mode update delay (DDR4 and DDR3 only)*/
6804 #undef DDR_PHY_DTPR1_TMOD_DEFVAL
6805 #undef DDR_PHY_DTPR1_TMOD_SHIFT
6806 #undef DDR_PHY_DTPR1_TMOD_MASK
6807 #define DDR_PHY_DTPR1_TMOD_DEFVAL                                                  0x5656041E
6808 #define DDR_PHY_DTPR1_TMOD_SHIFT                                                   8
6809 #define DDR_PHY_DTPR1_TMOD_MASK                                                    0x00000700U
6810
6811 /*Reserved. Return zeroes on reads.*/
6812 #undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL
6813 #undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
6814 #undef DDR_PHY_DTPR1_RESERVED_7_5_MASK
6815 #define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL                                          0x5656041E
6816 #define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT                                           5
6817 #define DDR_PHY_DTPR1_RESERVED_7_5_MASK                                            0x000000E0U
6818
6819 /*Load mode cycle time*/
6820 #undef DDR_PHY_DTPR1_TMRD_DEFVAL
6821 #undef DDR_PHY_DTPR1_TMRD_SHIFT
6822 #undef DDR_PHY_DTPR1_TMRD_MASK
6823 #define DDR_PHY_DTPR1_TMRD_DEFVAL                                                  0x5656041E
6824 #define DDR_PHY_DTPR1_TMRD_SHIFT                                                   0
6825 #define DDR_PHY_DTPR1_TMRD_MASK                                                    0x0000001FU
6826
6827 /*Reserved. Return zeroes on reads.*/
6828 #undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL
6829 #undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
6830 #undef DDR_PHY_DTPR2_RESERVED_31_29_MASK
6831 #define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL                                        0x000B01D0
6832 #define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT                                         29
6833 #define DDR_PHY_DTPR2_RESERVED_31_29_MASK                                          0xE0000000U
6834
6835 /*Read to Write command delay. Valid values are*/
6836 #undef DDR_PHY_DTPR2_TRTW_DEFVAL
6837 #undef DDR_PHY_DTPR2_TRTW_SHIFT
6838 #undef DDR_PHY_DTPR2_TRTW_MASK
6839 #define DDR_PHY_DTPR2_TRTW_DEFVAL                                                  0x000B01D0
6840 #define DDR_PHY_DTPR2_TRTW_SHIFT                                                   28
6841 #define DDR_PHY_DTPR2_TRTW_MASK                                                    0x10000000U
6842
6843 /*Reserved. Return zeroes on reads.*/
6844 #undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL
6845 #undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
6846 #undef DDR_PHY_DTPR2_RESERVED_27_25_MASK
6847 #define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL                                        0x000B01D0
6848 #define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT                                         25
6849 #define DDR_PHY_DTPR2_RESERVED_27_25_MASK                                          0x0E000000U
6850
6851 /*Read to ODT delay (DDR3 only)*/
6852 #undef DDR_PHY_DTPR2_TRTODT_DEFVAL
6853 #undef DDR_PHY_DTPR2_TRTODT_SHIFT
6854 #undef DDR_PHY_DTPR2_TRTODT_MASK
6855 #define DDR_PHY_DTPR2_TRTODT_DEFVAL                                                0x000B01D0
6856 #define DDR_PHY_DTPR2_TRTODT_SHIFT                                                 24
6857 #define DDR_PHY_DTPR2_TRTODT_MASK                                                  0x01000000U
6858
6859 /*Reserved. Return zeroes on reads.*/
6860 #undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL
6861 #undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
6862 #undef DDR_PHY_DTPR2_RESERVED_23_20_MASK
6863 #define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL                                        0x000B01D0
6864 #define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT                                         20
6865 #define DDR_PHY_DTPR2_RESERVED_23_20_MASK                                          0x00F00000U
6866
6867 /*CKE minimum pulse width*/
6868 #undef DDR_PHY_DTPR2_TCKE_DEFVAL
6869 #undef DDR_PHY_DTPR2_TCKE_SHIFT
6870 #undef DDR_PHY_DTPR2_TCKE_MASK
6871 #define DDR_PHY_DTPR2_TCKE_DEFVAL                                                  0x000B01D0
6872 #define DDR_PHY_DTPR2_TCKE_SHIFT                                                   16
6873 #define DDR_PHY_DTPR2_TCKE_MASK                                                    0x000F0000U
6874
6875 /*Reserved. Return zeroes on reads.*/
6876 #undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL
6877 #undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
6878 #undef DDR_PHY_DTPR2_RESERVED_15_10_MASK
6879 #define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL                                        0x000B01D0
6880 #define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT                                         10
6881 #define DDR_PHY_DTPR2_RESERVED_15_10_MASK                                          0x0000FC00U
6882
6883 /*Self refresh exit delay*/
6884 #undef DDR_PHY_DTPR2_TXS_DEFVAL
6885 #undef DDR_PHY_DTPR2_TXS_SHIFT
6886 #undef DDR_PHY_DTPR2_TXS_MASK
6887 #define DDR_PHY_DTPR2_TXS_DEFVAL                                                   0x000B01D0
6888 #define DDR_PHY_DTPR2_TXS_SHIFT                                                    0
6889 #define DDR_PHY_DTPR2_TXS_MASK                                                     0x000003FFU
6890
6891 /*ODT turn-off delay extension*/
6892 #undef DDR_PHY_DTPR3_TOFDX_DEFVAL
6893 #undef DDR_PHY_DTPR3_TOFDX_SHIFT
6894 #undef DDR_PHY_DTPR3_TOFDX_MASK
6895 #define DDR_PHY_DTPR3_TOFDX_DEFVAL                                                 0x02000804
6896 #define DDR_PHY_DTPR3_TOFDX_SHIFT                                                  29
6897 #define DDR_PHY_DTPR3_TOFDX_MASK                                                   0xE0000000U
6898
6899 /*Read to read and write to write command delay*/
6900 #undef DDR_PHY_DTPR3_TCCD_DEFVAL
6901 #undef DDR_PHY_DTPR3_TCCD_SHIFT
6902 #undef DDR_PHY_DTPR3_TCCD_MASK
6903 #define DDR_PHY_DTPR3_TCCD_DEFVAL                                                  0x02000804
6904 #define DDR_PHY_DTPR3_TCCD_SHIFT                                                   26
6905 #define DDR_PHY_DTPR3_TCCD_MASK                                                    0x1C000000U
6906
6907 /*DLL locking time*/
6908 #undef DDR_PHY_DTPR3_TDLLK_DEFVAL
6909 #undef DDR_PHY_DTPR3_TDLLK_SHIFT
6910 #undef DDR_PHY_DTPR3_TDLLK_MASK
6911 #define DDR_PHY_DTPR3_TDLLK_DEFVAL                                                 0x02000804
6912 #define DDR_PHY_DTPR3_TDLLK_SHIFT                                                  16
6913 #define DDR_PHY_DTPR3_TDLLK_MASK                                                   0x03FF0000U
6914
6915 /*Reserved. Return zeroes on reads.*/
6916 #undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL
6917 #undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
6918 #undef DDR_PHY_DTPR3_RESERVED_15_12_MASK
6919 #define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL                                        0x02000804
6920 #define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT                                         12
6921 #define DDR_PHY_DTPR3_RESERVED_15_12_MASK                                          0x0000F000U
6922
6923 /*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/
6924 #undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL
6925 #undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
6926 #undef DDR_PHY_DTPR3_TDQSCKMAX_MASK
6927 #define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL                                             0x02000804
6928 #define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT                                              8
6929 #define DDR_PHY_DTPR3_TDQSCKMAX_MASK                                               0x00000F00U
6930
6931 /*Reserved. Return zeroes on reads.*/
6932 #undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL
6933 #undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
6934 #undef DDR_PHY_DTPR3_RESERVED_7_3_MASK
6935 #define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL                                          0x02000804
6936 #define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT                                           3
6937 #define DDR_PHY_DTPR3_RESERVED_7_3_MASK                                            0x000000F8U
6938
6939 /*DQS output access time from CK/CK# (LPDDR2/3 only)*/
6940 #undef DDR_PHY_DTPR3_TDQSCK_DEFVAL
6941 #undef DDR_PHY_DTPR3_TDQSCK_SHIFT
6942 #undef DDR_PHY_DTPR3_TDQSCK_MASK
6943 #define DDR_PHY_DTPR3_TDQSCK_DEFVAL                                                0x02000804
6944 #define DDR_PHY_DTPR3_TDQSCK_SHIFT                                                 0
6945 #define DDR_PHY_DTPR3_TDQSCK_MASK                                                  0x00000007U
6946
6947 /*Reserved. Return zeroes on reads.*/
6948 #undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL
6949 #undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
6950 #undef DDR_PHY_DTPR4_RESERVED_31_30_MASK
6951 #define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL                                        0x01C02B10
6952 #define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT                                         30
6953 #define DDR_PHY_DTPR4_RESERVED_31_30_MASK                                          0xC0000000U
6954
6955 /*ODT turn-on/turn-off delays (DDR2 only)*/
6956 #undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL
6957 #undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
6958 #undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK
6959 #define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL                                           0x01C02B10
6960 #define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT                                            28
6961 #define DDR_PHY_DTPR4_TAOND_TAOFD_MASK                                             0x30000000U
6962
6963 /*Reserved. Return zeroes on reads.*/
6964 #undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL
6965 #undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
6966 #undef DDR_PHY_DTPR4_RESERVED_27_26_MASK
6967 #define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL                                        0x01C02B10
6968 #define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT                                         26
6969 #define DDR_PHY_DTPR4_RESERVED_27_26_MASK                                          0x0C000000U
6970
6971 /*Refresh-to-Refresh*/
6972 #undef DDR_PHY_DTPR4_TRFC_DEFVAL
6973 #undef DDR_PHY_DTPR4_TRFC_SHIFT
6974 #undef DDR_PHY_DTPR4_TRFC_MASK
6975 #define DDR_PHY_DTPR4_TRFC_DEFVAL                                                  0x01C02B10
6976 #define DDR_PHY_DTPR4_TRFC_SHIFT                                                   16
6977 #define DDR_PHY_DTPR4_TRFC_MASK                                                    0x03FF0000U
6978
6979 /*Reserved. Return zeroes on reads.*/
6980 #undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL
6981 #undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
6982 #undef DDR_PHY_DTPR4_RESERVED_15_14_MASK
6983 #define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL                                        0x01C02B10
6984 #define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT                                         14
6985 #define DDR_PHY_DTPR4_RESERVED_15_14_MASK                                          0x0000C000U
6986
6987 /*Write leveling output delay*/
6988 #undef DDR_PHY_DTPR4_TWLO_DEFVAL
6989 #undef DDR_PHY_DTPR4_TWLO_SHIFT
6990 #undef DDR_PHY_DTPR4_TWLO_MASK
6991 #define DDR_PHY_DTPR4_TWLO_DEFVAL                                                  0x01C02B10
6992 #define DDR_PHY_DTPR4_TWLO_SHIFT                                                   8
6993 #define DDR_PHY_DTPR4_TWLO_MASK                                                    0x00003F00U
6994
6995 /*Reserved. Return zeroes on reads.*/
6996 #undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL
6997 #undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
6998 #undef DDR_PHY_DTPR4_RESERVED_7_5_MASK
6999 #define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL                                          0x01C02B10
7000 #define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT                                           5
7001 #define DDR_PHY_DTPR4_RESERVED_7_5_MASK                                            0x000000E0U
7002
7003 /*Power down exit delay*/
7004 #undef DDR_PHY_DTPR4_TXP_DEFVAL
7005 #undef DDR_PHY_DTPR4_TXP_SHIFT
7006 #undef DDR_PHY_DTPR4_TXP_MASK
7007 #define DDR_PHY_DTPR4_TXP_DEFVAL                                                   0x01C02B10
7008 #define DDR_PHY_DTPR4_TXP_SHIFT                                                    0
7009 #define DDR_PHY_DTPR4_TXP_MASK                                                     0x0000001FU
7010
7011 /*Reserved. Return zeroes on reads.*/
7012 #undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL
7013 #undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
7014 #undef DDR_PHY_DTPR5_RESERVED_31_24_MASK
7015 #define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL                                        0x00872716
7016 #define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT                                         24
7017 #define DDR_PHY_DTPR5_RESERVED_31_24_MASK                                          0xFF000000U
7018
7019 /*Activate to activate command delay (same bank)*/
7020 #undef DDR_PHY_DTPR5_TRC_DEFVAL
7021 #undef DDR_PHY_DTPR5_TRC_SHIFT
7022 #undef DDR_PHY_DTPR5_TRC_MASK
7023 #define DDR_PHY_DTPR5_TRC_DEFVAL                                                   0x00872716
7024 #define DDR_PHY_DTPR5_TRC_SHIFT                                                    16
7025 #define DDR_PHY_DTPR5_TRC_MASK                                                     0x00FF0000U
7026
7027 /*Reserved. Return zeroes on reads.*/
7028 #undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL
7029 #undef DDR_PHY_DTPR5_RESERVED_15_SHIFT
7030 #undef DDR_PHY_DTPR5_RESERVED_15_MASK
7031 #define DDR_PHY_DTPR5_RESERVED_15_DEFVAL                                           0x00872716
7032 #define DDR_PHY_DTPR5_RESERVED_15_SHIFT                                            15
7033 #define DDR_PHY_DTPR5_RESERVED_15_MASK                                             0x00008000U
7034
7035 /*Activate to read or write delay*/
7036 #undef DDR_PHY_DTPR5_TRCD_DEFVAL
7037 #undef DDR_PHY_DTPR5_TRCD_SHIFT
7038 #undef DDR_PHY_DTPR5_TRCD_MASK
7039 #define DDR_PHY_DTPR5_TRCD_DEFVAL                                                  0x00872716
7040 #define DDR_PHY_DTPR5_TRCD_SHIFT                                                   8
7041 #define DDR_PHY_DTPR5_TRCD_MASK                                                    0x00007F00U
7042
7043 /*Reserved. Return zeroes on reads.*/
7044 #undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL
7045 #undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
7046 #undef DDR_PHY_DTPR5_RESERVED_7_5_MASK
7047 #define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL                                          0x00872716
7048 #define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT                                           5
7049 #define DDR_PHY_DTPR5_RESERVED_7_5_MASK                                            0x000000E0U
7050
7051 /*Internal write to read command delay*/
7052 #undef DDR_PHY_DTPR5_TWTR_DEFVAL
7053 #undef DDR_PHY_DTPR5_TWTR_SHIFT
7054 #undef DDR_PHY_DTPR5_TWTR_MASK
7055 #define DDR_PHY_DTPR5_TWTR_DEFVAL                                                  0x00872716
7056 #define DDR_PHY_DTPR5_TWTR_SHIFT                                                   0
7057 #define DDR_PHY_DTPR5_TWTR_MASK                                                    0x0000001FU
7058
7059 /*PUB Write Latency Enable*/
7060 #undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL
7061 #undef DDR_PHY_DTPR6_PUBWLEN_SHIFT
7062 #undef DDR_PHY_DTPR6_PUBWLEN_MASK
7063 #define DDR_PHY_DTPR6_PUBWLEN_DEFVAL                                               0x00000505
7064 #define DDR_PHY_DTPR6_PUBWLEN_SHIFT                                                31
7065 #define DDR_PHY_DTPR6_PUBWLEN_MASK                                                 0x80000000U
7066
7067 /*PUB Read Latency Enable*/
7068 #undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL
7069 #undef DDR_PHY_DTPR6_PUBRLEN_SHIFT
7070 #undef DDR_PHY_DTPR6_PUBRLEN_MASK
7071 #define DDR_PHY_DTPR6_PUBRLEN_DEFVAL                                               0x00000505
7072 #define DDR_PHY_DTPR6_PUBRLEN_SHIFT                                                30
7073 #define DDR_PHY_DTPR6_PUBRLEN_MASK                                                 0x40000000U
7074
7075 /*Reserved. Return zeroes on reads.*/
7076 #undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL
7077 #undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
7078 #undef DDR_PHY_DTPR6_RESERVED_29_14_MASK
7079 #define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL                                        0x00000505
7080 #define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT                                         14
7081 #define DDR_PHY_DTPR6_RESERVED_29_14_MASK                                          0x3FFFC000U
7082
7083 /*Write Latency*/
7084 #undef DDR_PHY_DTPR6_PUBWL_DEFVAL
7085 #undef DDR_PHY_DTPR6_PUBWL_SHIFT
7086 #undef DDR_PHY_DTPR6_PUBWL_MASK
7087 #define DDR_PHY_DTPR6_PUBWL_DEFVAL                                                 0x00000505
7088 #define DDR_PHY_DTPR6_PUBWL_SHIFT                                                  8
7089 #define DDR_PHY_DTPR6_PUBWL_MASK                                                   0x00003F00U
7090
7091 /*Reserved. Return zeroes on reads.*/
7092 #undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL
7093 #undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
7094 #undef DDR_PHY_DTPR6_RESERVED_7_6_MASK
7095 #define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL                                          0x00000505
7096 #define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT                                           6
7097 #define DDR_PHY_DTPR6_RESERVED_7_6_MASK                                            0x000000C0U
7098
7099 /*Read Latency*/
7100 #undef DDR_PHY_DTPR6_PUBRL_DEFVAL
7101 #undef DDR_PHY_DTPR6_PUBRL_SHIFT
7102 #undef DDR_PHY_DTPR6_PUBRL_MASK
7103 #define DDR_PHY_DTPR6_PUBRL_DEFVAL                                                 0x00000505
7104 #define DDR_PHY_DTPR6_PUBRL_SHIFT                                                  0
7105 #define DDR_PHY_DTPR6_PUBRL_MASK                                                   0x0000003FU
7106
7107 /*Reserved. Return zeroes on reads.*/
7108 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL
7109 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
7110 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK
7111 #define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL                                       0x08400020
7112 #define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT                                        31
7113 #define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK                                         0x80000000U
7114
7115 /*RDMIMM Quad CS Enable*/
7116 #undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL
7117 #undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
7118 #undef DDR_PHY_RDIMMGCR0_QCSEN_MASK
7119 #define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL                                             0x08400020
7120 #define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT                                              30
7121 #define DDR_PHY_RDIMMGCR0_QCSEN_MASK                                               0x40000000U
7122
7123 /*Reserved. Return zeroes on reads.*/
7124 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL
7125 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
7126 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK
7127 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL                                    0x08400020
7128 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT                                     28
7129 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK                                      0x30000000U
7130
7131 /*RDIMM Outputs I/O Mode*/
7132 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL
7133 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
7134 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK
7135 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL                                          0x08400020
7136 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT                                           27
7137 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK                                            0x08000000U
7138
7139 /*Reserved. Return zeroes on reads.*/
7140 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL
7141 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
7142 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK
7143 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL                                    0x08400020
7144 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT                                     24
7145 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK                                      0x07000000U
7146
7147 /*ERROUT# Output Enable*/
7148 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL
7149 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
7150 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK
7151 #define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL                                          0x08400020
7152 #define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT                                           23
7153 #define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK                                            0x00800000U
7154
7155 /*ERROUT# I/O Mode*/
7156 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL
7157 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
7158 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK
7159 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL                                         0x08400020
7160 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT                                          22
7161 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK                                           0x00400000U
7162
7163 /*ERROUT# Power Down Receiver*/
7164 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL
7165 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
7166 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK
7167 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL                                         0x08400020
7168 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT                                          21
7169 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK                                           0x00200000U
7170
7171 /*Reserved. Return zeroes on reads.*/
7172 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL
7173 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
7174 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK
7175 #define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL                                       0x08400020
7176 #define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT                                        20
7177 #define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK                                         0x00100000U
7178
7179 /*ERROUT# On-Die Termination*/
7180 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL
7181 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
7182 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK
7183 #define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL                                         0x08400020
7184 #define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT                                          19
7185 #define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK                                           0x00080000U
7186
7187 /*Load Reduced DIMM*/
7188 #undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL
7189 #undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
7190 #undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK
7191 #define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL                                            0x08400020
7192 #define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT                                             18
7193 #define DDR_PHY_RDIMMGCR0_LRDIMM_MASK                                              0x00040000U
7194
7195 /*PAR_IN I/O Mode*/
7196 #undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL
7197 #undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
7198 #undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK
7199 #define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL                                          0x08400020
7200 #define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT                                           17
7201 #define DDR_PHY_RDIMMGCR0_PARINIOM_MASK                                            0x00020000U
7202
7203 /*Reserved. Return zeroes on reads.*/
7204 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL
7205 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
7206 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK
7207 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL                                     0x08400020
7208 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT                                      8
7209 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK                                       0x0001FF00U
7210
7211 /*Reserved. Return zeroes on reads.*/
7212 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL
7213 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
7214 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK
7215 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL                                     0x08400020
7216 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT                                      6
7217 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK                                       0x000000C0U
7218
7219 /*Rank Mirror Enable.*/
7220 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL
7221 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
7222 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK
7223 #define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL                                          0x08400020
7224 #define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT                                           4
7225 #define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK                                            0x00000030U
7226
7227 /*Reserved. Return zeroes on reads.*/
7228 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL
7229 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
7230 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK
7231 #define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL                                        0x08400020
7232 #define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT                                         3
7233 #define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK                                          0x00000008U
7234
7235 /*Stop on Parity Error*/
7236 #undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL
7237 #undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
7238 #undef DDR_PHY_RDIMMGCR0_SOPERR_MASK
7239 #define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL                                            0x08400020
7240 #define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT                                             2
7241 #define DDR_PHY_RDIMMGCR0_SOPERR_MASK                                              0x00000004U
7242
7243 /*Parity Error No Registering*/
7244 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL
7245 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
7246 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK
7247 #define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL                                          0x08400020
7248 #define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT                                           1
7249 #define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK                                            0x00000002U
7250
7251 /*Registered DIMM*/
7252 #undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL
7253 #undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
7254 #undef DDR_PHY_RDIMMGCR0_RDIMM_MASK
7255 #define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL                                             0x08400020
7256 #define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT                                              0
7257 #define DDR_PHY_RDIMMGCR0_RDIMM_MASK                                               0x00000001U
7258
7259 /*Reserved. Return zeroes on reads.*/
7260 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL
7261 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
7262 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK
7263 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL                                    0x00000C80
7264 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT                                     29
7265 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK                                      0xE0000000U
7266
7267 /*Address [17] B-side Inversion Disable*/
7268 #undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL
7269 #undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT
7270 #undef DDR_PHY_RDIMMGCR1_A17BID_MASK
7271 #define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL                                            0x00000C80
7272 #define DDR_PHY_RDIMMGCR1_A17BID_SHIFT                                             28
7273 #define DDR_PHY_RDIMMGCR1_A17BID_MASK                                              0x10000000U
7274
7275 /*Reserved. Return zeroes on reads.*/
7276 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL
7277 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
7278 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK
7279 #define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL                                       0x00000C80
7280 #define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT                                        27
7281 #define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK                                         0x08000000U
7282
7283 /*Command word to command word programming delay*/
7284 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL
7285 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
7286 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK
7287 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL                                         0x00000C80
7288 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT                                          24
7289 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK                                           0x07000000U
7290
7291 /*Reserved. Return zeroes on reads.*/
7292 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL
7293 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
7294 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK
7295 #define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL                                       0x00000C80
7296 #define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT                                        23
7297 #define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK                                         0x00800000U
7298
7299 /*Command word to command word programming delay*/
7300 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL
7301 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
7302 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK
7303 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL                                          0x00000C80
7304 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT                                           20
7305 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK                                            0x00700000U
7306
7307 /*Reserved. Return zeroes on reads.*/
7308 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL
7309 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
7310 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK
7311 #define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL                                       0x00000C80
7312 #define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT                                        19
7313 #define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK                                         0x00080000U
7314
7315 /*Command word to command word programming delay*/
7316 #undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL
7317 #undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
7318 #undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK
7319 #define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL                                            0x00000C80
7320 #define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT                                             16
7321 #define DDR_PHY_RDIMMGCR1_TBCMRD_MASK                                              0x00070000U
7322
7323 /*Reserved. Return zeroes on reads.*/
7324 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL
7325 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
7326 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK
7327 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL                                    0x00000C80
7328 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT                                     14
7329 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK                                      0x0000C000U
7330
7331 /*Stabilization time*/
7332 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL
7333 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
7334 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK
7335 #define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL                                           0x00000C80
7336 #define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT                                            0
7337 #define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK                                             0x00003FFFU
7338
7339 /*DDR4/DDR3 Control Word 7*/
7340 #undef DDR_PHY_RDIMMCR0_RC7_DEFVAL
7341 #undef DDR_PHY_RDIMMCR0_RC7_SHIFT
7342 #undef DDR_PHY_RDIMMCR0_RC7_MASK
7343 #define DDR_PHY_RDIMMCR0_RC7_DEFVAL                                                0x00000000
7344 #define DDR_PHY_RDIMMCR0_RC7_SHIFT                                                 28
7345 #define DDR_PHY_RDIMMCR0_RC7_MASK                                                  0xF0000000U
7346
7347 /*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/
7348 #undef DDR_PHY_RDIMMCR0_RC6_DEFVAL
7349 #undef DDR_PHY_RDIMMCR0_RC6_SHIFT
7350 #undef DDR_PHY_RDIMMCR0_RC6_MASK
7351 #define DDR_PHY_RDIMMCR0_RC6_DEFVAL                                                0x00000000
7352 #define DDR_PHY_RDIMMCR0_RC6_SHIFT                                                 24
7353 #define DDR_PHY_RDIMMCR0_RC6_MASK                                                  0x0F000000U
7354
7355 /*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/
7356 #undef DDR_PHY_RDIMMCR0_RC5_DEFVAL
7357 #undef DDR_PHY_RDIMMCR0_RC5_SHIFT
7358 #undef DDR_PHY_RDIMMCR0_RC5_MASK
7359 #define DDR_PHY_RDIMMCR0_RC5_DEFVAL                                                0x00000000
7360 #define DDR_PHY_RDIMMCR0_RC5_SHIFT                                                 20
7361 #define DDR_PHY_RDIMMCR0_RC5_MASK                                                  0x00F00000U
7362
7363 /*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
7364                 aracteristics Control Word)*/
7365 #undef DDR_PHY_RDIMMCR0_RC4_DEFVAL
7366 #undef DDR_PHY_RDIMMCR0_RC4_SHIFT
7367 #undef DDR_PHY_RDIMMCR0_RC4_MASK
7368 #define DDR_PHY_RDIMMCR0_RC4_DEFVAL                                                0x00000000
7369 #define DDR_PHY_RDIMMCR0_RC4_SHIFT                                                 16
7370 #define DDR_PHY_RDIMMCR0_RC4_MASK                                                  0x000F0000U
7371
7372 /*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
7373                 ver Characteristrics Control Word)*/
7374 #undef DDR_PHY_RDIMMCR0_RC3_DEFVAL
7375 #undef DDR_PHY_RDIMMCR0_RC3_SHIFT
7376 #undef DDR_PHY_RDIMMCR0_RC3_MASK
7377 #define DDR_PHY_RDIMMCR0_RC3_DEFVAL                                                0x00000000
7378 #define DDR_PHY_RDIMMCR0_RC3_SHIFT                                                 12
7379 #define DDR_PHY_RDIMMCR0_RC3_MASK                                                  0x0000F000U
7380
7381 /*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/
7382 #undef DDR_PHY_RDIMMCR0_RC2_DEFVAL
7383 #undef DDR_PHY_RDIMMCR0_RC2_SHIFT
7384 #undef DDR_PHY_RDIMMCR0_RC2_MASK
7385 #define DDR_PHY_RDIMMCR0_RC2_DEFVAL                                                0x00000000
7386 #define DDR_PHY_RDIMMCR0_RC2_SHIFT                                                 8
7387 #define DDR_PHY_RDIMMCR0_RC2_MASK                                                  0x00000F00U
7388
7389 /*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/
7390 #undef DDR_PHY_RDIMMCR0_RC1_DEFVAL
7391 #undef DDR_PHY_RDIMMCR0_RC1_SHIFT
7392 #undef DDR_PHY_RDIMMCR0_RC1_MASK
7393 #define DDR_PHY_RDIMMCR0_RC1_DEFVAL                                                0x00000000
7394 #define DDR_PHY_RDIMMCR0_RC1_SHIFT                                                 4
7395 #define DDR_PHY_RDIMMCR0_RC1_MASK                                                  0x000000F0U
7396
7397 /*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/
7398 #undef DDR_PHY_RDIMMCR0_RC0_DEFVAL
7399 #undef DDR_PHY_RDIMMCR0_RC0_SHIFT
7400 #undef DDR_PHY_RDIMMCR0_RC0_MASK
7401 #define DDR_PHY_RDIMMCR0_RC0_DEFVAL                                                0x00000000
7402 #define DDR_PHY_RDIMMCR0_RC0_SHIFT                                                 0
7403 #define DDR_PHY_RDIMMCR0_RC0_MASK                                                  0x0000000FU
7404
7405 /*Control Word 15*/
7406 #undef DDR_PHY_RDIMMCR1_RC15_DEFVAL
7407 #undef DDR_PHY_RDIMMCR1_RC15_SHIFT
7408 #undef DDR_PHY_RDIMMCR1_RC15_MASK
7409 #define DDR_PHY_RDIMMCR1_RC15_DEFVAL                                               0x00000000
7410 #define DDR_PHY_RDIMMCR1_RC15_SHIFT                                                28
7411 #define DDR_PHY_RDIMMCR1_RC15_MASK                                                 0xF0000000U
7412
7413 /*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/
7414 #undef DDR_PHY_RDIMMCR1_RC14_DEFVAL
7415 #undef DDR_PHY_RDIMMCR1_RC14_SHIFT
7416 #undef DDR_PHY_RDIMMCR1_RC14_MASK
7417 #define DDR_PHY_RDIMMCR1_RC14_DEFVAL                                               0x00000000
7418 #define DDR_PHY_RDIMMCR1_RC14_SHIFT                                                24
7419 #define DDR_PHY_RDIMMCR1_RC14_MASK                                                 0x0F000000U
7420
7421 /*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/
7422 #undef DDR_PHY_RDIMMCR1_RC13_DEFVAL
7423 #undef DDR_PHY_RDIMMCR1_RC13_SHIFT
7424 #undef DDR_PHY_RDIMMCR1_RC13_MASK
7425 #define DDR_PHY_RDIMMCR1_RC13_DEFVAL                                               0x00000000
7426 #define DDR_PHY_RDIMMCR1_RC13_SHIFT                                                20
7427 #define DDR_PHY_RDIMMCR1_RC13_MASK                                                 0x00F00000U
7428
7429 /*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/
7430 #undef DDR_PHY_RDIMMCR1_RC12_DEFVAL
7431 #undef DDR_PHY_RDIMMCR1_RC12_SHIFT
7432 #undef DDR_PHY_RDIMMCR1_RC12_MASK
7433 #define DDR_PHY_RDIMMCR1_RC12_DEFVAL                                               0x00000000
7434 #define DDR_PHY_RDIMMCR1_RC12_SHIFT                                                16
7435 #define DDR_PHY_RDIMMCR1_RC12_MASK                                                 0x000F0000U
7436
7437 /*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
7438                 rol Word)*/
7439 #undef DDR_PHY_RDIMMCR1_RC11_DEFVAL
7440 #undef DDR_PHY_RDIMMCR1_RC11_SHIFT
7441 #undef DDR_PHY_RDIMMCR1_RC11_MASK
7442 #define DDR_PHY_RDIMMCR1_RC11_DEFVAL                                               0x00000000
7443 #define DDR_PHY_RDIMMCR1_RC11_SHIFT                                                12
7444 #define DDR_PHY_RDIMMCR1_RC11_MASK                                                 0x0000F000U
7445
7446 /*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/
7447 #undef DDR_PHY_RDIMMCR1_RC10_DEFVAL
7448 #undef DDR_PHY_RDIMMCR1_RC10_SHIFT
7449 #undef DDR_PHY_RDIMMCR1_RC10_MASK
7450 #define DDR_PHY_RDIMMCR1_RC10_DEFVAL                                               0x00000000
7451 #define DDR_PHY_RDIMMCR1_RC10_SHIFT                                                8
7452 #define DDR_PHY_RDIMMCR1_RC10_MASK                                                 0x00000F00U
7453
7454 /*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/
7455 #undef DDR_PHY_RDIMMCR1_RC9_DEFVAL
7456 #undef DDR_PHY_RDIMMCR1_RC9_SHIFT
7457 #undef DDR_PHY_RDIMMCR1_RC9_MASK
7458 #define DDR_PHY_RDIMMCR1_RC9_DEFVAL                                                0x00000000
7459 #define DDR_PHY_RDIMMCR1_RC9_SHIFT                                                 4
7460 #define DDR_PHY_RDIMMCR1_RC9_MASK                                                  0x000000F0U
7461
7462 /*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
7463                 Control Word)*/
7464 #undef DDR_PHY_RDIMMCR1_RC8_DEFVAL
7465 #undef DDR_PHY_RDIMMCR1_RC8_SHIFT
7466 #undef DDR_PHY_RDIMMCR1_RC8_MASK
7467 #define DDR_PHY_RDIMMCR1_RC8_DEFVAL                                                0x00000000
7468 #define DDR_PHY_RDIMMCR1_RC8_SHIFT                                                 0
7469 #define DDR_PHY_RDIMMCR1_RC8_MASK                                                  0x0000000FU
7470
7471 /*Reserved. Return zeroes on reads.*/
7472 #undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL
7473 #undef DDR_PHY_MR0_RESERVED_31_8_SHIFT
7474 #undef DDR_PHY_MR0_RESERVED_31_8_MASK
7475 #define DDR_PHY_MR0_RESERVED_31_8_DEFVAL                                           0x00000052
7476 #define DDR_PHY_MR0_RESERVED_31_8_SHIFT                                            8
7477 #define DDR_PHY_MR0_RESERVED_31_8_MASK                                             0xFFFFFF00U
7478
7479 /*CA Terminating Rank*/
7480 #undef DDR_PHY_MR0_CATR_DEFVAL
7481 #undef DDR_PHY_MR0_CATR_SHIFT
7482 #undef DDR_PHY_MR0_CATR_MASK
7483 #define DDR_PHY_MR0_CATR_DEFVAL                                                    0x00000052
7484 #define DDR_PHY_MR0_CATR_SHIFT                                                     7
7485 #define DDR_PHY_MR0_CATR_MASK                                                      0x00000080U
7486
7487 /*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7488 #undef DDR_PHY_MR0_RSVD_6_5_DEFVAL
7489 #undef DDR_PHY_MR0_RSVD_6_5_SHIFT
7490 #undef DDR_PHY_MR0_RSVD_6_5_MASK
7491 #define DDR_PHY_MR0_RSVD_6_5_DEFVAL                                                0x00000052
7492 #define DDR_PHY_MR0_RSVD_6_5_SHIFT                                                 5
7493 #define DDR_PHY_MR0_RSVD_6_5_MASK                                                  0x00000060U
7494
7495 /*Built-in Self-Test for RZQ*/
7496 #undef DDR_PHY_MR0_RZQI_DEFVAL
7497 #undef DDR_PHY_MR0_RZQI_SHIFT
7498 #undef DDR_PHY_MR0_RZQI_MASK
7499 #define DDR_PHY_MR0_RZQI_DEFVAL                                                    0x00000052
7500 #define DDR_PHY_MR0_RZQI_SHIFT                                                     3
7501 #define DDR_PHY_MR0_RZQI_MASK                                                      0x00000018U
7502
7503 /*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7504 #undef DDR_PHY_MR0_RSVD_2_0_DEFVAL
7505 #undef DDR_PHY_MR0_RSVD_2_0_SHIFT
7506 #undef DDR_PHY_MR0_RSVD_2_0_MASK
7507 #define DDR_PHY_MR0_RSVD_2_0_DEFVAL                                                0x00000052
7508 #define DDR_PHY_MR0_RSVD_2_0_SHIFT                                                 0
7509 #define DDR_PHY_MR0_RSVD_2_0_MASK                                                  0x00000007U
7510
7511 /*Reserved. Return zeroes on reads.*/
7512 #undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL
7513 #undef DDR_PHY_MR1_RESERVED_31_8_SHIFT
7514 #undef DDR_PHY_MR1_RESERVED_31_8_MASK
7515 #define DDR_PHY_MR1_RESERVED_31_8_DEFVAL                                           0x00000004
7516 #define DDR_PHY_MR1_RESERVED_31_8_SHIFT                                            8
7517 #define DDR_PHY_MR1_RESERVED_31_8_MASK                                             0xFFFFFF00U
7518
7519 /*Read Postamble Length*/
7520 #undef DDR_PHY_MR1_RDPST_DEFVAL
7521 #undef DDR_PHY_MR1_RDPST_SHIFT
7522 #undef DDR_PHY_MR1_RDPST_MASK
7523 #define DDR_PHY_MR1_RDPST_DEFVAL                                                   0x00000004
7524 #define DDR_PHY_MR1_RDPST_SHIFT                                                    7
7525 #define DDR_PHY_MR1_RDPST_MASK                                                     0x00000080U
7526
7527 /*Write-recovery for auto-precharge command*/
7528 #undef DDR_PHY_MR1_NWR_DEFVAL
7529 #undef DDR_PHY_MR1_NWR_SHIFT
7530 #undef DDR_PHY_MR1_NWR_MASK
7531 #define DDR_PHY_MR1_NWR_DEFVAL                                                     0x00000004
7532 #define DDR_PHY_MR1_NWR_SHIFT                                                      4
7533 #define DDR_PHY_MR1_NWR_MASK                                                       0x00000070U
7534
7535 /*Read Preamble Length*/
7536 #undef DDR_PHY_MR1_RDPRE_DEFVAL
7537 #undef DDR_PHY_MR1_RDPRE_SHIFT
7538 #undef DDR_PHY_MR1_RDPRE_MASK
7539 #define DDR_PHY_MR1_RDPRE_DEFVAL                                                   0x00000004
7540 #define DDR_PHY_MR1_RDPRE_SHIFT                                                    3
7541 #define DDR_PHY_MR1_RDPRE_MASK                                                     0x00000008U
7542
7543 /*Write Preamble Length*/
7544 #undef DDR_PHY_MR1_WRPRE_DEFVAL
7545 #undef DDR_PHY_MR1_WRPRE_SHIFT
7546 #undef DDR_PHY_MR1_WRPRE_MASK
7547 #define DDR_PHY_MR1_WRPRE_DEFVAL                                                   0x00000004
7548 #define DDR_PHY_MR1_WRPRE_SHIFT                                                    2
7549 #define DDR_PHY_MR1_WRPRE_MASK                                                     0x00000004U
7550
7551 /*Burst Length*/
7552 #undef DDR_PHY_MR1_BL_DEFVAL
7553 #undef DDR_PHY_MR1_BL_SHIFT
7554 #undef DDR_PHY_MR1_BL_MASK
7555 #define DDR_PHY_MR1_BL_DEFVAL                                                      0x00000004
7556 #define DDR_PHY_MR1_BL_SHIFT                                                       0
7557 #define DDR_PHY_MR1_BL_MASK                                                        0x00000003U
7558
7559 /*Reserved. Return zeroes on reads.*/
7560 #undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL
7561 #undef DDR_PHY_MR2_RESERVED_31_8_SHIFT
7562 #undef DDR_PHY_MR2_RESERVED_31_8_MASK
7563 #define DDR_PHY_MR2_RESERVED_31_8_DEFVAL                                           0x00000000
7564 #define DDR_PHY_MR2_RESERVED_31_8_SHIFT                                            8
7565 #define DDR_PHY_MR2_RESERVED_31_8_MASK                                             0xFFFFFF00U
7566
7567 /*Write Leveling*/
7568 #undef DDR_PHY_MR2_WRL_DEFVAL
7569 #undef DDR_PHY_MR2_WRL_SHIFT
7570 #undef DDR_PHY_MR2_WRL_MASK
7571 #define DDR_PHY_MR2_WRL_DEFVAL                                                     0x00000000
7572 #define DDR_PHY_MR2_WRL_SHIFT                                                      7
7573 #define DDR_PHY_MR2_WRL_MASK                                                       0x00000080U
7574
7575 /*Write Latency Set*/
7576 #undef DDR_PHY_MR2_WLS_DEFVAL
7577 #undef DDR_PHY_MR2_WLS_SHIFT
7578 #undef DDR_PHY_MR2_WLS_MASK
7579 #define DDR_PHY_MR2_WLS_DEFVAL                                                     0x00000000
7580 #define DDR_PHY_MR2_WLS_SHIFT                                                      6
7581 #define DDR_PHY_MR2_WLS_MASK                                                       0x00000040U
7582
7583 /*Write Latency*/
7584 #undef DDR_PHY_MR2_WL_DEFVAL
7585 #undef DDR_PHY_MR2_WL_SHIFT
7586 #undef DDR_PHY_MR2_WL_MASK
7587 #define DDR_PHY_MR2_WL_DEFVAL                                                      0x00000000
7588 #define DDR_PHY_MR2_WL_SHIFT                                                       3
7589 #define DDR_PHY_MR2_WL_MASK                                                        0x00000038U
7590
7591 /*Read Latency*/
7592 #undef DDR_PHY_MR2_RL_DEFVAL
7593 #undef DDR_PHY_MR2_RL_SHIFT
7594 #undef DDR_PHY_MR2_RL_MASK
7595 #define DDR_PHY_MR2_RL_DEFVAL                                                      0x00000000
7596 #define DDR_PHY_MR2_RL_SHIFT                                                       0
7597 #define DDR_PHY_MR2_RL_MASK                                                        0x00000007U
7598
7599 /*Reserved. Return zeroes on reads.*/
7600 #undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL
7601 #undef DDR_PHY_MR3_RESERVED_31_8_SHIFT
7602 #undef DDR_PHY_MR3_RESERVED_31_8_MASK
7603 #define DDR_PHY_MR3_RESERVED_31_8_DEFVAL                                           0x00000031
7604 #define DDR_PHY_MR3_RESERVED_31_8_SHIFT                                            8
7605 #define DDR_PHY_MR3_RESERVED_31_8_MASK                                             0xFFFFFF00U
7606
7607 /*DBI-Write Enable*/
7608 #undef DDR_PHY_MR3_DBIWR_DEFVAL
7609 #undef DDR_PHY_MR3_DBIWR_SHIFT
7610 #undef DDR_PHY_MR3_DBIWR_MASK
7611 #define DDR_PHY_MR3_DBIWR_DEFVAL                                                   0x00000031
7612 #define DDR_PHY_MR3_DBIWR_SHIFT                                                    7
7613 #define DDR_PHY_MR3_DBIWR_MASK                                                     0x00000080U
7614
7615 /*DBI-Read Enable*/
7616 #undef DDR_PHY_MR3_DBIRD_DEFVAL
7617 #undef DDR_PHY_MR3_DBIRD_SHIFT
7618 #undef DDR_PHY_MR3_DBIRD_MASK
7619 #define DDR_PHY_MR3_DBIRD_DEFVAL                                                   0x00000031
7620 #define DDR_PHY_MR3_DBIRD_SHIFT                                                    6
7621 #define DDR_PHY_MR3_DBIRD_MASK                                                     0x00000040U
7622
7623 /*Pull-down Drive Strength*/
7624 #undef DDR_PHY_MR3_PDDS_DEFVAL
7625 #undef DDR_PHY_MR3_PDDS_SHIFT
7626 #undef DDR_PHY_MR3_PDDS_MASK
7627 #define DDR_PHY_MR3_PDDS_DEFVAL                                                    0x00000031
7628 #define DDR_PHY_MR3_PDDS_SHIFT                                                     3
7629 #define DDR_PHY_MR3_PDDS_MASK                                                      0x00000038U
7630
7631 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7632 #undef DDR_PHY_MR3_RSVD_DEFVAL
7633 #undef DDR_PHY_MR3_RSVD_SHIFT
7634 #undef DDR_PHY_MR3_RSVD_MASK
7635 #define DDR_PHY_MR3_RSVD_DEFVAL                                                    0x00000031
7636 #define DDR_PHY_MR3_RSVD_SHIFT                                                     2
7637 #define DDR_PHY_MR3_RSVD_MASK                                                      0x00000004U
7638
7639 /*Write Postamble Length*/
7640 #undef DDR_PHY_MR3_WRPST_DEFVAL
7641 #undef DDR_PHY_MR3_WRPST_SHIFT
7642 #undef DDR_PHY_MR3_WRPST_MASK
7643 #define DDR_PHY_MR3_WRPST_DEFVAL                                                   0x00000031
7644 #define DDR_PHY_MR3_WRPST_SHIFT                                                    1
7645 #define DDR_PHY_MR3_WRPST_MASK                                                     0x00000002U
7646
7647 /*Pull-up Calibration Point*/
7648 #undef DDR_PHY_MR3_PUCAL_DEFVAL
7649 #undef DDR_PHY_MR3_PUCAL_SHIFT
7650 #undef DDR_PHY_MR3_PUCAL_MASK
7651 #define DDR_PHY_MR3_PUCAL_DEFVAL                                                   0x00000031
7652 #define DDR_PHY_MR3_PUCAL_SHIFT                                                    0
7653 #define DDR_PHY_MR3_PUCAL_MASK                                                     0x00000001U
7654
7655 /*Reserved. Return zeroes on reads.*/
7656 #undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL
7657 #undef DDR_PHY_MR4_RESERVED_31_16_SHIFT
7658 #undef DDR_PHY_MR4_RESERVED_31_16_MASK
7659 #define DDR_PHY_MR4_RESERVED_31_16_DEFVAL                                          0x00000000
7660 #define DDR_PHY_MR4_RESERVED_31_16_SHIFT                                           16
7661 #define DDR_PHY_MR4_RESERVED_31_16_MASK                                            0xFFFF0000U
7662
7663 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7664 #undef DDR_PHY_MR4_RSVD_15_13_DEFVAL
7665 #undef DDR_PHY_MR4_RSVD_15_13_SHIFT
7666 #undef DDR_PHY_MR4_RSVD_15_13_MASK
7667 #define DDR_PHY_MR4_RSVD_15_13_DEFVAL                                              0x00000000
7668 #define DDR_PHY_MR4_RSVD_15_13_SHIFT                                               13
7669 #define DDR_PHY_MR4_RSVD_15_13_MASK                                                0x0000E000U
7670
7671 /*Write Preamble*/
7672 #undef DDR_PHY_MR4_WRP_DEFVAL
7673 #undef DDR_PHY_MR4_WRP_SHIFT
7674 #undef DDR_PHY_MR4_WRP_MASK
7675 #define DDR_PHY_MR4_WRP_DEFVAL                                                     0x00000000
7676 #define DDR_PHY_MR4_WRP_SHIFT                                                      12
7677 #define DDR_PHY_MR4_WRP_MASK                                                       0x00001000U
7678
7679 /*Read Preamble*/
7680 #undef DDR_PHY_MR4_RDP_DEFVAL
7681 #undef DDR_PHY_MR4_RDP_SHIFT
7682 #undef DDR_PHY_MR4_RDP_MASK
7683 #define DDR_PHY_MR4_RDP_DEFVAL                                                     0x00000000
7684 #define DDR_PHY_MR4_RDP_SHIFT                                                      11
7685 #define DDR_PHY_MR4_RDP_MASK                                                       0x00000800U
7686
7687 /*Read Preamble Training Mode*/
7688 #undef DDR_PHY_MR4_RPTM_DEFVAL
7689 #undef DDR_PHY_MR4_RPTM_SHIFT
7690 #undef DDR_PHY_MR4_RPTM_MASK
7691 #define DDR_PHY_MR4_RPTM_DEFVAL                                                    0x00000000
7692 #define DDR_PHY_MR4_RPTM_SHIFT                                                     10
7693 #define DDR_PHY_MR4_RPTM_MASK                                                      0x00000400U
7694
7695 /*Self Refresh Abort*/
7696 #undef DDR_PHY_MR4_SRA_DEFVAL
7697 #undef DDR_PHY_MR4_SRA_SHIFT
7698 #undef DDR_PHY_MR4_SRA_MASK
7699 #define DDR_PHY_MR4_SRA_DEFVAL                                                     0x00000000
7700 #define DDR_PHY_MR4_SRA_SHIFT                                                      9
7701 #define DDR_PHY_MR4_SRA_MASK                                                       0x00000200U
7702
7703 /*CS to Command Latency Mode*/
7704 #undef DDR_PHY_MR4_CS2CMDL_DEFVAL
7705 #undef DDR_PHY_MR4_CS2CMDL_SHIFT
7706 #undef DDR_PHY_MR4_CS2CMDL_MASK
7707 #define DDR_PHY_MR4_CS2CMDL_DEFVAL                                                 0x00000000
7708 #define DDR_PHY_MR4_CS2CMDL_SHIFT                                                  6
7709 #define DDR_PHY_MR4_CS2CMDL_MASK                                                   0x000001C0U
7710
7711 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7712 #undef DDR_PHY_MR4_RSVD1_DEFVAL
7713 #undef DDR_PHY_MR4_RSVD1_SHIFT
7714 #undef DDR_PHY_MR4_RSVD1_MASK
7715 #define DDR_PHY_MR4_RSVD1_DEFVAL                                                   0x00000000
7716 #define DDR_PHY_MR4_RSVD1_SHIFT                                                    5
7717 #define DDR_PHY_MR4_RSVD1_MASK                                                     0x00000020U
7718
7719 /*Internal VREF Monitor*/
7720 #undef DDR_PHY_MR4_IVM_DEFVAL
7721 #undef DDR_PHY_MR4_IVM_SHIFT
7722 #undef DDR_PHY_MR4_IVM_MASK
7723 #define DDR_PHY_MR4_IVM_DEFVAL                                                     0x00000000
7724 #define DDR_PHY_MR4_IVM_SHIFT                                                      4
7725 #define DDR_PHY_MR4_IVM_MASK                                                       0x00000010U
7726
7727 /*Temperature Controlled Refresh Mode*/
7728 #undef DDR_PHY_MR4_TCRM_DEFVAL
7729 #undef DDR_PHY_MR4_TCRM_SHIFT
7730 #undef DDR_PHY_MR4_TCRM_MASK
7731 #define DDR_PHY_MR4_TCRM_DEFVAL                                                    0x00000000
7732 #define DDR_PHY_MR4_TCRM_SHIFT                                                     3
7733 #define DDR_PHY_MR4_TCRM_MASK                                                      0x00000008U
7734
7735 /*Temperature Controlled Refresh Range*/
7736 #undef DDR_PHY_MR4_TCRR_DEFVAL
7737 #undef DDR_PHY_MR4_TCRR_SHIFT
7738 #undef DDR_PHY_MR4_TCRR_MASK
7739 #define DDR_PHY_MR4_TCRR_DEFVAL                                                    0x00000000
7740 #define DDR_PHY_MR4_TCRR_SHIFT                                                     2
7741 #define DDR_PHY_MR4_TCRR_MASK                                                      0x00000004U
7742
7743 /*Maximum Power Down Mode*/
7744 #undef DDR_PHY_MR4_MPDM_DEFVAL
7745 #undef DDR_PHY_MR4_MPDM_SHIFT
7746 #undef DDR_PHY_MR4_MPDM_MASK
7747 #define DDR_PHY_MR4_MPDM_DEFVAL                                                    0x00000000
7748 #define DDR_PHY_MR4_MPDM_SHIFT                                                     1
7749 #define DDR_PHY_MR4_MPDM_MASK                                                      0x00000002U
7750
7751 /*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/
7752 #undef DDR_PHY_MR4_RSVD_0_DEFVAL
7753 #undef DDR_PHY_MR4_RSVD_0_SHIFT
7754 #undef DDR_PHY_MR4_RSVD_0_MASK
7755 #define DDR_PHY_MR4_RSVD_0_DEFVAL                                                  0x00000000
7756 #define DDR_PHY_MR4_RSVD_0_SHIFT                                                   0
7757 #define DDR_PHY_MR4_RSVD_0_MASK                                                    0x00000001U
7758
7759 /*Reserved. Return zeroes on reads.*/
7760 #undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL
7761 #undef DDR_PHY_MR5_RESERVED_31_16_SHIFT
7762 #undef DDR_PHY_MR5_RESERVED_31_16_MASK
7763 #define DDR_PHY_MR5_RESERVED_31_16_DEFVAL                                          0x00000000
7764 #define DDR_PHY_MR5_RESERVED_31_16_SHIFT                                           16
7765 #define DDR_PHY_MR5_RESERVED_31_16_MASK                                            0xFFFF0000U
7766
7767 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7768 #undef DDR_PHY_MR5_RSVD_DEFVAL
7769 #undef DDR_PHY_MR5_RSVD_SHIFT
7770 #undef DDR_PHY_MR5_RSVD_MASK
7771 #define DDR_PHY_MR5_RSVD_DEFVAL                                                    0x00000000
7772 #define DDR_PHY_MR5_RSVD_SHIFT                                                     13
7773 #define DDR_PHY_MR5_RSVD_MASK                                                      0x0000E000U
7774
7775 /*Read DBI*/
7776 #undef DDR_PHY_MR5_RDBI_DEFVAL
7777 #undef DDR_PHY_MR5_RDBI_SHIFT
7778 #undef DDR_PHY_MR5_RDBI_MASK
7779 #define DDR_PHY_MR5_RDBI_DEFVAL                                                    0x00000000
7780 #define DDR_PHY_MR5_RDBI_SHIFT                                                     12
7781 #define DDR_PHY_MR5_RDBI_MASK                                                      0x00001000U
7782
7783 /*Write DBI*/
7784 #undef DDR_PHY_MR5_WDBI_DEFVAL
7785 #undef DDR_PHY_MR5_WDBI_SHIFT
7786 #undef DDR_PHY_MR5_WDBI_MASK
7787 #define DDR_PHY_MR5_WDBI_DEFVAL                                                    0x00000000
7788 #define DDR_PHY_MR5_WDBI_SHIFT                                                     11
7789 #define DDR_PHY_MR5_WDBI_MASK                                                      0x00000800U
7790
7791 /*Data Mask*/
7792 #undef DDR_PHY_MR5_DM_DEFVAL
7793 #undef DDR_PHY_MR5_DM_SHIFT
7794 #undef DDR_PHY_MR5_DM_MASK
7795 #define DDR_PHY_MR5_DM_DEFVAL                                                      0x00000000
7796 #define DDR_PHY_MR5_DM_SHIFT                                                       10
7797 #define DDR_PHY_MR5_DM_MASK                                                        0x00000400U
7798
7799 /*CA Parity Persistent Error*/
7800 #undef DDR_PHY_MR5_CAPPE_DEFVAL
7801 #undef DDR_PHY_MR5_CAPPE_SHIFT
7802 #undef DDR_PHY_MR5_CAPPE_MASK
7803 #define DDR_PHY_MR5_CAPPE_DEFVAL                                                   0x00000000
7804 #define DDR_PHY_MR5_CAPPE_SHIFT                                                    9
7805 #define DDR_PHY_MR5_CAPPE_MASK                                                     0x00000200U
7806
7807 /*RTT_PARK*/
7808 #undef DDR_PHY_MR5_RTTPARK_DEFVAL
7809 #undef DDR_PHY_MR5_RTTPARK_SHIFT
7810 #undef DDR_PHY_MR5_RTTPARK_MASK
7811 #define DDR_PHY_MR5_RTTPARK_DEFVAL                                                 0x00000000
7812 #define DDR_PHY_MR5_RTTPARK_SHIFT                                                  6
7813 #define DDR_PHY_MR5_RTTPARK_MASK                                                   0x000001C0U
7814
7815 /*ODT Input Buffer during Power Down mode*/
7816 #undef DDR_PHY_MR5_ODTIBPD_DEFVAL
7817 #undef DDR_PHY_MR5_ODTIBPD_SHIFT
7818 #undef DDR_PHY_MR5_ODTIBPD_MASK
7819 #define DDR_PHY_MR5_ODTIBPD_DEFVAL                                                 0x00000000
7820 #define DDR_PHY_MR5_ODTIBPD_SHIFT                                                  5
7821 #define DDR_PHY_MR5_ODTIBPD_MASK                                                   0x00000020U
7822
7823 /*C/A Parity Error Status*/
7824 #undef DDR_PHY_MR5_CAPES_DEFVAL
7825 #undef DDR_PHY_MR5_CAPES_SHIFT
7826 #undef DDR_PHY_MR5_CAPES_MASK
7827 #define DDR_PHY_MR5_CAPES_DEFVAL                                                   0x00000000
7828 #define DDR_PHY_MR5_CAPES_SHIFT                                                    4
7829 #define DDR_PHY_MR5_CAPES_MASK                                                     0x00000010U
7830
7831 /*CRC Error Clear*/
7832 #undef DDR_PHY_MR5_CRCEC_DEFVAL
7833 #undef DDR_PHY_MR5_CRCEC_SHIFT
7834 #undef DDR_PHY_MR5_CRCEC_MASK
7835 #define DDR_PHY_MR5_CRCEC_DEFVAL                                                   0x00000000
7836 #define DDR_PHY_MR5_CRCEC_SHIFT                                                    3
7837 #define DDR_PHY_MR5_CRCEC_MASK                                                     0x00000008U
7838
7839 /*C/A Parity Latency Mode*/
7840 #undef DDR_PHY_MR5_CAPM_DEFVAL
7841 #undef DDR_PHY_MR5_CAPM_SHIFT
7842 #undef DDR_PHY_MR5_CAPM_MASK
7843 #define DDR_PHY_MR5_CAPM_DEFVAL                                                    0x00000000
7844 #define DDR_PHY_MR5_CAPM_SHIFT                                                     0
7845 #define DDR_PHY_MR5_CAPM_MASK                                                      0x00000007U
7846
7847 /*Reserved. Return zeroes on reads.*/
7848 #undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL
7849 #undef DDR_PHY_MR6_RESERVED_31_16_SHIFT
7850 #undef DDR_PHY_MR6_RESERVED_31_16_MASK
7851 #define DDR_PHY_MR6_RESERVED_31_16_DEFVAL                                          0x00000000
7852 #define DDR_PHY_MR6_RESERVED_31_16_SHIFT                                           16
7853 #define DDR_PHY_MR6_RESERVED_31_16_MASK                                            0xFFFF0000U
7854
7855 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7856 #undef DDR_PHY_MR6_RSVD_15_13_DEFVAL
7857 #undef DDR_PHY_MR6_RSVD_15_13_SHIFT
7858 #undef DDR_PHY_MR6_RSVD_15_13_MASK
7859 #define DDR_PHY_MR6_RSVD_15_13_DEFVAL                                              0x00000000
7860 #define DDR_PHY_MR6_RSVD_15_13_SHIFT                                               13
7861 #define DDR_PHY_MR6_RSVD_15_13_MASK                                                0x0000E000U
7862
7863 /*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/
7864 #undef DDR_PHY_MR6_TCCDL_DEFVAL
7865 #undef DDR_PHY_MR6_TCCDL_SHIFT
7866 #undef DDR_PHY_MR6_TCCDL_MASK
7867 #define DDR_PHY_MR6_TCCDL_DEFVAL                                                   0x00000000
7868 #define DDR_PHY_MR6_TCCDL_SHIFT                                                    10
7869 #define DDR_PHY_MR6_TCCDL_MASK                                                     0x00001C00U
7870
7871 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7872 #undef DDR_PHY_MR6_RSVD_9_8_DEFVAL
7873 #undef DDR_PHY_MR6_RSVD_9_8_SHIFT
7874 #undef DDR_PHY_MR6_RSVD_9_8_MASK
7875 #define DDR_PHY_MR6_RSVD_9_8_DEFVAL                                                0x00000000
7876 #define DDR_PHY_MR6_RSVD_9_8_SHIFT                                                 8
7877 #define DDR_PHY_MR6_RSVD_9_8_MASK                                                  0x00000300U
7878
7879 /*VrefDQ Training Enable*/
7880 #undef DDR_PHY_MR6_VDDQTEN_DEFVAL
7881 #undef DDR_PHY_MR6_VDDQTEN_SHIFT
7882 #undef DDR_PHY_MR6_VDDQTEN_MASK
7883 #define DDR_PHY_MR6_VDDQTEN_DEFVAL                                                 0x00000000
7884 #define DDR_PHY_MR6_VDDQTEN_SHIFT                                                  7
7885 #define DDR_PHY_MR6_VDDQTEN_MASK                                                   0x00000080U
7886
7887 /*VrefDQ Training Range*/
7888 #undef DDR_PHY_MR6_VDQTRG_DEFVAL
7889 #undef DDR_PHY_MR6_VDQTRG_SHIFT
7890 #undef DDR_PHY_MR6_VDQTRG_MASK
7891 #define DDR_PHY_MR6_VDQTRG_DEFVAL                                                  0x00000000
7892 #define DDR_PHY_MR6_VDQTRG_SHIFT                                                   6
7893 #define DDR_PHY_MR6_VDQTRG_MASK                                                    0x00000040U
7894
7895 /*VrefDQ Training Values*/
7896 #undef DDR_PHY_MR6_VDQTVAL_DEFVAL
7897 #undef DDR_PHY_MR6_VDQTVAL_SHIFT
7898 #undef DDR_PHY_MR6_VDQTVAL_MASK
7899 #define DDR_PHY_MR6_VDQTVAL_DEFVAL                                                 0x00000000
7900 #define DDR_PHY_MR6_VDQTVAL_SHIFT                                                  0
7901 #define DDR_PHY_MR6_VDQTVAL_MASK                                                   0x0000003FU
7902
7903 /*Reserved. Return zeroes on reads.*/
7904 #undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL
7905 #undef DDR_PHY_MR11_RESERVED_31_8_SHIFT
7906 #undef DDR_PHY_MR11_RESERVED_31_8_MASK
7907 #define DDR_PHY_MR11_RESERVED_31_8_DEFVAL                                          0x00000000
7908 #define DDR_PHY_MR11_RESERVED_31_8_SHIFT                                           8
7909 #define DDR_PHY_MR11_RESERVED_31_8_MASK                                            0xFFFFFF00U
7910
7911 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7912 #undef DDR_PHY_MR11_RSVD_DEFVAL
7913 #undef DDR_PHY_MR11_RSVD_SHIFT
7914 #undef DDR_PHY_MR11_RSVD_MASK
7915 #define DDR_PHY_MR11_RSVD_DEFVAL                                                   0x00000000
7916 #define DDR_PHY_MR11_RSVD_SHIFT                                                    3
7917 #define DDR_PHY_MR11_RSVD_MASK                                                     0x000000F8U
7918
7919 /*Power Down Control*/
7920 #undef DDR_PHY_MR11_PDCTL_DEFVAL
7921 #undef DDR_PHY_MR11_PDCTL_SHIFT
7922 #undef DDR_PHY_MR11_PDCTL_MASK
7923 #define DDR_PHY_MR11_PDCTL_DEFVAL                                                  0x00000000
7924 #define DDR_PHY_MR11_PDCTL_SHIFT                                                   2
7925 #define DDR_PHY_MR11_PDCTL_MASK                                                    0x00000004U
7926
7927 /*DQ Bus Receiver On-Die-Termination*/
7928 #undef DDR_PHY_MR11_DQODT_DEFVAL
7929 #undef DDR_PHY_MR11_DQODT_SHIFT
7930 #undef DDR_PHY_MR11_DQODT_MASK
7931 #define DDR_PHY_MR11_DQODT_DEFVAL                                                  0x00000000
7932 #define DDR_PHY_MR11_DQODT_SHIFT                                                   0
7933 #define DDR_PHY_MR11_DQODT_MASK                                                    0x00000003U
7934
7935 /*Reserved. Return zeroes on reads.*/
7936 #undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL
7937 #undef DDR_PHY_MR12_RESERVED_31_8_SHIFT
7938 #undef DDR_PHY_MR12_RESERVED_31_8_MASK
7939 #define DDR_PHY_MR12_RESERVED_31_8_DEFVAL                                          0x0000004D
7940 #define DDR_PHY_MR12_RESERVED_31_8_SHIFT                                           8
7941 #define DDR_PHY_MR12_RESERVED_31_8_MASK                                            0xFFFFFF00U
7942
7943 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7944 #undef DDR_PHY_MR12_RSVD_DEFVAL
7945 #undef DDR_PHY_MR12_RSVD_SHIFT
7946 #undef DDR_PHY_MR12_RSVD_MASK
7947 #define DDR_PHY_MR12_RSVD_DEFVAL                                                   0x0000004D
7948 #define DDR_PHY_MR12_RSVD_SHIFT                                                    7
7949 #define DDR_PHY_MR12_RSVD_MASK                                                     0x00000080U
7950
7951 /*VREF_CA Range Select.*/
7952 #undef DDR_PHY_MR12_VR_CA_DEFVAL
7953 #undef DDR_PHY_MR12_VR_CA_SHIFT
7954 #undef DDR_PHY_MR12_VR_CA_MASK
7955 #define DDR_PHY_MR12_VR_CA_DEFVAL                                                  0x0000004D
7956 #define DDR_PHY_MR12_VR_CA_SHIFT                                                   6
7957 #define DDR_PHY_MR12_VR_CA_MASK                                                    0x00000040U
7958
7959 /*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/
7960 #undef DDR_PHY_MR12_VREF_CA_DEFVAL
7961 #undef DDR_PHY_MR12_VREF_CA_SHIFT
7962 #undef DDR_PHY_MR12_VREF_CA_MASK
7963 #define DDR_PHY_MR12_VREF_CA_DEFVAL                                                0x0000004D
7964 #define DDR_PHY_MR12_VREF_CA_SHIFT                                                 0
7965 #define DDR_PHY_MR12_VREF_CA_MASK                                                  0x0000003FU
7966
7967 /*Reserved. Return zeroes on reads.*/
7968 #undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL
7969 #undef DDR_PHY_MR13_RESERVED_31_8_SHIFT
7970 #undef DDR_PHY_MR13_RESERVED_31_8_MASK
7971 #define DDR_PHY_MR13_RESERVED_31_8_DEFVAL                                          0x00000000
7972 #define DDR_PHY_MR13_RESERVED_31_8_SHIFT                                           8
7973 #define DDR_PHY_MR13_RESERVED_31_8_MASK                                            0xFFFFFF00U
7974
7975 /*Frequency Set Point Operation Mode*/
7976 #undef DDR_PHY_MR13_FSPOP_DEFVAL
7977 #undef DDR_PHY_MR13_FSPOP_SHIFT
7978 #undef DDR_PHY_MR13_FSPOP_MASK
7979 #define DDR_PHY_MR13_FSPOP_DEFVAL                                                  0x00000000
7980 #define DDR_PHY_MR13_FSPOP_SHIFT                                                   7
7981 #define DDR_PHY_MR13_FSPOP_MASK                                                    0x00000080U
7982
7983 /*Frequency Set Point Write Enable*/
7984 #undef DDR_PHY_MR13_FSPWR_DEFVAL
7985 #undef DDR_PHY_MR13_FSPWR_SHIFT
7986 #undef DDR_PHY_MR13_FSPWR_MASK
7987 #define DDR_PHY_MR13_FSPWR_DEFVAL                                                  0x00000000
7988 #define DDR_PHY_MR13_FSPWR_SHIFT                                                   6
7989 #define DDR_PHY_MR13_FSPWR_MASK                                                    0x00000040U
7990
7991 /*Data Mask Enable*/
7992 #undef DDR_PHY_MR13_DMD_DEFVAL
7993 #undef DDR_PHY_MR13_DMD_SHIFT
7994 #undef DDR_PHY_MR13_DMD_MASK
7995 #define DDR_PHY_MR13_DMD_DEFVAL                                                    0x00000000
7996 #define DDR_PHY_MR13_DMD_SHIFT                                                     5
7997 #define DDR_PHY_MR13_DMD_MASK                                                      0x00000020U
7998
7999 /*Refresh Rate Option*/
8000 #undef DDR_PHY_MR13_RRO_DEFVAL
8001 #undef DDR_PHY_MR13_RRO_SHIFT
8002 #undef DDR_PHY_MR13_RRO_MASK
8003 #define DDR_PHY_MR13_RRO_DEFVAL                                                    0x00000000
8004 #define DDR_PHY_MR13_RRO_SHIFT                                                     4
8005 #define DDR_PHY_MR13_RRO_MASK                                                      0x00000010U
8006
8007 /*VREF Current Generator*/
8008 #undef DDR_PHY_MR13_VRCG_DEFVAL
8009 #undef DDR_PHY_MR13_VRCG_SHIFT
8010 #undef DDR_PHY_MR13_VRCG_MASK
8011 #define DDR_PHY_MR13_VRCG_DEFVAL                                                   0x00000000
8012 #define DDR_PHY_MR13_VRCG_SHIFT                                                    3
8013 #define DDR_PHY_MR13_VRCG_MASK                                                     0x00000008U
8014
8015 /*VREF Output*/
8016 #undef DDR_PHY_MR13_VRO_DEFVAL
8017 #undef DDR_PHY_MR13_VRO_SHIFT
8018 #undef DDR_PHY_MR13_VRO_MASK
8019 #define DDR_PHY_MR13_VRO_DEFVAL                                                    0x00000000
8020 #define DDR_PHY_MR13_VRO_SHIFT                                                     2
8021 #define DDR_PHY_MR13_VRO_MASK                                                      0x00000004U
8022
8023 /*Read Preamble Training Mode*/
8024 #undef DDR_PHY_MR13_RPT_DEFVAL
8025 #undef DDR_PHY_MR13_RPT_SHIFT
8026 #undef DDR_PHY_MR13_RPT_MASK
8027 #define DDR_PHY_MR13_RPT_DEFVAL                                                    0x00000000
8028 #define DDR_PHY_MR13_RPT_SHIFT                                                     1
8029 #define DDR_PHY_MR13_RPT_MASK                                                      0x00000002U
8030
8031 /*Command Bus Training*/
8032 #undef DDR_PHY_MR13_CBT_DEFVAL
8033 #undef DDR_PHY_MR13_CBT_SHIFT
8034 #undef DDR_PHY_MR13_CBT_MASK
8035 #define DDR_PHY_MR13_CBT_DEFVAL                                                    0x00000000
8036 #define DDR_PHY_MR13_CBT_SHIFT                                                     0
8037 #define DDR_PHY_MR13_CBT_MASK                                                      0x00000001U
8038
8039 /*Reserved. Return zeroes on reads.*/
8040 #undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL
8041 #undef DDR_PHY_MR14_RESERVED_31_8_SHIFT
8042 #undef DDR_PHY_MR14_RESERVED_31_8_MASK
8043 #define DDR_PHY_MR14_RESERVED_31_8_DEFVAL                                          0x0000004D
8044 #define DDR_PHY_MR14_RESERVED_31_8_SHIFT                                           8
8045 #define DDR_PHY_MR14_RESERVED_31_8_MASK                                            0xFFFFFF00U
8046
8047 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8048 #undef DDR_PHY_MR14_RSVD_DEFVAL
8049 #undef DDR_PHY_MR14_RSVD_SHIFT
8050 #undef DDR_PHY_MR14_RSVD_MASK
8051 #define DDR_PHY_MR14_RSVD_DEFVAL                                                   0x0000004D
8052 #define DDR_PHY_MR14_RSVD_SHIFT                                                    7
8053 #define DDR_PHY_MR14_RSVD_MASK                                                     0x00000080U
8054
8055 /*VREFDQ Range Selects.*/
8056 #undef DDR_PHY_MR14_VR_DQ_DEFVAL
8057 #undef DDR_PHY_MR14_VR_DQ_SHIFT
8058 #undef DDR_PHY_MR14_VR_DQ_MASK
8059 #define DDR_PHY_MR14_VR_DQ_DEFVAL                                                  0x0000004D
8060 #define DDR_PHY_MR14_VR_DQ_SHIFT                                                   6
8061 #define DDR_PHY_MR14_VR_DQ_MASK                                                    0x00000040U
8062
8063 /*Reserved. Return zeroes on reads.*/
8064 #undef DDR_PHY_MR14_VREF_DQ_DEFVAL
8065 #undef DDR_PHY_MR14_VREF_DQ_SHIFT
8066 #undef DDR_PHY_MR14_VREF_DQ_MASK
8067 #define DDR_PHY_MR14_VREF_DQ_DEFVAL                                                0x0000004D
8068 #define DDR_PHY_MR14_VREF_DQ_SHIFT                                                 0
8069 #define DDR_PHY_MR14_VREF_DQ_MASK                                                  0x0000003FU
8070
8071 /*Reserved. Return zeroes on reads.*/
8072 #undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL
8073 #undef DDR_PHY_MR22_RESERVED_31_8_SHIFT
8074 #undef DDR_PHY_MR22_RESERVED_31_8_MASK
8075 #define DDR_PHY_MR22_RESERVED_31_8_DEFVAL                                          0x00000000
8076 #define DDR_PHY_MR22_RESERVED_31_8_SHIFT                                           8
8077 #define DDR_PHY_MR22_RESERVED_31_8_MASK                                            0xFFFFFF00U
8078
8079 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8080 #undef DDR_PHY_MR22_RSVD_DEFVAL
8081 #undef DDR_PHY_MR22_RSVD_SHIFT
8082 #undef DDR_PHY_MR22_RSVD_MASK
8083 #define DDR_PHY_MR22_RSVD_DEFVAL                                                   0x00000000
8084 #define DDR_PHY_MR22_RSVD_SHIFT                                                    6
8085 #define DDR_PHY_MR22_RSVD_MASK                                                     0x000000C0U
8086
8087 /*CA ODT termination disable.*/
8088 #undef DDR_PHY_MR22_ODTD_CA_DEFVAL
8089 #undef DDR_PHY_MR22_ODTD_CA_SHIFT
8090 #undef DDR_PHY_MR22_ODTD_CA_MASK
8091 #define DDR_PHY_MR22_ODTD_CA_DEFVAL                                                0x00000000
8092 #define DDR_PHY_MR22_ODTD_CA_SHIFT                                                 5
8093 #define DDR_PHY_MR22_ODTD_CA_MASK                                                  0x00000020U
8094
8095 /*ODT CS override.*/
8096 #undef DDR_PHY_MR22_ODTE_CS_DEFVAL
8097 #undef DDR_PHY_MR22_ODTE_CS_SHIFT
8098 #undef DDR_PHY_MR22_ODTE_CS_MASK
8099 #define DDR_PHY_MR22_ODTE_CS_DEFVAL                                                0x00000000
8100 #define DDR_PHY_MR22_ODTE_CS_SHIFT                                                 4
8101 #define DDR_PHY_MR22_ODTE_CS_MASK                                                  0x00000010U
8102
8103 /*ODT CK override.*/
8104 #undef DDR_PHY_MR22_ODTE_CK_DEFVAL
8105 #undef DDR_PHY_MR22_ODTE_CK_SHIFT
8106 #undef DDR_PHY_MR22_ODTE_CK_MASK
8107 #define DDR_PHY_MR22_ODTE_CK_DEFVAL                                                0x00000000
8108 #define DDR_PHY_MR22_ODTE_CK_SHIFT                                                 3
8109 #define DDR_PHY_MR22_ODTE_CK_MASK                                                  0x00000008U
8110
8111 /*Controller ODT value for VOH calibration.*/
8112 #undef DDR_PHY_MR22_CODT_DEFVAL
8113 #undef DDR_PHY_MR22_CODT_SHIFT
8114 #undef DDR_PHY_MR22_CODT_MASK
8115 #define DDR_PHY_MR22_CODT_DEFVAL                                                   0x00000000
8116 #define DDR_PHY_MR22_CODT_SHIFT                                                    0
8117 #define DDR_PHY_MR22_CODT_MASK                                                     0x00000007U
8118
8119 /*Refresh During Training*/
8120 #undef DDR_PHY_DTCR0_RFSHDT_DEFVAL
8121 #undef DDR_PHY_DTCR0_RFSHDT_SHIFT
8122 #undef DDR_PHY_DTCR0_RFSHDT_MASK
8123 #define DDR_PHY_DTCR0_RFSHDT_DEFVAL                                                0x800091C7
8124 #define DDR_PHY_DTCR0_RFSHDT_SHIFT                                                 28
8125 #define DDR_PHY_DTCR0_RFSHDT_MASK                                                  0xF0000000U
8126
8127 /*Reserved. Return zeroes on reads.*/
8128 #undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL
8129 #undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
8130 #undef DDR_PHY_DTCR0_RESERVED_27_26_MASK
8131 #define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL                                        0x800091C7
8132 #define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT                                         26
8133 #define DDR_PHY_DTCR0_RESERVED_27_26_MASK                                          0x0C000000U
8134
8135 /*Data Training Debug Rank Select*/
8136 #undef DDR_PHY_DTCR0_DTDRS_DEFVAL
8137 #undef DDR_PHY_DTCR0_DTDRS_SHIFT
8138 #undef DDR_PHY_DTCR0_DTDRS_MASK
8139 #define DDR_PHY_DTCR0_DTDRS_DEFVAL                                                 0x800091C7
8140 #define DDR_PHY_DTCR0_DTDRS_SHIFT                                                  24
8141 #define DDR_PHY_DTCR0_DTDRS_MASK                                                   0x03000000U
8142
8143 /*Data Training with Early/Extended Gate*/
8144 #undef DDR_PHY_DTCR0_DTEXG_DEFVAL
8145 #undef DDR_PHY_DTCR0_DTEXG_SHIFT
8146 #undef DDR_PHY_DTCR0_DTEXG_MASK
8147 #define DDR_PHY_DTCR0_DTEXG_DEFVAL                                                 0x800091C7
8148 #define DDR_PHY_DTCR0_DTEXG_SHIFT                                                  23
8149 #define DDR_PHY_DTCR0_DTEXG_MASK                                                   0x00800000U
8150
8151 /*Data Training Extended Write DQS*/
8152 #undef DDR_PHY_DTCR0_DTEXD_DEFVAL
8153 #undef DDR_PHY_DTCR0_DTEXD_SHIFT
8154 #undef DDR_PHY_DTCR0_DTEXD_MASK
8155 #define DDR_PHY_DTCR0_DTEXD_DEFVAL                                                 0x800091C7
8156 #define DDR_PHY_DTCR0_DTEXD_SHIFT                                                  22
8157 #define DDR_PHY_DTCR0_DTEXD_MASK                                                   0x00400000U
8158
8159 /*Data Training Debug Step*/
8160 #undef DDR_PHY_DTCR0_DTDSTP_DEFVAL
8161 #undef DDR_PHY_DTCR0_DTDSTP_SHIFT
8162 #undef DDR_PHY_DTCR0_DTDSTP_MASK
8163 #define DDR_PHY_DTCR0_DTDSTP_DEFVAL                                                0x800091C7
8164 #define DDR_PHY_DTCR0_DTDSTP_SHIFT                                                 21
8165 #define DDR_PHY_DTCR0_DTDSTP_MASK                                                  0x00200000U
8166
8167 /*Data Training Debug Enable*/
8168 #undef DDR_PHY_DTCR0_DTDEN_DEFVAL
8169 #undef DDR_PHY_DTCR0_DTDEN_SHIFT
8170 #undef DDR_PHY_DTCR0_DTDEN_MASK
8171 #define DDR_PHY_DTCR0_DTDEN_DEFVAL                                                 0x800091C7
8172 #define DDR_PHY_DTCR0_DTDEN_SHIFT                                                  20
8173 #define DDR_PHY_DTCR0_DTDEN_MASK                                                   0x00100000U
8174
8175 /*Data Training Debug Byte Select*/
8176 #undef DDR_PHY_DTCR0_DTDBS_DEFVAL
8177 #undef DDR_PHY_DTCR0_DTDBS_SHIFT
8178 #undef DDR_PHY_DTCR0_DTDBS_MASK
8179 #define DDR_PHY_DTCR0_DTDBS_DEFVAL                                                 0x800091C7
8180 #define DDR_PHY_DTCR0_DTDBS_SHIFT                                                  16
8181 #define DDR_PHY_DTCR0_DTDBS_MASK                                                   0x000F0000U
8182
8183 /*Data Training read DBI deskewing configuration*/
8184 #undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL
8185 #undef DDR_PHY_DTCR0_DTRDBITR_SHIFT
8186 #undef DDR_PHY_DTCR0_DTRDBITR_MASK
8187 #define DDR_PHY_DTCR0_DTRDBITR_DEFVAL                                              0x800091C7
8188 #define DDR_PHY_DTCR0_DTRDBITR_SHIFT                                               14
8189 #define DDR_PHY_DTCR0_DTRDBITR_MASK                                                0x0000C000U
8190
8191 /*Reserved. Return zeroes on reads.*/
8192 #undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL
8193 #undef DDR_PHY_DTCR0_RESERVED_13_SHIFT
8194 #undef DDR_PHY_DTCR0_RESERVED_13_MASK
8195 #define DDR_PHY_DTCR0_RESERVED_13_DEFVAL                                           0x800091C7
8196 #define DDR_PHY_DTCR0_RESERVED_13_SHIFT                                            13
8197 #define DDR_PHY_DTCR0_RESERVED_13_MASK                                             0x00002000U
8198
8199 /*Data Training Write Bit Deskew Data Mask*/
8200 #undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL
8201 #undef DDR_PHY_DTCR0_DTWBDDM_SHIFT
8202 #undef DDR_PHY_DTCR0_DTWBDDM_MASK
8203 #define DDR_PHY_DTCR0_DTWBDDM_DEFVAL                                               0x800091C7
8204 #define DDR_PHY_DTCR0_DTWBDDM_SHIFT                                                12
8205 #define DDR_PHY_DTCR0_DTWBDDM_MASK                                                 0x00001000U
8206
8207 /*Refreshes Issued During Entry to Training*/
8208 #undef DDR_PHY_DTCR0_RFSHEN_DEFVAL
8209 #undef DDR_PHY_DTCR0_RFSHEN_SHIFT
8210 #undef DDR_PHY_DTCR0_RFSHEN_MASK
8211 #define DDR_PHY_DTCR0_RFSHEN_DEFVAL                                                0x800091C7
8212 #define DDR_PHY_DTCR0_RFSHEN_SHIFT                                                 8
8213 #define DDR_PHY_DTCR0_RFSHEN_MASK                                                  0x00000F00U
8214
8215 /*Data Training Compare Data*/
8216 #undef DDR_PHY_DTCR0_DTCMPD_DEFVAL
8217 #undef DDR_PHY_DTCR0_DTCMPD_SHIFT
8218 #undef DDR_PHY_DTCR0_DTCMPD_MASK
8219 #define DDR_PHY_DTCR0_DTCMPD_DEFVAL                                                0x800091C7
8220 #define DDR_PHY_DTCR0_DTCMPD_SHIFT                                                 7
8221 #define DDR_PHY_DTCR0_DTCMPD_MASK                                                  0x00000080U
8222
8223 /*Data Training Using MPR*/
8224 #undef DDR_PHY_DTCR0_DTMPR_DEFVAL
8225 #undef DDR_PHY_DTCR0_DTMPR_SHIFT
8226 #undef DDR_PHY_DTCR0_DTMPR_MASK
8227 #define DDR_PHY_DTCR0_DTMPR_DEFVAL                                                 0x800091C7
8228 #define DDR_PHY_DTCR0_DTMPR_SHIFT                                                  6
8229 #define DDR_PHY_DTCR0_DTMPR_MASK                                                   0x00000040U
8230
8231 /*Reserved. Return zeroes on reads.*/
8232 #undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL
8233 #undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
8234 #undef DDR_PHY_DTCR0_RESERVED_5_4_MASK
8235 #define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL                                          0x800091C7
8236 #define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT                                           4
8237 #define DDR_PHY_DTCR0_RESERVED_5_4_MASK                                            0x00000030U
8238
8239 /*Data Training Repeat Number*/
8240 #undef DDR_PHY_DTCR0_DTRPTN_DEFVAL
8241 #undef DDR_PHY_DTCR0_DTRPTN_SHIFT
8242 #undef DDR_PHY_DTCR0_DTRPTN_MASK
8243 #define DDR_PHY_DTCR0_DTRPTN_DEFVAL                                                0x800091C7
8244 #define DDR_PHY_DTCR0_DTRPTN_SHIFT                                                 0
8245 #define DDR_PHY_DTCR0_DTRPTN_MASK                                                  0x0000000FU
8246
8247 /*Rank Enable.*/
8248 #undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL
8249 #undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
8250 #undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK
8251 #define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL                                           0x00030237
8252 #define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT                                            18
8253 #define DDR_PHY_DTCR1_RANKEN_RSVD_MASK                                             0xFFFC0000U
8254
8255 /*Rank Enable.*/
8256 #undef DDR_PHY_DTCR1_RANKEN_DEFVAL
8257 #undef DDR_PHY_DTCR1_RANKEN_SHIFT
8258 #undef DDR_PHY_DTCR1_RANKEN_MASK
8259 #define DDR_PHY_DTCR1_RANKEN_DEFVAL                                                0x00030237
8260 #define DDR_PHY_DTCR1_RANKEN_SHIFT                                                 16
8261 #define DDR_PHY_DTCR1_RANKEN_MASK                                                  0x00030000U
8262
8263 /*Reserved. Return zeroes on reads.*/
8264 #undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL
8265 #undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
8266 #undef DDR_PHY_DTCR1_RESERVED_15_14_MASK
8267 #define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL                                        0x00030237
8268 #define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT                                         14
8269 #define DDR_PHY_DTCR1_RESERVED_15_14_MASK                                          0x0000C000U
8270
8271 /*Data Training Rank*/
8272 #undef DDR_PHY_DTCR1_DTRANK_DEFVAL
8273 #undef DDR_PHY_DTCR1_DTRANK_SHIFT
8274 #undef DDR_PHY_DTCR1_DTRANK_MASK
8275 #define DDR_PHY_DTCR1_DTRANK_DEFVAL                                                0x00030237
8276 #define DDR_PHY_DTCR1_DTRANK_SHIFT                                                 12
8277 #define DDR_PHY_DTCR1_DTRANK_MASK                                                  0x00003000U
8278
8279 /*Reserved. Return zeroes on reads.*/
8280 #undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL
8281 #undef DDR_PHY_DTCR1_RESERVED_11_SHIFT
8282 #undef DDR_PHY_DTCR1_RESERVED_11_MASK
8283 #define DDR_PHY_DTCR1_RESERVED_11_DEFVAL                                           0x00030237
8284 #define DDR_PHY_DTCR1_RESERVED_11_SHIFT                                            11
8285 #define DDR_PHY_DTCR1_RESERVED_11_MASK                                             0x00000800U
8286
8287 /*Read Leveling Gate Sampling Difference*/
8288 #undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL
8289 #undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
8290 #undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK
8291 #define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL                                            0x00030237
8292 #define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT                                             8
8293 #define DDR_PHY_DTCR1_RDLVLGDIFF_MASK                                              0x00000700U
8294
8295 /*Reserved. Return zeroes on reads.*/
8296 #undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL
8297 #undef DDR_PHY_DTCR1_RESERVED_7_SHIFT
8298 #undef DDR_PHY_DTCR1_RESERVED_7_MASK
8299 #define DDR_PHY_DTCR1_RESERVED_7_DEFVAL                                            0x00030237
8300 #define DDR_PHY_DTCR1_RESERVED_7_SHIFT                                             7
8301 #define DDR_PHY_DTCR1_RESERVED_7_MASK                                              0x00000080U
8302
8303 /*Read Leveling Gate Shift*/
8304 #undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL
8305 #undef DDR_PHY_DTCR1_RDLVLGS_SHIFT
8306 #undef DDR_PHY_DTCR1_RDLVLGS_MASK
8307 #define DDR_PHY_DTCR1_RDLVLGS_DEFVAL                                               0x00030237
8308 #define DDR_PHY_DTCR1_RDLVLGS_SHIFT                                                4
8309 #define DDR_PHY_DTCR1_RDLVLGS_MASK                                                 0x00000070U
8310
8311 /*Reserved. Return zeroes on reads.*/
8312 #undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL
8313 #undef DDR_PHY_DTCR1_RESERVED_3_SHIFT
8314 #undef DDR_PHY_DTCR1_RESERVED_3_MASK
8315 #define DDR_PHY_DTCR1_RESERVED_3_DEFVAL                                            0x00030237
8316 #define DDR_PHY_DTCR1_RESERVED_3_SHIFT                                             3
8317 #define DDR_PHY_DTCR1_RESERVED_3_MASK                                              0x00000008U
8318
8319 /*Read Preamble Training enable*/
8320 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL
8321 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
8322 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK
8323 #define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL                                           0x00030237
8324 #define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT                                            2
8325 #define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK                                             0x00000004U
8326
8327 /*Read Leveling Enable*/
8328 #undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL
8329 #undef DDR_PHY_DTCR1_RDLVLEN_SHIFT
8330 #undef DDR_PHY_DTCR1_RDLVLEN_MASK
8331 #define DDR_PHY_DTCR1_RDLVLEN_DEFVAL                                               0x00030237
8332 #define DDR_PHY_DTCR1_RDLVLEN_SHIFT                                                1
8333 #define DDR_PHY_DTCR1_RDLVLEN_MASK                                                 0x00000002U
8334
8335 /*Basic Gate Training Enable*/
8336 #undef DDR_PHY_DTCR1_BSTEN_DEFVAL
8337 #undef DDR_PHY_DTCR1_BSTEN_SHIFT
8338 #undef DDR_PHY_DTCR1_BSTEN_MASK
8339 #define DDR_PHY_DTCR1_BSTEN_DEFVAL                                                 0x00030237
8340 #define DDR_PHY_DTCR1_BSTEN_SHIFT                                                  0
8341 #define DDR_PHY_DTCR1_BSTEN_MASK                                                   0x00000001U
8342
8343 /*Reserved. Return zeroes on reads.*/
8344 #undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL
8345 #undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT
8346 #undef DDR_PHY_CATR0_RESERVED_31_21_MASK
8347 #define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL                                        0x00141054
8348 #define DDR_PHY_CATR0_RESERVED_31_21_SHIFT                                         21
8349 #define DDR_PHY_CATR0_RESERVED_31_21_MASK                                          0xFFE00000U
8350
8351 /*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/
8352 #undef DDR_PHY_CATR0_CACD_DEFVAL
8353 #undef DDR_PHY_CATR0_CACD_SHIFT
8354 #undef DDR_PHY_CATR0_CACD_MASK
8355 #define DDR_PHY_CATR0_CACD_DEFVAL                                                  0x00141054
8356 #define DDR_PHY_CATR0_CACD_SHIFT                                                   16
8357 #define DDR_PHY_CATR0_CACD_MASK                                                    0x001F0000U
8358
8359 /*Reserved. Return zeroes on reads.*/
8360 #undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL
8361 #undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT
8362 #undef DDR_PHY_CATR0_RESERVED_15_13_MASK
8363 #define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL                                        0x00141054
8364 #define DDR_PHY_CATR0_RESERVED_15_13_SHIFT                                         13
8365 #define DDR_PHY_CATR0_RESERVED_15_13_MASK                                          0x0000E000U
8366
8367 /*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
8368                  been sent to the memory*/
8369 #undef DDR_PHY_CATR0_CAADR_DEFVAL
8370 #undef DDR_PHY_CATR0_CAADR_SHIFT
8371 #undef DDR_PHY_CATR0_CAADR_MASK
8372 #define DDR_PHY_CATR0_CAADR_DEFVAL                                                 0x00141054
8373 #define DDR_PHY_CATR0_CAADR_SHIFT                                                  8
8374 #define DDR_PHY_CATR0_CAADR_MASK                                                   0x00001F00U
8375
8376 /*CA_1 Response Byte Lane 1*/
8377 #undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL
8378 #undef DDR_PHY_CATR0_CA1BYTE1_SHIFT
8379 #undef DDR_PHY_CATR0_CA1BYTE1_MASK
8380 #define DDR_PHY_CATR0_CA1BYTE1_DEFVAL                                              0x00141054
8381 #define DDR_PHY_CATR0_CA1BYTE1_SHIFT                                               4
8382 #define DDR_PHY_CATR0_CA1BYTE1_MASK                                                0x000000F0U
8383
8384 /*CA_1 Response Byte Lane 0*/
8385 #undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL
8386 #undef DDR_PHY_CATR0_CA1BYTE0_SHIFT
8387 #undef DDR_PHY_CATR0_CA1BYTE0_MASK
8388 #define DDR_PHY_CATR0_CA1BYTE0_DEFVAL                                              0x00141054
8389 #define DDR_PHY_CATR0_CA1BYTE0_SHIFT                                               0
8390 #define DDR_PHY_CATR0_CA1BYTE0_MASK                                                0x0000000FU
8391
8392 /*LFSR seed for pseudo-random BIST patterns*/
8393 #undef DDR_PHY_BISTLSR_SEED_DEFVAL
8394 #undef DDR_PHY_BISTLSR_SEED_SHIFT
8395 #undef DDR_PHY_BISTLSR_SEED_MASK
8396 #define DDR_PHY_BISTLSR_SEED_DEFVAL
8397 #define DDR_PHY_BISTLSR_SEED_SHIFT                                                 0
8398 #define DDR_PHY_BISTLSR_SEED_MASK                                                  0xFFFFFFFFU
8399
8400 /*Reserved. Return zeroes on reads.*/
8401 #undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL
8402 #undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
8403 #undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK
8404 #define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL                                       0x00000005
8405 #define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT                                        16
8406 #define DDR_PHY_RIOCR5_RESERVED_31_16_MASK                                         0xFFFF0000U
8407
8408 /*Reserved. Return zeros on reads.*/
8409 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL
8410 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
8411 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK
8412 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL                                       0x00000005
8413 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT                                        4
8414 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK                                         0x0000FFF0U
8415
8416 /*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/
8417 #undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL
8418 #undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
8419 #undef DDR_PHY_RIOCR5_ODTOEMODE_MASK
8420 #define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL                                            0x00000005
8421 #define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT                                             0
8422 #define DDR_PHY_RIOCR5_ODTOEMODE_MASK                                              0x0000000FU
8423
8424 /*Address/Command Slew Rate (D3F I/O Only)*/
8425 #undef DDR_PHY_ACIOCR0_ACSR_DEFVAL
8426 #undef DDR_PHY_ACIOCR0_ACSR_SHIFT
8427 #undef DDR_PHY_ACIOCR0_ACSR_MASK
8428 #define DDR_PHY_ACIOCR0_ACSR_DEFVAL                                                0x30000000
8429 #define DDR_PHY_ACIOCR0_ACSR_SHIFT                                                 30
8430 #define DDR_PHY_ACIOCR0_ACSR_MASK                                                  0xC0000000U
8431
8432 /*SDRAM Reset I/O Mode*/
8433 #undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL
8434 #undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT
8435 #undef DDR_PHY_ACIOCR0_RSTIOM_MASK
8436 #define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL                                              0x30000000
8437 #define DDR_PHY_ACIOCR0_RSTIOM_SHIFT                                               29
8438 #define DDR_PHY_ACIOCR0_RSTIOM_MASK                                                0x20000000U
8439
8440 /*SDRAM Reset Power Down Receiver*/
8441 #undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL
8442 #undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT
8443 #undef DDR_PHY_ACIOCR0_RSTPDR_MASK
8444 #define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL                                              0x30000000
8445 #define DDR_PHY_ACIOCR0_RSTPDR_SHIFT                                               28
8446 #define DDR_PHY_ACIOCR0_RSTPDR_MASK                                                0x10000000U
8447
8448 /*Reserved. Return zeroes on reads.*/
8449 #undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL
8450 #undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
8451 #undef DDR_PHY_ACIOCR0_RESERVED_27_MASK
8452 #define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL                                         0x30000000
8453 #define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT                                          27
8454 #define DDR_PHY_ACIOCR0_RESERVED_27_MASK                                           0x08000000U
8455
8456 /*SDRAM Reset On-Die Termination*/
8457 #undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL
8458 #undef DDR_PHY_ACIOCR0_RSTODT_SHIFT
8459 #undef DDR_PHY_ACIOCR0_RSTODT_MASK
8460 #define DDR_PHY_ACIOCR0_RSTODT_DEFVAL                                              0x30000000
8461 #define DDR_PHY_ACIOCR0_RSTODT_SHIFT                                               26
8462 #define DDR_PHY_ACIOCR0_RSTODT_MASK                                                0x04000000U
8463
8464 /*Reserved. Return zeroes on reads.*/
8465 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL
8466 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
8467 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK
8468 #define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL                                      0x30000000
8469 #define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT                                       10
8470 #define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK                                        0x03FFFC00U
8471
8472 /*CK Duty Cycle Correction*/
8473 #undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL
8474 #undef DDR_PHY_ACIOCR0_CKDCC_SHIFT
8475 #undef DDR_PHY_ACIOCR0_CKDCC_MASK
8476 #define DDR_PHY_ACIOCR0_CKDCC_DEFVAL                                               0x30000000
8477 #define DDR_PHY_ACIOCR0_CKDCC_SHIFT                                                6
8478 #define DDR_PHY_ACIOCR0_CKDCC_MASK                                                 0x000003C0U
8479
8480 /*AC Power Down Receiver Mode*/
8481 #undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL
8482 #undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
8483 #undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK
8484 #define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL                                           0x30000000
8485 #define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT                                            4
8486 #define DDR_PHY_ACIOCR0_ACPDRMODE_MASK                                             0x00000030U
8487
8488 /*AC On-die Termination Mode*/
8489 #undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL
8490 #undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
8491 #undef DDR_PHY_ACIOCR0_ACODTMODE_MASK
8492 #define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL                                           0x30000000
8493 #define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT                                            2
8494 #define DDR_PHY_ACIOCR0_ACODTMODE_MASK                                             0x0000000CU
8495
8496 /*Reserved. Return zeroes on reads.*/
8497 #undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL
8498 #undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
8499 #undef DDR_PHY_ACIOCR0_RESERVED_1_MASK
8500 #define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL                                          0x30000000
8501 #define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT                                           1
8502 #define DDR_PHY_ACIOCR0_RESERVED_1_MASK                                            0x00000002U
8503
8504 /*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/
8505 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL
8506 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
8507 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK
8508 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL                                        0x30000000
8509 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT                                         0
8510 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK                                          0x00000001U
8511
8512 /*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/
8513 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL
8514 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
8515 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK
8516 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL                                       0x00000000
8517 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT                                        31
8518 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK                                         0x80000000U
8519
8520 /*Clock gating for Output Enable D slices [0]*/
8521 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL
8522 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
8523 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK
8524 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL                                        0x00000000
8525 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT                                         30
8526 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK                                          0x40000000U
8527
8528 /*Clock gating for Power Down Receiver D slices [0]*/
8529 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL
8530 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
8531 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK
8532 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL                                       0x00000000
8533 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT                                        29
8534 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK                                         0x20000000U
8535
8536 /*Clock gating for Termination Enable D slices [0]*/
8537 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL
8538 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
8539 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK
8540 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL                                        0x00000000
8541 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT                                         28
8542 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK                                          0x10000000U
8543
8544 /*Clock gating for CK# D slices [1:0]*/
8545 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL
8546 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
8547 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK
8548 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL                                         0x00000000
8549 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT                                          26
8550 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK                                           0x0C000000U
8551
8552 /*Clock gating for CK D slices [1:0]*/
8553 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL
8554 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
8555 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK
8556 #define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL                                          0x00000000
8557 #define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT                                           24
8558 #define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK                                            0x03000000U
8559
8560 /*Clock gating for AC D slices [23:0]*/
8561 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL
8562 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
8563 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK
8564 #define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL                                          0x00000000
8565 #define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT                                           0
8566 #define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK                                            0x00FFFFFFU
8567
8568 /*SDRAM Parity Output Enable (OE) Mode Selection*/
8569 #undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL
8570 #undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
8571 #undef DDR_PHY_ACIOCR3_PAROEMODE_MASK
8572 #define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL                                           0x00000005
8573 #define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT                                            30
8574 #define DDR_PHY_ACIOCR3_PAROEMODE_MASK                                             0xC0000000U
8575
8576 /*SDRAM Bank Group Output Enable (OE) Mode Selection*/
8577 #undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL
8578 #undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
8579 #undef DDR_PHY_ACIOCR3_BGOEMODE_MASK
8580 #define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL                                            0x00000005
8581 #define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT                                             26
8582 #define DDR_PHY_ACIOCR3_BGOEMODE_MASK                                              0x3C000000U
8583
8584 /*SDRAM Bank Address Output Enable (OE) Mode Selection*/
8585 #undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL
8586 #undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
8587 #undef DDR_PHY_ACIOCR3_BAOEMODE_MASK
8588 #define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL                                            0x00000005
8589 #define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT                                             22
8590 #define DDR_PHY_ACIOCR3_BAOEMODE_MASK                                              0x03C00000U
8591
8592 /*SDRAM A[17] Output Enable (OE) Mode Selection*/
8593 #undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL
8594 #undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
8595 #undef DDR_PHY_ACIOCR3_A17OEMODE_MASK
8596 #define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL                                           0x00000005
8597 #define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT                                            20
8598 #define DDR_PHY_ACIOCR3_A17OEMODE_MASK                                             0x00300000U
8599
8600 /*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/
8601 #undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL
8602 #undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
8603 #undef DDR_PHY_ACIOCR3_A16OEMODE_MASK
8604 #define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL                                           0x00000005
8605 #define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT                                            18
8606 #define DDR_PHY_ACIOCR3_A16OEMODE_MASK                                             0x000C0000U
8607
8608 /*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/
8609 #undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL
8610 #undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
8611 #undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK
8612 #define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL                                           0x00000005
8613 #define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT                                            16
8614 #define DDR_PHY_ACIOCR3_ACTOEMODE_MASK                                             0x00030000U
8615
8616 /*Reserved. Return zeroes on reads.*/
8617 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL
8618 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
8619 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK
8620 #define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL                                       0x00000005
8621 #define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT                                        8
8622 #define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK                                         0x0000FF00U
8623
8624 /*Reserved. Return zeros on reads.*/
8625 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL
8626 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
8627 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK
8628 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL                                       0x00000005
8629 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT                                        4
8630 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK                                         0x000000F0U
8631
8632 /*SDRAM CK Output Enable (OE) Mode Selection.*/
8633 #undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL
8634 #undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
8635 #undef DDR_PHY_ACIOCR3_CKOEMODE_MASK
8636 #define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL                                            0x00000005
8637 #define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT                                             0
8638 #define DDR_PHY_ACIOCR3_CKOEMODE_MASK                                              0x0000000FU
8639
8640 /*Clock gating for AC LB slices and loopback read valid slices*/
8641 #undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL
8642 #undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
8643 #undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK
8644 #define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL                                           0x00000000
8645 #define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT                                            31
8646 #define DDR_PHY_ACIOCR4_LBCLKGATE_MASK                                             0x80000000U
8647
8648 /*Clock gating for Output Enable D slices [1]*/
8649 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL
8650 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
8651 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK
8652 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL                                        0x00000000
8653 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT                                         30
8654 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK                                          0x40000000U
8655
8656 /*Clock gating for Power Down Receiver D slices [1]*/
8657 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL
8658 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
8659 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK
8660 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL                                       0x00000000
8661 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT                                        29
8662 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK                                         0x20000000U
8663
8664 /*Clock gating for Termination Enable D slices [1]*/
8665 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL
8666 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
8667 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK
8668 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL                                        0x00000000
8669 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT                                         28
8670 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK                                          0x10000000U
8671
8672 /*Clock gating for CK# D slices [3:2]*/
8673 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL
8674 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
8675 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK
8676 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL                                         0x00000000
8677 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT                                          26
8678 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK                                           0x0C000000U
8679
8680 /*Clock gating for CK D slices [3:2]*/
8681 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL
8682 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
8683 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK
8684 #define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL                                          0x00000000
8685 #define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT                                           24
8686 #define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK                                            0x03000000U
8687
8688 /*Clock gating for AC D slices [47:24]*/
8689 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL
8690 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
8691 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK
8692 #define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL                                          0x00000000
8693 #define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT                                           0
8694 #define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK                                            0x00FFFFFFU
8695
8696 /*Reserved. Return zeroes on reads.*/
8697 #undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL
8698 #undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
8699 #undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK
8700 #define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL                                       0x0F000000
8701 #define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT                                        29
8702 #define DDR_PHY_IOVCR0_RESERVED_31_29_MASK                                         0xE0000000U
8703
8704 /*Address/command lane VREF Pad Enable*/
8705 #undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL
8706 #undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT
8707 #undef DDR_PHY_IOVCR0_ACREFPEN_MASK
8708 #define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL                                             0x0F000000
8709 #define DDR_PHY_IOVCR0_ACREFPEN_SHIFT                                              28
8710 #define DDR_PHY_IOVCR0_ACREFPEN_MASK                                               0x10000000U
8711
8712 /*Address/command lane Internal VREF Enable*/
8713 #undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL
8714 #undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT
8715 #undef DDR_PHY_IOVCR0_ACREFEEN_MASK
8716 #define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL                                             0x0F000000
8717 #define DDR_PHY_IOVCR0_ACREFEEN_SHIFT                                              26
8718 #define DDR_PHY_IOVCR0_ACREFEEN_MASK                                               0x0C000000U
8719
8720 /*Address/command lane Single-End VREF Enable*/
8721 #undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL
8722 #undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT
8723 #undef DDR_PHY_IOVCR0_ACREFSEN_MASK
8724 #define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL                                             0x0F000000
8725 #define DDR_PHY_IOVCR0_ACREFSEN_SHIFT                                              25
8726 #define DDR_PHY_IOVCR0_ACREFSEN_MASK                                               0x02000000U
8727
8728 /*Address/command lane Internal VREF Enable*/
8729 #undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL
8730 #undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT
8731 #undef DDR_PHY_IOVCR0_ACREFIEN_MASK
8732 #define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL                                             0x0F000000
8733 #define DDR_PHY_IOVCR0_ACREFIEN_SHIFT                                              24
8734 #define DDR_PHY_IOVCR0_ACREFIEN_MASK                                               0x01000000U
8735
8736 /*External VREF generato REFSEL range select*/
8737 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL
8738 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
8739 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK
8740 #define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL                                       0x0F000000
8741 #define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT                                        23
8742 #define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK                                         0x00800000U
8743
8744 /*Address/command lane External VREF Select*/
8745 #undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL
8746 #undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT
8747 #undef DDR_PHY_IOVCR0_ACREFESEL_MASK
8748 #define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL                                            0x0F000000
8749 #define DDR_PHY_IOVCR0_ACREFESEL_SHIFT                                             16
8750 #define DDR_PHY_IOVCR0_ACREFESEL_MASK                                              0x007F0000U
8751
8752 /*Single ended VREF generator REFSEL range select*/
8753 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL
8754 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
8755 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK
8756 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL                                       0x0F000000
8757 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT                                        15
8758 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK                                         0x00008000U
8759
8760 /*Address/command lane Single-End VREF Select*/
8761 #undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL
8762 #undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
8763 #undef DDR_PHY_IOVCR0_ACREFSSEL_MASK
8764 #define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL                                            0x0F000000
8765 #define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT                                             8
8766 #define DDR_PHY_IOVCR0_ACREFSSEL_MASK                                              0x00007F00U
8767
8768 /*Internal VREF generator REFSEL ragne select*/
8769 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL
8770 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
8771 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK
8772 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL                                      0x0F000000
8773 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT                                       7
8774 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK                                        0x00000080U
8775
8776 /*REFSEL Control for internal AC IOs*/
8777 #undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL
8778 #undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
8779 #undef DDR_PHY_IOVCR0_ACVREFISEL_MASK
8780 #define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL                                           0x0F000000
8781 #define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT                                            0
8782 #define DDR_PHY_IOVCR0_ACVREFISEL_MASK                                             0x0000007FU
8783
8784 /*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/
8785 #undef DDR_PHY_VTCR0_TVREF_DEFVAL
8786 #undef DDR_PHY_VTCR0_TVREF_SHIFT
8787 #undef DDR_PHY_VTCR0_TVREF_MASK
8788 #define DDR_PHY_VTCR0_TVREF_DEFVAL                                                 0x70032019
8789 #define DDR_PHY_VTCR0_TVREF_SHIFT                                                  29
8790 #define DDR_PHY_VTCR0_TVREF_MASK                                                   0xE0000000U
8791
8792 /*DRM DQ VREF training Enable*/
8793 #undef DDR_PHY_VTCR0_DVEN_DEFVAL
8794 #undef DDR_PHY_VTCR0_DVEN_SHIFT
8795 #undef DDR_PHY_VTCR0_DVEN_MASK
8796 #define DDR_PHY_VTCR0_DVEN_DEFVAL                                                  0x70032019
8797 #define DDR_PHY_VTCR0_DVEN_SHIFT                                                   28
8798 #define DDR_PHY_VTCR0_DVEN_MASK                                                    0x10000000U
8799
8800 /*Per Device Addressability Enable*/
8801 #undef DDR_PHY_VTCR0_PDAEN_DEFVAL
8802 #undef DDR_PHY_VTCR0_PDAEN_SHIFT
8803 #undef DDR_PHY_VTCR0_PDAEN_MASK
8804 #define DDR_PHY_VTCR0_PDAEN_DEFVAL                                                 0x70032019
8805 #define DDR_PHY_VTCR0_PDAEN_SHIFT                                                  27
8806 #define DDR_PHY_VTCR0_PDAEN_MASK                                                   0x08000000U
8807
8808 /*Reserved. Returns zeroes on reads.*/
8809 #undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL
8810 #undef DDR_PHY_VTCR0_RESERVED_26_SHIFT
8811 #undef DDR_PHY_VTCR0_RESERVED_26_MASK
8812 #define DDR_PHY_VTCR0_RESERVED_26_DEFVAL                                           0x70032019
8813 #define DDR_PHY_VTCR0_RESERVED_26_SHIFT                                            26
8814 #define DDR_PHY_VTCR0_RESERVED_26_MASK                                             0x04000000U
8815
8816 /*VREF Word Count*/
8817 #undef DDR_PHY_VTCR0_VWCR_DEFVAL
8818 #undef DDR_PHY_VTCR0_VWCR_SHIFT
8819 #undef DDR_PHY_VTCR0_VWCR_MASK
8820 #define DDR_PHY_VTCR0_VWCR_DEFVAL                                                  0x70032019
8821 #define DDR_PHY_VTCR0_VWCR_SHIFT                                                   22
8822 #define DDR_PHY_VTCR0_VWCR_MASK                                                    0x03C00000U
8823
8824 /*DRAM DQ VREF step size used during DRAM VREF training*/
8825 #undef DDR_PHY_VTCR0_DVSS_DEFVAL
8826 #undef DDR_PHY_VTCR0_DVSS_SHIFT
8827 #undef DDR_PHY_VTCR0_DVSS_MASK
8828 #define DDR_PHY_VTCR0_DVSS_DEFVAL                                                  0x70032019
8829 #define DDR_PHY_VTCR0_DVSS_SHIFT                                                   18
8830 #define DDR_PHY_VTCR0_DVSS_MASK                                                    0x003C0000U
8831
8832 /*Maximum VREF limit value used during DRAM VREF training*/
8833 #undef DDR_PHY_VTCR0_DVMAX_DEFVAL
8834 #undef DDR_PHY_VTCR0_DVMAX_SHIFT
8835 #undef DDR_PHY_VTCR0_DVMAX_MASK
8836 #define DDR_PHY_VTCR0_DVMAX_DEFVAL                                                 0x70032019
8837 #define DDR_PHY_VTCR0_DVMAX_SHIFT                                                  12
8838 #define DDR_PHY_VTCR0_DVMAX_MASK                                                   0x0003F000U
8839
8840 /*Minimum VREF limit value used during DRAM VREF training*/
8841 #undef DDR_PHY_VTCR0_DVMIN_DEFVAL
8842 #undef DDR_PHY_VTCR0_DVMIN_SHIFT
8843 #undef DDR_PHY_VTCR0_DVMIN_MASK
8844 #define DDR_PHY_VTCR0_DVMIN_DEFVAL                                                 0x70032019
8845 #define DDR_PHY_VTCR0_DVMIN_SHIFT                                                  6
8846 #define DDR_PHY_VTCR0_DVMIN_MASK                                                   0x00000FC0U
8847
8848 /*Initial DRAM DQ VREF value used during DRAM VREF training*/
8849 #undef DDR_PHY_VTCR0_DVINIT_DEFVAL
8850 #undef DDR_PHY_VTCR0_DVINIT_SHIFT
8851 #undef DDR_PHY_VTCR0_DVINIT_MASK
8852 #define DDR_PHY_VTCR0_DVINIT_DEFVAL                                                0x70032019
8853 #define DDR_PHY_VTCR0_DVINIT_SHIFT                                                 0
8854 #define DDR_PHY_VTCR0_DVINIT_MASK                                                  0x0000003FU
8855
8856 /*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/
8857 #undef DDR_PHY_VTCR1_HVSS_DEFVAL
8858 #undef DDR_PHY_VTCR1_HVSS_SHIFT
8859 #undef DDR_PHY_VTCR1_HVSS_MASK
8860 #define DDR_PHY_VTCR1_HVSS_DEFVAL                                                  0x07F00072
8861 #define DDR_PHY_VTCR1_HVSS_SHIFT                                                   28
8862 #define DDR_PHY_VTCR1_HVSS_MASK                                                    0xF0000000U
8863
8864 /*Reserved. Returns zeroes on reads.*/
8865 #undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL
8866 #undef DDR_PHY_VTCR1_RESERVED_27_SHIFT
8867 #undef DDR_PHY_VTCR1_RESERVED_27_MASK
8868 #define DDR_PHY_VTCR1_RESERVED_27_DEFVAL                                           0x07F00072
8869 #define DDR_PHY_VTCR1_RESERVED_27_SHIFT                                            27
8870 #define DDR_PHY_VTCR1_RESERVED_27_MASK                                             0x08000000U
8871
8872 /*Maximum VREF limit value used during DRAM VREF training.*/
8873 #undef DDR_PHY_VTCR1_HVMAX_DEFVAL
8874 #undef DDR_PHY_VTCR1_HVMAX_SHIFT
8875 #undef DDR_PHY_VTCR1_HVMAX_MASK
8876 #define DDR_PHY_VTCR1_HVMAX_DEFVAL                                                 0x07F00072
8877 #define DDR_PHY_VTCR1_HVMAX_SHIFT                                                  20
8878 #define DDR_PHY_VTCR1_HVMAX_MASK                                                   0x07F00000U
8879
8880 /*Reserved. Returns zeroes on reads.*/
8881 #undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL
8882 #undef DDR_PHY_VTCR1_RESERVED_19_SHIFT
8883 #undef DDR_PHY_VTCR1_RESERVED_19_MASK
8884 #define DDR_PHY_VTCR1_RESERVED_19_DEFVAL                                           0x07F00072
8885 #define DDR_PHY_VTCR1_RESERVED_19_SHIFT                                            19
8886 #define DDR_PHY_VTCR1_RESERVED_19_MASK                                             0x00080000U
8887
8888 /*Minimum VREF limit value used during DRAM VREF training.*/
8889 #undef DDR_PHY_VTCR1_HVMIN_DEFVAL
8890 #undef DDR_PHY_VTCR1_HVMIN_SHIFT
8891 #undef DDR_PHY_VTCR1_HVMIN_MASK
8892 #define DDR_PHY_VTCR1_HVMIN_DEFVAL                                                 0x07F00072
8893 #define DDR_PHY_VTCR1_HVMIN_SHIFT                                                  12
8894 #define DDR_PHY_VTCR1_HVMIN_MASK                                                   0x0007F000U
8895
8896 /*Reserved. Returns zeroes on reads.*/
8897 #undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL
8898 #undef DDR_PHY_VTCR1_RESERVED_11_SHIFT
8899 #undef DDR_PHY_VTCR1_RESERVED_11_MASK
8900 #define DDR_PHY_VTCR1_RESERVED_11_DEFVAL                                           0x07F00072
8901 #define DDR_PHY_VTCR1_RESERVED_11_SHIFT                                            11
8902 #define DDR_PHY_VTCR1_RESERVED_11_MASK                                             0x00000800U
8903
8904 /*Static Host Vref Rank Value*/
8905 #undef DDR_PHY_VTCR1_SHRNK_DEFVAL
8906 #undef DDR_PHY_VTCR1_SHRNK_SHIFT
8907 #undef DDR_PHY_VTCR1_SHRNK_MASK
8908 #define DDR_PHY_VTCR1_SHRNK_DEFVAL                                                 0x07F00072
8909 #define DDR_PHY_VTCR1_SHRNK_SHIFT                                                  9
8910 #define DDR_PHY_VTCR1_SHRNK_MASK                                                   0x00000600U
8911
8912 /*Static Host Vref Rank Enable*/
8913 #undef DDR_PHY_VTCR1_SHREN_DEFVAL
8914 #undef DDR_PHY_VTCR1_SHREN_SHIFT
8915 #undef DDR_PHY_VTCR1_SHREN_MASK
8916 #define DDR_PHY_VTCR1_SHREN_DEFVAL                                                 0x07F00072
8917 #define DDR_PHY_VTCR1_SHREN_SHIFT                                                  8
8918 #define DDR_PHY_VTCR1_SHREN_MASK                                                   0x00000100U
8919
8920 /*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/
8921 #undef DDR_PHY_VTCR1_TVREFIO_DEFVAL
8922 #undef DDR_PHY_VTCR1_TVREFIO_SHIFT
8923 #undef DDR_PHY_VTCR1_TVREFIO_MASK
8924 #define DDR_PHY_VTCR1_TVREFIO_DEFVAL                                               0x07F00072
8925 #define DDR_PHY_VTCR1_TVREFIO_SHIFT                                                5
8926 #define DDR_PHY_VTCR1_TVREFIO_MASK                                                 0x000000E0U
8927
8928 /*Eye LCDL Offset value for VREF training*/
8929 #undef DDR_PHY_VTCR1_EOFF_DEFVAL
8930 #undef DDR_PHY_VTCR1_EOFF_SHIFT
8931 #undef DDR_PHY_VTCR1_EOFF_MASK
8932 #define DDR_PHY_VTCR1_EOFF_DEFVAL                                                  0x07F00072
8933 #define DDR_PHY_VTCR1_EOFF_SHIFT                                                   3
8934 #define DDR_PHY_VTCR1_EOFF_MASK                                                    0x00000018U
8935
8936 /*Number of LCDL Eye points for which VREF training is repeated*/
8937 #undef DDR_PHY_VTCR1_ENUM_DEFVAL
8938 #undef DDR_PHY_VTCR1_ENUM_SHIFT
8939 #undef DDR_PHY_VTCR1_ENUM_MASK
8940 #define DDR_PHY_VTCR1_ENUM_DEFVAL                                                  0x07F00072
8941 #define DDR_PHY_VTCR1_ENUM_SHIFT                                                   2
8942 #define DDR_PHY_VTCR1_ENUM_MASK                                                    0x00000004U
8943
8944 /*HOST (IO) internal VREF training Enable*/
8945 #undef DDR_PHY_VTCR1_HVEN_DEFVAL
8946 #undef DDR_PHY_VTCR1_HVEN_SHIFT
8947 #undef DDR_PHY_VTCR1_HVEN_MASK
8948 #define DDR_PHY_VTCR1_HVEN_DEFVAL                                                  0x07F00072
8949 #define DDR_PHY_VTCR1_HVEN_SHIFT                                                   1
8950 #define DDR_PHY_VTCR1_HVEN_MASK                                                    0x00000002U
8951
8952 /*Host IO Type Control*/
8953 #undef DDR_PHY_VTCR1_HVIO_DEFVAL
8954 #undef DDR_PHY_VTCR1_HVIO_SHIFT
8955 #undef DDR_PHY_VTCR1_HVIO_MASK
8956 #define DDR_PHY_VTCR1_HVIO_DEFVAL                                                  0x07F00072
8957 #define DDR_PHY_VTCR1_HVIO_SHIFT                                                   0
8958 #define DDR_PHY_VTCR1_HVIO_MASK                                                    0x00000001U
8959
8960 /*Reserved. Return zeroes on reads.*/
8961 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL
8962 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
8963 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK
8964 #define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL                                      0x00000000
8965 #define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT                                       30
8966 #define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK                                        0xC0000000U
8967
8968 /*Delay select for the BDL on Parity.*/
8969 #undef DDR_PHY_ACBDLR1_PARBD_DEFVAL
8970 #undef DDR_PHY_ACBDLR1_PARBD_SHIFT
8971 #undef DDR_PHY_ACBDLR1_PARBD_MASK
8972 #define DDR_PHY_ACBDLR1_PARBD_DEFVAL                                               0x00000000
8973 #define DDR_PHY_ACBDLR1_PARBD_SHIFT                                                24
8974 #define DDR_PHY_ACBDLR1_PARBD_MASK                                                 0x3F000000U
8975
8976 /*Reserved. Return zeroes on reads.*/
8977 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL
8978 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
8979 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK
8980 #define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL                                      0x00000000
8981 #define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT                                       22
8982 #define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK                                        0x00C00000U
8983
8984 /*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/
8985 #undef DDR_PHY_ACBDLR1_A16BD_DEFVAL
8986 #undef DDR_PHY_ACBDLR1_A16BD_SHIFT
8987 #undef DDR_PHY_ACBDLR1_A16BD_MASK
8988 #define DDR_PHY_ACBDLR1_A16BD_DEFVAL                                               0x00000000
8989 #define DDR_PHY_ACBDLR1_A16BD_SHIFT                                                16
8990 #define DDR_PHY_ACBDLR1_A16BD_MASK                                                 0x003F0000U
8991
8992 /*Reserved. Return zeroes on reads.*/
8993 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL
8994 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
8995 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK
8996 #define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL                                      0x00000000
8997 #define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT                                       14
8998 #define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK                                        0x0000C000U
8999
9000 /*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/
9001 #undef DDR_PHY_ACBDLR1_A17BD_DEFVAL
9002 #undef DDR_PHY_ACBDLR1_A17BD_SHIFT
9003 #undef DDR_PHY_ACBDLR1_A17BD_MASK
9004 #define DDR_PHY_ACBDLR1_A17BD_DEFVAL                                               0x00000000
9005 #define DDR_PHY_ACBDLR1_A17BD_SHIFT                                                8
9006 #define DDR_PHY_ACBDLR1_A17BD_MASK                                                 0x00003F00U
9007
9008 /*Reserved. Return zeroes on reads.*/
9009 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL
9010 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
9011 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK
9012 #define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL                                        0x00000000
9013 #define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT                                         6
9014 #define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK                                          0x000000C0U
9015
9016 /*Delay select for the BDL on ACTN.*/
9017 #undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL
9018 #undef DDR_PHY_ACBDLR1_ACTBD_SHIFT
9019 #undef DDR_PHY_ACBDLR1_ACTBD_MASK
9020 #define DDR_PHY_ACBDLR1_ACTBD_DEFVAL                                               0x00000000
9021 #define DDR_PHY_ACBDLR1_ACTBD_SHIFT                                                0
9022 #define DDR_PHY_ACBDLR1_ACTBD_MASK                                                 0x0000003FU
9023
9024 /*Reserved. Return zeroes on reads.*/
9025 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL
9026 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
9027 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK
9028 #define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL                                      0x00000000
9029 #define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT                                       30
9030 #define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK                                        0xC0000000U
9031
9032 /*Delay select for the BDL on BG[1].*/
9033 #undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL
9034 #undef DDR_PHY_ACBDLR2_BG1BD_SHIFT
9035 #undef DDR_PHY_ACBDLR2_BG1BD_MASK
9036 #define DDR_PHY_ACBDLR2_BG1BD_DEFVAL                                               0x00000000
9037 #define DDR_PHY_ACBDLR2_BG1BD_SHIFT                                                24
9038 #define DDR_PHY_ACBDLR2_BG1BD_MASK                                                 0x3F000000U
9039
9040 /*Reserved. Return zeroes on reads.*/
9041 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL
9042 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
9043 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK
9044 #define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL                                      0x00000000
9045 #define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT                                       22
9046 #define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK                                        0x00C00000U
9047
9048 /*Delay select for the BDL on BG[0].*/
9049 #undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL
9050 #undef DDR_PHY_ACBDLR2_BG0BD_SHIFT
9051 #undef DDR_PHY_ACBDLR2_BG0BD_MASK
9052 #define DDR_PHY_ACBDLR2_BG0BD_DEFVAL                                               0x00000000
9053 #define DDR_PHY_ACBDLR2_BG0BD_SHIFT                                                16
9054 #define DDR_PHY_ACBDLR2_BG0BD_MASK                                                 0x003F0000U
9055
9056 /*Reser.ved Return zeroes on reads.*/
9057 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL
9058 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
9059 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK
9060 #define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL                                      0x00000000
9061 #define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT                                       14
9062 #define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK                                        0x0000C000U
9063
9064 /*Delay select for the BDL on BA[1].*/
9065 #undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL
9066 #undef DDR_PHY_ACBDLR2_BA1BD_SHIFT
9067 #undef DDR_PHY_ACBDLR2_BA1BD_MASK
9068 #define DDR_PHY_ACBDLR2_BA1BD_DEFVAL                                               0x00000000
9069 #define DDR_PHY_ACBDLR2_BA1BD_SHIFT                                                8
9070 #define DDR_PHY_ACBDLR2_BA1BD_MASK                                                 0x00003F00U
9071
9072 /*Reserved. Return zeroes on reads.*/
9073 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL
9074 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
9075 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK
9076 #define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL                                        0x00000000
9077 #define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT                                         6
9078 #define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK                                          0x000000C0U
9079
9080 /*Delay select for the BDL on BA[0].*/
9081 #undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL
9082 #undef DDR_PHY_ACBDLR2_BA0BD_SHIFT
9083 #undef DDR_PHY_ACBDLR2_BA0BD_MASK
9084 #define DDR_PHY_ACBDLR2_BA0BD_DEFVAL                                               0x00000000
9085 #define DDR_PHY_ACBDLR2_BA0BD_SHIFT                                                0
9086 #define DDR_PHY_ACBDLR2_BA0BD_MASK                                                 0x0000003FU
9087
9088 /*Reserved. Return zeroes on reads.*/
9089 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL
9090 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
9091 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK
9092 #define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL                                      0x00000000
9093 #define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT                                       30
9094 #define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK                                        0xC0000000U
9095
9096 /*Delay select for the BDL on Address A[3].*/
9097 #undef DDR_PHY_ACBDLR6_A03BD_DEFVAL
9098 #undef DDR_PHY_ACBDLR6_A03BD_SHIFT
9099 #undef DDR_PHY_ACBDLR6_A03BD_MASK
9100 #define DDR_PHY_ACBDLR6_A03BD_DEFVAL                                               0x00000000
9101 #define DDR_PHY_ACBDLR6_A03BD_SHIFT                                                24
9102 #define DDR_PHY_ACBDLR6_A03BD_MASK                                                 0x3F000000U
9103
9104 /*Reserved. Return zeroes on reads.*/
9105 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL
9106 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
9107 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK
9108 #define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL                                      0x00000000
9109 #define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT                                       22
9110 #define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK                                        0x00C00000U
9111
9112 /*Delay select for the BDL on Address A[2].*/
9113 #undef DDR_PHY_ACBDLR6_A02BD_DEFVAL
9114 #undef DDR_PHY_ACBDLR6_A02BD_SHIFT
9115 #undef DDR_PHY_ACBDLR6_A02BD_MASK
9116 #define DDR_PHY_ACBDLR6_A02BD_DEFVAL                                               0x00000000
9117 #define DDR_PHY_ACBDLR6_A02BD_SHIFT                                                16
9118 #define DDR_PHY_ACBDLR6_A02BD_MASK                                                 0x003F0000U
9119
9120 /*Reserved. Return zeroes on reads.*/
9121 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL
9122 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
9123 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK
9124 #define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL                                      0x00000000
9125 #define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT                                       14
9126 #define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK                                        0x0000C000U
9127
9128 /*Delay select for the BDL on Address A[1].*/
9129 #undef DDR_PHY_ACBDLR6_A01BD_DEFVAL
9130 #undef DDR_PHY_ACBDLR6_A01BD_SHIFT
9131 #undef DDR_PHY_ACBDLR6_A01BD_MASK
9132 #define DDR_PHY_ACBDLR6_A01BD_DEFVAL                                               0x00000000
9133 #define DDR_PHY_ACBDLR6_A01BD_SHIFT                                                8
9134 #define DDR_PHY_ACBDLR6_A01BD_MASK                                                 0x00003F00U
9135
9136 /*Reserved. Return zeroes on reads.*/
9137 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL
9138 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
9139 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK
9140 #define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL                                        0x00000000
9141 #define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT                                         6
9142 #define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK                                          0x000000C0U
9143
9144 /*Delay select for the BDL on Address A[0].*/
9145 #undef DDR_PHY_ACBDLR6_A00BD_DEFVAL
9146 #undef DDR_PHY_ACBDLR6_A00BD_SHIFT
9147 #undef DDR_PHY_ACBDLR6_A00BD_MASK
9148 #define DDR_PHY_ACBDLR6_A00BD_DEFVAL                                               0x00000000
9149 #define DDR_PHY_ACBDLR6_A00BD_SHIFT                                                0
9150 #define DDR_PHY_ACBDLR6_A00BD_MASK                                                 0x0000003FU
9151
9152 /*Reserved. Return zeroes on reads.*/
9153 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL
9154 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
9155 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK
9156 #define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL                                      0x00000000
9157 #define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT                                       30
9158 #define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK                                        0xC0000000U
9159
9160 /*Delay select for the BDL on Address A[7].*/
9161 #undef DDR_PHY_ACBDLR7_A07BD_DEFVAL
9162 #undef DDR_PHY_ACBDLR7_A07BD_SHIFT
9163 #undef DDR_PHY_ACBDLR7_A07BD_MASK
9164 #define DDR_PHY_ACBDLR7_A07BD_DEFVAL                                               0x00000000
9165 #define DDR_PHY_ACBDLR7_A07BD_SHIFT                                                24
9166 #define DDR_PHY_ACBDLR7_A07BD_MASK                                                 0x3F000000U
9167
9168 /*Reserved. Return zeroes on reads.*/
9169 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL
9170 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
9171 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK
9172 #define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL                                      0x00000000
9173 #define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT                                       22
9174 #define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK                                        0x00C00000U
9175
9176 /*Delay select for the BDL on Address A[6].*/
9177 #undef DDR_PHY_ACBDLR7_A06BD_DEFVAL
9178 #undef DDR_PHY_ACBDLR7_A06BD_SHIFT
9179 #undef DDR_PHY_ACBDLR7_A06BD_MASK
9180 #define DDR_PHY_ACBDLR7_A06BD_DEFVAL                                               0x00000000
9181 #define DDR_PHY_ACBDLR7_A06BD_SHIFT                                                16
9182 #define DDR_PHY_ACBDLR7_A06BD_MASK                                                 0x003F0000U
9183
9184 /*Reserved. Return zeroes on reads.*/
9185 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL
9186 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
9187 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK
9188 #define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL                                      0x00000000
9189 #define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT                                       14
9190 #define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK                                        0x0000C000U
9191
9192 /*Delay select for the BDL on Address A[5].*/
9193 #undef DDR_PHY_ACBDLR7_A05BD_DEFVAL
9194 #undef DDR_PHY_ACBDLR7_A05BD_SHIFT
9195 #undef DDR_PHY_ACBDLR7_A05BD_MASK
9196 #define DDR_PHY_ACBDLR7_A05BD_DEFVAL                                               0x00000000
9197 #define DDR_PHY_ACBDLR7_A05BD_SHIFT                                                8
9198 #define DDR_PHY_ACBDLR7_A05BD_MASK                                                 0x00003F00U
9199
9200 /*Reserved. Return zeroes on reads.*/
9201 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL
9202 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
9203 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK
9204 #define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL                                        0x00000000
9205 #define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT                                         6
9206 #define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK                                          0x000000C0U
9207
9208 /*Delay select for the BDL on Address A[4].*/
9209 #undef DDR_PHY_ACBDLR7_A04BD_DEFVAL
9210 #undef DDR_PHY_ACBDLR7_A04BD_SHIFT
9211 #undef DDR_PHY_ACBDLR7_A04BD_MASK
9212 #define DDR_PHY_ACBDLR7_A04BD_DEFVAL                                               0x00000000
9213 #define DDR_PHY_ACBDLR7_A04BD_SHIFT                                                0
9214 #define DDR_PHY_ACBDLR7_A04BD_MASK                                                 0x0000003FU
9215
9216 /*Reserved. Return zeroes on reads.*/
9217 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL
9218 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
9219 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK
9220 #define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL                                      0x00000000
9221 #define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT                                       30
9222 #define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK                                        0xC0000000U
9223
9224 /*Delay select for the BDL on Address A[11].*/
9225 #undef DDR_PHY_ACBDLR8_A11BD_DEFVAL
9226 #undef DDR_PHY_ACBDLR8_A11BD_SHIFT
9227 #undef DDR_PHY_ACBDLR8_A11BD_MASK
9228 #define DDR_PHY_ACBDLR8_A11BD_DEFVAL                                               0x00000000
9229 #define DDR_PHY_ACBDLR8_A11BD_SHIFT                                                24
9230 #define DDR_PHY_ACBDLR8_A11BD_MASK                                                 0x3F000000U
9231
9232 /*Reserved. Return zeroes on reads.*/
9233 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL
9234 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
9235 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK
9236 #define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL                                      0x00000000
9237 #define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT                                       22
9238 #define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK                                        0x00C00000U
9239
9240 /*Delay select for the BDL on Address A[10].*/
9241 #undef DDR_PHY_ACBDLR8_A10BD_DEFVAL
9242 #undef DDR_PHY_ACBDLR8_A10BD_SHIFT
9243 #undef DDR_PHY_ACBDLR8_A10BD_MASK
9244 #define DDR_PHY_ACBDLR8_A10BD_DEFVAL                                               0x00000000
9245 #define DDR_PHY_ACBDLR8_A10BD_SHIFT                                                16
9246 #define DDR_PHY_ACBDLR8_A10BD_MASK                                                 0x003F0000U
9247
9248 /*Reserved. Return zeroes on reads.*/
9249 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL
9250 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
9251 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK
9252 #define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL                                      0x00000000
9253 #define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT                                       14
9254 #define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK                                        0x0000C000U
9255
9256 /*Delay select for the BDL on Address A[9].*/
9257 #undef DDR_PHY_ACBDLR8_A09BD_DEFVAL
9258 #undef DDR_PHY_ACBDLR8_A09BD_SHIFT
9259 #undef DDR_PHY_ACBDLR8_A09BD_MASK
9260 #define DDR_PHY_ACBDLR8_A09BD_DEFVAL                                               0x00000000
9261 #define DDR_PHY_ACBDLR8_A09BD_SHIFT                                                8
9262 #define DDR_PHY_ACBDLR8_A09BD_MASK                                                 0x00003F00U
9263
9264 /*Reserved. Return zeroes on reads.*/
9265 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL
9266 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
9267 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK
9268 #define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL                                        0x00000000
9269 #define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT                                         6
9270 #define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK                                          0x000000C0U
9271
9272 /*Delay select for the BDL on Address A[8].*/
9273 #undef DDR_PHY_ACBDLR8_A08BD_DEFVAL
9274 #undef DDR_PHY_ACBDLR8_A08BD_SHIFT
9275 #undef DDR_PHY_ACBDLR8_A08BD_MASK
9276 #define DDR_PHY_ACBDLR8_A08BD_DEFVAL                                               0x00000000
9277 #define DDR_PHY_ACBDLR8_A08BD_SHIFT                                                0
9278 #define DDR_PHY_ACBDLR8_A08BD_MASK                                                 0x0000003FU
9279
9280 /*Reserved. Return zeroes on reads.*/
9281 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL
9282 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
9283 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK
9284 #define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL                                      0x00000000
9285 #define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT                                       30
9286 #define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK                                        0xC0000000U
9287
9288 /*Delay select for the BDL on Address A[15].*/
9289 #undef DDR_PHY_ACBDLR9_A15BD_DEFVAL
9290 #undef DDR_PHY_ACBDLR9_A15BD_SHIFT
9291 #undef DDR_PHY_ACBDLR9_A15BD_MASK
9292 #define DDR_PHY_ACBDLR9_A15BD_DEFVAL                                               0x00000000
9293 #define DDR_PHY_ACBDLR9_A15BD_SHIFT                                                24
9294 #define DDR_PHY_ACBDLR9_A15BD_MASK                                                 0x3F000000U
9295
9296 /*Reserved. Return zeroes on reads.*/
9297 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL
9298 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
9299 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK
9300 #define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL                                      0x00000000
9301 #define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT                                       22
9302 #define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK                                        0x00C00000U
9303
9304 /*Delay select for the BDL on Address A[14].*/
9305 #undef DDR_PHY_ACBDLR9_A14BD_DEFVAL
9306 #undef DDR_PHY_ACBDLR9_A14BD_SHIFT
9307 #undef DDR_PHY_ACBDLR9_A14BD_MASK
9308 #define DDR_PHY_ACBDLR9_A14BD_DEFVAL                                               0x00000000
9309 #define DDR_PHY_ACBDLR9_A14BD_SHIFT                                                16
9310 #define DDR_PHY_ACBDLR9_A14BD_MASK                                                 0x003F0000U
9311
9312 /*Reserved. Return zeroes on reads.*/
9313 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL
9314 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
9315 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK
9316 #define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL                                      0x00000000
9317 #define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT                                       14
9318 #define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK                                        0x0000C000U
9319
9320 /*Delay select for the BDL on Address A[13].*/
9321 #undef DDR_PHY_ACBDLR9_A13BD_DEFVAL
9322 #undef DDR_PHY_ACBDLR9_A13BD_SHIFT
9323 #undef DDR_PHY_ACBDLR9_A13BD_MASK
9324 #define DDR_PHY_ACBDLR9_A13BD_DEFVAL                                               0x00000000
9325 #define DDR_PHY_ACBDLR9_A13BD_SHIFT                                                8
9326 #define DDR_PHY_ACBDLR9_A13BD_MASK                                                 0x00003F00U
9327
9328 /*Reserved. Return zeroes on reads.*/
9329 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL
9330 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
9331 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK
9332 #define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL                                        0x00000000
9333 #define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT                                         6
9334 #define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK                                          0x000000C0U
9335
9336 /*Delay select for the BDL on Address A[12].*/
9337 #undef DDR_PHY_ACBDLR9_A12BD_DEFVAL
9338 #undef DDR_PHY_ACBDLR9_A12BD_SHIFT
9339 #undef DDR_PHY_ACBDLR9_A12BD_MASK
9340 #define DDR_PHY_ACBDLR9_A12BD_DEFVAL                                               0x00000000
9341 #define DDR_PHY_ACBDLR9_A12BD_SHIFT                                                0
9342 #define DDR_PHY_ACBDLR9_A12BD_MASK                                                 0x0000003FU
9343
9344 /*Reserved. Return zeroes on reads.*/
9345 #undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL
9346 #undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
9347 #undef DDR_PHY_ZQCR_RESERVED_31_26_MASK
9348 #define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL                                         0x008A2858
9349 #define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT                                          26
9350 #define DDR_PHY_ZQCR_RESERVED_31_26_MASK                                           0xFC000000U
9351
9352 /*ZQ VREF Range*/
9353 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL
9354 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
9355 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK
9356 #define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL                                         0x008A2858
9357 #define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT                                          25
9358 #define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK                                           0x02000000U
9359
9360 /*Programmable Wait for Frequency B*/
9361 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL
9362 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
9363 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK
9364 #define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL                                            0x008A2858
9365 #define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT                                             19
9366 #define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK                                              0x01F80000U
9367
9368 /*Programmable Wait for Frequency A*/
9369 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL
9370 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
9371 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK
9372 #define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL                                            0x008A2858
9373 #define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT                                             13
9374 #define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK                                              0x0007E000U
9375
9376 /*ZQ VREF Pad Enable*/
9377 #undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL
9378 #undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT
9379 #undef DDR_PHY_ZQCR_ZQREFPEN_MASK
9380 #define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL                                               0x008A2858
9381 #define DDR_PHY_ZQCR_ZQREFPEN_SHIFT                                                12
9382 #define DDR_PHY_ZQCR_ZQREFPEN_MASK                                                 0x00001000U
9383
9384 /*ZQ Internal VREF Enable*/
9385 #undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL
9386 #undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT
9387 #undef DDR_PHY_ZQCR_ZQREFIEN_MASK
9388 #define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL                                               0x008A2858
9389 #define DDR_PHY_ZQCR_ZQREFIEN_SHIFT                                                11
9390 #define DDR_PHY_ZQCR_ZQREFIEN_MASK                                                 0x00000800U
9391
9392 /*Choice of termination mode*/
9393 #undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL
9394 #undef DDR_PHY_ZQCR_ODT_MODE_SHIFT
9395 #undef DDR_PHY_ZQCR_ODT_MODE_MASK
9396 #define DDR_PHY_ZQCR_ODT_MODE_DEFVAL                                               0x008A2858
9397 #define DDR_PHY_ZQCR_ODT_MODE_SHIFT                                                9
9398 #define DDR_PHY_ZQCR_ODT_MODE_MASK                                                 0x00000600U
9399
9400 /*Force ZCAL VT update*/
9401 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL
9402 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
9403 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK
9404 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL                                   0x008A2858
9405 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT                                    8
9406 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK                                     0x00000100U
9407
9408 /*IO VT Drift Limit*/
9409 #undef DDR_PHY_ZQCR_IODLMT_DEFVAL
9410 #undef DDR_PHY_ZQCR_IODLMT_SHIFT
9411 #undef DDR_PHY_ZQCR_IODLMT_MASK
9412 #define DDR_PHY_ZQCR_IODLMT_DEFVAL                                                 0x008A2858
9413 #define DDR_PHY_ZQCR_IODLMT_SHIFT                                                  5
9414 #define DDR_PHY_ZQCR_IODLMT_MASK                                                   0x000000E0U
9415
9416 /*Averaging algorithm enable, if set, enables averaging algorithm*/
9417 #undef DDR_PHY_ZQCR_AVGEN_DEFVAL
9418 #undef DDR_PHY_ZQCR_AVGEN_SHIFT
9419 #undef DDR_PHY_ZQCR_AVGEN_MASK
9420 #define DDR_PHY_ZQCR_AVGEN_DEFVAL                                                  0x008A2858
9421 #define DDR_PHY_ZQCR_AVGEN_SHIFT                                                   4
9422 #define DDR_PHY_ZQCR_AVGEN_MASK                                                    0x00000010U
9423
9424 /*Maximum number of averaging rounds to be used by averaging algorithm*/
9425 #undef DDR_PHY_ZQCR_AVGMAX_DEFVAL
9426 #undef DDR_PHY_ZQCR_AVGMAX_SHIFT
9427 #undef DDR_PHY_ZQCR_AVGMAX_MASK
9428 #define DDR_PHY_ZQCR_AVGMAX_DEFVAL                                                 0x008A2858
9429 #define DDR_PHY_ZQCR_AVGMAX_SHIFT                                                  2
9430 #define DDR_PHY_ZQCR_AVGMAX_MASK                                                   0x0000000CU
9431
9432 /*ZQ Calibration Type*/
9433 #undef DDR_PHY_ZQCR_ZCALT_DEFVAL
9434 #undef DDR_PHY_ZQCR_ZCALT_SHIFT
9435 #undef DDR_PHY_ZQCR_ZCALT_MASK
9436 #define DDR_PHY_ZQCR_ZCALT_DEFVAL                                                  0x008A2858
9437 #define DDR_PHY_ZQCR_ZCALT_SHIFT                                                   1
9438 #define DDR_PHY_ZQCR_ZCALT_MASK                                                    0x00000002U
9439
9440 /*ZQ Power Down*/
9441 #undef DDR_PHY_ZQCR_ZQPD_DEFVAL
9442 #undef DDR_PHY_ZQCR_ZQPD_SHIFT
9443 #undef DDR_PHY_ZQCR_ZQPD_MASK
9444 #define DDR_PHY_ZQCR_ZQPD_DEFVAL                                                   0x008A2858
9445 #define DDR_PHY_ZQCR_ZQPD_SHIFT                                                    0
9446 #define DDR_PHY_ZQCR_ZQPD_MASK                                                     0x00000001U
9447
9448 /*Pull-down drive strength ZCTRL over-ride enable*/
9449 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL
9450 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
9451 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK
9452 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL                                          0x000077BB
9453 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT                                           31
9454 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK                                            0x80000000U
9455
9456 /*Pull-up drive strength ZCTRL over-ride enable*/
9457 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL
9458 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
9459 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK
9460 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL                                          0x000077BB
9461 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT                                           30
9462 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK                                            0x40000000U
9463
9464 /*Pull-down termination ZCTRL over-ride enable*/
9465 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL
9466 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
9467 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK
9468 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL                                          0x000077BB
9469 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT                                           29
9470 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK                                            0x20000000U
9471
9472 /*Pull-up termination ZCTRL over-ride enable*/
9473 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL
9474 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
9475 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK
9476 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL                                          0x000077BB
9477 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT                                           28
9478 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK                                            0x10000000U
9479
9480 /*Calibration segment bypass*/
9481 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL
9482 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
9483 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK
9484 #define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL                                              0x000077BB
9485 #define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT                                               27
9486 #define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK                                                0x08000000U
9487
9488 /*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
9489 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL
9490 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
9491 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK
9492 #define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL                                             0x000077BB
9493 #define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT                                              25
9494 #define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK                                               0x06000000U
9495
9496 /*Termination adjustment*/
9497 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL
9498 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
9499 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK
9500 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL                                           0x000077BB
9501 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT                                            22
9502 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK                                             0x01C00000U
9503
9504 /*Pulldown drive strength adjustment*/
9505 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL
9506 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
9507 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK
9508 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL                                        0x000077BB
9509 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT                                         19
9510 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK                                          0x00380000U
9511
9512 /*Pullup drive strength adjustment*/
9513 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL
9514 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
9515 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK
9516 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL                                        0x000077BB
9517 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT                                         16
9518 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK                                          0x00070000U
9519
9520 /*DRAM Impedance Divide Ratio*/
9521 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL
9522 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
9523 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK
9524 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL                                       0x000077BB
9525 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT                                        12
9526 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK                                         0x0000F000U
9527
9528 /*HOST Impedance Divide Ratio*/
9529 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL
9530 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
9531 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK
9532 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL                                       0x000077BB
9533 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT                                        8
9534 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK                                         0x00000F00U
9535
9536 /*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
9537 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL
9538 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
9539 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK
9540 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL                                    0x000077BB
9541 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT                                     4
9542 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK                                      0x000000F0U
9543
9544 /*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
9545 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL
9546 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
9547 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK
9548 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL                                    0x000077BB
9549 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT                                     0
9550 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK                                      0x0000000FU
9551
9552 /*Reserved. Return zeros on reads.*/
9553 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL
9554 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
9555 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK
9556 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL                                       0x00000000
9557 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT                                        26
9558 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK                                         0xFC000000U
9559
9560 /*Override value for the pull-up output impedance*/
9561 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL
9562 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
9563 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK
9564 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL                                    0x00000000
9565 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT                                     16
9566 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK                                      0x03FF0000U
9567
9568 /*Reserved. Return zeros on reads.*/
9569 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL
9570 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
9571 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK
9572 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL                                       0x00000000
9573 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT                                        10
9574 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK                                         0x0000FC00U
9575
9576 /*Override value for the pull-down output impedance*/
9577 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL
9578 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
9579 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK
9580 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL                                    0x00000000
9581 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT                                     0
9582 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK                                      0x000003FFU
9583
9584 /*Reserved. Return zeros on reads.*/
9585 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL
9586 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
9587 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK
9588 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL                                       0x00000000
9589 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT                                        26
9590 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK                                         0xFC000000U
9591
9592 /*Override value for the pull-up termination*/
9593 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL
9594 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
9595 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK
9596 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL                                    0x00000000
9597 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT                                     16
9598 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK                                      0x03FF0000U
9599
9600 /*Reserved. Return zeros on reads.*/
9601 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL
9602 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
9603 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK
9604 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL                                       0x00000000
9605 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT                                        10
9606 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK                                         0x0000FC00U
9607
9608 /*Override value for the pull-down termination*/
9609 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL
9610 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
9611 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK
9612 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL                                    0x00000000
9613 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT                                     0
9614 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK                                      0x000003FFU
9615
9616 /*Pull-down drive strength ZCTRL over-ride enable*/
9617 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL
9618 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
9619 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK
9620 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL                                          0x000077BB
9621 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT                                           31
9622 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK                                            0x80000000U
9623
9624 /*Pull-up drive strength ZCTRL over-ride enable*/
9625 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL
9626 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
9627 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK
9628 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL                                          0x000077BB
9629 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT                                           30
9630 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK                                            0x40000000U
9631
9632 /*Pull-down termination ZCTRL over-ride enable*/
9633 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL
9634 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
9635 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK
9636 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL                                          0x000077BB
9637 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT                                           29
9638 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK                                            0x20000000U
9639
9640 /*Pull-up termination ZCTRL over-ride enable*/
9641 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL
9642 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
9643 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK
9644 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL                                          0x000077BB
9645 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT                                           28
9646 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK                                            0x10000000U
9647
9648 /*Calibration segment bypass*/
9649 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL
9650 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
9651 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK
9652 #define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL                                              0x000077BB
9653 #define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT                                               27
9654 #define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK                                                0x08000000U
9655
9656 /*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
9657 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL
9658 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
9659 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK
9660 #define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL                                             0x000077BB
9661 #define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT                                              25
9662 #define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK                                               0x06000000U
9663
9664 /*Termination adjustment*/
9665 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL
9666 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
9667 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK
9668 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL                                           0x000077BB
9669 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT                                            22
9670 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK                                             0x01C00000U
9671
9672 /*Pulldown drive strength adjustment*/
9673 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL
9674 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
9675 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK
9676 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL                                        0x000077BB
9677 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT                                         19
9678 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK                                          0x00380000U
9679
9680 /*Pullup drive strength adjustment*/
9681 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL
9682 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
9683 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK
9684 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL                                        0x000077BB
9685 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT                                         16
9686 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK                                          0x00070000U
9687
9688 /*DRAM Impedance Divide Ratio*/
9689 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL
9690 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
9691 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK
9692 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL                                       0x000077BB
9693 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT                                        12
9694 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK                                         0x0000F000U
9695
9696 /*HOST Impedance Divide Ratio*/
9697 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL
9698 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
9699 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK
9700 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL                                       0x000077BB
9701 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT                                        8
9702 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK                                         0x00000F00U
9703
9704 /*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
9705 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL
9706 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
9707 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK
9708 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL                                    0x000077BB
9709 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT                                     4
9710 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK                                      0x000000F0U
9711
9712 /*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
9713 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL
9714 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
9715 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK
9716 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL                                    0x000077BB
9717 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT                                     0
9718 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK                                      0x0000000FU
9719
9720 /*Calibration Bypass*/
9721 #undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL
9722 #undef DDR_PHY_DX0GCR0_CALBYP_SHIFT
9723 #undef DDR_PHY_DX0GCR0_CALBYP_MASK
9724 #define DDR_PHY_DX0GCR0_CALBYP_DEFVAL                                              0x40200204
9725 #define DDR_PHY_DX0GCR0_CALBYP_SHIFT                                               31
9726 #define DDR_PHY_DX0GCR0_CALBYP_MASK                                                0x80000000U
9727
9728 /*Master Delay Line Enable*/
9729 #undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL
9730 #undef DDR_PHY_DX0GCR0_MDLEN_SHIFT
9731 #undef DDR_PHY_DX0GCR0_MDLEN_MASK
9732 #define DDR_PHY_DX0GCR0_MDLEN_DEFVAL                                               0x40200204
9733 #define DDR_PHY_DX0GCR0_MDLEN_SHIFT                                                30
9734 #define DDR_PHY_DX0GCR0_MDLEN_MASK                                                 0x40000000U
9735
9736 /*Configurable ODT(TE) Phase Shift*/
9737 #undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL
9738 #undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
9739 #undef DDR_PHY_DX0GCR0_CODTSHFT_MASK
9740 #define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL                                            0x40200204
9741 #define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT                                             28
9742 #define DDR_PHY_DX0GCR0_CODTSHFT_MASK                                              0x30000000U
9743
9744 /*DQS Duty Cycle Correction*/
9745 #undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL
9746 #undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT
9747 #undef DDR_PHY_DX0GCR0_DQSDCC_MASK
9748 #define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL                                              0x40200204
9749 #define DDR_PHY_DX0GCR0_DQSDCC_SHIFT                                               24
9750 #define DDR_PHY_DX0GCR0_DQSDCC_MASK                                                0x0F000000U
9751
9752 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
9753 #undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL
9754 #undef DDR_PHY_DX0GCR0_RDDLY_SHIFT
9755 #undef DDR_PHY_DX0GCR0_RDDLY_MASK
9756 #define DDR_PHY_DX0GCR0_RDDLY_DEFVAL                                               0x40200204
9757 #define DDR_PHY_DX0GCR0_RDDLY_SHIFT                                                20
9758 #define DDR_PHY_DX0GCR0_RDDLY_MASK                                                 0x00F00000U
9759
9760 /*Reserved. Return zeroes on reads.*/
9761 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL
9762 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
9763 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK
9764 #define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
9765 #define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT                                       14
9766 #define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK                                        0x000FC000U
9767
9768 /*DQSNSE Power Down Receiver*/
9769 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL
9770 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
9771 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK
9772 #define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
9773 #define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT                                            13
9774 #define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK                                             0x00002000U
9775
9776 /*DQSSE Power Down Receiver*/
9777 #undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL
9778 #undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
9779 #undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK
9780 #define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL                                            0x40200204
9781 #define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT                                             12
9782 #define DDR_PHY_DX0GCR0_DQSSEPDR_MASK                                              0x00001000U
9783
9784 /*RTT On Additive Latency*/
9785 #undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL
9786 #undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT
9787 #undef DDR_PHY_DX0GCR0_RTTOAL_MASK
9788 #define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL                                              0x40200204
9789 #define DDR_PHY_DX0GCR0_RTTOAL_SHIFT                                               11
9790 #define DDR_PHY_DX0GCR0_RTTOAL_MASK                                                0x00000800U
9791
9792 /*RTT Output Hold*/
9793 #undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL
9794 #undef DDR_PHY_DX0GCR0_RTTOH_SHIFT
9795 #undef DDR_PHY_DX0GCR0_RTTOH_MASK
9796 #define DDR_PHY_DX0GCR0_RTTOH_DEFVAL                                               0x40200204
9797 #define DDR_PHY_DX0GCR0_RTTOH_SHIFT                                                9
9798 #define DDR_PHY_DX0GCR0_RTTOH_MASK                                                 0x00000600U
9799
9800 /*Configurable PDR Phase Shift*/
9801 #undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL
9802 #undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
9803 #undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK
9804 #define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL                                            0x40200204
9805 #define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT                                             7
9806 #define DDR_PHY_DX0GCR0_CPDRSHFT_MASK                                              0x00000180U
9807
9808 /*DQSR Power Down*/
9809 #undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL
9810 #undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT
9811 #undef DDR_PHY_DX0GCR0_DQSRPD_MASK
9812 #define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL                                              0x40200204
9813 #define DDR_PHY_DX0GCR0_DQSRPD_SHIFT                                               6
9814 #define DDR_PHY_DX0GCR0_DQSRPD_MASK                                                0x00000040U
9815
9816 /*DQSG Power Down Receiver*/
9817 #undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL
9818 #undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
9819 #undef DDR_PHY_DX0GCR0_DQSGPDR_MASK
9820 #define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL                                             0x40200204
9821 #define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT                                              5
9822 #define DDR_PHY_DX0GCR0_DQSGPDR_MASK                                               0x00000020U
9823
9824 /*Reserved. Return zeroes on reads.*/
9825 #undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL
9826 #undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
9827 #undef DDR_PHY_DX0GCR0_RESERVED_4_MASK
9828 #define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL                                          0x40200204
9829 #define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT                                           4
9830 #define DDR_PHY_DX0GCR0_RESERVED_4_MASK                                            0x00000010U
9831
9832 /*DQSG On-Die Termination*/
9833 #undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL
9834 #undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT
9835 #undef DDR_PHY_DX0GCR0_DQSGODT_MASK
9836 #define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL                                             0x40200204
9837 #define DDR_PHY_DX0GCR0_DQSGODT_SHIFT                                              3
9838 #define DDR_PHY_DX0GCR0_DQSGODT_MASK                                               0x00000008U
9839
9840 /*DQSG Output Enable*/
9841 #undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL
9842 #undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT
9843 #undef DDR_PHY_DX0GCR0_DQSGOE_MASK
9844 #define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL                                              0x40200204
9845 #define DDR_PHY_DX0GCR0_DQSGOE_SHIFT                                               2
9846 #define DDR_PHY_DX0GCR0_DQSGOE_MASK                                                0x00000004U
9847
9848 /*Reserved. Return zeroes on reads.*/
9849 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL
9850 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
9851 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK
9852 #define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
9853 #define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT                                         0
9854 #define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK                                          0x00000003U
9855
9856 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
9857 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL
9858 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
9859 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK
9860 #define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
9861 #define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT                                       29
9862 #define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK                                        0xE0000000U
9863
9864 /*Byte Lane VREF Pad Enable*/
9865 #undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL
9866 #undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
9867 #undef DDR_PHY_DX0GCR4_DXREFPEN_MASK
9868 #define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
9869 #define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT                                             28
9870 #define DDR_PHY_DX0GCR4_DXREFPEN_MASK                                              0x10000000U
9871
9872 /*Byte Lane Internal VREF Enable*/
9873 #undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL
9874 #undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
9875 #undef DDR_PHY_DX0GCR4_DXREFEEN_MASK
9876 #define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
9877 #define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT                                             26
9878 #define DDR_PHY_DX0GCR4_DXREFEEN_MASK                                              0x0C000000U
9879
9880 /*Byte Lane Single-End VREF Enable*/
9881 #undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL
9882 #undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
9883 #undef DDR_PHY_DX0GCR4_DXREFSEN_MASK
9884 #define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
9885 #define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT                                             25
9886 #define DDR_PHY_DX0GCR4_DXREFSEN_MASK                                              0x02000000U
9887
9888 /*Reserved. Returns zeros on reads.*/
9889 #undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL
9890 #undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
9891 #undef DDR_PHY_DX0GCR4_RESERVED_24_MASK
9892 #define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
9893 #define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT                                          24
9894 #define DDR_PHY_DX0GCR4_RESERVED_24_MASK                                           0x01000000U
9895
9896 /*External VREF generator REFSEL range select*/
9897 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL
9898 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
9899 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK
9900 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
9901 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT                                       23
9902 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK                                        0x00800000U
9903
9904 /*Byte Lane External VREF Select*/
9905 #undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL
9906 #undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
9907 #undef DDR_PHY_DX0GCR4_DXREFESEL_MASK
9908 #define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
9909 #define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT                                            16
9910 #define DDR_PHY_DX0GCR4_DXREFESEL_MASK                                             0x007F0000U
9911
9912 /*Single ended VREF generator REFSEL range select*/
9913 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL
9914 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
9915 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK
9916 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
9917 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT                                       15
9918 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
9919
9920 /*Byte Lane Single-End VREF Select*/
9921 #undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL
9922 #undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
9923 #undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK
9924 #define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
9925 #define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT                                            8
9926 #define DDR_PHY_DX0GCR4_DXREFSSEL_MASK                                             0x00007F00U
9927
9928 /*Reserved. Returns zeros on reads.*/
9929 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL
9930 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
9931 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK
9932 #define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
9933 #define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT                                         6
9934 #define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK                                          0x000000C0U
9935
9936 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
9937 #undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL
9938 #undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
9939 #undef DDR_PHY_DX0GCR4_DXREFIEN_MASK
9940 #define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
9941 #define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT                                             2
9942 #define DDR_PHY_DX0GCR4_DXREFIEN_MASK                                              0x0000003CU
9943
9944 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
9945 #undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL
9946 #undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
9947 #undef DDR_PHY_DX0GCR4_DXREFIMON_MASK
9948 #define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
9949 #define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT                                            0
9950 #define DDR_PHY_DX0GCR4_DXREFIMON_MASK                                             0x00000003U
9951
9952 /*Reserved. Returns zeros on reads.*/
9953 #undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL
9954 #undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
9955 #undef DDR_PHY_DX0GCR5_RESERVED_31_MASK
9956 #define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL                                         0x09090909
9957 #define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT                                          31
9958 #define DDR_PHY_DX0GCR5_RESERVED_31_MASK                                           0x80000000U
9959
9960 /*Byte Lane internal VREF Select for Rank 3*/
9961 #undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL
9962 #undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
9963 #undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK
9964 #define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL                                         0x09090909
9965 #define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT                                          24
9966 #define DDR_PHY_DX0GCR5_DXREFISELR3_MASK                                           0x7F000000U
9967
9968 /*Reserved. Returns zeros on reads.*/
9969 #undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL
9970 #undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
9971 #undef DDR_PHY_DX0GCR5_RESERVED_23_MASK
9972 #define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL                                         0x09090909
9973 #define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT                                          23
9974 #define DDR_PHY_DX0GCR5_RESERVED_23_MASK                                           0x00800000U
9975
9976 /*Byte Lane internal VREF Select for Rank 2*/
9977 #undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL
9978 #undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
9979 #undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK
9980 #define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL                                         0x09090909
9981 #define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT                                          16
9982 #define DDR_PHY_DX0GCR5_DXREFISELR2_MASK                                           0x007F0000U
9983
9984 /*Reserved. Returns zeros on reads.*/
9985 #undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL
9986 #undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
9987 #undef DDR_PHY_DX0GCR5_RESERVED_15_MASK
9988 #define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL                                         0x09090909
9989 #define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT                                          15
9990 #define DDR_PHY_DX0GCR5_RESERVED_15_MASK                                           0x00008000U
9991
9992 /*Byte Lane internal VREF Select for Rank 1*/
9993 #undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL
9994 #undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
9995 #undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK
9996 #define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL                                         0x09090909
9997 #define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT                                          8
9998 #define DDR_PHY_DX0GCR5_DXREFISELR1_MASK                                           0x00007F00U
9999
10000 /*Reserved. Returns zeros on reads.*/
10001 #undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL
10002 #undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
10003 #undef DDR_PHY_DX0GCR5_RESERVED_7_MASK
10004 #define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL                                          0x09090909
10005 #define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT                                           7
10006 #define DDR_PHY_DX0GCR5_RESERVED_7_MASK                                            0x00000080U
10007
10008 /*Byte Lane internal VREF Select for Rank 0*/
10009 #undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL
10010 #undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
10011 #undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK
10012 #define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL                                         0x09090909
10013 #define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT                                          0
10014 #define DDR_PHY_DX0GCR5_DXREFISELR0_MASK                                           0x0000007FU
10015
10016 /*Reserved. Returns zeros on reads.*/
10017 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL
10018 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
10019 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK
10020 #define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
10021 #define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT                                       30
10022 #define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK                                        0xC0000000U
10023
10024 /*DRAM DQ VREF Select for Rank3*/
10025 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL
10026 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
10027 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK
10028 #define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
10029 #define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT                                           24
10030 #define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK                                            0x3F000000U
10031
10032 /*Reserved. Returns zeros on reads.*/
10033 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL
10034 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
10035 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK
10036 #define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
10037 #define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT                                       22
10038 #define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK                                        0x00C00000U
10039
10040 /*DRAM DQ VREF Select for Rank2*/
10041 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL
10042 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
10043 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK
10044 #define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
10045 #define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT                                           16
10046 #define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK                                            0x003F0000U
10047
10048 /*Reserved. Returns zeros on reads.*/
10049 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL
10050 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
10051 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK
10052 #define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
10053 #define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT                                       14
10054 #define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK                                        0x0000C000U
10055
10056 /*DRAM DQ VREF Select for Rank1*/
10057 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL
10058 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
10059 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK
10060 #define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
10061 #define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT                                           8
10062 #define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK                                            0x00003F00U
10063
10064 /*Reserved. Returns zeros on reads.*/
10065 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL
10066 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
10067 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK
10068 #define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
10069 #define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT                                         6
10070 #define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK                                          0x000000C0U
10071
10072 /*DRAM DQ VREF Select for Rank0*/
10073 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL
10074 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
10075 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK
10076 #define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
10077 #define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT                                           0
10078 #define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK                                            0x0000003FU
10079
10080 /*Reserved. Return zeroes on reads.*/
10081 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL
10082 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT
10083 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK
10084 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
10085 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT                                     25
10086 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
10087
10088 /*Reserved. Caution, do not write to this register field.*/
10089 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL
10090 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT
10091 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK
10092 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
10093 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT                                     16
10094 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
10095
10096 /*Reserved. Return zeroes on reads.*/
10097 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL
10098 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT
10099 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK
10100 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
10101 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT                                      9
10102 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
10103
10104 /*Read DQS Gating Delay*/
10105 #undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL
10106 #undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT
10107 #undef DDR_PHY_DX0LCDLR2_DQSGD_MASK
10108 #define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL                                             0x00000000
10109 #define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT                                              0
10110 #define DDR_PHY_DX0LCDLR2_DQSGD_MASK                                               0x000001FFU
10111
10112 /*Reserved. Return zeroes on reads.*/
10113 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL
10114 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT
10115 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK
10116 #define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
10117 #define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT                                       27
10118 #define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK                                        0xF8000000U
10119
10120 /*DQ Write Path Latency Pipeline*/
10121 #undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL
10122 #undef DDR_PHY_DX0GTR0_WDQSL_SHIFT
10123 #undef DDR_PHY_DX0GTR0_WDQSL_MASK
10124 #define DDR_PHY_DX0GTR0_WDQSL_DEFVAL                                               0x00020000
10125 #define DDR_PHY_DX0GTR0_WDQSL_SHIFT                                                24
10126 #define DDR_PHY_DX0GTR0_WDQSL_MASK                                                 0x07000000U
10127
10128 /*Reserved. Caution, do not write to this register field.*/
10129 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL
10130 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT
10131 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK
10132 #define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
10133 #define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT                                       20
10134 #define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK                                        0x00F00000U
10135
10136 /*Write Leveling System Latency*/
10137 #undef DDR_PHY_DX0GTR0_WLSL_DEFVAL
10138 #undef DDR_PHY_DX0GTR0_WLSL_SHIFT
10139 #undef DDR_PHY_DX0GTR0_WLSL_MASK
10140 #define DDR_PHY_DX0GTR0_WLSL_DEFVAL                                                0x00020000
10141 #define DDR_PHY_DX0GTR0_WLSL_SHIFT                                                 16
10142 #define DDR_PHY_DX0GTR0_WLSL_MASK                                                  0x000F0000U
10143
10144 /*Reserved. Return zeroes on reads.*/
10145 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL
10146 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT
10147 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK
10148 #define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
10149 #define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT                                       13
10150 #define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK                                        0x0000E000U
10151
10152 /*Reserved. Caution, do not write to this register field.*/
10153 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL
10154 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT
10155 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK
10156 #define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
10157 #define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT                                        8
10158 #define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK                                         0x00001F00U
10159
10160 /*Reserved. Return zeroes on reads.*/
10161 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL
10162 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT
10163 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK
10164 #define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
10165 #define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT                                         5
10166 #define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK                                          0x000000E0U
10167
10168 /*DQS Gating System Latency*/
10169 #undef DDR_PHY_DX0GTR0_DGSL_DEFVAL
10170 #undef DDR_PHY_DX0GTR0_DGSL_SHIFT
10171 #undef DDR_PHY_DX0GTR0_DGSL_MASK
10172 #define DDR_PHY_DX0GTR0_DGSL_DEFVAL                                                0x00020000
10173 #define DDR_PHY_DX0GTR0_DGSL_SHIFT                                                 0
10174 #define DDR_PHY_DX0GTR0_DGSL_MASK                                                  0x0000001FU
10175
10176 /*Calibration Bypass*/
10177 #undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL
10178 #undef DDR_PHY_DX1GCR0_CALBYP_SHIFT
10179 #undef DDR_PHY_DX1GCR0_CALBYP_MASK
10180 #define DDR_PHY_DX1GCR0_CALBYP_DEFVAL                                              0x40200204
10181 #define DDR_PHY_DX1GCR0_CALBYP_SHIFT                                               31
10182 #define DDR_PHY_DX1GCR0_CALBYP_MASK                                                0x80000000U
10183
10184 /*Master Delay Line Enable*/
10185 #undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL
10186 #undef DDR_PHY_DX1GCR0_MDLEN_SHIFT
10187 #undef DDR_PHY_DX1GCR0_MDLEN_MASK
10188 #define DDR_PHY_DX1GCR0_MDLEN_DEFVAL                                               0x40200204
10189 #define DDR_PHY_DX1GCR0_MDLEN_SHIFT                                                30
10190 #define DDR_PHY_DX1GCR0_MDLEN_MASK                                                 0x40000000U
10191
10192 /*Configurable ODT(TE) Phase Shift*/
10193 #undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL
10194 #undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
10195 #undef DDR_PHY_DX1GCR0_CODTSHFT_MASK
10196 #define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL                                            0x40200204
10197 #define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT                                             28
10198 #define DDR_PHY_DX1GCR0_CODTSHFT_MASK                                              0x30000000U
10199
10200 /*DQS Duty Cycle Correction*/
10201 #undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL
10202 #undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT
10203 #undef DDR_PHY_DX1GCR0_DQSDCC_MASK
10204 #define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL                                              0x40200204
10205 #define DDR_PHY_DX1GCR0_DQSDCC_SHIFT                                               24
10206 #define DDR_PHY_DX1GCR0_DQSDCC_MASK                                                0x0F000000U
10207
10208 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
10209 #undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL
10210 #undef DDR_PHY_DX1GCR0_RDDLY_SHIFT
10211 #undef DDR_PHY_DX1GCR0_RDDLY_MASK
10212 #define DDR_PHY_DX1GCR0_RDDLY_DEFVAL                                               0x40200204
10213 #define DDR_PHY_DX1GCR0_RDDLY_SHIFT                                                20
10214 #define DDR_PHY_DX1GCR0_RDDLY_MASK                                                 0x00F00000U
10215
10216 /*Reserved. Return zeroes on reads.*/
10217 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL
10218 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
10219 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK
10220 #define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
10221 #define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT                                       14
10222 #define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK                                        0x000FC000U
10223
10224 /*DQSNSE Power Down Receiver*/
10225 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL
10226 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
10227 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK
10228 #define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
10229 #define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT                                            13
10230 #define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK                                             0x00002000U
10231
10232 /*DQSSE Power Down Receiver*/
10233 #undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL
10234 #undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
10235 #undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK
10236 #define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL                                            0x40200204
10237 #define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT                                             12
10238 #define DDR_PHY_DX1GCR0_DQSSEPDR_MASK                                              0x00001000U
10239
10240 /*RTT On Additive Latency*/
10241 #undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL
10242 #undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT
10243 #undef DDR_PHY_DX1GCR0_RTTOAL_MASK
10244 #define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL                                              0x40200204
10245 #define DDR_PHY_DX1GCR0_RTTOAL_SHIFT                                               11
10246 #define DDR_PHY_DX1GCR0_RTTOAL_MASK                                                0x00000800U
10247
10248 /*RTT Output Hold*/
10249 #undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL
10250 #undef DDR_PHY_DX1GCR0_RTTOH_SHIFT
10251 #undef DDR_PHY_DX1GCR0_RTTOH_MASK
10252 #define DDR_PHY_DX1GCR0_RTTOH_DEFVAL                                               0x40200204
10253 #define DDR_PHY_DX1GCR0_RTTOH_SHIFT                                                9
10254 #define DDR_PHY_DX1GCR0_RTTOH_MASK                                                 0x00000600U
10255
10256 /*Configurable PDR Phase Shift*/
10257 #undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL
10258 #undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
10259 #undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK
10260 #define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL                                            0x40200204
10261 #define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT                                             7
10262 #define DDR_PHY_DX1GCR0_CPDRSHFT_MASK                                              0x00000180U
10263
10264 /*DQSR Power Down*/
10265 #undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL
10266 #undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT
10267 #undef DDR_PHY_DX1GCR0_DQSRPD_MASK
10268 #define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL                                              0x40200204
10269 #define DDR_PHY_DX1GCR0_DQSRPD_SHIFT                                               6
10270 #define DDR_PHY_DX1GCR0_DQSRPD_MASK                                                0x00000040U
10271
10272 /*DQSG Power Down Receiver*/
10273 #undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL
10274 #undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
10275 #undef DDR_PHY_DX1GCR0_DQSGPDR_MASK
10276 #define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL                                             0x40200204
10277 #define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT                                              5
10278 #define DDR_PHY_DX1GCR0_DQSGPDR_MASK                                               0x00000020U
10279
10280 /*Reserved. Return zeroes on reads.*/
10281 #undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL
10282 #undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
10283 #undef DDR_PHY_DX1GCR0_RESERVED_4_MASK
10284 #define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL                                          0x40200204
10285 #define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT                                           4
10286 #define DDR_PHY_DX1GCR0_RESERVED_4_MASK                                            0x00000010U
10287
10288 /*DQSG On-Die Termination*/
10289 #undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL
10290 #undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT
10291 #undef DDR_PHY_DX1GCR0_DQSGODT_MASK
10292 #define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL                                             0x40200204
10293 #define DDR_PHY_DX1GCR0_DQSGODT_SHIFT                                              3
10294 #define DDR_PHY_DX1GCR0_DQSGODT_MASK                                               0x00000008U
10295
10296 /*DQSG Output Enable*/
10297 #undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL
10298 #undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT
10299 #undef DDR_PHY_DX1GCR0_DQSGOE_MASK
10300 #define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL                                              0x40200204
10301 #define DDR_PHY_DX1GCR0_DQSGOE_SHIFT                                               2
10302 #define DDR_PHY_DX1GCR0_DQSGOE_MASK                                                0x00000004U
10303
10304 /*Reserved. Return zeroes on reads.*/
10305 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL
10306 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
10307 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK
10308 #define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
10309 #define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT                                         0
10310 #define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK                                          0x00000003U
10311
10312 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
10313 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL
10314 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
10315 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK
10316 #define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
10317 #define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT                                       29
10318 #define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK                                        0xE0000000U
10319
10320 /*Byte Lane VREF Pad Enable*/
10321 #undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL
10322 #undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
10323 #undef DDR_PHY_DX1GCR4_DXREFPEN_MASK
10324 #define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
10325 #define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT                                             28
10326 #define DDR_PHY_DX1GCR4_DXREFPEN_MASK                                              0x10000000U
10327
10328 /*Byte Lane Internal VREF Enable*/
10329 #undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL
10330 #undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
10331 #undef DDR_PHY_DX1GCR4_DXREFEEN_MASK
10332 #define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
10333 #define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT                                             26
10334 #define DDR_PHY_DX1GCR4_DXREFEEN_MASK                                              0x0C000000U
10335
10336 /*Byte Lane Single-End VREF Enable*/
10337 #undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL
10338 #undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
10339 #undef DDR_PHY_DX1GCR4_DXREFSEN_MASK
10340 #define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
10341 #define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT                                             25
10342 #define DDR_PHY_DX1GCR4_DXREFSEN_MASK                                              0x02000000U
10343
10344 /*Reserved. Returns zeros on reads.*/
10345 #undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL
10346 #undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
10347 #undef DDR_PHY_DX1GCR4_RESERVED_24_MASK
10348 #define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
10349 #define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT                                          24
10350 #define DDR_PHY_DX1GCR4_RESERVED_24_MASK                                           0x01000000U
10351
10352 /*External VREF generator REFSEL range select*/
10353 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL
10354 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
10355 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK
10356 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
10357 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT                                       23
10358 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK                                        0x00800000U
10359
10360 /*Byte Lane External VREF Select*/
10361 #undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL
10362 #undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
10363 #undef DDR_PHY_DX1GCR4_DXREFESEL_MASK
10364 #define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
10365 #define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT                                            16
10366 #define DDR_PHY_DX1GCR4_DXREFESEL_MASK                                             0x007F0000U
10367
10368 /*Single ended VREF generator REFSEL range select*/
10369 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL
10370 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
10371 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK
10372 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
10373 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT                                       15
10374 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
10375
10376 /*Byte Lane Single-End VREF Select*/
10377 #undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL
10378 #undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
10379 #undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK
10380 #define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
10381 #define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT                                            8
10382 #define DDR_PHY_DX1GCR4_DXREFSSEL_MASK                                             0x00007F00U
10383
10384 /*Reserved. Returns zeros on reads.*/
10385 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL
10386 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
10387 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK
10388 #define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
10389 #define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT                                         6
10390 #define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK                                          0x000000C0U
10391
10392 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
10393 #undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL
10394 #undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
10395 #undef DDR_PHY_DX1GCR4_DXREFIEN_MASK
10396 #define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
10397 #define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT                                             2
10398 #define DDR_PHY_DX1GCR4_DXREFIEN_MASK                                              0x0000003CU
10399
10400 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
10401 #undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL
10402 #undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
10403 #undef DDR_PHY_DX1GCR4_DXREFIMON_MASK
10404 #define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
10405 #define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT                                            0
10406 #define DDR_PHY_DX1GCR4_DXREFIMON_MASK                                             0x00000003U
10407
10408 /*Reserved. Returns zeros on reads.*/
10409 #undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL
10410 #undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
10411 #undef DDR_PHY_DX1GCR5_RESERVED_31_MASK
10412 #define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL                                         0x09090909
10413 #define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT                                          31
10414 #define DDR_PHY_DX1GCR5_RESERVED_31_MASK                                           0x80000000U
10415
10416 /*Byte Lane internal VREF Select for Rank 3*/
10417 #undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL
10418 #undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
10419 #undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK
10420 #define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL                                         0x09090909
10421 #define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT                                          24
10422 #define DDR_PHY_DX1GCR5_DXREFISELR3_MASK                                           0x7F000000U
10423
10424 /*Reserved. Returns zeros on reads.*/
10425 #undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL
10426 #undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
10427 #undef DDR_PHY_DX1GCR5_RESERVED_23_MASK
10428 #define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL                                         0x09090909
10429 #define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT                                          23
10430 #define DDR_PHY_DX1GCR5_RESERVED_23_MASK                                           0x00800000U
10431
10432 /*Byte Lane internal VREF Select for Rank 2*/
10433 #undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL
10434 #undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
10435 #undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK
10436 #define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL                                         0x09090909
10437 #define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT                                          16
10438 #define DDR_PHY_DX1GCR5_DXREFISELR2_MASK                                           0x007F0000U
10439
10440 /*Reserved. Returns zeros on reads.*/
10441 #undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL
10442 #undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
10443 #undef DDR_PHY_DX1GCR5_RESERVED_15_MASK
10444 #define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL                                         0x09090909
10445 #define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT                                          15
10446 #define DDR_PHY_DX1GCR5_RESERVED_15_MASK                                           0x00008000U
10447
10448 /*Byte Lane internal VREF Select for Rank 1*/
10449 #undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL
10450 #undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
10451 #undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK
10452 #define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL                                         0x09090909
10453 #define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT                                          8
10454 #define DDR_PHY_DX1GCR5_DXREFISELR1_MASK                                           0x00007F00U
10455
10456 /*Reserved. Returns zeros on reads.*/
10457 #undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL
10458 #undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
10459 #undef DDR_PHY_DX1GCR5_RESERVED_7_MASK
10460 #define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL                                          0x09090909
10461 #define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT                                           7
10462 #define DDR_PHY_DX1GCR5_RESERVED_7_MASK                                            0x00000080U
10463
10464 /*Byte Lane internal VREF Select for Rank 0*/
10465 #undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL
10466 #undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
10467 #undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK
10468 #define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL                                         0x09090909
10469 #define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT                                          0
10470 #define DDR_PHY_DX1GCR5_DXREFISELR0_MASK                                           0x0000007FU
10471
10472 /*Reserved. Returns zeros on reads.*/
10473 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL
10474 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
10475 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK
10476 #define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
10477 #define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT                                       30
10478 #define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK                                        0xC0000000U
10479
10480 /*DRAM DQ VREF Select for Rank3*/
10481 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL
10482 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
10483 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK
10484 #define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
10485 #define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT                                           24
10486 #define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK                                            0x3F000000U
10487
10488 /*Reserved. Returns zeros on reads.*/
10489 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL
10490 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
10491 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK
10492 #define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
10493 #define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT                                       22
10494 #define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK                                        0x00C00000U
10495
10496 /*DRAM DQ VREF Select for Rank2*/
10497 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL
10498 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
10499 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK
10500 #define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
10501 #define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT                                           16
10502 #define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK                                            0x003F0000U
10503
10504 /*Reserved. Returns zeros on reads.*/
10505 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL
10506 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
10507 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK
10508 #define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
10509 #define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT                                       14
10510 #define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK                                        0x0000C000U
10511
10512 /*DRAM DQ VREF Select for Rank1*/
10513 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL
10514 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
10515 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK
10516 #define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
10517 #define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT                                           8
10518 #define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK                                            0x00003F00U
10519
10520 /*Reserved. Returns zeros on reads.*/
10521 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL
10522 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
10523 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK
10524 #define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
10525 #define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT                                         6
10526 #define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK                                          0x000000C0U
10527
10528 /*DRAM DQ VREF Select for Rank0*/
10529 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL
10530 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
10531 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK
10532 #define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
10533 #define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT                                           0
10534 #define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK                                            0x0000003FU
10535
10536 /*Reserved. Return zeroes on reads.*/
10537 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL
10538 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT
10539 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK
10540 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
10541 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT                                     25
10542 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
10543
10544 /*Reserved. Caution, do not write to this register field.*/
10545 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL
10546 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT
10547 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK
10548 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
10549 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT                                     16
10550 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
10551
10552 /*Reserved. Return zeroes on reads.*/
10553 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL
10554 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT
10555 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK
10556 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
10557 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT                                      9
10558 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
10559
10560 /*Read DQS Gating Delay*/
10561 #undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL
10562 #undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT
10563 #undef DDR_PHY_DX1LCDLR2_DQSGD_MASK
10564 #define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL                                             0x00000000
10565 #define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT                                              0
10566 #define DDR_PHY_DX1LCDLR2_DQSGD_MASK                                               0x000001FFU
10567
10568 /*Reserved. Return zeroes on reads.*/
10569 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL
10570 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT
10571 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK
10572 #define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
10573 #define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT                                       27
10574 #define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK                                        0xF8000000U
10575
10576 /*DQ Write Path Latency Pipeline*/
10577 #undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL
10578 #undef DDR_PHY_DX1GTR0_WDQSL_SHIFT
10579 #undef DDR_PHY_DX1GTR0_WDQSL_MASK
10580 #define DDR_PHY_DX1GTR0_WDQSL_DEFVAL                                               0x00020000
10581 #define DDR_PHY_DX1GTR0_WDQSL_SHIFT                                                24
10582 #define DDR_PHY_DX1GTR0_WDQSL_MASK                                                 0x07000000U
10583
10584 /*Reserved. Caution, do not write to this register field.*/
10585 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL
10586 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT
10587 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK
10588 #define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
10589 #define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT                                       20
10590 #define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK                                        0x00F00000U
10591
10592 /*Write Leveling System Latency*/
10593 #undef DDR_PHY_DX1GTR0_WLSL_DEFVAL
10594 #undef DDR_PHY_DX1GTR0_WLSL_SHIFT
10595 #undef DDR_PHY_DX1GTR0_WLSL_MASK
10596 #define DDR_PHY_DX1GTR0_WLSL_DEFVAL                                                0x00020000
10597 #define DDR_PHY_DX1GTR0_WLSL_SHIFT                                                 16
10598 #define DDR_PHY_DX1GTR0_WLSL_MASK                                                  0x000F0000U
10599
10600 /*Reserved. Return zeroes on reads.*/
10601 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL
10602 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT
10603 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK
10604 #define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
10605 #define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT                                       13
10606 #define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK                                        0x0000E000U
10607
10608 /*Reserved. Caution, do not write to this register field.*/
10609 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL
10610 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT
10611 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK
10612 #define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
10613 #define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT                                        8
10614 #define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK                                         0x00001F00U
10615
10616 /*Reserved. Return zeroes on reads.*/
10617 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL
10618 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT
10619 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK
10620 #define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
10621 #define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT                                         5
10622 #define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK                                          0x000000E0U
10623
10624 /*DQS Gating System Latency*/
10625 #undef DDR_PHY_DX1GTR0_DGSL_DEFVAL
10626 #undef DDR_PHY_DX1GTR0_DGSL_SHIFT
10627 #undef DDR_PHY_DX1GTR0_DGSL_MASK
10628 #define DDR_PHY_DX1GTR0_DGSL_DEFVAL                                                0x00020000
10629 #define DDR_PHY_DX1GTR0_DGSL_SHIFT                                                 0
10630 #define DDR_PHY_DX1GTR0_DGSL_MASK                                                  0x0000001FU
10631
10632 /*Calibration Bypass*/
10633 #undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL
10634 #undef DDR_PHY_DX2GCR0_CALBYP_SHIFT
10635 #undef DDR_PHY_DX2GCR0_CALBYP_MASK
10636 #define DDR_PHY_DX2GCR0_CALBYP_DEFVAL                                              0x40200204
10637 #define DDR_PHY_DX2GCR0_CALBYP_SHIFT                                               31
10638 #define DDR_PHY_DX2GCR0_CALBYP_MASK                                                0x80000000U
10639
10640 /*Master Delay Line Enable*/
10641 #undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL
10642 #undef DDR_PHY_DX2GCR0_MDLEN_SHIFT
10643 #undef DDR_PHY_DX2GCR0_MDLEN_MASK
10644 #define DDR_PHY_DX2GCR0_MDLEN_DEFVAL                                               0x40200204
10645 #define DDR_PHY_DX2GCR0_MDLEN_SHIFT                                                30
10646 #define DDR_PHY_DX2GCR0_MDLEN_MASK                                                 0x40000000U
10647
10648 /*Configurable ODT(TE) Phase Shift*/
10649 #undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL
10650 #undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
10651 #undef DDR_PHY_DX2GCR0_CODTSHFT_MASK
10652 #define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL                                            0x40200204
10653 #define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT                                             28
10654 #define DDR_PHY_DX2GCR0_CODTSHFT_MASK                                              0x30000000U
10655
10656 /*DQS Duty Cycle Correction*/
10657 #undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL
10658 #undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT
10659 #undef DDR_PHY_DX2GCR0_DQSDCC_MASK
10660 #define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL                                              0x40200204
10661 #define DDR_PHY_DX2GCR0_DQSDCC_SHIFT                                               24
10662 #define DDR_PHY_DX2GCR0_DQSDCC_MASK                                                0x0F000000U
10663
10664 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
10665 #undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL
10666 #undef DDR_PHY_DX2GCR0_RDDLY_SHIFT
10667 #undef DDR_PHY_DX2GCR0_RDDLY_MASK
10668 #define DDR_PHY_DX2GCR0_RDDLY_DEFVAL                                               0x40200204
10669 #define DDR_PHY_DX2GCR0_RDDLY_SHIFT                                                20
10670 #define DDR_PHY_DX2GCR0_RDDLY_MASK                                                 0x00F00000U
10671
10672 /*Reserved. Return zeroes on reads.*/
10673 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL
10674 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
10675 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK
10676 #define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
10677 #define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT                                       14
10678 #define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK                                        0x000FC000U
10679
10680 /*DQSNSE Power Down Receiver*/
10681 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL
10682 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
10683 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK
10684 #define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
10685 #define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT                                            13
10686 #define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK                                             0x00002000U
10687
10688 /*DQSSE Power Down Receiver*/
10689 #undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL
10690 #undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
10691 #undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK
10692 #define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL                                            0x40200204
10693 #define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT                                             12
10694 #define DDR_PHY_DX2GCR0_DQSSEPDR_MASK                                              0x00001000U
10695
10696 /*RTT On Additive Latency*/
10697 #undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL
10698 #undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT
10699 #undef DDR_PHY_DX2GCR0_RTTOAL_MASK
10700 #define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL                                              0x40200204
10701 #define DDR_PHY_DX2GCR0_RTTOAL_SHIFT                                               11
10702 #define DDR_PHY_DX2GCR0_RTTOAL_MASK                                                0x00000800U
10703
10704 /*RTT Output Hold*/
10705 #undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL
10706 #undef DDR_PHY_DX2GCR0_RTTOH_SHIFT
10707 #undef DDR_PHY_DX2GCR0_RTTOH_MASK
10708 #define DDR_PHY_DX2GCR0_RTTOH_DEFVAL                                               0x40200204
10709 #define DDR_PHY_DX2GCR0_RTTOH_SHIFT                                                9
10710 #define DDR_PHY_DX2GCR0_RTTOH_MASK                                                 0x00000600U
10711
10712 /*Configurable PDR Phase Shift*/
10713 #undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL
10714 #undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
10715 #undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK
10716 #define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL                                            0x40200204
10717 #define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT                                             7
10718 #define DDR_PHY_DX2GCR0_CPDRSHFT_MASK                                              0x00000180U
10719
10720 /*DQSR Power Down*/
10721 #undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL
10722 #undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT
10723 #undef DDR_PHY_DX2GCR0_DQSRPD_MASK
10724 #define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL                                              0x40200204
10725 #define DDR_PHY_DX2GCR0_DQSRPD_SHIFT                                               6
10726 #define DDR_PHY_DX2GCR0_DQSRPD_MASK                                                0x00000040U
10727
10728 /*DQSG Power Down Receiver*/
10729 #undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL
10730 #undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
10731 #undef DDR_PHY_DX2GCR0_DQSGPDR_MASK
10732 #define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL                                             0x40200204
10733 #define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT                                              5
10734 #define DDR_PHY_DX2GCR0_DQSGPDR_MASK                                               0x00000020U
10735
10736 /*Reserved. Return zeroes on reads.*/
10737 #undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL
10738 #undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
10739 #undef DDR_PHY_DX2GCR0_RESERVED_4_MASK
10740 #define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL                                          0x40200204
10741 #define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT                                           4
10742 #define DDR_PHY_DX2GCR0_RESERVED_4_MASK                                            0x00000010U
10743
10744 /*DQSG On-Die Termination*/
10745 #undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL
10746 #undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT
10747 #undef DDR_PHY_DX2GCR0_DQSGODT_MASK
10748 #define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL                                             0x40200204
10749 #define DDR_PHY_DX2GCR0_DQSGODT_SHIFT                                              3
10750 #define DDR_PHY_DX2GCR0_DQSGODT_MASK                                               0x00000008U
10751
10752 /*DQSG Output Enable*/
10753 #undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL
10754 #undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT
10755 #undef DDR_PHY_DX2GCR0_DQSGOE_MASK
10756 #define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL                                              0x40200204
10757 #define DDR_PHY_DX2GCR0_DQSGOE_SHIFT                                               2
10758 #define DDR_PHY_DX2GCR0_DQSGOE_MASK                                                0x00000004U
10759
10760 /*Reserved. Return zeroes on reads.*/
10761 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL
10762 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
10763 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK
10764 #define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
10765 #define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT                                         0
10766 #define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK                                          0x00000003U
10767
10768 /*Enables the PDR mode for DQ[7:0]*/
10769 #undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL
10770 #undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
10771 #undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK
10772 #define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
10773 #define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT                                            16
10774 #define DDR_PHY_DX2GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
10775
10776 /*Reserved. Returns zeroes on reads.*/
10777 #undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL
10778 #undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
10779 #undef DDR_PHY_DX2GCR1_RESERVED_15_MASK
10780 #define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
10781 #define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT                                          15
10782 #define DDR_PHY_DX2GCR1_RESERVED_15_MASK                                           0x00008000U
10783
10784 /*Select the delayed or non-delayed read data strobe #*/
10785 #undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL
10786 #undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT
10787 #undef DDR_PHY_DX2GCR1_QSNSEL_MASK
10788 #define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL                                              0x00007FFF
10789 #define DDR_PHY_DX2GCR1_QSNSEL_SHIFT                                               14
10790 #define DDR_PHY_DX2GCR1_QSNSEL_MASK                                                0x00004000U
10791
10792 /*Select the delayed or non-delayed read data strobe*/
10793 #undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL
10794 #undef DDR_PHY_DX2GCR1_QSSEL_SHIFT
10795 #undef DDR_PHY_DX2GCR1_QSSEL_MASK
10796 #define DDR_PHY_DX2GCR1_QSSEL_DEFVAL                                               0x00007FFF
10797 #define DDR_PHY_DX2GCR1_QSSEL_SHIFT                                                13
10798 #define DDR_PHY_DX2GCR1_QSSEL_MASK                                                 0x00002000U
10799
10800 /*Enables Read Data Strobe in a byte lane*/
10801 #undef DDR_PHY_DX2GCR1_OEEN_DEFVAL
10802 #undef DDR_PHY_DX2GCR1_OEEN_SHIFT
10803 #undef DDR_PHY_DX2GCR1_OEEN_MASK
10804 #define DDR_PHY_DX2GCR1_OEEN_DEFVAL                                                0x00007FFF
10805 #define DDR_PHY_DX2GCR1_OEEN_SHIFT                                                 12
10806 #define DDR_PHY_DX2GCR1_OEEN_MASK                                                  0x00001000U
10807
10808 /*Enables PDR in a byte lane*/
10809 #undef DDR_PHY_DX2GCR1_PDREN_DEFVAL
10810 #undef DDR_PHY_DX2GCR1_PDREN_SHIFT
10811 #undef DDR_PHY_DX2GCR1_PDREN_MASK
10812 #define DDR_PHY_DX2GCR1_PDREN_DEFVAL                                               0x00007FFF
10813 #define DDR_PHY_DX2GCR1_PDREN_SHIFT                                                11
10814 #define DDR_PHY_DX2GCR1_PDREN_MASK                                                 0x00000800U
10815
10816 /*Enables ODT/TE in a byte lane*/
10817 #undef DDR_PHY_DX2GCR1_TEEN_DEFVAL
10818 #undef DDR_PHY_DX2GCR1_TEEN_SHIFT
10819 #undef DDR_PHY_DX2GCR1_TEEN_MASK
10820 #define DDR_PHY_DX2GCR1_TEEN_DEFVAL                                                0x00007FFF
10821 #define DDR_PHY_DX2GCR1_TEEN_SHIFT                                                 10
10822 #define DDR_PHY_DX2GCR1_TEEN_MASK                                                  0x00000400U
10823
10824 /*Enables Write Data strobe in a byte lane*/
10825 #undef DDR_PHY_DX2GCR1_DSEN_DEFVAL
10826 #undef DDR_PHY_DX2GCR1_DSEN_SHIFT
10827 #undef DDR_PHY_DX2GCR1_DSEN_MASK
10828 #define DDR_PHY_DX2GCR1_DSEN_DEFVAL                                                0x00007FFF
10829 #define DDR_PHY_DX2GCR1_DSEN_SHIFT                                                 9
10830 #define DDR_PHY_DX2GCR1_DSEN_MASK                                                  0x00000200U
10831
10832 /*Enables DM pin in a byte lane*/
10833 #undef DDR_PHY_DX2GCR1_DMEN_DEFVAL
10834 #undef DDR_PHY_DX2GCR1_DMEN_SHIFT
10835 #undef DDR_PHY_DX2GCR1_DMEN_MASK
10836 #define DDR_PHY_DX2GCR1_DMEN_DEFVAL                                                0x00007FFF
10837 #define DDR_PHY_DX2GCR1_DMEN_SHIFT                                                 8
10838 #define DDR_PHY_DX2GCR1_DMEN_MASK                                                  0x00000100U
10839
10840 /*Enables DQ corresponding to each bit in a byte*/
10841 #undef DDR_PHY_DX2GCR1_DQEN_DEFVAL
10842 #undef DDR_PHY_DX2GCR1_DQEN_SHIFT
10843 #undef DDR_PHY_DX2GCR1_DQEN_MASK
10844 #define DDR_PHY_DX2GCR1_DQEN_DEFVAL                                                0x00007FFF
10845 #define DDR_PHY_DX2GCR1_DQEN_SHIFT                                                 0
10846 #define DDR_PHY_DX2GCR1_DQEN_MASK                                                  0x000000FFU
10847
10848 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
10849 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL
10850 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
10851 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK
10852 #define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
10853 #define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT                                       29
10854 #define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK                                        0xE0000000U
10855
10856 /*Byte Lane VREF Pad Enable*/
10857 #undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL
10858 #undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
10859 #undef DDR_PHY_DX2GCR4_DXREFPEN_MASK
10860 #define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
10861 #define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT                                             28
10862 #define DDR_PHY_DX2GCR4_DXREFPEN_MASK                                              0x10000000U
10863
10864 /*Byte Lane Internal VREF Enable*/
10865 #undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL
10866 #undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
10867 #undef DDR_PHY_DX2GCR4_DXREFEEN_MASK
10868 #define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
10869 #define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT                                             26
10870 #define DDR_PHY_DX2GCR4_DXREFEEN_MASK                                              0x0C000000U
10871
10872 /*Byte Lane Single-End VREF Enable*/
10873 #undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL
10874 #undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
10875 #undef DDR_PHY_DX2GCR4_DXREFSEN_MASK
10876 #define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
10877 #define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT                                             25
10878 #define DDR_PHY_DX2GCR4_DXREFSEN_MASK                                              0x02000000U
10879
10880 /*Reserved. Returns zeros on reads.*/
10881 #undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL
10882 #undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
10883 #undef DDR_PHY_DX2GCR4_RESERVED_24_MASK
10884 #define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
10885 #define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT                                          24
10886 #define DDR_PHY_DX2GCR4_RESERVED_24_MASK                                           0x01000000U
10887
10888 /*External VREF generator REFSEL range select*/
10889 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL
10890 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
10891 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK
10892 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
10893 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT                                       23
10894 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK                                        0x00800000U
10895
10896 /*Byte Lane External VREF Select*/
10897 #undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL
10898 #undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
10899 #undef DDR_PHY_DX2GCR4_DXREFESEL_MASK
10900 #define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
10901 #define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT                                            16
10902 #define DDR_PHY_DX2GCR4_DXREFESEL_MASK                                             0x007F0000U
10903
10904 /*Single ended VREF generator REFSEL range select*/
10905 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL
10906 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
10907 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK
10908 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
10909 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT                                       15
10910 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
10911
10912 /*Byte Lane Single-End VREF Select*/
10913 #undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL
10914 #undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
10915 #undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK
10916 #define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
10917 #define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT                                            8
10918 #define DDR_PHY_DX2GCR4_DXREFSSEL_MASK                                             0x00007F00U
10919
10920 /*Reserved. Returns zeros on reads.*/
10921 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL
10922 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
10923 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK
10924 #define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
10925 #define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT                                         6
10926 #define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK                                          0x000000C0U
10927
10928 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
10929 #undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL
10930 #undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
10931 #undef DDR_PHY_DX2GCR4_DXREFIEN_MASK
10932 #define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
10933 #define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT                                             2
10934 #define DDR_PHY_DX2GCR4_DXREFIEN_MASK                                              0x0000003CU
10935
10936 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
10937 #undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL
10938 #undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
10939 #undef DDR_PHY_DX2GCR4_DXREFIMON_MASK
10940 #define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
10941 #define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT                                            0
10942 #define DDR_PHY_DX2GCR4_DXREFIMON_MASK                                             0x00000003U
10943
10944 /*Reserved. Returns zeros on reads.*/
10945 #undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL
10946 #undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
10947 #undef DDR_PHY_DX2GCR5_RESERVED_31_MASK
10948 #define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL                                         0x09090909
10949 #define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT                                          31
10950 #define DDR_PHY_DX2GCR5_RESERVED_31_MASK                                           0x80000000U
10951
10952 /*Byte Lane internal VREF Select for Rank 3*/
10953 #undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL
10954 #undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
10955 #undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK
10956 #define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL                                         0x09090909
10957 #define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT                                          24
10958 #define DDR_PHY_DX2GCR5_DXREFISELR3_MASK                                           0x7F000000U
10959
10960 /*Reserved. Returns zeros on reads.*/
10961 #undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL
10962 #undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
10963 #undef DDR_PHY_DX2GCR5_RESERVED_23_MASK
10964 #define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL                                         0x09090909
10965 #define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT                                          23
10966 #define DDR_PHY_DX2GCR5_RESERVED_23_MASK                                           0x00800000U
10967
10968 /*Byte Lane internal VREF Select for Rank 2*/
10969 #undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL
10970 #undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
10971 #undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK
10972 #define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL                                         0x09090909
10973 #define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT                                          16
10974 #define DDR_PHY_DX2GCR5_DXREFISELR2_MASK                                           0x007F0000U
10975
10976 /*Reserved. Returns zeros on reads.*/
10977 #undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL
10978 #undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
10979 #undef DDR_PHY_DX2GCR5_RESERVED_15_MASK
10980 #define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL                                         0x09090909
10981 #define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT                                          15
10982 #define DDR_PHY_DX2GCR5_RESERVED_15_MASK                                           0x00008000U
10983
10984 /*Byte Lane internal VREF Select for Rank 1*/
10985 #undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL
10986 #undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
10987 #undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK
10988 #define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL                                         0x09090909
10989 #define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT                                          8
10990 #define DDR_PHY_DX2GCR5_DXREFISELR1_MASK                                           0x00007F00U
10991
10992 /*Reserved. Returns zeros on reads.*/
10993 #undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL
10994 #undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
10995 #undef DDR_PHY_DX2GCR5_RESERVED_7_MASK
10996 #define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL                                          0x09090909
10997 #define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT                                           7
10998 #define DDR_PHY_DX2GCR5_RESERVED_7_MASK                                            0x00000080U
10999
11000 /*Byte Lane internal VREF Select for Rank 0*/
11001 #undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL
11002 #undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
11003 #undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK
11004 #define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL                                         0x09090909
11005 #define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT                                          0
11006 #define DDR_PHY_DX2GCR5_DXREFISELR0_MASK                                           0x0000007FU
11007
11008 /*Reserved. Returns zeros on reads.*/
11009 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL
11010 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
11011 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK
11012 #define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
11013 #define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT                                       30
11014 #define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK                                        0xC0000000U
11015
11016 /*DRAM DQ VREF Select for Rank3*/
11017 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL
11018 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
11019 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK
11020 #define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
11021 #define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT                                           24
11022 #define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK                                            0x3F000000U
11023
11024 /*Reserved. Returns zeros on reads.*/
11025 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL
11026 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
11027 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK
11028 #define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
11029 #define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT                                       22
11030 #define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK                                        0x00C00000U
11031
11032 /*DRAM DQ VREF Select for Rank2*/
11033 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL
11034 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
11035 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK
11036 #define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
11037 #define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT                                           16
11038 #define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK                                            0x003F0000U
11039
11040 /*Reserved. Returns zeros on reads.*/
11041 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL
11042 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
11043 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK
11044 #define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
11045 #define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT                                       14
11046 #define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK                                        0x0000C000U
11047
11048 /*DRAM DQ VREF Select for Rank1*/
11049 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL
11050 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
11051 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK
11052 #define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
11053 #define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT                                           8
11054 #define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK                                            0x00003F00U
11055
11056 /*Reserved. Returns zeros on reads.*/
11057 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL
11058 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
11059 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK
11060 #define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
11061 #define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT                                         6
11062 #define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK                                          0x000000C0U
11063
11064 /*DRAM DQ VREF Select for Rank0*/
11065 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL
11066 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
11067 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK
11068 #define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
11069 #define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT                                           0
11070 #define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK                                            0x0000003FU
11071
11072 /*Reserved. Return zeroes on reads.*/
11073 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL
11074 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT
11075 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK
11076 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
11077 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT                                     25
11078 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
11079
11080 /*Reserved. Caution, do not write to this register field.*/
11081 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL
11082 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT
11083 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK
11084 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
11085 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT                                     16
11086 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
11087
11088 /*Reserved. Return zeroes on reads.*/
11089 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL
11090 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT
11091 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK
11092 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
11093 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT                                      9
11094 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
11095
11096 /*Read DQS Gating Delay*/
11097 #undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL
11098 #undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT
11099 #undef DDR_PHY_DX2LCDLR2_DQSGD_MASK
11100 #define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL                                             0x00000000
11101 #define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT                                              0
11102 #define DDR_PHY_DX2LCDLR2_DQSGD_MASK                                               0x000001FFU
11103
11104 /*Reserved. Return zeroes on reads.*/
11105 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL
11106 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT
11107 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK
11108 #define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
11109 #define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT                                       27
11110 #define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK                                        0xF8000000U
11111
11112 /*DQ Write Path Latency Pipeline*/
11113 #undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL
11114 #undef DDR_PHY_DX2GTR0_WDQSL_SHIFT
11115 #undef DDR_PHY_DX2GTR0_WDQSL_MASK
11116 #define DDR_PHY_DX2GTR0_WDQSL_DEFVAL                                               0x00020000
11117 #define DDR_PHY_DX2GTR0_WDQSL_SHIFT                                                24
11118 #define DDR_PHY_DX2GTR0_WDQSL_MASK                                                 0x07000000U
11119
11120 /*Reserved. Caution, do not write to this register field.*/
11121 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL
11122 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT
11123 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK
11124 #define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
11125 #define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT                                       20
11126 #define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK                                        0x00F00000U
11127
11128 /*Write Leveling System Latency*/
11129 #undef DDR_PHY_DX2GTR0_WLSL_DEFVAL
11130 #undef DDR_PHY_DX2GTR0_WLSL_SHIFT
11131 #undef DDR_PHY_DX2GTR0_WLSL_MASK
11132 #define DDR_PHY_DX2GTR0_WLSL_DEFVAL                                                0x00020000
11133 #define DDR_PHY_DX2GTR0_WLSL_SHIFT                                                 16
11134 #define DDR_PHY_DX2GTR0_WLSL_MASK                                                  0x000F0000U
11135
11136 /*Reserved. Return zeroes on reads.*/
11137 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL
11138 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT
11139 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK
11140 #define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
11141 #define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT                                       13
11142 #define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK                                        0x0000E000U
11143
11144 /*Reserved. Caution, do not write to this register field.*/
11145 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL
11146 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT
11147 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK
11148 #define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
11149 #define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT                                        8
11150 #define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK                                         0x00001F00U
11151
11152 /*Reserved. Return zeroes on reads.*/
11153 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL
11154 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT
11155 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK
11156 #define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
11157 #define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT                                         5
11158 #define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK                                          0x000000E0U
11159
11160 /*DQS Gating System Latency*/
11161 #undef DDR_PHY_DX2GTR0_DGSL_DEFVAL
11162 #undef DDR_PHY_DX2GTR0_DGSL_SHIFT
11163 #undef DDR_PHY_DX2GTR0_DGSL_MASK
11164 #define DDR_PHY_DX2GTR0_DGSL_DEFVAL                                                0x00020000
11165 #define DDR_PHY_DX2GTR0_DGSL_SHIFT                                                 0
11166 #define DDR_PHY_DX2GTR0_DGSL_MASK                                                  0x0000001FU
11167
11168 /*Calibration Bypass*/
11169 #undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL
11170 #undef DDR_PHY_DX3GCR0_CALBYP_SHIFT
11171 #undef DDR_PHY_DX3GCR0_CALBYP_MASK
11172 #define DDR_PHY_DX3GCR0_CALBYP_DEFVAL                                              0x40200204
11173 #define DDR_PHY_DX3GCR0_CALBYP_SHIFT                                               31
11174 #define DDR_PHY_DX3GCR0_CALBYP_MASK                                                0x80000000U
11175
11176 /*Master Delay Line Enable*/
11177 #undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL
11178 #undef DDR_PHY_DX3GCR0_MDLEN_SHIFT
11179 #undef DDR_PHY_DX3GCR0_MDLEN_MASK
11180 #define DDR_PHY_DX3GCR0_MDLEN_DEFVAL                                               0x40200204
11181 #define DDR_PHY_DX3GCR0_MDLEN_SHIFT                                                30
11182 #define DDR_PHY_DX3GCR0_MDLEN_MASK                                                 0x40000000U
11183
11184 /*Configurable ODT(TE) Phase Shift*/
11185 #undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL
11186 #undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
11187 #undef DDR_PHY_DX3GCR0_CODTSHFT_MASK
11188 #define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL                                            0x40200204
11189 #define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT                                             28
11190 #define DDR_PHY_DX3GCR0_CODTSHFT_MASK                                              0x30000000U
11191
11192 /*DQS Duty Cycle Correction*/
11193 #undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL
11194 #undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT
11195 #undef DDR_PHY_DX3GCR0_DQSDCC_MASK
11196 #define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL                                              0x40200204
11197 #define DDR_PHY_DX3GCR0_DQSDCC_SHIFT                                               24
11198 #define DDR_PHY_DX3GCR0_DQSDCC_MASK                                                0x0F000000U
11199
11200 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
11201 #undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL
11202 #undef DDR_PHY_DX3GCR0_RDDLY_SHIFT
11203 #undef DDR_PHY_DX3GCR0_RDDLY_MASK
11204 #define DDR_PHY_DX3GCR0_RDDLY_DEFVAL                                               0x40200204
11205 #define DDR_PHY_DX3GCR0_RDDLY_SHIFT                                                20
11206 #define DDR_PHY_DX3GCR0_RDDLY_MASK                                                 0x00F00000U
11207
11208 /*Reserved. Return zeroes on reads.*/
11209 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL
11210 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
11211 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK
11212 #define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
11213 #define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT                                       14
11214 #define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK                                        0x000FC000U
11215
11216 /*DQSNSE Power Down Receiver*/
11217 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL
11218 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
11219 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK
11220 #define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
11221 #define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT                                            13
11222 #define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK                                             0x00002000U
11223
11224 /*DQSSE Power Down Receiver*/
11225 #undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL
11226 #undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
11227 #undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK
11228 #define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL                                            0x40200204
11229 #define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT                                             12
11230 #define DDR_PHY_DX3GCR0_DQSSEPDR_MASK                                              0x00001000U
11231
11232 /*RTT On Additive Latency*/
11233 #undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL
11234 #undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT
11235 #undef DDR_PHY_DX3GCR0_RTTOAL_MASK
11236 #define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL                                              0x40200204
11237 #define DDR_PHY_DX3GCR0_RTTOAL_SHIFT                                               11
11238 #define DDR_PHY_DX3GCR0_RTTOAL_MASK                                                0x00000800U
11239
11240 /*RTT Output Hold*/
11241 #undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL
11242 #undef DDR_PHY_DX3GCR0_RTTOH_SHIFT
11243 #undef DDR_PHY_DX3GCR0_RTTOH_MASK
11244 #define DDR_PHY_DX3GCR0_RTTOH_DEFVAL                                               0x40200204
11245 #define DDR_PHY_DX3GCR0_RTTOH_SHIFT                                                9
11246 #define DDR_PHY_DX3GCR0_RTTOH_MASK                                                 0x00000600U
11247
11248 /*Configurable PDR Phase Shift*/
11249 #undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL
11250 #undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
11251 #undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK
11252 #define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL                                            0x40200204
11253 #define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT                                             7
11254 #define DDR_PHY_DX3GCR0_CPDRSHFT_MASK                                              0x00000180U
11255
11256 /*DQSR Power Down*/
11257 #undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL
11258 #undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT
11259 #undef DDR_PHY_DX3GCR0_DQSRPD_MASK
11260 #define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL                                              0x40200204
11261 #define DDR_PHY_DX3GCR0_DQSRPD_SHIFT                                               6
11262 #define DDR_PHY_DX3GCR0_DQSRPD_MASK                                                0x00000040U
11263
11264 /*DQSG Power Down Receiver*/
11265 #undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL
11266 #undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
11267 #undef DDR_PHY_DX3GCR0_DQSGPDR_MASK
11268 #define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL                                             0x40200204
11269 #define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT                                              5
11270 #define DDR_PHY_DX3GCR0_DQSGPDR_MASK                                               0x00000020U
11271
11272 /*Reserved. Return zeroes on reads.*/
11273 #undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL
11274 #undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
11275 #undef DDR_PHY_DX3GCR0_RESERVED_4_MASK
11276 #define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL                                          0x40200204
11277 #define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT                                           4
11278 #define DDR_PHY_DX3GCR0_RESERVED_4_MASK                                            0x00000010U
11279
11280 /*DQSG On-Die Termination*/
11281 #undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL
11282 #undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT
11283 #undef DDR_PHY_DX3GCR0_DQSGODT_MASK
11284 #define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL                                             0x40200204
11285 #define DDR_PHY_DX3GCR0_DQSGODT_SHIFT                                              3
11286 #define DDR_PHY_DX3GCR0_DQSGODT_MASK                                               0x00000008U
11287
11288 /*DQSG Output Enable*/
11289 #undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL
11290 #undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT
11291 #undef DDR_PHY_DX3GCR0_DQSGOE_MASK
11292 #define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL                                              0x40200204
11293 #define DDR_PHY_DX3GCR0_DQSGOE_SHIFT                                               2
11294 #define DDR_PHY_DX3GCR0_DQSGOE_MASK                                                0x00000004U
11295
11296 /*Reserved. Return zeroes on reads.*/
11297 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL
11298 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
11299 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK
11300 #define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
11301 #define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT                                         0
11302 #define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK                                          0x00000003U
11303
11304 /*Enables the PDR mode for DQ[7:0]*/
11305 #undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL
11306 #undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
11307 #undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK
11308 #define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
11309 #define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT                                            16
11310 #define DDR_PHY_DX3GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
11311
11312 /*Reserved. Returns zeroes on reads.*/
11313 #undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL
11314 #undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
11315 #undef DDR_PHY_DX3GCR1_RESERVED_15_MASK
11316 #define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
11317 #define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT                                          15
11318 #define DDR_PHY_DX3GCR1_RESERVED_15_MASK                                           0x00008000U
11319
11320 /*Select the delayed or non-delayed read data strobe #*/
11321 #undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL
11322 #undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT
11323 #undef DDR_PHY_DX3GCR1_QSNSEL_MASK
11324 #define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL                                              0x00007FFF
11325 #define DDR_PHY_DX3GCR1_QSNSEL_SHIFT                                               14
11326 #define DDR_PHY_DX3GCR1_QSNSEL_MASK                                                0x00004000U
11327
11328 /*Select the delayed or non-delayed read data strobe*/
11329 #undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL
11330 #undef DDR_PHY_DX3GCR1_QSSEL_SHIFT
11331 #undef DDR_PHY_DX3GCR1_QSSEL_MASK
11332 #define DDR_PHY_DX3GCR1_QSSEL_DEFVAL                                               0x00007FFF
11333 #define DDR_PHY_DX3GCR1_QSSEL_SHIFT                                                13
11334 #define DDR_PHY_DX3GCR1_QSSEL_MASK                                                 0x00002000U
11335
11336 /*Enables Read Data Strobe in a byte lane*/
11337 #undef DDR_PHY_DX3GCR1_OEEN_DEFVAL
11338 #undef DDR_PHY_DX3GCR1_OEEN_SHIFT
11339 #undef DDR_PHY_DX3GCR1_OEEN_MASK
11340 #define DDR_PHY_DX3GCR1_OEEN_DEFVAL                                                0x00007FFF
11341 #define DDR_PHY_DX3GCR1_OEEN_SHIFT                                                 12
11342 #define DDR_PHY_DX3GCR1_OEEN_MASK                                                  0x00001000U
11343
11344 /*Enables PDR in a byte lane*/
11345 #undef DDR_PHY_DX3GCR1_PDREN_DEFVAL
11346 #undef DDR_PHY_DX3GCR1_PDREN_SHIFT
11347 #undef DDR_PHY_DX3GCR1_PDREN_MASK
11348 #define DDR_PHY_DX3GCR1_PDREN_DEFVAL                                               0x00007FFF
11349 #define DDR_PHY_DX3GCR1_PDREN_SHIFT                                                11
11350 #define DDR_PHY_DX3GCR1_PDREN_MASK                                                 0x00000800U
11351
11352 /*Enables ODT/TE in a byte lane*/
11353 #undef DDR_PHY_DX3GCR1_TEEN_DEFVAL
11354 #undef DDR_PHY_DX3GCR1_TEEN_SHIFT
11355 #undef DDR_PHY_DX3GCR1_TEEN_MASK
11356 #define DDR_PHY_DX3GCR1_TEEN_DEFVAL                                                0x00007FFF
11357 #define DDR_PHY_DX3GCR1_TEEN_SHIFT                                                 10
11358 #define DDR_PHY_DX3GCR1_TEEN_MASK                                                  0x00000400U
11359
11360 /*Enables Write Data strobe in a byte lane*/
11361 #undef DDR_PHY_DX3GCR1_DSEN_DEFVAL
11362 #undef DDR_PHY_DX3GCR1_DSEN_SHIFT
11363 #undef DDR_PHY_DX3GCR1_DSEN_MASK
11364 #define DDR_PHY_DX3GCR1_DSEN_DEFVAL                                                0x00007FFF
11365 #define DDR_PHY_DX3GCR1_DSEN_SHIFT                                                 9
11366 #define DDR_PHY_DX3GCR1_DSEN_MASK                                                  0x00000200U
11367
11368 /*Enables DM pin in a byte lane*/
11369 #undef DDR_PHY_DX3GCR1_DMEN_DEFVAL
11370 #undef DDR_PHY_DX3GCR1_DMEN_SHIFT
11371 #undef DDR_PHY_DX3GCR1_DMEN_MASK
11372 #define DDR_PHY_DX3GCR1_DMEN_DEFVAL                                                0x00007FFF
11373 #define DDR_PHY_DX3GCR1_DMEN_SHIFT                                                 8
11374 #define DDR_PHY_DX3GCR1_DMEN_MASK                                                  0x00000100U
11375
11376 /*Enables DQ corresponding to each bit in a byte*/
11377 #undef DDR_PHY_DX3GCR1_DQEN_DEFVAL
11378 #undef DDR_PHY_DX3GCR1_DQEN_SHIFT
11379 #undef DDR_PHY_DX3GCR1_DQEN_MASK
11380 #define DDR_PHY_DX3GCR1_DQEN_DEFVAL                                                0x00007FFF
11381 #define DDR_PHY_DX3GCR1_DQEN_SHIFT                                                 0
11382 #define DDR_PHY_DX3GCR1_DQEN_MASK                                                  0x000000FFU
11383
11384 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
11385 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL
11386 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
11387 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK
11388 #define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
11389 #define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT                                       29
11390 #define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK                                        0xE0000000U
11391
11392 /*Byte Lane VREF Pad Enable*/
11393 #undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL
11394 #undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
11395 #undef DDR_PHY_DX3GCR4_DXREFPEN_MASK
11396 #define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
11397 #define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT                                             28
11398 #define DDR_PHY_DX3GCR4_DXREFPEN_MASK                                              0x10000000U
11399
11400 /*Byte Lane Internal VREF Enable*/
11401 #undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL
11402 #undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
11403 #undef DDR_PHY_DX3GCR4_DXREFEEN_MASK
11404 #define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
11405 #define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT                                             26
11406 #define DDR_PHY_DX3GCR4_DXREFEEN_MASK                                              0x0C000000U
11407
11408 /*Byte Lane Single-End VREF Enable*/
11409 #undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL
11410 #undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
11411 #undef DDR_PHY_DX3GCR4_DXREFSEN_MASK
11412 #define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
11413 #define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT                                             25
11414 #define DDR_PHY_DX3GCR4_DXREFSEN_MASK                                              0x02000000U
11415
11416 /*Reserved. Returns zeros on reads.*/
11417 #undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL
11418 #undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
11419 #undef DDR_PHY_DX3GCR4_RESERVED_24_MASK
11420 #define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
11421 #define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT                                          24
11422 #define DDR_PHY_DX3GCR4_RESERVED_24_MASK                                           0x01000000U
11423
11424 /*External VREF generator REFSEL range select*/
11425 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL
11426 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
11427 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK
11428 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
11429 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT                                       23
11430 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK                                        0x00800000U
11431
11432 /*Byte Lane External VREF Select*/
11433 #undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL
11434 #undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
11435 #undef DDR_PHY_DX3GCR4_DXREFESEL_MASK
11436 #define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
11437 #define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT                                            16
11438 #define DDR_PHY_DX3GCR4_DXREFESEL_MASK                                             0x007F0000U
11439
11440 /*Single ended VREF generator REFSEL range select*/
11441 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL
11442 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
11443 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK
11444 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
11445 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT                                       15
11446 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
11447
11448 /*Byte Lane Single-End VREF Select*/
11449 #undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL
11450 #undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
11451 #undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK
11452 #define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
11453 #define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT                                            8
11454 #define DDR_PHY_DX3GCR4_DXREFSSEL_MASK                                             0x00007F00U
11455
11456 /*Reserved. Returns zeros on reads.*/
11457 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL
11458 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
11459 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK
11460 #define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
11461 #define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT                                         6
11462 #define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK                                          0x000000C0U
11463
11464 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
11465 #undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL
11466 #undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
11467 #undef DDR_PHY_DX3GCR4_DXREFIEN_MASK
11468 #define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
11469 #define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT                                             2
11470 #define DDR_PHY_DX3GCR4_DXREFIEN_MASK                                              0x0000003CU
11471
11472 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
11473 #undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL
11474 #undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
11475 #undef DDR_PHY_DX3GCR4_DXREFIMON_MASK
11476 #define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
11477 #define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT                                            0
11478 #define DDR_PHY_DX3GCR4_DXREFIMON_MASK                                             0x00000003U
11479
11480 /*Reserved. Returns zeros on reads.*/
11481 #undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL
11482 #undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
11483 #undef DDR_PHY_DX3GCR5_RESERVED_31_MASK
11484 #define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL                                         0x09090909
11485 #define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT                                          31
11486 #define DDR_PHY_DX3GCR5_RESERVED_31_MASK                                           0x80000000U
11487
11488 /*Byte Lane internal VREF Select for Rank 3*/
11489 #undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL
11490 #undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
11491 #undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK
11492 #define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL                                         0x09090909
11493 #define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT                                          24
11494 #define DDR_PHY_DX3GCR5_DXREFISELR3_MASK                                           0x7F000000U
11495
11496 /*Reserved. Returns zeros on reads.*/
11497 #undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL
11498 #undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
11499 #undef DDR_PHY_DX3GCR5_RESERVED_23_MASK
11500 #define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL                                         0x09090909
11501 #define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT                                          23
11502 #define DDR_PHY_DX3GCR5_RESERVED_23_MASK                                           0x00800000U
11503
11504 /*Byte Lane internal VREF Select for Rank 2*/
11505 #undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL
11506 #undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
11507 #undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK
11508 #define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL                                         0x09090909
11509 #define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT                                          16
11510 #define DDR_PHY_DX3GCR5_DXREFISELR2_MASK                                           0x007F0000U
11511
11512 /*Reserved. Returns zeros on reads.*/
11513 #undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL
11514 #undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
11515 #undef DDR_PHY_DX3GCR5_RESERVED_15_MASK
11516 #define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL                                         0x09090909
11517 #define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT                                          15
11518 #define DDR_PHY_DX3GCR5_RESERVED_15_MASK                                           0x00008000U
11519
11520 /*Byte Lane internal VREF Select for Rank 1*/
11521 #undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL
11522 #undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
11523 #undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK
11524 #define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL                                         0x09090909
11525 #define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT                                          8
11526 #define DDR_PHY_DX3GCR5_DXREFISELR1_MASK                                           0x00007F00U
11527
11528 /*Reserved. Returns zeros on reads.*/
11529 #undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL
11530 #undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
11531 #undef DDR_PHY_DX3GCR5_RESERVED_7_MASK
11532 #define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL                                          0x09090909
11533 #define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT                                           7
11534 #define DDR_PHY_DX3GCR5_RESERVED_7_MASK                                            0x00000080U
11535
11536 /*Byte Lane internal VREF Select for Rank 0*/
11537 #undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL
11538 #undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
11539 #undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK
11540 #define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL                                         0x09090909
11541 #define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT                                          0
11542 #define DDR_PHY_DX3GCR5_DXREFISELR0_MASK                                           0x0000007FU
11543
11544 /*Reserved. Returns zeros on reads.*/
11545 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL
11546 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
11547 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK
11548 #define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
11549 #define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT                                       30
11550 #define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK                                        0xC0000000U
11551
11552 /*DRAM DQ VREF Select for Rank3*/
11553 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL
11554 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
11555 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK
11556 #define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
11557 #define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT                                           24
11558 #define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK                                            0x3F000000U
11559
11560 /*Reserved. Returns zeros on reads.*/
11561 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL
11562 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
11563 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK
11564 #define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
11565 #define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT                                       22
11566 #define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK                                        0x00C00000U
11567
11568 /*DRAM DQ VREF Select for Rank2*/
11569 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL
11570 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
11571 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK
11572 #define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
11573 #define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT                                           16
11574 #define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK                                            0x003F0000U
11575
11576 /*Reserved. Returns zeros on reads.*/
11577 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL
11578 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
11579 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK
11580 #define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
11581 #define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT                                       14
11582 #define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK                                        0x0000C000U
11583
11584 /*DRAM DQ VREF Select for Rank1*/
11585 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL
11586 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
11587 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK
11588 #define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
11589 #define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT                                           8
11590 #define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK                                            0x00003F00U
11591
11592 /*Reserved. Returns zeros on reads.*/
11593 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL
11594 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
11595 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK
11596 #define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
11597 #define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT                                         6
11598 #define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK                                          0x000000C0U
11599
11600 /*DRAM DQ VREF Select for Rank0*/
11601 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL
11602 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
11603 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK
11604 #define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
11605 #define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT                                           0
11606 #define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK                                            0x0000003FU
11607
11608 /*Reserved. Return zeroes on reads.*/
11609 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL
11610 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT
11611 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK
11612 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
11613 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT                                     25
11614 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
11615
11616 /*Reserved. Caution, do not write to this register field.*/
11617 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL
11618 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT
11619 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK
11620 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
11621 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT                                     16
11622 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
11623
11624 /*Reserved. Return zeroes on reads.*/
11625 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL
11626 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT
11627 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK
11628 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
11629 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT                                      9
11630 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
11631
11632 /*Read DQS Gating Delay*/
11633 #undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL
11634 #undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT
11635 #undef DDR_PHY_DX3LCDLR2_DQSGD_MASK
11636 #define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL                                             0x00000000
11637 #define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT                                              0
11638 #define DDR_PHY_DX3LCDLR2_DQSGD_MASK                                               0x000001FFU
11639
11640 /*Reserved. Return zeroes on reads.*/
11641 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL
11642 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT
11643 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK
11644 #define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
11645 #define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT                                       27
11646 #define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK                                        0xF8000000U
11647
11648 /*DQ Write Path Latency Pipeline*/
11649 #undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL
11650 #undef DDR_PHY_DX3GTR0_WDQSL_SHIFT
11651 #undef DDR_PHY_DX3GTR0_WDQSL_MASK
11652 #define DDR_PHY_DX3GTR0_WDQSL_DEFVAL                                               0x00020000
11653 #define DDR_PHY_DX3GTR0_WDQSL_SHIFT                                                24
11654 #define DDR_PHY_DX3GTR0_WDQSL_MASK                                                 0x07000000U
11655
11656 /*Reserved. Caution, do not write to this register field.*/
11657 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL
11658 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT
11659 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK
11660 #define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
11661 #define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT                                       20
11662 #define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK                                        0x00F00000U
11663
11664 /*Write Leveling System Latency*/
11665 #undef DDR_PHY_DX3GTR0_WLSL_DEFVAL
11666 #undef DDR_PHY_DX3GTR0_WLSL_SHIFT
11667 #undef DDR_PHY_DX3GTR0_WLSL_MASK
11668 #define DDR_PHY_DX3GTR0_WLSL_DEFVAL                                                0x00020000
11669 #define DDR_PHY_DX3GTR0_WLSL_SHIFT                                                 16
11670 #define DDR_PHY_DX3GTR0_WLSL_MASK                                                  0x000F0000U
11671
11672 /*Reserved. Return zeroes on reads.*/
11673 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL
11674 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT
11675 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK
11676 #define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
11677 #define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT                                       13
11678 #define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK                                        0x0000E000U
11679
11680 /*Reserved. Caution, do not write to this register field.*/
11681 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL
11682 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT
11683 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK
11684 #define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
11685 #define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT                                        8
11686 #define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK                                         0x00001F00U
11687
11688 /*Reserved. Return zeroes on reads.*/
11689 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL
11690 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT
11691 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK
11692 #define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
11693 #define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT                                         5
11694 #define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK                                          0x000000E0U
11695
11696 /*DQS Gating System Latency*/
11697 #undef DDR_PHY_DX3GTR0_DGSL_DEFVAL
11698 #undef DDR_PHY_DX3GTR0_DGSL_SHIFT
11699 #undef DDR_PHY_DX3GTR0_DGSL_MASK
11700 #define DDR_PHY_DX3GTR0_DGSL_DEFVAL                                                0x00020000
11701 #define DDR_PHY_DX3GTR0_DGSL_SHIFT                                                 0
11702 #define DDR_PHY_DX3GTR0_DGSL_MASK                                                  0x0000001FU
11703
11704 /*Calibration Bypass*/
11705 #undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL
11706 #undef DDR_PHY_DX4GCR0_CALBYP_SHIFT
11707 #undef DDR_PHY_DX4GCR0_CALBYP_MASK
11708 #define DDR_PHY_DX4GCR0_CALBYP_DEFVAL                                              0x40200204
11709 #define DDR_PHY_DX4GCR0_CALBYP_SHIFT                                               31
11710 #define DDR_PHY_DX4GCR0_CALBYP_MASK                                                0x80000000U
11711
11712 /*Master Delay Line Enable*/
11713 #undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL
11714 #undef DDR_PHY_DX4GCR0_MDLEN_SHIFT
11715 #undef DDR_PHY_DX4GCR0_MDLEN_MASK
11716 #define DDR_PHY_DX4GCR0_MDLEN_DEFVAL                                               0x40200204
11717 #define DDR_PHY_DX4GCR0_MDLEN_SHIFT                                                30
11718 #define DDR_PHY_DX4GCR0_MDLEN_MASK                                                 0x40000000U
11719
11720 /*Configurable ODT(TE) Phase Shift*/
11721 #undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL
11722 #undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
11723 #undef DDR_PHY_DX4GCR0_CODTSHFT_MASK
11724 #define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL                                            0x40200204
11725 #define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT                                             28
11726 #define DDR_PHY_DX4GCR0_CODTSHFT_MASK                                              0x30000000U
11727
11728 /*DQS Duty Cycle Correction*/
11729 #undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL
11730 #undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT
11731 #undef DDR_PHY_DX4GCR0_DQSDCC_MASK
11732 #define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL                                              0x40200204
11733 #define DDR_PHY_DX4GCR0_DQSDCC_SHIFT                                               24
11734 #define DDR_PHY_DX4GCR0_DQSDCC_MASK                                                0x0F000000U
11735
11736 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
11737 #undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL
11738 #undef DDR_PHY_DX4GCR0_RDDLY_SHIFT
11739 #undef DDR_PHY_DX4GCR0_RDDLY_MASK
11740 #define DDR_PHY_DX4GCR0_RDDLY_DEFVAL                                               0x40200204
11741 #define DDR_PHY_DX4GCR0_RDDLY_SHIFT                                                20
11742 #define DDR_PHY_DX4GCR0_RDDLY_MASK                                                 0x00F00000U
11743
11744 /*Reserved. Return zeroes on reads.*/
11745 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL
11746 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
11747 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK
11748 #define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
11749 #define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT                                       14
11750 #define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK                                        0x000FC000U
11751
11752 /*DQSNSE Power Down Receiver*/
11753 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL
11754 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
11755 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK
11756 #define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
11757 #define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT                                            13
11758 #define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK                                             0x00002000U
11759
11760 /*DQSSE Power Down Receiver*/
11761 #undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL
11762 #undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
11763 #undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK
11764 #define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL                                            0x40200204
11765 #define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT                                             12
11766 #define DDR_PHY_DX4GCR0_DQSSEPDR_MASK                                              0x00001000U
11767
11768 /*RTT On Additive Latency*/
11769 #undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL
11770 #undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT
11771 #undef DDR_PHY_DX4GCR0_RTTOAL_MASK
11772 #define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL                                              0x40200204
11773 #define DDR_PHY_DX4GCR0_RTTOAL_SHIFT                                               11
11774 #define DDR_PHY_DX4GCR0_RTTOAL_MASK                                                0x00000800U
11775
11776 /*RTT Output Hold*/
11777 #undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL
11778 #undef DDR_PHY_DX4GCR0_RTTOH_SHIFT
11779 #undef DDR_PHY_DX4GCR0_RTTOH_MASK
11780 #define DDR_PHY_DX4GCR0_RTTOH_DEFVAL                                               0x40200204
11781 #define DDR_PHY_DX4GCR0_RTTOH_SHIFT                                                9
11782 #define DDR_PHY_DX4GCR0_RTTOH_MASK                                                 0x00000600U
11783
11784 /*Configurable PDR Phase Shift*/
11785 #undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL
11786 #undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
11787 #undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK
11788 #define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL                                            0x40200204
11789 #define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT                                             7
11790 #define DDR_PHY_DX4GCR0_CPDRSHFT_MASK                                              0x00000180U
11791
11792 /*DQSR Power Down*/
11793 #undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL
11794 #undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT
11795 #undef DDR_PHY_DX4GCR0_DQSRPD_MASK
11796 #define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL                                              0x40200204
11797 #define DDR_PHY_DX4GCR0_DQSRPD_SHIFT                                               6
11798 #define DDR_PHY_DX4GCR0_DQSRPD_MASK                                                0x00000040U
11799
11800 /*DQSG Power Down Receiver*/
11801 #undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL
11802 #undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
11803 #undef DDR_PHY_DX4GCR0_DQSGPDR_MASK
11804 #define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL                                             0x40200204
11805 #define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT                                              5
11806 #define DDR_PHY_DX4GCR0_DQSGPDR_MASK                                               0x00000020U
11807
11808 /*Reserved. Return zeroes on reads.*/
11809 #undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL
11810 #undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
11811 #undef DDR_PHY_DX4GCR0_RESERVED_4_MASK
11812 #define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL                                          0x40200204
11813 #define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT                                           4
11814 #define DDR_PHY_DX4GCR0_RESERVED_4_MASK                                            0x00000010U
11815
11816 /*DQSG On-Die Termination*/
11817 #undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL
11818 #undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT
11819 #undef DDR_PHY_DX4GCR0_DQSGODT_MASK
11820 #define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL                                             0x40200204
11821 #define DDR_PHY_DX4GCR0_DQSGODT_SHIFT                                              3
11822 #define DDR_PHY_DX4GCR0_DQSGODT_MASK                                               0x00000008U
11823
11824 /*DQSG Output Enable*/
11825 #undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL
11826 #undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT
11827 #undef DDR_PHY_DX4GCR0_DQSGOE_MASK
11828 #define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL                                              0x40200204
11829 #define DDR_PHY_DX4GCR0_DQSGOE_SHIFT                                               2
11830 #define DDR_PHY_DX4GCR0_DQSGOE_MASK                                                0x00000004U
11831
11832 /*Reserved. Return zeroes on reads.*/
11833 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL
11834 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
11835 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK
11836 #define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
11837 #define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT                                         0
11838 #define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK                                          0x00000003U
11839
11840 /*Enables the PDR mode for DQ[7:0]*/
11841 #undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL
11842 #undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
11843 #undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK
11844 #define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
11845 #define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT                                            16
11846 #define DDR_PHY_DX4GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
11847
11848 /*Reserved. Returns zeroes on reads.*/
11849 #undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL
11850 #undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
11851 #undef DDR_PHY_DX4GCR1_RESERVED_15_MASK
11852 #define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
11853 #define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT                                          15
11854 #define DDR_PHY_DX4GCR1_RESERVED_15_MASK                                           0x00008000U
11855
11856 /*Select the delayed or non-delayed read data strobe #*/
11857 #undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL
11858 #undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT
11859 #undef DDR_PHY_DX4GCR1_QSNSEL_MASK
11860 #define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL                                              0x00007FFF
11861 #define DDR_PHY_DX4GCR1_QSNSEL_SHIFT                                               14
11862 #define DDR_PHY_DX4GCR1_QSNSEL_MASK                                                0x00004000U
11863
11864 /*Select the delayed or non-delayed read data strobe*/
11865 #undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL
11866 #undef DDR_PHY_DX4GCR1_QSSEL_SHIFT
11867 #undef DDR_PHY_DX4GCR1_QSSEL_MASK
11868 #define DDR_PHY_DX4GCR1_QSSEL_DEFVAL                                               0x00007FFF
11869 #define DDR_PHY_DX4GCR1_QSSEL_SHIFT                                                13
11870 #define DDR_PHY_DX4GCR1_QSSEL_MASK                                                 0x00002000U
11871
11872 /*Enables Read Data Strobe in a byte lane*/
11873 #undef DDR_PHY_DX4GCR1_OEEN_DEFVAL
11874 #undef DDR_PHY_DX4GCR1_OEEN_SHIFT
11875 #undef DDR_PHY_DX4GCR1_OEEN_MASK
11876 #define DDR_PHY_DX4GCR1_OEEN_DEFVAL                                                0x00007FFF
11877 #define DDR_PHY_DX4GCR1_OEEN_SHIFT                                                 12
11878 #define DDR_PHY_DX4GCR1_OEEN_MASK                                                  0x00001000U
11879
11880 /*Enables PDR in a byte lane*/
11881 #undef DDR_PHY_DX4GCR1_PDREN_DEFVAL
11882 #undef DDR_PHY_DX4GCR1_PDREN_SHIFT
11883 #undef DDR_PHY_DX4GCR1_PDREN_MASK
11884 #define DDR_PHY_DX4GCR1_PDREN_DEFVAL                                               0x00007FFF
11885 #define DDR_PHY_DX4GCR1_PDREN_SHIFT                                                11
11886 #define DDR_PHY_DX4GCR1_PDREN_MASK                                                 0x00000800U
11887
11888 /*Enables ODT/TE in a byte lane*/
11889 #undef DDR_PHY_DX4GCR1_TEEN_DEFVAL
11890 #undef DDR_PHY_DX4GCR1_TEEN_SHIFT
11891 #undef DDR_PHY_DX4GCR1_TEEN_MASK
11892 #define DDR_PHY_DX4GCR1_TEEN_DEFVAL                                                0x00007FFF
11893 #define DDR_PHY_DX4GCR1_TEEN_SHIFT                                                 10
11894 #define DDR_PHY_DX4GCR1_TEEN_MASK                                                  0x00000400U
11895
11896 /*Enables Write Data strobe in a byte lane*/
11897 #undef DDR_PHY_DX4GCR1_DSEN_DEFVAL
11898 #undef DDR_PHY_DX4GCR1_DSEN_SHIFT
11899 #undef DDR_PHY_DX4GCR1_DSEN_MASK
11900 #define DDR_PHY_DX4GCR1_DSEN_DEFVAL                                                0x00007FFF
11901 #define DDR_PHY_DX4GCR1_DSEN_SHIFT                                                 9
11902 #define DDR_PHY_DX4GCR1_DSEN_MASK                                                  0x00000200U
11903
11904 /*Enables DM pin in a byte lane*/
11905 #undef DDR_PHY_DX4GCR1_DMEN_DEFVAL
11906 #undef DDR_PHY_DX4GCR1_DMEN_SHIFT
11907 #undef DDR_PHY_DX4GCR1_DMEN_MASK
11908 #define DDR_PHY_DX4GCR1_DMEN_DEFVAL                                                0x00007FFF
11909 #define DDR_PHY_DX4GCR1_DMEN_SHIFT                                                 8
11910 #define DDR_PHY_DX4GCR1_DMEN_MASK                                                  0x00000100U
11911
11912 /*Enables DQ corresponding to each bit in a byte*/
11913 #undef DDR_PHY_DX4GCR1_DQEN_DEFVAL
11914 #undef DDR_PHY_DX4GCR1_DQEN_SHIFT
11915 #undef DDR_PHY_DX4GCR1_DQEN_MASK
11916 #define DDR_PHY_DX4GCR1_DQEN_DEFVAL                                                0x00007FFF
11917 #define DDR_PHY_DX4GCR1_DQEN_SHIFT                                                 0
11918 #define DDR_PHY_DX4GCR1_DQEN_MASK                                                  0x000000FFU
11919
11920 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
11921 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL
11922 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
11923 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK
11924 #define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
11925 #define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT                                       29
11926 #define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK                                        0xE0000000U
11927
11928 /*Byte Lane VREF Pad Enable*/
11929 #undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL
11930 #undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
11931 #undef DDR_PHY_DX4GCR4_DXREFPEN_MASK
11932 #define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
11933 #define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT                                             28
11934 #define DDR_PHY_DX4GCR4_DXREFPEN_MASK                                              0x10000000U
11935
11936 /*Byte Lane Internal VREF Enable*/
11937 #undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL
11938 #undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
11939 #undef DDR_PHY_DX4GCR4_DXREFEEN_MASK
11940 #define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
11941 #define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT                                             26
11942 #define DDR_PHY_DX4GCR4_DXREFEEN_MASK                                              0x0C000000U
11943
11944 /*Byte Lane Single-End VREF Enable*/
11945 #undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL
11946 #undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
11947 #undef DDR_PHY_DX4GCR4_DXREFSEN_MASK
11948 #define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
11949 #define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT                                             25
11950 #define DDR_PHY_DX4GCR4_DXREFSEN_MASK                                              0x02000000U
11951
11952 /*Reserved. Returns zeros on reads.*/
11953 #undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL
11954 #undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
11955 #undef DDR_PHY_DX4GCR4_RESERVED_24_MASK
11956 #define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
11957 #define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT                                          24
11958 #define DDR_PHY_DX4GCR4_RESERVED_24_MASK                                           0x01000000U
11959
11960 /*External VREF generator REFSEL range select*/
11961 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL
11962 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
11963 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK
11964 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
11965 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT                                       23
11966 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK                                        0x00800000U
11967
11968 /*Byte Lane External VREF Select*/
11969 #undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL
11970 #undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
11971 #undef DDR_PHY_DX4GCR4_DXREFESEL_MASK
11972 #define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
11973 #define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT                                            16
11974 #define DDR_PHY_DX4GCR4_DXREFESEL_MASK                                             0x007F0000U
11975
11976 /*Single ended VREF generator REFSEL range select*/
11977 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL
11978 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
11979 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK
11980 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
11981 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT                                       15
11982 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
11983
11984 /*Byte Lane Single-End VREF Select*/
11985 #undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL
11986 #undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
11987 #undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK
11988 #define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
11989 #define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT                                            8
11990 #define DDR_PHY_DX4GCR4_DXREFSSEL_MASK                                             0x00007F00U
11991
11992 /*Reserved. Returns zeros on reads.*/
11993 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL
11994 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
11995 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK
11996 #define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
11997 #define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT                                         6
11998 #define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK                                          0x000000C0U
11999
12000 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
12001 #undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL
12002 #undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
12003 #undef DDR_PHY_DX4GCR4_DXREFIEN_MASK
12004 #define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
12005 #define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT                                             2
12006 #define DDR_PHY_DX4GCR4_DXREFIEN_MASK                                              0x0000003CU
12007
12008 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
12009 #undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL
12010 #undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
12011 #undef DDR_PHY_DX4GCR4_DXREFIMON_MASK
12012 #define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
12013 #define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT                                            0
12014 #define DDR_PHY_DX4GCR4_DXREFIMON_MASK                                             0x00000003U
12015
12016 /*Reserved. Returns zeros on reads.*/
12017 #undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL
12018 #undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
12019 #undef DDR_PHY_DX4GCR5_RESERVED_31_MASK
12020 #define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL                                         0x09090909
12021 #define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT                                          31
12022 #define DDR_PHY_DX4GCR5_RESERVED_31_MASK                                           0x80000000U
12023
12024 /*Byte Lane internal VREF Select for Rank 3*/
12025 #undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL
12026 #undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
12027 #undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK
12028 #define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL                                         0x09090909
12029 #define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT                                          24
12030 #define DDR_PHY_DX4GCR5_DXREFISELR3_MASK                                           0x7F000000U
12031
12032 /*Reserved. Returns zeros on reads.*/
12033 #undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL
12034 #undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
12035 #undef DDR_PHY_DX4GCR5_RESERVED_23_MASK
12036 #define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL                                         0x09090909
12037 #define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT                                          23
12038 #define DDR_PHY_DX4GCR5_RESERVED_23_MASK                                           0x00800000U
12039
12040 /*Byte Lane internal VREF Select for Rank 2*/
12041 #undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL
12042 #undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
12043 #undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK
12044 #define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL                                         0x09090909
12045 #define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT                                          16
12046 #define DDR_PHY_DX4GCR5_DXREFISELR2_MASK                                           0x007F0000U
12047
12048 /*Reserved. Returns zeros on reads.*/
12049 #undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL
12050 #undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
12051 #undef DDR_PHY_DX4GCR5_RESERVED_15_MASK
12052 #define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL                                         0x09090909
12053 #define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT                                          15
12054 #define DDR_PHY_DX4GCR5_RESERVED_15_MASK                                           0x00008000U
12055
12056 /*Byte Lane internal VREF Select for Rank 1*/
12057 #undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL
12058 #undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
12059 #undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK
12060 #define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL                                         0x09090909
12061 #define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT                                          8
12062 #define DDR_PHY_DX4GCR5_DXREFISELR1_MASK                                           0x00007F00U
12063
12064 /*Reserved. Returns zeros on reads.*/
12065 #undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL
12066 #undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
12067 #undef DDR_PHY_DX4GCR5_RESERVED_7_MASK
12068 #define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL                                          0x09090909
12069 #define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT                                           7
12070 #define DDR_PHY_DX4GCR5_RESERVED_7_MASK                                            0x00000080U
12071
12072 /*Byte Lane internal VREF Select for Rank 0*/
12073 #undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL
12074 #undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
12075 #undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK
12076 #define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL                                         0x09090909
12077 #define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT                                          0
12078 #define DDR_PHY_DX4GCR5_DXREFISELR0_MASK                                           0x0000007FU
12079
12080 /*Reserved. Returns zeros on reads.*/
12081 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL
12082 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
12083 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK
12084 #define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
12085 #define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT                                       30
12086 #define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK                                        0xC0000000U
12087
12088 /*DRAM DQ VREF Select for Rank3*/
12089 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL
12090 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
12091 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK
12092 #define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
12093 #define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT                                           24
12094 #define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK                                            0x3F000000U
12095
12096 /*Reserved. Returns zeros on reads.*/
12097 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL
12098 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
12099 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK
12100 #define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
12101 #define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT                                       22
12102 #define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK                                        0x00C00000U
12103
12104 /*DRAM DQ VREF Select for Rank2*/
12105 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL
12106 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
12107 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK
12108 #define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
12109 #define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT                                           16
12110 #define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK                                            0x003F0000U
12111
12112 /*Reserved. Returns zeros on reads.*/
12113 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL
12114 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
12115 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK
12116 #define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
12117 #define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT                                       14
12118 #define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK                                        0x0000C000U
12119
12120 /*DRAM DQ VREF Select for Rank1*/
12121 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL
12122 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
12123 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK
12124 #define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
12125 #define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT                                           8
12126 #define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK                                            0x00003F00U
12127
12128 /*Reserved. Returns zeros on reads.*/
12129 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL
12130 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
12131 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK
12132 #define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
12133 #define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT                                         6
12134 #define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK                                          0x000000C0U
12135
12136 /*DRAM DQ VREF Select for Rank0*/
12137 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL
12138 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
12139 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK
12140 #define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
12141 #define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT                                           0
12142 #define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK                                            0x0000003FU
12143
12144 /*Reserved. Return zeroes on reads.*/
12145 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL
12146 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT
12147 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK
12148 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
12149 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT                                     25
12150 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
12151
12152 /*Reserved. Caution, do not write to this register field.*/
12153 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL
12154 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT
12155 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK
12156 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
12157 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT                                     16
12158 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
12159
12160 /*Reserved. Return zeroes on reads.*/
12161 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL
12162 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT
12163 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK
12164 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
12165 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT                                      9
12166 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
12167
12168 /*Read DQS Gating Delay*/
12169 #undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL
12170 #undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT
12171 #undef DDR_PHY_DX4LCDLR2_DQSGD_MASK
12172 #define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL                                             0x00000000
12173 #define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT                                              0
12174 #define DDR_PHY_DX4LCDLR2_DQSGD_MASK                                               0x000001FFU
12175
12176 /*Reserved. Return zeroes on reads.*/
12177 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL
12178 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT
12179 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK
12180 #define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
12181 #define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT                                       27
12182 #define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK                                        0xF8000000U
12183
12184 /*DQ Write Path Latency Pipeline*/
12185 #undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL
12186 #undef DDR_PHY_DX4GTR0_WDQSL_SHIFT
12187 #undef DDR_PHY_DX4GTR0_WDQSL_MASK
12188 #define DDR_PHY_DX4GTR0_WDQSL_DEFVAL                                               0x00020000
12189 #define DDR_PHY_DX4GTR0_WDQSL_SHIFT                                                24
12190 #define DDR_PHY_DX4GTR0_WDQSL_MASK                                                 0x07000000U
12191
12192 /*Reserved. Caution, do not write to this register field.*/
12193 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL
12194 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT
12195 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK
12196 #define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
12197 #define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT                                       20
12198 #define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK                                        0x00F00000U
12199
12200 /*Write Leveling System Latency*/
12201 #undef DDR_PHY_DX4GTR0_WLSL_DEFVAL
12202 #undef DDR_PHY_DX4GTR0_WLSL_SHIFT
12203 #undef DDR_PHY_DX4GTR0_WLSL_MASK
12204 #define DDR_PHY_DX4GTR0_WLSL_DEFVAL                                                0x00020000
12205 #define DDR_PHY_DX4GTR0_WLSL_SHIFT                                                 16
12206 #define DDR_PHY_DX4GTR0_WLSL_MASK                                                  0x000F0000U
12207
12208 /*Reserved. Return zeroes on reads.*/
12209 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL
12210 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT
12211 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK
12212 #define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
12213 #define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT                                       13
12214 #define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK                                        0x0000E000U
12215
12216 /*Reserved. Caution, do not write to this register field.*/
12217 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL
12218 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT
12219 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK
12220 #define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
12221 #define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT                                        8
12222 #define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK                                         0x00001F00U
12223
12224 /*Reserved. Return zeroes on reads.*/
12225 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL
12226 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT
12227 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK
12228 #define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
12229 #define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT                                         5
12230 #define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK                                          0x000000E0U
12231
12232 /*DQS Gating System Latency*/
12233 #undef DDR_PHY_DX4GTR0_DGSL_DEFVAL
12234 #undef DDR_PHY_DX4GTR0_DGSL_SHIFT
12235 #undef DDR_PHY_DX4GTR0_DGSL_MASK
12236 #define DDR_PHY_DX4GTR0_DGSL_DEFVAL                                                0x00020000
12237 #define DDR_PHY_DX4GTR0_DGSL_SHIFT                                                 0
12238 #define DDR_PHY_DX4GTR0_DGSL_MASK                                                  0x0000001FU
12239
12240 /*Calibration Bypass*/
12241 #undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL
12242 #undef DDR_PHY_DX5GCR0_CALBYP_SHIFT
12243 #undef DDR_PHY_DX5GCR0_CALBYP_MASK
12244 #define DDR_PHY_DX5GCR0_CALBYP_DEFVAL                                              0x40200204
12245 #define DDR_PHY_DX5GCR0_CALBYP_SHIFT                                               31
12246 #define DDR_PHY_DX5GCR0_CALBYP_MASK                                                0x80000000U
12247
12248 /*Master Delay Line Enable*/
12249 #undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL
12250 #undef DDR_PHY_DX5GCR0_MDLEN_SHIFT
12251 #undef DDR_PHY_DX5GCR0_MDLEN_MASK
12252 #define DDR_PHY_DX5GCR0_MDLEN_DEFVAL                                               0x40200204
12253 #define DDR_PHY_DX5GCR0_MDLEN_SHIFT                                                30
12254 #define DDR_PHY_DX5GCR0_MDLEN_MASK                                                 0x40000000U
12255
12256 /*Configurable ODT(TE) Phase Shift*/
12257 #undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL
12258 #undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
12259 #undef DDR_PHY_DX5GCR0_CODTSHFT_MASK
12260 #define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL                                            0x40200204
12261 #define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT                                             28
12262 #define DDR_PHY_DX5GCR0_CODTSHFT_MASK                                              0x30000000U
12263
12264 /*DQS Duty Cycle Correction*/
12265 #undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL
12266 #undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT
12267 #undef DDR_PHY_DX5GCR0_DQSDCC_MASK
12268 #define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL                                              0x40200204
12269 #define DDR_PHY_DX5GCR0_DQSDCC_SHIFT                                               24
12270 #define DDR_PHY_DX5GCR0_DQSDCC_MASK                                                0x0F000000U
12271
12272 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
12273 #undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL
12274 #undef DDR_PHY_DX5GCR0_RDDLY_SHIFT
12275 #undef DDR_PHY_DX5GCR0_RDDLY_MASK
12276 #define DDR_PHY_DX5GCR0_RDDLY_DEFVAL                                               0x40200204
12277 #define DDR_PHY_DX5GCR0_RDDLY_SHIFT                                                20
12278 #define DDR_PHY_DX5GCR0_RDDLY_MASK                                                 0x00F00000U
12279
12280 /*Reserved. Return zeroes on reads.*/
12281 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL
12282 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
12283 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK
12284 #define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
12285 #define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT                                       14
12286 #define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK                                        0x000FC000U
12287
12288 /*DQSNSE Power Down Receiver*/
12289 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL
12290 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
12291 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK
12292 #define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
12293 #define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT                                            13
12294 #define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK                                             0x00002000U
12295
12296 /*DQSSE Power Down Receiver*/
12297 #undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL
12298 #undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
12299 #undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK
12300 #define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL                                            0x40200204
12301 #define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT                                             12
12302 #define DDR_PHY_DX5GCR0_DQSSEPDR_MASK                                              0x00001000U
12303
12304 /*RTT On Additive Latency*/
12305 #undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL
12306 #undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT
12307 #undef DDR_PHY_DX5GCR0_RTTOAL_MASK
12308 #define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL                                              0x40200204
12309 #define DDR_PHY_DX5GCR0_RTTOAL_SHIFT                                               11
12310 #define DDR_PHY_DX5GCR0_RTTOAL_MASK                                                0x00000800U
12311
12312 /*RTT Output Hold*/
12313 #undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL
12314 #undef DDR_PHY_DX5GCR0_RTTOH_SHIFT
12315 #undef DDR_PHY_DX5GCR0_RTTOH_MASK
12316 #define DDR_PHY_DX5GCR0_RTTOH_DEFVAL                                               0x40200204
12317 #define DDR_PHY_DX5GCR0_RTTOH_SHIFT                                                9
12318 #define DDR_PHY_DX5GCR0_RTTOH_MASK                                                 0x00000600U
12319
12320 /*Configurable PDR Phase Shift*/
12321 #undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL
12322 #undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
12323 #undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK
12324 #define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL                                            0x40200204
12325 #define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT                                             7
12326 #define DDR_PHY_DX5GCR0_CPDRSHFT_MASK                                              0x00000180U
12327
12328 /*DQSR Power Down*/
12329 #undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL
12330 #undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT
12331 #undef DDR_PHY_DX5GCR0_DQSRPD_MASK
12332 #define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL                                              0x40200204
12333 #define DDR_PHY_DX5GCR0_DQSRPD_SHIFT                                               6
12334 #define DDR_PHY_DX5GCR0_DQSRPD_MASK                                                0x00000040U
12335
12336 /*DQSG Power Down Receiver*/
12337 #undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL
12338 #undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
12339 #undef DDR_PHY_DX5GCR0_DQSGPDR_MASK
12340 #define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL                                             0x40200204
12341 #define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT                                              5
12342 #define DDR_PHY_DX5GCR0_DQSGPDR_MASK                                               0x00000020U
12343
12344 /*Reserved. Return zeroes on reads.*/
12345 #undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL
12346 #undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
12347 #undef DDR_PHY_DX5GCR0_RESERVED_4_MASK
12348 #define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL                                          0x40200204
12349 #define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT                                           4
12350 #define DDR_PHY_DX5GCR0_RESERVED_4_MASK                                            0x00000010U
12351
12352 /*DQSG On-Die Termination*/
12353 #undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL
12354 #undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT
12355 #undef DDR_PHY_DX5GCR0_DQSGODT_MASK
12356 #define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL                                             0x40200204
12357 #define DDR_PHY_DX5GCR0_DQSGODT_SHIFT                                              3
12358 #define DDR_PHY_DX5GCR0_DQSGODT_MASK                                               0x00000008U
12359
12360 /*DQSG Output Enable*/
12361 #undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL
12362 #undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT
12363 #undef DDR_PHY_DX5GCR0_DQSGOE_MASK
12364 #define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL                                              0x40200204
12365 #define DDR_PHY_DX5GCR0_DQSGOE_SHIFT                                               2
12366 #define DDR_PHY_DX5GCR0_DQSGOE_MASK                                                0x00000004U
12367
12368 /*Reserved. Return zeroes on reads.*/
12369 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL
12370 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
12371 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK
12372 #define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
12373 #define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT                                         0
12374 #define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK                                          0x00000003U
12375
12376 /*Enables the PDR mode for DQ[7:0]*/
12377 #undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL
12378 #undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
12379 #undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK
12380 #define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
12381 #define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT                                            16
12382 #define DDR_PHY_DX5GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
12383
12384 /*Reserved. Returns zeroes on reads.*/
12385 #undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL
12386 #undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
12387 #undef DDR_PHY_DX5GCR1_RESERVED_15_MASK
12388 #define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
12389 #define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT                                          15
12390 #define DDR_PHY_DX5GCR1_RESERVED_15_MASK                                           0x00008000U
12391
12392 /*Select the delayed or non-delayed read data strobe #*/
12393 #undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL
12394 #undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT
12395 #undef DDR_PHY_DX5GCR1_QSNSEL_MASK
12396 #define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL                                              0x00007FFF
12397 #define DDR_PHY_DX5GCR1_QSNSEL_SHIFT                                               14
12398 #define DDR_PHY_DX5GCR1_QSNSEL_MASK                                                0x00004000U
12399
12400 /*Select the delayed or non-delayed read data strobe*/
12401 #undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL
12402 #undef DDR_PHY_DX5GCR1_QSSEL_SHIFT
12403 #undef DDR_PHY_DX5GCR1_QSSEL_MASK
12404 #define DDR_PHY_DX5GCR1_QSSEL_DEFVAL                                               0x00007FFF
12405 #define DDR_PHY_DX5GCR1_QSSEL_SHIFT                                                13
12406 #define DDR_PHY_DX5GCR1_QSSEL_MASK                                                 0x00002000U
12407
12408 /*Enables Read Data Strobe in a byte lane*/
12409 #undef DDR_PHY_DX5GCR1_OEEN_DEFVAL
12410 #undef DDR_PHY_DX5GCR1_OEEN_SHIFT
12411 #undef DDR_PHY_DX5GCR1_OEEN_MASK
12412 #define DDR_PHY_DX5GCR1_OEEN_DEFVAL                                                0x00007FFF
12413 #define DDR_PHY_DX5GCR1_OEEN_SHIFT                                                 12
12414 #define DDR_PHY_DX5GCR1_OEEN_MASK                                                  0x00001000U
12415
12416 /*Enables PDR in a byte lane*/
12417 #undef DDR_PHY_DX5GCR1_PDREN_DEFVAL
12418 #undef DDR_PHY_DX5GCR1_PDREN_SHIFT
12419 #undef DDR_PHY_DX5GCR1_PDREN_MASK
12420 #define DDR_PHY_DX5GCR1_PDREN_DEFVAL                                               0x00007FFF
12421 #define DDR_PHY_DX5GCR1_PDREN_SHIFT                                                11
12422 #define DDR_PHY_DX5GCR1_PDREN_MASK                                                 0x00000800U
12423
12424 /*Enables ODT/TE in a byte lane*/
12425 #undef DDR_PHY_DX5GCR1_TEEN_DEFVAL
12426 #undef DDR_PHY_DX5GCR1_TEEN_SHIFT
12427 #undef DDR_PHY_DX5GCR1_TEEN_MASK
12428 #define DDR_PHY_DX5GCR1_TEEN_DEFVAL                                                0x00007FFF
12429 #define DDR_PHY_DX5GCR1_TEEN_SHIFT                                                 10
12430 #define DDR_PHY_DX5GCR1_TEEN_MASK                                                  0x00000400U
12431
12432 /*Enables Write Data strobe in a byte lane*/
12433 #undef DDR_PHY_DX5GCR1_DSEN_DEFVAL
12434 #undef DDR_PHY_DX5GCR1_DSEN_SHIFT
12435 #undef DDR_PHY_DX5GCR1_DSEN_MASK
12436 #define DDR_PHY_DX5GCR1_DSEN_DEFVAL                                                0x00007FFF
12437 #define DDR_PHY_DX5GCR1_DSEN_SHIFT                                                 9
12438 #define DDR_PHY_DX5GCR1_DSEN_MASK                                                  0x00000200U
12439
12440 /*Enables DM pin in a byte lane*/
12441 #undef DDR_PHY_DX5GCR1_DMEN_DEFVAL
12442 #undef DDR_PHY_DX5GCR1_DMEN_SHIFT
12443 #undef DDR_PHY_DX5GCR1_DMEN_MASK
12444 #define DDR_PHY_DX5GCR1_DMEN_DEFVAL                                                0x00007FFF
12445 #define DDR_PHY_DX5GCR1_DMEN_SHIFT                                                 8
12446 #define DDR_PHY_DX5GCR1_DMEN_MASK                                                  0x00000100U
12447
12448 /*Enables DQ corresponding to each bit in a byte*/
12449 #undef DDR_PHY_DX5GCR1_DQEN_DEFVAL
12450 #undef DDR_PHY_DX5GCR1_DQEN_SHIFT
12451 #undef DDR_PHY_DX5GCR1_DQEN_MASK
12452 #define DDR_PHY_DX5GCR1_DQEN_DEFVAL                                                0x00007FFF
12453 #define DDR_PHY_DX5GCR1_DQEN_SHIFT                                                 0
12454 #define DDR_PHY_DX5GCR1_DQEN_MASK                                                  0x000000FFU
12455
12456 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
12457 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL
12458 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
12459 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK
12460 #define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
12461 #define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT                                       29
12462 #define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK                                        0xE0000000U
12463
12464 /*Byte Lane VREF Pad Enable*/
12465 #undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL
12466 #undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
12467 #undef DDR_PHY_DX5GCR4_DXREFPEN_MASK
12468 #define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
12469 #define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT                                             28
12470 #define DDR_PHY_DX5GCR4_DXREFPEN_MASK                                              0x10000000U
12471
12472 /*Byte Lane Internal VREF Enable*/
12473 #undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL
12474 #undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
12475 #undef DDR_PHY_DX5GCR4_DXREFEEN_MASK
12476 #define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
12477 #define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT                                             26
12478 #define DDR_PHY_DX5GCR4_DXREFEEN_MASK                                              0x0C000000U
12479
12480 /*Byte Lane Single-End VREF Enable*/
12481 #undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL
12482 #undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
12483 #undef DDR_PHY_DX5GCR4_DXREFSEN_MASK
12484 #define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
12485 #define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT                                             25
12486 #define DDR_PHY_DX5GCR4_DXREFSEN_MASK                                              0x02000000U
12487
12488 /*Reserved. Returns zeros on reads.*/
12489 #undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL
12490 #undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
12491 #undef DDR_PHY_DX5GCR4_RESERVED_24_MASK
12492 #define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
12493 #define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT                                          24
12494 #define DDR_PHY_DX5GCR4_RESERVED_24_MASK                                           0x01000000U
12495
12496 /*External VREF generator REFSEL range select*/
12497 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL
12498 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
12499 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK
12500 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
12501 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT                                       23
12502 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK                                        0x00800000U
12503
12504 /*Byte Lane External VREF Select*/
12505 #undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL
12506 #undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
12507 #undef DDR_PHY_DX5GCR4_DXREFESEL_MASK
12508 #define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
12509 #define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT                                            16
12510 #define DDR_PHY_DX5GCR4_DXREFESEL_MASK                                             0x007F0000U
12511
12512 /*Single ended VREF generator REFSEL range select*/
12513 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL
12514 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
12515 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK
12516 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
12517 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT                                       15
12518 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
12519
12520 /*Byte Lane Single-End VREF Select*/
12521 #undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL
12522 #undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
12523 #undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK
12524 #define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
12525 #define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT                                            8
12526 #define DDR_PHY_DX5GCR4_DXREFSSEL_MASK                                             0x00007F00U
12527
12528 /*Reserved. Returns zeros on reads.*/
12529 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL
12530 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
12531 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK
12532 #define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
12533 #define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT                                         6
12534 #define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK                                          0x000000C0U
12535
12536 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
12537 #undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL
12538 #undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
12539 #undef DDR_PHY_DX5GCR4_DXREFIEN_MASK
12540 #define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
12541 #define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT                                             2
12542 #define DDR_PHY_DX5GCR4_DXREFIEN_MASK                                              0x0000003CU
12543
12544 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
12545 #undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL
12546 #undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
12547 #undef DDR_PHY_DX5GCR4_DXREFIMON_MASK
12548 #define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
12549 #define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT                                            0
12550 #define DDR_PHY_DX5GCR4_DXREFIMON_MASK                                             0x00000003U
12551
12552 /*Reserved. Returns zeros on reads.*/
12553 #undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL
12554 #undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
12555 #undef DDR_PHY_DX5GCR5_RESERVED_31_MASK
12556 #define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL                                         0x09090909
12557 #define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT                                          31
12558 #define DDR_PHY_DX5GCR5_RESERVED_31_MASK                                           0x80000000U
12559
12560 /*Byte Lane internal VREF Select for Rank 3*/
12561 #undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL
12562 #undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
12563 #undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK
12564 #define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL                                         0x09090909
12565 #define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT                                          24
12566 #define DDR_PHY_DX5GCR5_DXREFISELR3_MASK                                           0x7F000000U
12567
12568 /*Reserved. Returns zeros on reads.*/
12569 #undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL
12570 #undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
12571 #undef DDR_PHY_DX5GCR5_RESERVED_23_MASK
12572 #define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL                                         0x09090909
12573 #define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT                                          23
12574 #define DDR_PHY_DX5GCR5_RESERVED_23_MASK                                           0x00800000U
12575
12576 /*Byte Lane internal VREF Select for Rank 2*/
12577 #undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL
12578 #undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
12579 #undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK
12580 #define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL                                         0x09090909
12581 #define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT                                          16
12582 #define DDR_PHY_DX5GCR5_DXREFISELR2_MASK                                           0x007F0000U
12583
12584 /*Reserved. Returns zeros on reads.*/
12585 #undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL
12586 #undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
12587 #undef DDR_PHY_DX5GCR5_RESERVED_15_MASK
12588 #define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL                                         0x09090909
12589 #define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT                                          15
12590 #define DDR_PHY_DX5GCR5_RESERVED_15_MASK                                           0x00008000U
12591
12592 /*Byte Lane internal VREF Select for Rank 1*/
12593 #undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL
12594 #undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
12595 #undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK
12596 #define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL                                         0x09090909
12597 #define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT                                          8
12598 #define DDR_PHY_DX5GCR5_DXREFISELR1_MASK                                           0x00007F00U
12599
12600 /*Reserved. Returns zeros on reads.*/
12601 #undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL
12602 #undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
12603 #undef DDR_PHY_DX5GCR5_RESERVED_7_MASK
12604 #define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL                                          0x09090909
12605 #define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT                                           7
12606 #define DDR_PHY_DX5GCR5_RESERVED_7_MASK                                            0x00000080U
12607
12608 /*Byte Lane internal VREF Select for Rank 0*/
12609 #undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL
12610 #undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
12611 #undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK
12612 #define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL                                         0x09090909
12613 #define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT                                          0
12614 #define DDR_PHY_DX5GCR5_DXREFISELR0_MASK                                           0x0000007FU
12615
12616 /*Reserved. Returns zeros on reads.*/
12617 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL
12618 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
12619 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK
12620 #define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
12621 #define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT                                       30
12622 #define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK                                        0xC0000000U
12623
12624 /*DRAM DQ VREF Select for Rank3*/
12625 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL
12626 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
12627 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK
12628 #define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
12629 #define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT                                           24
12630 #define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK                                            0x3F000000U
12631
12632 /*Reserved. Returns zeros on reads.*/
12633 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL
12634 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
12635 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK
12636 #define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
12637 #define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT                                       22
12638 #define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK                                        0x00C00000U
12639
12640 /*DRAM DQ VREF Select for Rank2*/
12641 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL
12642 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
12643 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK
12644 #define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
12645 #define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT                                           16
12646 #define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK                                            0x003F0000U
12647
12648 /*Reserved. Returns zeros on reads.*/
12649 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL
12650 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
12651 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK
12652 #define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
12653 #define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT                                       14
12654 #define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK                                        0x0000C000U
12655
12656 /*DRAM DQ VREF Select for Rank1*/
12657 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL
12658 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
12659 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK
12660 #define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
12661 #define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT                                           8
12662 #define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK                                            0x00003F00U
12663
12664 /*Reserved. Returns zeros on reads.*/
12665 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL
12666 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
12667 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK
12668 #define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
12669 #define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT                                         6
12670 #define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK                                          0x000000C0U
12671
12672 /*DRAM DQ VREF Select for Rank0*/
12673 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL
12674 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
12675 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK
12676 #define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
12677 #define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT                                           0
12678 #define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK                                            0x0000003FU
12679
12680 /*Reserved. Return zeroes on reads.*/
12681 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL
12682 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT
12683 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK
12684 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
12685 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT                                     25
12686 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
12687
12688 /*Reserved. Caution, do not write to this register field.*/
12689 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL
12690 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT
12691 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK
12692 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
12693 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT                                     16
12694 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
12695
12696 /*Reserved. Return zeroes on reads.*/
12697 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL
12698 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT
12699 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK
12700 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
12701 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT                                      9
12702 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
12703
12704 /*Read DQS Gating Delay*/
12705 #undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL
12706 #undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT
12707 #undef DDR_PHY_DX5LCDLR2_DQSGD_MASK
12708 #define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL                                             0x00000000
12709 #define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT                                              0
12710 #define DDR_PHY_DX5LCDLR2_DQSGD_MASK                                               0x000001FFU
12711
12712 /*Reserved. Return zeroes on reads.*/
12713 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL
12714 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT
12715 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK
12716 #define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
12717 #define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT                                       27
12718 #define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK                                        0xF8000000U
12719
12720 /*DQ Write Path Latency Pipeline*/
12721 #undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL
12722 #undef DDR_PHY_DX5GTR0_WDQSL_SHIFT
12723 #undef DDR_PHY_DX5GTR0_WDQSL_MASK
12724 #define DDR_PHY_DX5GTR0_WDQSL_DEFVAL                                               0x00020000
12725 #define DDR_PHY_DX5GTR0_WDQSL_SHIFT                                                24
12726 #define DDR_PHY_DX5GTR0_WDQSL_MASK                                                 0x07000000U
12727
12728 /*Reserved. Caution, do not write to this register field.*/
12729 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL
12730 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT
12731 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK
12732 #define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
12733 #define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT                                       20
12734 #define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK                                        0x00F00000U
12735
12736 /*Write Leveling System Latency*/
12737 #undef DDR_PHY_DX5GTR0_WLSL_DEFVAL
12738 #undef DDR_PHY_DX5GTR0_WLSL_SHIFT
12739 #undef DDR_PHY_DX5GTR0_WLSL_MASK
12740 #define DDR_PHY_DX5GTR0_WLSL_DEFVAL                                                0x00020000
12741 #define DDR_PHY_DX5GTR0_WLSL_SHIFT                                                 16
12742 #define DDR_PHY_DX5GTR0_WLSL_MASK                                                  0x000F0000U
12743
12744 /*Reserved. Return zeroes on reads.*/
12745 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL
12746 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT
12747 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK
12748 #define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
12749 #define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT                                       13
12750 #define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK                                        0x0000E000U
12751
12752 /*Reserved. Caution, do not write to this register field.*/
12753 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL
12754 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT
12755 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK
12756 #define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
12757 #define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT                                        8
12758 #define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK                                         0x00001F00U
12759
12760 /*Reserved. Return zeroes on reads.*/
12761 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL
12762 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT
12763 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK
12764 #define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
12765 #define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT                                         5
12766 #define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK                                          0x000000E0U
12767
12768 /*DQS Gating System Latency*/
12769 #undef DDR_PHY_DX5GTR0_DGSL_DEFVAL
12770 #undef DDR_PHY_DX5GTR0_DGSL_SHIFT
12771 #undef DDR_PHY_DX5GTR0_DGSL_MASK
12772 #define DDR_PHY_DX5GTR0_DGSL_DEFVAL                                                0x00020000
12773 #define DDR_PHY_DX5GTR0_DGSL_SHIFT                                                 0
12774 #define DDR_PHY_DX5GTR0_DGSL_MASK                                                  0x0000001FU
12775
12776 /*Calibration Bypass*/
12777 #undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL
12778 #undef DDR_PHY_DX6GCR0_CALBYP_SHIFT
12779 #undef DDR_PHY_DX6GCR0_CALBYP_MASK
12780 #define DDR_PHY_DX6GCR0_CALBYP_DEFVAL                                              0x40200204
12781 #define DDR_PHY_DX6GCR0_CALBYP_SHIFT                                               31
12782 #define DDR_PHY_DX6GCR0_CALBYP_MASK                                                0x80000000U
12783
12784 /*Master Delay Line Enable*/
12785 #undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL
12786 #undef DDR_PHY_DX6GCR0_MDLEN_SHIFT
12787 #undef DDR_PHY_DX6GCR0_MDLEN_MASK
12788 #define DDR_PHY_DX6GCR0_MDLEN_DEFVAL                                               0x40200204
12789 #define DDR_PHY_DX6GCR0_MDLEN_SHIFT                                                30
12790 #define DDR_PHY_DX6GCR0_MDLEN_MASK                                                 0x40000000U
12791
12792 /*Configurable ODT(TE) Phase Shift*/
12793 #undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL
12794 #undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
12795 #undef DDR_PHY_DX6GCR0_CODTSHFT_MASK
12796 #define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL                                            0x40200204
12797 #define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT                                             28
12798 #define DDR_PHY_DX6GCR0_CODTSHFT_MASK                                              0x30000000U
12799
12800 /*DQS Duty Cycle Correction*/
12801 #undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL
12802 #undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT
12803 #undef DDR_PHY_DX6GCR0_DQSDCC_MASK
12804 #define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL                                              0x40200204
12805 #define DDR_PHY_DX6GCR0_DQSDCC_SHIFT                                               24
12806 #define DDR_PHY_DX6GCR0_DQSDCC_MASK                                                0x0F000000U
12807
12808 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
12809 #undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL
12810 #undef DDR_PHY_DX6GCR0_RDDLY_SHIFT
12811 #undef DDR_PHY_DX6GCR0_RDDLY_MASK
12812 #define DDR_PHY_DX6GCR0_RDDLY_DEFVAL                                               0x40200204
12813 #define DDR_PHY_DX6GCR0_RDDLY_SHIFT                                                20
12814 #define DDR_PHY_DX6GCR0_RDDLY_MASK                                                 0x00F00000U
12815
12816 /*Reserved. Return zeroes on reads.*/
12817 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL
12818 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
12819 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK
12820 #define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
12821 #define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT                                       14
12822 #define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK                                        0x000FC000U
12823
12824 /*DQSNSE Power Down Receiver*/
12825 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL
12826 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
12827 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK
12828 #define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
12829 #define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT                                            13
12830 #define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK                                             0x00002000U
12831
12832 /*DQSSE Power Down Receiver*/
12833 #undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL
12834 #undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
12835 #undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK
12836 #define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL                                            0x40200204
12837 #define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT                                             12
12838 #define DDR_PHY_DX6GCR0_DQSSEPDR_MASK                                              0x00001000U
12839
12840 /*RTT On Additive Latency*/
12841 #undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL
12842 #undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT
12843 #undef DDR_PHY_DX6GCR0_RTTOAL_MASK
12844 #define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL                                              0x40200204
12845 #define DDR_PHY_DX6GCR0_RTTOAL_SHIFT                                               11
12846 #define DDR_PHY_DX6GCR0_RTTOAL_MASK                                                0x00000800U
12847
12848 /*RTT Output Hold*/
12849 #undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL
12850 #undef DDR_PHY_DX6GCR0_RTTOH_SHIFT
12851 #undef DDR_PHY_DX6GCR0_RTTOH_MASK
12852 #define DDR_PHY_DX6GCR0_RTTOH_DEFVAL                                               0x40200204
12853 #define DDR_PHY_DX6GCR0_RTTOH_SHIFT                                                9
12854 #define DDR_PHY_DX6GCR0_RTTOH_MASK                                                 0x00000600U
12855
12856 /*Configurable PDR Phase Shift*/
12857 #undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL
12858 #undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
12859 #undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK
12860 #define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL                                            0x40200204
12861 #define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT                                             7
12862 #define DDR_PHY_DX6GCR0_CPDRSHFT_MASK                                              0x00000180U
12863
12864 /*DQSR Power Down*/
12865 #undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL
12866 #undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT
12867 #undef DDR_PHY_DX6GCR0_DQSRPD_MASK
12868 #define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL                                              0x40200204
12869 #define DDR_PHY_DX6GCR0_DQSRPD_SHIFT                                               6
12870 #define DDR_PHY_DX6GCR0_DQSRPD_MASK                                                0x00000040U
12871
12872 /*DQSG Power Down Receiver*/
12873 #undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL
12874 #undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
12875 #undef DDR_PHY_DX6GCR0_DQSGPDR_MASK
12876 #define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL                                             0x40200204
12877 #define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT                                              5
12878 #define DDR_PHY_DX6GCR0_DQSGPDR_MASK                                               0x00000020U
12879
12880 /*Reserved. Return zeroes on reads.*/
12881 #undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL
12882 #undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
12883 #undef DDR_PHY_DX6GCR0_RESERVED_4_MASK
12884 #define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL                                          0x40200204
12885 #define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT                                           4
12886 #define DDR_PHY_DX6GCR0_RESERVED_4_MASK                                            0x00000010U
12887
12888 /*DQSG On-Die Termination*/
12889 #undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL
12890 #undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT
12891 #undef DDR_PHY_DX6GCR0_DQSGODT_MASK
12892 #define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL                                             0x40200204
12893 #define DDR_PHY_DX6GCR0_DQSGODT_SHIFT                                              3
12894 #define DDR_PHY_DX6GCR0_DQSGODT_MASK                                               0x00000008U
12895
12896 /*DQSG Output Enable*/
12897 #undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL
12898 #undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT
12899 #undef DDR_PHY_DX6GCR0_DQSGOE_MASK
12900 #define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL                                              0x40200204
12901 #define DDR_PHY_DX6GCR0_DQSGOE_SHIFT                                               2
12902 #define DDR_PHY_DX6GCR0_DQSGOE_MASK                                                0x00000004U
12903
12904 /*Reserved. Return zeroes on reads.*/
12905 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL
12906 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
12907 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK
12908 #define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
12909 #define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT                                         0
12910 #define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK                                          0x00000003U
12911
12912 /*Enables the PDR mode for DQ[7:0]*/
12913 #undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL
12914 #undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
12915 #undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK
12916 #define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
12917 #define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT                                            16
12918 #define DDR_PHY_DX6GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
12919
12920 /*Reserved. Returns zeroes on reads.*/
12921 #undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL
12922 #undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
12923 #undef DDR_PHY_DX6GCR1_RESERVED_15_MASK
12924 #define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
12925 #define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT                                          15
12926 #define DDR_PHY_DX6GCR1_RESERVED_15_MASK                                           0x00008000U
12927
12928 /*Select the delayed or non-delayed read data strobe #*/
12929 #undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL
12930 #undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT
12931 #undef DDR_PHY_DX6GCR1_QSNSEL_MASK
12932 #define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL                                              0x00007FFF
12933 #define DDR_PHY_DX6GCR1_QSNSEL_SHIFT                                               14
12934 #define DDR_PHY_DX6GCR1_QSNSEL_MASK                                                0x00004000U
12935
12936 /*Select the delayed or non-delayed read data strobe*/
12937 #undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL
12938 #undef DDR_PHY_DX6GCR1_QSSEL_SHIFT
12939 #undef DDR_PHY_DX6GCR1_QSSEL_MASK
12940 #define DDR_PHY_DX6GCR1_QSSEL_DEFVAL                                               0x00007FFF
12941 #define DDR_PHY_DX6GCR1_QSSEL_SHIFT                                                13
12942 #define DDR_PHY_DX6GCR1_QSSEL_MASK                                                 0x00002000U
12943
12944 /*Enables Read Data Strobe in a byte lane*/
12945 #undef DDR_PHY_DX6GCR1_OEEN_DEFVAL
12946 #undef DDR_PHY_DX6GCR1_OEEN_SHIFT
12947 #undef DDR_PHY_DX6GCR1_OEEN_MASK
12948 #define DDR_PHY_DX6GCR1_OEEN_DEFVAL                                                0x00007FFF
12949 #define DDR_PHY_DX6GCR1_OEEN_SHIFT                                                 12
12950 #define DDR_PHY_DX6GCR1_OEEN_MASK                                                  0x00001000U
12951
12952 /*Enables PDR in a byte lane*/
12953 #undef DDR_PHY_DX6GCR1_PDREN_DEFVAL
12954 #undef DDR_PHY_DX6GCR1_PDREN_SHIFT
12955 #undef DDR_PHY_DX6GCR1_PDREN_MASK
12956 #define DDR_PHY_DX6GCR1_PDREN_DEFVAL                                               0x00007FFF
12957 #define DDR_PHY_DX6GCR1_PDREN_SHIFT                                                11
12958 #define DDR_PHY_DX6GCR1_PDREN_MASK                                                 0x00000800U
12959
12960 /*Enables ODT/TE in a byte lane*/
12961 #undef DDR_PHY_DX6GCR1_TEEN_DEFVAL
12962 #undef DDR_PHY_DX6GCR1_TEEN_SHIFT
12963 #undef DDR_PHY_DX6GCR1_TEEN_MASK
12964 #define DDR_PHY_DX6GCR1_TEEN_DEFVAL                                                0x00007FFF
12965 #define DDR_PHY_DX6GCR1_TEEN_SHIFT                                                 10
12966 #define DDR_PHY_DX6GCR1_TEEN_MASK                                                  0x00000400U
12967
12968 /*Enables Write Data strobe in a byte lane*/
12969 #undef DDR_PHY_DX6GCR1_DSEN_DEFVAL
12970 #undef DDR_PHY_DX6GCR1_DSEN_SHIFT
12971 #undef DDR_PHY_DX6GCR1_DSEN_MASK
12972 #define DDR_PHY_DX6GCR1_DSEN_DEFVAL                                                0x00007FFF
12973 #define DDR_PHY_DX6GCR1_DSEN_SHIFT                                                 9
12974 #define DDR_PHY_DX6GCR1_DSEN_MASK                                                  0x00000200U
12975
12976 /*Enables DM pin in a byte lane*/
12977 #undef DDR_PHY_DX6GCR1_DMEN_DEFVAL
12978 #undef DDR_PHY_DX6GCR1_DMEN_SHIFT
12979 #undef DDR_PHY_DX6GCR1_DMEN_MASK
12980 #define DDR_PHY_DX6GCR1_DMEN_DEFVAL                                                0x00007FFF
12981 #define DDR_PHY_DX6GCR1_DMEN_SHIFT                                                 8
12982 #define DDR_PHY_DX6GCR1_DMEN_MASK                                                  0x00000100U
12983
12984 /*Enables DQ corresponding to each bit in a byte*/
12985 #undef DDR_PHY_DX6GCR1_DQEN_DEFVAL
12986 #undef DDR_PHY_DX6GCR1_DQEN_SHIFT
12987 #undef DDR_PHY_DX6GCR1_DQEN_MASK
12988 #define DDR_PHY_DX6GCR1_DQEN_DEFVAL                                                0x00007FFF
12989 #define DDR_PHY_DX6GCR1_DQEN_SHIFT                                                 0
12990 #define DDR_PHY_DX6GCR1_DQEN_MASK                                                  0x000000FFU
12991
12992 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
12993 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL
12994 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
12995 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK
12996 #define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
12997 #define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT                                       29
12998 #define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK                                        0xE0000000U
12999
13000 /*Byte Lane VREF Pad Enable*/
13001 #undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL
13002 #undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
13003 #undef DDR_PHY_DX6GCR4_DXREFPEN_MASK
13004 #define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
13005 #define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT                                             28
13006 #define DDR_PHY_DX6GCR4_DXREFPEN_MASK                                              0x10000000U
13007
13008 /*Byte Lane Internal VREF Enable*/
13009 #undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL
13010 #undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
13011 #undef DDR_PHY_DX6GCR4_DXREFEEN_MASK
13012 #define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
13013 #define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT                                             26
13014 #define DDR_PHY_DX6GCR4_DXREFEEN_MASK                                              0x0C000000U
13015
13016 /*Byte Lane Single-End VREF Enable*/
13017 #undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL
13018 #undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
13019 #undef DDR_PHY_DX6GCR4_DXREFSEN_MASK
13020 #define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
13021 #define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT                                             25
13022 #define DDR_PHY_DX6GCR4_DXREFSEN_MASK                                              0x02000000U
13023
13024 /*Reserved. Returns zeros on reads.*/
13025 #undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL
13026 #undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
13027 #undef DDR_PHY_DX6GCR4_RESERVED_24_MASK
13028 #define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
13029 #define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT                                          24
13030 #define DDR_PHY_DX6GCR4_RESERVED_24_MASK                                           0x01000000U
13031
13032 /*External VREF generator REFSEL range select*/
13033 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL
13034 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
13035 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK
13036 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
13037 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT                                       23
13038 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK                                        0x00800000U
13039
13040 /*Byte Lane External VREF Select*/
13041 #undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL
13042 #undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
13043 #undef DDR_PHY_DX6GCR4_DXREFESEL_MASK
13044 #define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
13045 #define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT                                            16
13046 #define DDR_PHY_DX6GCR4_DXREFESEL_MASK                                             0x007F0000U
13047
13048 /*Single ended VREF generator REFSEL range select*/
13049 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL
13050 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
13051 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK
13052 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
13053 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT                                       15
13054 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
13055
13056 /*Byte Lane Single-End VREF Select*/
13057 #undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL
13058 #undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
13059 #undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK
13060 #define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
13061 #define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT                                            8
13062 #define DDR_PHY_DX6GCR4_DXREFSSEL_MASK                                             0x00007F00U
13063
13064 /*Reserved. Returns zeros on reads.*/
13065 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL
13066 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
13067 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK
13068 #define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
13069 #define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT                                         6
13070 #define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK                                          0x000000C0U
13071
13072 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
13073 #undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL
13074 #undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
13075 #undef DDR_PHY_DX6GCR4_DXREFIEN_MASK
13076 #define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
13077 #define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT                                             2
13078 #define DDR_PHY_DX6GCR4_DXREFIEN_MASK                                              0x0000003CU
13079
13080 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
13081 #undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL
13082 #undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
13083 #undef DDR_PHY_DX6GCR4_DXREFIMON_MASK
13084 #define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
13085 #define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT                                            0
13086 #define DDR_PHY_DX6GCR4_DXREFIMON_MASK                                             0x00000003U
13087
13088 /*Reserved. Returns zeros on reads.*/
13089 #undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL
13090 #undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
13091 #undef DDR_PHY_DX6GCR5_RESERVED_31_MASK
13092 #define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL                                         0x09090909
13093 #define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT                                          31
13094 #define DDR_PHY_DX6GCR5_RESERVED_31_MASK                                           0x80000000U
13095
13096 /*Byte Lane internal VREF Select for Rank 3*/
13097 #undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL
13098 #undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
13099 #undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK
13100 #define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL                                         0x09090909
13101 #define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT                                          24
13102 #define DDR_PHY_DX6GCR5_DXREFISELR3_MASK                                           0x7F000000U
13103
13104 /*Reserved. Returns zeros on reads.*/
13105 #undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL
13106 #undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
13107 #undef DDR_PHY_DX6GCR5_RESERVED_23_MASK
13108 #define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL                                         0x09090909
13109 #define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT                                          23
13110 #define DDR_PHY_DX6GCR5_RESERVED_23_MASK                                           0x00800000U
13111
13112 /*Byte Lane internal VREF Select for Rank 2*/
13113 #undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL
13114 #undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
13115 #undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK
13116 #define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL                                         0x09090909
13117 #define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT                                          16
13118 #define DDR_PHY_DX6GCR5_DXREFISELR2_MASK                                           0x007F0000U
13119
13120 /*Reserved. Returns zeros on reads.*/
13121 #undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL
13122 #undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
13123 #undef DDR_PHY_DX6GCR5_RESERVED_15_MASK
13124 #define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL                                         0x09090909
13125 #define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT                                          15
13126 #define DDR_PHY_DX6GCR5_RESERVED_15_MASK                                           0x00008000U
13127
13128 /*Byte Lane internal VREF Select for Rank 1*/
13129 #undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL
13130 #undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
13131 #undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK
13132 #define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL                                         0x09090909
13133 #define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT                                          8
13134 #define DDR_PHY_DX6GCR5_DXREFISELR1_MASK                                           0x00007F00U
13135
13136 /*Reserved. Returns zeros on reads.*/
13137 #undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL
13138 #undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
13139 #undef DDR_PHY_DX6GCR5_RESERVED_7_MASK
13140 #define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL                                          0x09090909
13141 #define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT                                           7
13142 #define DDR_PHY_DX6GCR5_RESERVED_7_MASK                                            0x00000080U
13143
13144 /*Byte Lane internal VREF Select for Rank 0*/
13145 #undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL
13146 #undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
13147 #undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK
13148 #define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL                                         0x09090909
13149 #define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT                                          0
13150 #define DDR_PHY_DX6GCR5_DXREFISELR0_MASK                                           0x0000007FU
13151
13152 /*Reserved. Returns zeros on reads.*/
13153 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL
13154 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
13155 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK
13156 #define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
13157 #define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT                                       30
13158 #define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK                                        0xC0000000U
13159
13160 /*DRAM DQ VREF Select for Rank3*/
13161 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL
13162 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
13163 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK
13164 #define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
13165 #define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT                                           24
13166 #define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK                                            0x3F000000U
13167
13168 /*Reserved. Returns zeros on reads.*/
13169 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL
13170 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
13171 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK
13172 #define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
13173 #define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT                                       22
13174 #define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK                                        0x00C00000U
13175
13176 /*DRAM DQ VREF Select for Rank2*/
13177 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL
13178 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
13179 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK
13180 #define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
13181 #define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT                                           16
13182 #define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK                                            0x003F0000U
13183
13184 /*Reserved. Returns zeros on reads.*/
13185 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL
13186 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
13187 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK
13188 #define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
13189 #define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT                                       14
13190 #define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK                                        0x0000C000U
13191
13192 /*DRAM DQ VREF Select for Rank1*/
13193 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL
13194 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
13195 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK
13196 #define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
13197 #define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT                                           8
13198 #define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK                                            0x00003F00U
13199
13200 /*Reserved. Returns zeros on reads.*/
13201 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL
13202 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
13203 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK
13204 #define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
13205 #define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT                                         6
13206 #define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK                                          0x000000C0U
13207
13208 /*DRAM DQ VREF Select for Rank0*/
13209 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL
13210 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
13211 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK
13212 #define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
13213 #define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT                                           0
13214 #define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK                                            0x0000003FU
13215
13216 /*Reserved. Return zeroes on reads.*/
13217 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL
13218 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT
13219 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK
13220 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
13221 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT                                     25
13222 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
13223
13224 /*Reserved. Caution, do not write to this register field.*/
13225 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL
13226 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT
13227 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK
13228 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
13229 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT                                     16
13230 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
13231
13232 /*Reserved. Return zeroes on reads.*/
13233 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL
13234 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT
13235 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK
13236 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
13237 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT                                      9
13238 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
13239
13240 /*Read DQS Gating Delay*/
13241 #undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL
13242 #undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT
13243 #undef DDR_PHY_DX6LCDLR2_DQSGD_MASK
13244 #define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL                                             0x00000000
13245 #define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT                                              0
13246 #define DDR_PHY_DX6LCDLR2_DQSGD_MASK                                               0x000001FFU
13247
13248 /*Reserved. Return zeroes on reads.*/
13249 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL
13250 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT
13251 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK
13252 #define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
13253 #define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT                                       27
13254 #define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK                                        0xF8000000U
13255
13256 /*DQ Write Path Latency Pipeline*/
13257 #undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL
13258 #undef DDR_PHY_DX6GTR0_WDQSL_SHIFT
13259 #undef DDR_PHY_DX6GTR0_WDQSL_MASK
13260 #define DDR_PHY_DX6GTR0_WDQSL_DEFVAL                                               0x00020000
13261 #define DDR_PHY_DX6GTR0_WDQSL_SHIFT                                                24
13262 #define DDR_PHY_DX6GTR0_WDQSL_MASK                                                 0x07000000U
13263
13264 /*Reserved. Caution, do not write to this register field.*/
13265 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL
13266 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT
13267 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK
13268 #define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
13269 #define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT                                       20
13270 #define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK                                        0x00F00000U
13271
13272 /*Write Leveling System Latency*/
13273 #undef DDR_PHY_DX6GTR0_WLSL_DEFVAL
13274 #undef DDR_PHY_DX6GTR0_WLSL_SHIFT
13275 #undef DDR_PHY_DX6GTR0_WLSL_MASK
13276 #define DDR_PHY_DX6GTR0_WLSL_DEFVAL                                                0x00020000
13277 #define DDR_PHY_DX6GTR0_WLSL_SHIFT                                                 16
13278 #define DDR_PHY_DX6GTR0_WLSL_MASK                                                  0x000F0000U
13279
13280 /*Reserved. Return zeroes on reads.*/
13281 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL
13282 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT
13283 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK
13284 #define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
13285 #define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT                                       13
13286 #define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK                                        0x0000E000U
13287
13288 /*Reserved. Caution, do not write to this register field.*/
13289 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL
13290 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT
13291 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK
13292 #define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
13293 #define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT                                        8
13294 #define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK                                         0x00001F00U
13295
13296 /*Reserved. Return zeroes on reads.*/
13297 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL
13298 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT
13299 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK
13300 #define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
13301 #define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT                                         5
13302 #define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK                                          0x000000E0U
13303
13304 /*DQS Gating System Latency*/
13305 #undef DDR_PHY_DX6GTR0_DGSL_DEFVAL
13306 #undef DDR_PHY_DX6GTR0_DGSL_SHIFT
13307 #undef DDR_PHY_DX6GTR0_DGSL_MASK
13308 #define DDR_PHY_DX6GTR0_DGSL_DEFVAL                                                0x00020000
13309 #define DDR_PHY_DX6GTR0_DGSL_SHIFT                                                 0
13310 #define DDR_PHY_DX6GTR0_DGSL_MASK                                                  0x0000001FU
13311
13312 /*Calibration Bypass*/
13313 #undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL
13314 #undef DDR_PHY_DX7GCR0_CALBYP_SHIFT
13315 #undef DDR_PHY_DX7GCR0_CALBYP_MASK
13316 #define DDR_PHY_DX7GCR0_CALBYP_DEFVAL                                              0x40200204
13317 #define DDR_PHY_DX7GCR0_CALBYP_SHIFT                                               31
13318 #define DDR_PHY_DX7GCR0_CALBYP_MASK                                                0x80000000U
13319
13320 /*Master Delay Line Enable*/
13321 #undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL
13322 #undef DDR_PHY_DX7GCR0_MDLEN_SHIFT
13323 #undef DDR_PHY_DX7GCR0_MDLEN_MASK
13324 #define DDR_PHY_DX7GCR0_MDLEN_DEFVAL                                               0x40200204
13325 #define DDR_PHY_DX7GCR0_MDLEN_SHIFT                                                30
13326 #define DDR_PHY_DX7GCR0_MDLEN_MASK                                                 0x40000000U
13327
13328 /*Configurable ODT(TE) Phase Shift*/
13329 #undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL
13330 #undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
13331 #undef DDR_PHY_DX7GCR0_CODTSHFT_MASK
13332 #define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL                                            0x40200204
13333 #define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT                                             28
13334 #define DDR_PHY_DX7GCR0_CODTSHFT_MASK                                              0x30000000U
13335
13336 /*DQS Duty Cycle Correction*/
13337 #undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL
13338 #undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT
13339 #undef DDR_PHY_DX7GCR0_DQSDCC_MASK
13340 #define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL                                              0x40200204
13341 #define DDR_PHY_DX7GCR0_DQSDCC_SHIFT                                               24
13342 #define DDR_PHY_DX7GCR0_DQSDCC_MASK                                                0x0F000000U
13343
13344 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
13345 #undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL
13346 #undef DDR_PHY_DX7GCR0_RDDLY_SHIFT
13347 #undef DDR_PHY_DX7GCR0_RDDLY_MASK
13348 #define DDR_PHY_DX7GCR0_RDDLY_DEFVAL                                               0x40200204
13349 #define DDR_PHY_DX7GCR0_RDDLY_SHIFT                                                20
13350 #define DDR_PHY_DX7GCR0_RDDLY_MASK                                                 0x00F00000U
13351
13352 /*Reserved. Return zeroes on reads.*/
13353 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL
13354 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
13355 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK
13356 #define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
13357 #define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT                                       14
13358 #define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK                                        0x000FC000U
13359
13360 /*DQSNSE Power Down Receiver*/
13361 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL
13362 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
13363 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK
13364 #define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
13365 #define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT                                            13
13366 #define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK                                             0x00002000U
13367
13368 /*DQSSE Power Down Receiver*/
13369 #undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL
13370 #undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
13371 #undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK
13372 #define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL                                            0x40200204
13373 #define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT                                             12
13374 #define DDR_PHY_DX7GCR0_DQSSEPDR_MASK                                              0x00001000U
13375
13376 /*RTT On Additive Latency*/
13377 #undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL
13378 #undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT
13379 #undef DDR_PHY_DX7GCR0_RTTOAL_MASK
13380 #define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL                                              0x40200204
13381 #define DDR_PHY_DX7GCR0_RTTOAL_SHIFT                                               11
13382 #define DDR_PHY_DX7GCR0_RTTOAL_MASK                                                0x00000800U
13383
13384 /*RTT Output Hold*/
13385 #undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL
13386 #undef DDR_PHY_DX7GCR0_RTTOH_SHIFT
13387 #undef DDR_PHY_DX7GCR0_RTTOH_MASK
13388 #define DDR_PHY_DX7GCR0_RTTOH_DEFVAL                                               0x40200204
13389 #define DDR_PHY_DX7GCR0_RTTOH_SHIFT                                                9
13390 #define DDR_PHY_DX7GCR0_RTTOH_MASK                                                 0x00000600U
13391
13392 /*Configurable PDR Phase Shift*/
13393 #undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL
13394 #undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
13395 #undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK
13396 #define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL                                            0x40200204
13397 #define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT                                             7
13398 #define DDR_PHY_DX7GCR0_CPDRSHFT_MASK                                              0x00000180U
13399
13400 /*DQSR Power Down*/
13401 #undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL
13402 #undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT
13403 #undef DDR_PHY_DX7GCR0_DQSRPD_MASK
13404 #define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL                                              0x40200204
13405 #define DDR_PHY_DX7GCR0_DQSRPD_SHIFT                                               6
13406 #define DDR_PHY_DX7GCR0_DQSRPD_MASK                                                0x00000040U
13407
13408 /*DQSG Power Down Receiver*/
13409 #undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL
13410 #undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
13411 #undef DDR_PHY_DX7GCR0_DQSGPDR_MASK
13412 #define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL                                             0x40200204
13413 #define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT                                              5
13414 #define DDR_PHY_DX7GCR0_DQSGPDR_MASK                                               0x00000020U
13415
13416 /*Reserved. Return zeroes on reads.*/
13417 #undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL
13418 #undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
13419 #undef DDR_PHY_DX7GCR0_RESERVED_4_MASK
13420 #define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL                                          0x40200204
13421 #define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT                                           4
13422 #define DDR_PHY_DX7GCR0_RESERVED_4_MASK                                            0x00000010U
13423
13424 /*DQSG On-Die Termination*/
13425 #undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL
13426 #undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT
13427 #undef DDR_PHY_DX7GCR0_DQSGODT_MASK
13428 #define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL                                             0x40200204
13429 #define DDR_PHY_DX7GCR0_DQSGODT_SHIFT                                              3
13430 #define DDR_PHY_DX7GCR0_DQSGODT_MASK                                               0x00000008U
13431
13432 /*DQSG Output Enable*/
13433 #undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL
13434 #undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT
13435 #undef DDR_PHY_DX7GCR0_DQSGOE_MASK
13436 #define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL                                              0x40200204
13437 #define DDR_PHY_DX7GCR0_DQSGOE_SHIFT                                               2
13438 #define DDR_PHY_DX7GCR0_DQSGOE_MASK                                                0x00000004U
13439
13440 /*Reserved. Return zeroes on reads.*/
13441 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL
13442 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
13443 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK
13444 #define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
13445 #define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT                                         0
13446 #define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK                                          0x00000003U
13447
13448 /*Enables the PDR mode for DQ[7:0]*/
13449 #undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL
13450 #undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
13451 #undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK
13452 #define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
13453 #define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT                                            16
13454 #define DDR_PHY_DX7GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
13455
13456 /*Reserved. Returns zeroes on reads.*/
13457 #undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL
13458 #undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
13459 #undef DDR_PHY_DX7GCR1_RESERVED_15_MASK
13460 #define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
13461 #define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT                                          15
13462 #define DDR_PHY_DX7GCR1_RESERVED_15_MASK                                           0x00008000U
13463
13464 /*Select the delayed or non-delayed read data strobe #*/
13465 #undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL
13466 #undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT
13467 #undef DDR_PHY_DX7GCR1_QSNSEL_MASK
13468 #define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL                                              0x00007FFF
13469 #define DDR_PHY_DX7GCR1_QSNSEL_SHIFT                                               14
13470 #define DDR_PHY_DX7GCR1_QSNSEL_MASK                                                0x00004000U
13471
13472 /*Select the delayed or non-delayed read data strobe*/
13473 #undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL
13474 #undef DDR_PHY_DX7GCR1_QSSEL_SHIFT
13475 #undef DDR_PHY_DX7GCR1_QSSEL_MASK
13476 #define DDR_PHY_DX7GCR1_QSSEL_DEFVAL                                               0x00007FFF
13477 #define DDR_PHY_DX7GCR1_QSSEL_SHIFT                                                13
13478 #define DDR_PHY_DX7GCR1_QSSEL_MASK                                                 0x00002000U
13479
13480 /*Enables Read Data Strobe in a byte lane*/
13481 #undef DDR_PHY_DX7GCR1_OEEN_DEFVAL
13482 #undef DDR_PHY_DX7GCR1_OEEN_SHIFT
13483 #undef DDR_PHY_DX7GCR1_OEEN_MASK
13484 #define DDR_PHY_DX7GCR1_OEEN_DEFVAL                                                0x00007FFF
13485 #define DDR_PHY_DX7GCR1_OEEN_SHIFT                                                 12
13486 #define DDR_PHY_DX7GCR1_OEEN_MASK                                                  0x00001000U
13487
13488 /*Enables PDR in a byte lane*/
13489 #undef DDR_PHY_DX7GCR1_PDREN_DEFVAL
13490 #undef DDR_PHY_DX7GCR1_PDREN_SHIFT
13491 #undef DDR_PHY_DX7GCR1_PDREN_MASK
13492 #define DDR_PHY_DX7GCR1_PDREN_DEFVAL                                               0x00007FFF
13493 #define DDR_PHY_DX7GCR1_PDREN_SHIFT                                                11
13494 #define DDR_PHY_DX7GCR1_PDREN_MASK                                                 0x00000800U
13495
13496 /*Enables ODT/TE in a byte lane*/
13497 #undef DDR_PHY_DX7GCR1_TEEN_DEFVAL
13498 #undef DDR_PHY_DX7GCR1_TEEN_SHIFT
13499 #undef DDR_PHY_DX7GCR1_TEEN_MASK
13500 #define DDR_PHY_DX7GCR1_TEEN_DEFVAL                                                0x00007FFF
13501 #define DDR_PHY_DX7GCR1_TEEN_SHIFT                                                 10
13502 #define DDR_PHY_DX7GCR1_TEEN_MASK                                                  0x00000400U
13503
13504 /*Enables Write Data strobe in a byte lane*/
13505 #undef DDR_PHY_DX7GCR1_DSEN_DEFVAL
13506 #undef DDR_PHY_DX7GCR1_DSEN_SHIFT
13507 #undef DDR_PHY_DX7GCR1_DSEN_MASK
13508 #define DDR_PHY_DX7GCR1_DSEN_DEFVAL                                                0x00007FFF
13509 #define DDR_PHY_DX7GCR1_DSEN_SHIFT                                                 9
13510 #define DDR_PHY_DX7GCR1_DSEN_MASK                                                  0x00000200U
13511
13512 /*Enables DM pin in a byte lane*/
13513 #undef DDR_PHY_DX7GCR1_DMEN_DEFVAL
13514 #undef DDR_PHY_DX7GCR1_DMEN_SHIFT
13515 #undef DDR_PHY_DX7GCR1_DMEN_MASK
13516 #define DDR_PHY_DX7GCR1_DMEN_DEFVAL                                                0x00007FFF
13517 #define DDR_PHY_DX7GCR1_DMEN_SHIFT                                                 8
13518 #define DDR_PHY_DX7GCR1_DMEN_MASK                                                  0x00000100U
13519
13520 /*Enables DQ corresponding to each bit in a byte*/
13521 #undef DDR_PHY_DX7GCR1_DQEN_DEFVAL
13522 #undef DDR_PHY_DX7GCR1_DQEN_SHIFT
13523 #undef DDR_PHY_DX7GCR1_DQEN_MASK
13524 #define DDR_PHY_DX7GCR1_DQEN_DEFVAL                                                0x00007FFF
13525 #define DDR_PHY_DX7GCR1_DQEN_SHIFT                                                 0
13526 #define DDR_PHY_DX7GCR1_DQEN_MASK                                                  0x000000FFU
13527
13528 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
13529 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL
13530 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
13531 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK
13532 #define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
13533 #define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT                                       29
13534 #define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK                                        0xE0000000U
13535
13536 /*Byte Lane VREF Pad Enable*/
13537 #undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL
13538 #undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
13539 #undef DDR_PHY_DX7GCR4_DXREFPEN_MASK
13540 #define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
13541 #define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT                                             28
13542 #define DDR_PHY_DX7GCR4_DXREFPEN_MASK                                              0x10000000U
13543
13544 /*Byte Lane Internal VREF Enable*/
13545 #undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL
13546 #undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
13547 #undef DDR_PHY_DX7GCR4_DXREFEEN_MASK
13548 #define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
13549 #define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT                                             26
13550 #define DDR_PHY_DX7GCR4_DXREFEEN_MASK                                              0x0C000000U
13551
13552 /*Byte Lane Single-End VREF Enable*/
13553 #undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL
13554 #undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
13555 #undef DDR_PHY_DX7GCR4_DXREFSEN_MASK
13556 #define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
13557 #define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT                                             25
13558 #define DDR_PHY_DX7GCR4_DXREFSEN_MASK                                              0x02000000U
13559
13560 /*Reserved. Returns zeros on reads.*/
13561 #undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL
13562 #undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
13563 #undef DDR_PHY_DX7GCR4_RESERVED_24_MASK
13564 #define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
13565 #define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT                                          24
13566 #define DDR_PHY_DX7GCR4_RESERVED_24_MASK                                           0x01000000U
13567
13568 /*External VREF generator REFSEL range select*/
13569 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL
13570 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
13571 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK
13572 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
13573 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT                                       23
13574 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK                                        0x00800000U
13575
13576 /*Byte Lane External VREF Select*/
13577 #undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL
13578 #undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
13579 #undef DDR_PHY_DX7GCR4_DXREFESEL_MASK
13580 #define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
13581 #define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT                                            16
13582 #define DDR_PHY_DX7GCR4_DXREFESEL_MASK                                             0x007F0000U
13583
13584 /*Single ended VREF generator REFSEL range select*/
13585 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL
13586 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
13587 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK
13588 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
13589 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT                                       15
13590 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
13591
13592 /*Byte Lane Single-End VREF Select*/
13593 #undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL
13594 #undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
13595 #undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK
13596 #define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
13597 #define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT                                            8
13598 #define DDR_PHY_DX7GCR4_DXREFSSEL_MASK                                             0x00007F00U
13599
13600 /*Reserved. Returns zeros on reads.*/
13601 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL
13602 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
13603 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK
13604 #define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
13605 #define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT                                         6
13606 #define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK                                          0x000000C0U
13607
13608 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
13609 #undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL
13610 #undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
13611 #undef DDR_PHY_DX7GCR4_DXREFIEN_MASK
13612 #define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
13613 #define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT                                             2
13614 #define DDR_PHY_DX7GCR4_DXREFIEN_MASK                                              0x0000003CU
13615
13616 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
13617 #undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL
13618 #undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
13619 #undef DDR_PHY_DX7GCR4_DXREFIMON_MASK
13620 #define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
13621 #define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT                                            0
13622 #define DDR_PHY_DX7GCR4_DXREFIMON_MASK                                             0x00000003U
13623
13624 /*Reserved. Returns zeros on reads.*/
13625 #undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL
13626 #undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
13627 #undef DDR_PHY_DX7GCR5_RESERVED_31_MASK
13628 #define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL                                         0x09090909
13629 #define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT                                          31
13630 #define DDR_PHY_DX7GCR5_RESERVED_31_MASK                                           0x80000000U
13631
13632 /*Byte Lane internal VREF Select for Rank 3*/
13633 #undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL
13634 #undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
13635 #undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK
13636 #define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL                                         0x09090909
13637 #define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT                                          24
13638 #define DDR_PHY_DX7GCR5_DXREFISELR3_MASK                                           0x7F000000U
13639
13640 /*Reserved. Returns zeros on reads.*/
13641 #undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL
13642 #undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
13643 #undef DDR_PHY_DX7GCR5_RESERVED_23_MASK
13644 #define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL                                         0x09090909
13645 #define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT                                          23
13646 #define DDR_PHY_DX7GCR5_RESERVED_23_MASK                                           0x00800000U
13647
13648 /*Byte Lane internal VREF Select for Rank 2*/
13649 #undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL
13650 #undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
13651 #undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK
13652 #define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL                                         0x09090909
13653 #define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT                                          16
13654 #define DDR_PHY_DX7GCR5_DXREFISELR2_MASK                                           0x007F0000U
13655
13656 /*Reserved. Returns zeros on reads.*/
13657 #undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL
13658 #undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
13659 #undef DDR_PHY_DX7GCR5_RESERVED_15_MASK
13660 #define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL                                         0x09090909
13661 #define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT                                          15
13662 #define DDR_PHY_DX7GCR5_RESERVED_15_MASK                                           0x00008000U
13663
13664 /*Byte Lane internal VREF Select for Rank 1*/
13665 #undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL
13666 #undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
13667 #undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK
13668 #define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL                                         0x09090909
13669 #define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT                                          8
13670 #define DDR_PHY_DX7GCR5_DXREFISELR1_MASK                                           0x00007F00U
13671
13672 /*Reserved. Returns zeros on reads.*/
13673 #undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL
13674 #undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
13675 #undef DDR_PHY_DX7GCR5_RESERVED_7_MASK
13676 #define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL                                          0x09090909
13677 #define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT                                           7
13678 #define DDR_PHY_DX7GCR5_RESERVED_7_MASK                                            0x00000080U
13679
13680 /*Byte Lane internal VREF Select for Rank 0*/
13681 #undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL
13682 #undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
13683 #undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK
13684 #define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL                                         0x09090909
13685 #define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT                                          0
13686 #define DDR_PHY_DX7GCR5_DXREFISELR0_MASK                                           0x0000007FU
13687
13688 /*Reserved. Returns zeros on reads.*/
13689 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL
13690 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
13691 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK
13692 #define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
13693 #define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT                                       30
13694 #define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK                                        0xC0000000U
13695
13696 /*DRAM DQ VREF Select for Rank3*/
13697 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL
13698 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
13699 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK
13700 #define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
13701 #define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT                                           24
13702 #define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK                                            0x3F000000U
13703
13704 /*Reserved. Returns zeros on reads.*/
13705 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL
13706 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
13707 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK
13708 #define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
13709 #define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT                                       22
13710 #define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK                                        0x00C00000U
13711
13712 /*DRAM DQ VREF Select for Rank2*/
13713 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL
13714 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
13715 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK
13716 #define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
13717 #define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT                                           16
13718 #define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK                                            0x003F0000U
13719
13720 /*Reserved. Returns zeros on reads.*/
13721 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL
13722 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
13723 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK
13724 #define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
13725 #define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT                                       14
13726 #define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK                                        0x0000C000U
13727
13728 /*DRAM DQ VREF Select for Rank1*/
13729 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL
13730 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
13731 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK
13732 #define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
13733 #define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT                                           8
13734 #define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK                                            0x00003F00U
13735
13736 /*Reserved. Returns zeros on reads.*/
13737 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL
13738 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
13739 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK
13740 #define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
13741 #define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT                                         6
13742 #define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK                                          0x000000C0U
13743
13744 /*DRAM DQ VREF Select for Rank0*/
13745 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL
13746 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
13747 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK
13748 #define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
13749 #define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT                                           0
13750 #define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK                                            0x0000003FU
13751
13752 /*Reserved. Return zeroes on reads.*/
13753 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL
13754 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT
13755 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK
13756 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
13757 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT                                     25
13758 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
13759
13760 /*Reserved. Caution, do not write to this register field.*/
13761 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL
13762 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT
13763 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK
13764 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
13765 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT                                     16
13766 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
13767
13768 /*Reserved. Return zeroes on reads.*/
13769 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL
13770 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT
13771 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK
13772 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
13773 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT                                      9
13774 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
13775
13776 /*Read DQS Gating Delay*/
13777 #undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL
13778 #undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT
13779 #undef DDR_PHY_DX7LCDLR2_DQSGD_MASK
13780 #define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL                                             0x00000000
13781 #define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT                                              0
13782 #define DDR_PHY_DX7LCDLR2_DQSGD_MASK                                               0x000001FFU
13783
13784 /*Reserved. Return zeroes on reads.*/
13785 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL
13786 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT
13787 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK
13788 #define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
13789 #define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT                                       27
13790 #define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK                                        0xF8000000U
13791
13792 /*DQ Write Path Latency Pipeline*/
13793 #undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL
13794 #undef DDR_PHY_DX7GTR0_WDQSL_SHIFT
13795 #undef DDR_PHY_DX7GTR0_WDQSL_MASK
13796 #define DDR_PHY_DX7GTR0_WDQSL_DEFVAL                                               0x00020000
13797 #define DDR_PHY_DX7GTR0_WDQSL_SHIFT                                                24
13798 #define DDR_PHY_DX7GTR0_WDQSL_MASK                                                 0x07000000U
13799
13800 /*Reserved. Caution, do not write to this register field.*/
13801 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL
13802 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT
13803 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK
13804 #define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
13805 #define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT                                       20
13806 #define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK                                        0x00F00000U
13807
13808 /*Write Leveling System Latency*/
13809 #undef DDR_PHY_DX7GTR0_WLSL_DEFVAL
13810 #undef DDR_PHY_DX7GTR0_WLSL_SHIFT
13811 #undef DDR_PHY_DX7GTR0_WLSL_MASK
13812 #define DDR_PHY_DX7GTR0_WLSL_DEFVAL                                                0x00020000
13813 #define DDR_PHY_DX7GTR0_WLSL_SHIFT                                                 16
13814 #define DDR_PHY_DX7GTR0_WLSL_MASK                                                  0x000F0000U
13815
13816 /*Reserved. Return zeroes on reads.*/
13817 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL
13818 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT
13819 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK
13820 #define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
13821 #define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT                                       13
13822 #define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK                                        0x0000E000U
13823
13824 /*Reserved. Caution, do not write to this register field.*/
13825 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL
13826 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT
13827 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK
13828 #define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
13829 #define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT                                        8
13830 #define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK                                         0x00001F00U
13831
13832 /*Reserved. Return zeroes on reads.*/
13833 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL
13834 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT
13835 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK
13836 #define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
13837 #define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT                                         5
13838 #define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK                                          0x000000E0U
13839
13840 /*DQS Gating System Latency*/
13841 #undef DDR_PHY_DX7GTR0_DGSL_DEFVAL
13842 #undef DDR_PHY_DX7GTR0_DGSL_SHIFT
13843 #undef DDR_PHY_DX7GTR0_DGSL_MASK
13844 #define DDR_PHY_DX7GTR0_DGSL_DEFVAL                                                0x00020000
13845 #define DDR_PHY_DX7GTR0_DGSL_SHIFT                                                 0
13846 #define DDR_PHY_DX7GTR0_DGSL_MASK                                                  0x0000001FU
13847
13848 /*Calibration Bypass*/
13849 #undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL
13850 #undef DDR_PHY_DX8GCR0_CALBYP_SHIFT
13851 #undef DDR_PHY_DX8GCR0_CALBYP_MASK
13852 #define DDR_PHY_DX8GCR0_CALBYP_DEFVAL                                              0x40200204
13853 #define DDR_PHY_DX8GCR0_CALBYP_SHIFT                                               31
13854 #define DDR_PHY_DX8GCR0_CALBYP_MASK                                                0x80000000U
13855
13856 /*Master Delay Line Enable*/
13857 #undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL
13858 #undef DDR_PHY_DX8GCR0_MDLEN_SHIFT
13859 #undef DDR_PHY_DX8GCR0_MDLEN_MASK
13860 #define DDR_PHY_DX8GCR0_MDLEN_DEFVAL                                               0x40200204
13861 #define DDR_PHY_DX8GCR0_MDLEN_SHIFT                                                30
13862 #define DDR_PHY_DX8GCR0_MDLEN_MASK                                                 0x40000000U
13863
13864 /*Configurable ODT(TE) Phase Shift*/
13865 #undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL
13866 #undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
13867 #undef DDR_PHY_DX8GCR0_CODTSHFT_MASK
13868 #define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL                                            0x40200204
13869 #define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT                                             28
13870 #define DDR_PHY_DX8GCR0_CODTSHFT_MASK                                              0x30000000U
13871
13872 /*DQS Duty Cycle Correction*/
13873 #undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL
13874 #undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT
13875 #undef DDR_PHY_DX8GCR0_DQSDCC_MASK
13876 #define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL                                              0x40200204
13877 #define DDR_PHY_DX8GCR0_DQSDCC_SHIFT                                               24
13878 #define DDR_PHY_DX8GCR0_DQSDCC_MASK                                                0x0F000000U
13879
13880 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
13881 #undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL
13882 #undef DDR_PHY_DX8GCR0_RDDLY_SHIFT
13883 #undef DDR_PHY_DX8GCR0_RDDLY_MASK
13884 #define DDR_PHY_DX8GCR0_RDDLY_DEFVAL                                               0x40200204
13885 #define DDR_PHY_DX8GCR0_RDDLY_SHIFT                                                20
13886 #define DDR_PHY_DX8GCR0_RDDLY_MASK                                                 0x00F00000U
13887
13888 /*Reserved. Return zeroes on reads.*/
13889 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL
13890 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
13891 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK
13892 #define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
13893 #define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT                                       14
13894 #define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK                                        0x000FC000U
13895
13896 /*DQSNSE Power Down Receiver*/
13897 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL
13898 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
13899 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK
13900 #define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
13901 #define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT                                            13
13902 #define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK                                             0x00002000U
13903
13904 /*DQSSE Power Down Receiver*/
13905 #undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL
13906 #undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
13907 #undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK
13908 #define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL                                            0x40200204
13909 #define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT                                             12
13910 #define DDR_PHY_DX8GCR0_DQSSEPDR_MASK                                              0x00001000U
13911
13912 /*RTT On Additive Latency*/
13913 #undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL
13914 #undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT
13915 #undef DDR_PHY_DX8GCR0_RTTOAL_MASK
13916 #define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL                                              0x40200204
13917 #define DDR_PHY_DX8GCR0_RTTOAL_SHIFT                                               11
13918 #define DDR_PHY_DX8GCR0_RTTOAL_MASK                                                0x00000800U
13919
13920 /*RTT Output Hold*/
13921 #undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL
13922 #undef DDR_PHY_DX8GCR0_RTTOH_SHIFT
13923 #undef DDR_PHY_DX8GCR0_RTTOH_MASK
13924 #define DDR_PHY_DX8GCR0_RTTOH_DEFVAL                                               0x40200204
13925 #define DDR_PHY_DX8GCR0_RTTOH_SHIFT                                                9
13926 #define DDR_PHY_DX8GCR0_RTTOH_MASK                                                 0x00000600U
13927
13928 /*Configurable PDR Phase Shift*/
13929 #undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL
13930 #undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
13931 #undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK
13932 #define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL                                            0x40200204
13933 #define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT                                             7
13934 #define DDR_PHY_DX8GCR0_CPDRSHFT_MASK                                              0x00000180U
13935
13936 /*DQSR Power Down*/
13937 #undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL
13938 #undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT
13939 #undef DDR_PHY_DX8GCR0_DQSRPD_MASK
13940 #define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL                                              0x40200204
13941 #define DDR_PHY_DX8GCR0_DQSRPD_SHIFT                                               6
13942 #define DDR_PHY_DX8GCR0_DQSRPD_MASK                                                0x00000040U
13943
13944 /*DQSG Power Down Receiver*/
13945 #undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL
13946 #undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
13947 #undef DDR_PHY_DX8GCR0_DQSGPDR_MASK
13948 #define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL                                             0x40200204
13949 #define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT                                              5
13950 #define DDR_PHY_DX8GCR0_DQSGPDR_MASK                                               0x00000020U
13951
13952 /*Reserved. Return zeroes on reads.*/
13953 #undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL
13954 #undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
13955 #undef DDR_PHY_DX8GCR0_RESERVED_4_MASK
13956 #define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL                                          0x40200204
13957 #define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT                                           4
13958 #define DDR_PHY_DX8GCR0_RESERVED_4_MASK                                            0x00000010U
13959
13960 /*DQSG On-Die Termination*/
13961 #undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL
13962 #undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT
13963 #undef DDR_PHY_DX8GCR0_DQSGODT_MASK
13964 #define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL                                             0x40200204
13965 #define DDR_PHY_DX8GCR0_DQSGODT_SHIFT                                              3
13966 #define DDR_PHY_DX8GCR0_DQSGODT_MASK                                               0x00000008U
13967
13968 /*DQSG Output Enable*/
13969 #undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL
13970 #undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT
13971 #undef DDR_PHY_DX8GCR0_DQSGOE_MASK
13972 #define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL                                              0x40200204
13973 #define DDR_PHY_DX8GCR0_DQSGOE_SHIFT                                               2
13974 #define DDR_PHY_DX8GCR0_DQSGOE_MASK                                                0x00000004U
13975
13976 /*Reserved. Return zeroes on reads.*/
13977 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL
13978 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
13979 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK
13980 #define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
13981 #define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT                                         0
13982 #define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK                                          0x00000003U
13983
13984 /*Enables the PDR mode for DQ[7:0]*/
13985 #undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL
13986 #undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
13987 #undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK
13988 #define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
13989 #define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT                                            16
13990 #define DDR_PHY_DX8GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
13991
13992 /*Reserved. Returns zeroes on reads.*/
13993 #undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL
13994 #undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
13995 #undef DDR_PHY_DX8GCR1_RESERVED_15_MASK
13996 #define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
13997 #define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT                                          15
13998 #define DDR_PHY_DX8GCR1_RESERVED_15_MASK                                           0x00008000U
13999
14000 /*Select the delayed or non-delayed read data strobe #*/
14001 #undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL
14002 #undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT
14003 #undef DDR_PHY_DX8GCR1_QSNSEL_MASK
14004 #define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL                                              0x00007FFF
14005 #define DDR_PHY_DX8GCR1_QSNSEL_SHIFT                                               14
14006 #define DDR_PHY_DX8GCR1_QSNSEL_MASK                                                0x00004000U
14007
14008 /*Select the delayed or non-delayed read data strobe*/
14009 #undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL
14010 #undef DDR_PHY_DX8GCR1_QSSEL_SHIFT
14011 #undef DDR_PHY_DX8GCR1_QSSEL_MASK
14012 #define DDR_PHY_DX8GCR1_QSSEL_DEFVAL                                               0x00007FFF
14013 #define DDR_PHY_DX8GCR1_QSSEL_SHIFT                                                13
14014 #define DDR_PHY_DX8GCR1_QSSEL_MASK                                                 0x00002000U
14015
14016 /*Enables Read Data Strobe in a byte lane*/
14017 #undef DDR_PHY_DX8GCR1_OEEN_DEFVAL
14018 #undef DDR_PHY_DX8GCR1_OEEN_SHIFT
14019 #undef DDR_PHY_DX8GCR1_OEEN_MASK
14020 #define DDR_PHY_DX8GCR1_OEEN_DEFVAL                                                0x00007FFF
14021 #define DDR_PHY_DX8GCR1_OEEN_SHIFT                                                 12
14022 #define DDR_PHY_DX8GCR1_OEEN_MASK                                                  0x00001000U
14023
14024 /*Enables PDR in a byte lane*/
14025 #undef DDR_PHY_DX8GCR1_PDREN_DEFVAL
14026 #undef DDR_PHY_DX8GCR1_PDREN_SHIFT
14027 #undef DDR_PHY_DX8GCR1_PDREN_MASK
14028 #define DDR_PHY_DX8GCR1_PDREN_DEFVAL                                               0x00007FFF
14029 #define DDR_PHY_DX8GCR1_PDREN_SHIFT                                                11
14030 #define DDR_PHY_DX8GCR1_PDREN_MASK                                                 0x00000800U
14031
14032 /*Enables ODT/TE in a byte lane*/
14033 #undef DDR_PHY_DX8GCR1_TEEN_DEFVAL
14034 #undef DDR_PHY_DX8GCR1_TEEN_SHIFT
14035 #undef DDR_PHY_DX8GCR1_TEEN_MASK
14036 #define DDR_PHY_DX8GCR1_TEEN_DEFVAL                                                0x00007FFF
14037 #define DDR_PHY_DX8GCR1_TEEN_SHIFT                                                 10
14038 #define DDR_PHY_DX8GCR1_TEEN_MASK                                                  0x00000400U
14039
14040 /*Enables Write Data strobe in a byte lane*/
14041 #undef DDR_PHY_DX8GCR1_DSEN_DEFVAL
14042 #undef DDR_PHY_DX8GCR1_DSEN_SHIFT
14043 #undef DDR_PHY_DX8GCR1_DSEN_MASK
14044 #define DDR_PHY_DX8GCR1_DSEN_DEFVAL                                                0x00007FFF
14045 #define DDR_PHY_DX8GCR1_DSEN_SHIFT                                                 9
14046 #define DDR_PHY_DX8GCR1_DSEN_MASK                                                  0x00000200U
14047
14048 /*Enables DM pin in a byte lane*/
14049 #undef DDR_PHY_DX8GCR1_DMEN_DEFVAL
14050 #undef DDR_PHY_DX8GCR1_DMEN_SHIFT
14051 #undef DDR_PHY_DX8GCR1_DMEN_MASK
14052 #define DDR_PHY_DX8GCR1_DMEN_DEFVAL                                                0x00007FFF
14053 #define DDR_PHY_DX8GCR1_DMEN_SHIFT                                                 8
14054 #define DDR_PHY_DX8GCR1_DMEN_MASK                                                  0x00000100U
14055
14056 /*Enables DQ corresponding to each bit in a byte*/
14057 #undef DDR_PHY_DX8GCR1_DQEN_DEFVAL
14058 #undef DDR_PHY_DX8GCR1_DQEN_SHIFT
14059 #undef DDR_PHY_DX8GCR1_DQEN_MASK
14060 #define DDR_PHY_DX8GCR1_DQEN_DEFVAL                                                0x00007FFF
14061 #define DDR_PHY_DX8GCR1_DQEN_SHIFT                                                 0
14062 #define DDR_PHY_DX8GCR1_DQEN_MASK                                                  0x000000FFU
14063
14064 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
14065 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL
14066 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
14067 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK
14068 #define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
14069 #define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT                                       29
14070 #define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK                                        0xE0000000U
14071
14072 /*Byte Lane VREF Pad Enable*/
14073 #undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL
14074 #undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
14075 #undef DDR_PHY_DX8GCR4_DXREFPEN_MASK
14076 #define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
14077 #define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT                                             28
14078 #define DDR_PHY_DX8GCR4_DXREFPEN_MASK                                              0x10000000U
14079
14080 /*Byte Lane Internal VREF Enable*/
14081 #undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL
14082 #undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
14083 #undef DDR_PHY_DX8GCR4_DXREFEEN_MASK
14084 #define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
14085 #define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT                                             26
14086 #define DDR_PHY_DX8GCR4_DXREFEEN_MASK                                              0x0C000000U
14087
14088 /*Byte Lane Single-End VREF Enable*/
14089 #undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL
14090 #undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
14091 #undef DDR_PHY_DX8GCR4_DXREFSEN_MASK
14092 #define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
14093 #define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT                                             25
14094 #define DDR_PHY_DX8GCR4_DXREFSEN_MASK                                              0x02000000U
14095
14096 /*Reserved. Returns zeros on reads.*/
14097 #undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL
14098 #undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
14099 #undef DDR_PHY_DX8GCR4_RESERVED_24_MASK
14100 #define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
14101 #define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT                                          24
14102 #define DDR_PHY_DX8GCR4_RESERVED_24_MASK                                           0x01000000U
14103
14104 /*External VREF generator REFSEL range select*/
14105 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL
14106 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
14107 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK
14108 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
14109 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT                                       23
14110 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK                                        0x00800000U
14111
14112 /*Byte Lane External VREF Select*/
14113 #undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL
14114 #undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
14115 #undef DDR_PHY_DX8GCR4_DXREFESEL_MASK
14116 #define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
14117 #define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT                                            16
14118 #define DDR_PHY_DX8GCR4_DXREFESEL_MASK                                             0x007F0000U
14119
14120 /*Single ended VREF generator REFSEL range select*/
14121 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL
14122 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
14123 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK
14124 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
14125 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT                                       15
14126 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
14127
14128 /*Byte Lane Single-End VREF Select*/
14129 #undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL
14130 #undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
14131 #undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK
14132 #define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
14133 #define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT                                            8
14134 #define DDR_PHY_DX8GCR4_DXREFSSEL_MASK                                             0x00007F00U
14135
14136 /*Reserved. Returns zeros on reads.*/
14137 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL
14138 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
14139 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK
14140 #define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
14141 #define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT                                         6
14142 #define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK                                          0x000000C0U
14143
14144 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
14145 #undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL
14146 #undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
14147 #undef DDR_PHY_DX8GCR4_DXREFIEN_MASK
14148 #define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
14149 #define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT                                             2
14150 #define DDR_PHY_DX8GCR4_DXREFIEN_MASK                                              0x0000003CU
14151
14152 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
14153 #undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL
14154 #undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
14155 #undef DDR_PHY_DX8GCR4_DXREFIMON_MASK
14156 #define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
14157 #define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT                                            0
14158 #define DDR_PHY_DX8GCR4_DXREFIMON_MASK                                             0x00000003U
14159
14160 /*Reserved. Returns zeros on reads.*/
14161 #undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL
14162 #undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
14163 #undef DDR_PHY_DX8GCR5_RESERVED_31_MASK
14164 #define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL                                         0x09090909
14165 #define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT                                          31
14166 #define DDR_PHY_DX8GCR5_RESERVED_31_MASK                                           0x80000000U
14167
14168 /*Byte Lane internal VREF Select for Rank 3*/
14169 #undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL
14170 #undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
14171 #undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK
14172 #define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL                                         0x09090909
14173 #define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT                                          24
14174 #define DDR_PHY_DX8GCR5_DXREFISELR3_MASK                                           0x7F000000U
14175
14176 /*Reserved. Returns zeros on reads.*/
14177 #undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL
14178 #undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
14179 #undef DDR_PHY_DX8GCR5_RESERVED_23_MASK
14180 #define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL                                         0x09090909
14181 #define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT                                          23
14182 #define DDR_PHY_DX8GCR5_RESERVED_23_MASK                                           0x00800000U
14183
14184 /*Byte Lane internal VREF Select for Rank 2*/
14185 #undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL
14186 #undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
14187 #undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK
14188 #define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL                                         0x09090909
14189 #define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT                                          16
14190 #define DDR_PHY_DX8GCR5_DXREFISELR2_MASK                                           0x007F0000U
14191
14192 /*Reserved. Returns zeros on reads.*/
14193 #undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL
14194 #undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
14195 #undef DDR_PHY_DX8GCR5_RESERVED_15_MASK
14196 #define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL                                         0x09090909
14197 #define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT                                          15
14198 #define DDR_PHY_DX8GCR5_RESERVED_15_MASK                                           0x00008000U
14199
14200 /*Byte Lane internal VREF Select for Rank 1*/
14201 #undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL
14202 #undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
14203 #undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK
14204 #define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL                                         0x09090909
14205 #define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT                                          8
14206 #define DDR_PHY_DX8GCR5_DXREFISELR1_MASK                                           0x00007F00U
14207
14208 /*Reserved. Returns zeros on reads.*/
14209 #undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL
14210 #undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
14211 #undef DDR_PHY_DX8GCR5_RESERVED_7_MASK
14212 #define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL                                          0x09090909
14213 #define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT                                           7
14214 #define DDR_PHY_DX8GCR5_RESERVED_7_MASK                                            0x00000080U
14215
14216 /*Byte Lane internal VREF Select for Rank 0*/
14217 #undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL
14218 #undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
14219 #undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK
14220 #define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL                                         0x09090909
14221 #define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT                                          0
14222 #define DDR_PHY_DX8GCR5_DXREFISELR0_MASK                                           0x0000007FU
14223
14224 /*Reserved. Returns zeros on reads.*/
14225 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL
14226 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
14227 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK
14228 #define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
14229 #define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT                                       30
14230 #define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK                                        0xC0000000U
14231
14232 /*DRAM DQ VREF Select for Rank3*/
14233 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL
14234 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
14235 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK
14236 #define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
14237 #define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT                                           24
14238 #define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK                                            0x3F000000U
14239
14240 /*Reserved. Returns zeros on reads.*/
14241 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL
14242 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
14243 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK
14244 #define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
14245 #define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT                                       22
14246 #define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK                                        0x00C00000U
14247
14248 /*DRAM DQ VREF Select for Rank2*/
14249 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL
14250 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
14251 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK
14252 #define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
14253 #define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT                                           16
14254 #define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK                                            0x003F0000U
14255
14256 /*Reserved. Returns zeros on reads.*/
14257 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL
14258 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
14259 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK
14260 #define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
14261 #define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT                                       14
14262 #define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK                                        0x0000C000U
14263
14264 /*DRAM DQ VREF Select for Rank1*/
14265 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL
14266 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
14267 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK
14268 #define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
14269 #define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT                                           8
14270 #define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK                                            0x00003F00U
14271
14272 /*Reserved. Returns zeros on reads.*/
14273 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL
14274 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
14275 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK
14276 #define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
14277 #define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT                                         6
14278 #define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK                                          0x000000C0U
14279
14280 /*DRAM DQ VREF Select for Rank0*/
14281 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL
14282 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
14283 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK
14284 #define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
14285 #define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT                                           0
14286 #define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK                                            0x0000003FU
14287
14288 /*Reserved. Return zeroes on reads.*/
14289 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL
14290 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT
14291 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK
14292 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
14293 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT                                     25
14294 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
14295
14296 /*Reserved. Caution, do not write to this register field.*/
14297 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL
14298 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT
14299 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK
14300 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
14301 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT                                     16
14302 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
14303
14304 /*Reserved. Return zeroes on reads.*/
14305 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL
14306 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT
14307 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK
14308 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
14309 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT                                      9
14310 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
14311
14312 /*Read DQS Gating Delay*/
14313 #undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL
14314 #undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT
14315 #undef DDR_PHY_DX8LCDLR2_DQSGD_MASK
14316 #define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL                                             0x00000000
14317 #define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT                                              0
14318 #define DDR_PHY_DX8LCDLR2_DQSGD_MASK                                               0x000001FFU
14319
14320 /*Reserved. Return zeroes on reads.*/
14321 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL
14322 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT
14323 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK
14324 #define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
14325 #define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT                                       27
14326 #define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK                                        0xF8000000U
14327
14328 /*DQ Write Path Latency Pipeline*/
14329 #undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL
14330 #undef DDR_PHY_DX8GTR0_WDQSL_SHIFT
14331 #undef DDR_PHY_DX8GTR0_WDQSL_MASK
14332 #define DDR_PHY_DX8GTR0_WDQSL_DEFVAL                                               0x00020000
14333 #define DDR_PHY_DX8GTR0_WDQSL_SHIFT                                                24
14334 #define DDR_PHY_DX8GTR0_WDQSL_MASK                                                 0x07000000U
14335
14336 /*Reserved. Caution, do not write to this register field.*/
14337 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL
14338 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT
14339 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK
14340 #define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
14341 #define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT                                       20
14342 #define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK                                        0x00F00000U
14343
14344 /*Write Leveling System Latency*/
14345 #undef DDR_PHY_DX8GTR0_WLSL_DEFVAL
14346 #undef DDR_PHY_DX8GTR0_WLSL_SHIFT
14347 #undef DDR_PHY_DX8GTR0_WLSL_MASK
14348 #define DDR_PHY_DX8GTR0_WLSL_DEFVAL                                                0x00020000
14349 #define DDR_PHY_DX8GTR0_WLSL_SHIFT                                                 16
14350 #define DDR_PHY_DX8GTR0_WLSL_MASK                                                  0x000F0000U
14351
14352 /*Reserved. Return zeroes on reads.*/
14353 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL
14354 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT
14355 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK
14356 #define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
14357 #define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT                                       13
14358 #define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK                                        0x0000E000U
14359
14360 /*Reserved. Caution, do not write to this register field.*/
14361 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL
14362 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT
14363 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK
14364 #define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
14365 #define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT                                        8
14366 #define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK                                         0x00001F00U
14367
14368 /*Reserved. Return zeroes on reads.*/
14369 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL
14370 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT
14371 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK
14372 #define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
14373 #define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT                                         5
14374 #define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK                                          0x000000E0U
14375
14376 /*DQS Gating System Latency*/
14377 #undef DDR_PHY_DX8GTR0_DGSL_DEFVAL
14378 #undef DDR_PHY_DX8GTR0_DGSL_SHIFT
14379 #undef DDR_PHY_DX8GTR0_DGSL_MASK
14380 #define DDR_PHY_DX8GTR0_DGSL_DEFVAL                                                0x00020000
14381 #define DDR_PHY_DX8GTR0_DGSL_SHIFT                                                 0
14382 #define DDR_PHY_DX8GTR0_DGSL_MASK                                                  0x0000001FU
14383
14384 /*Reserved. Return zeroes on reads.*/
14385 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL
14386 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
14387 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK
14388 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL                                    0x00019FFE
14389 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT                                     30
14390 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK                                      0xC0000000U
14391
14392 /*Enable Clock Gating for DX ddr_clk*/
14393 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL
14394 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
14395 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK
14396 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL                                       0x00019FFE
14397 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT                                        28
14398 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK                                         0x30000000U
14399
14400 /*Enable Clock Gating for DX ctl_rd_clk*/
14401 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL
14402 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
14403 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK
14404 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL                                      0x00019FFE
14405 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT                                       26
14406 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK                                        0x0C000000U
14407
14408 /*Enable Clock Gating for DX ctl_clk*/
14409 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL
14410 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
14411 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK
14412 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL                                      0x00019FFE
14413 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT                                       24
14414 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK                                        0x03000000U
14415
14416 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
14417 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL
14418 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
14419 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK
14420 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL                                          0x00019FFE
14421 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT                                           22
14422 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK                                            0x00C00000U
14423
14424 /*Loopback Mode*/
14425 #undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL
14426 #undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
14427 #undef DDR_PHY_DX8SL0OSC_LBMODE_MASK
14428 #define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL                                            0x00019FFE
14429 #define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT                                             21
14430 #define DDR_PHY_DX8SL0OSC_LBMODE_MASK                                              0x00200000U
14431
14432 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
14433 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL
14434 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
14435 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK
14436 #define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL                                           0x00019FFE
14437 #define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT                                            20
14438 #define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK                                             0x00100000U
14439
14440 /*Loopback DQS Gating*/
14441 #undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL
14442 #undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
14443 #undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK
14444 #define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL                                            0x00019FFE
14445 #define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT                                             18
14446 #define DDR_PHY_DX8SL0OSC_LBGDQS_MASK                                              0x000C0000U
14447
14448 /*Loopback DQS Shift*/
14449 #undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL
14450 #undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
14451 #undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK
14452 #define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL                                            0x00019FFE
14453 #define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT                                             17
14454 #define DDR_PHY_DX8SL0OSC_LBDQSS_MASK                                              0x00020000U
14455
14456 /*PHY High-Speed Reset*/
14457 #undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL
14458 #undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
14459 #undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK
14460 #define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL                                           0x00019FFE
14461 #define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT                                            16
14462 #define DDR_PHY_DX8SL0OSC_PHYHRST_MASK                                             0x00010000U
14463
14464 /*PHY FIFO Reset*/
14465 #undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL
14466 #undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
14467 #undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK
14468 #define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL                                           0x00019FFE
14469 #define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT                                            15
14470 #define DDR_PHY_DX8SL0OSC_PHYFRST_MASK                                             0x00008000U
14471
14472 /*Delay Line Test Start*/
14473 #undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL
14474 #undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT
14475 #undef DDR_PHY_DX8SL0OSC_DLTST_MASK
14476 #define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL                                             0x00019FFE
14477 #define DDR_PHY_DX8SL0OSC_DLTST_SHIFT                                              14
14478 #define DDR_PHY_DX8SL0OSC_DLTST_MASK                                               0x00004000U
14479
14480 /*Delay Line Test Mode*/
14481 #undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL
14482 #undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
14483 #undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK
14484 #define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL                                           0x00019FFE
14485 #define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT                                            13
14486 #define DDR_PHY_DX8SL0OSC_DLTMODE_MASK                                             0x00002000U
14487
14488 /*Reserved. Caution, do not write to this register field.*/
14489 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL
14490 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
14491 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK
14492 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL                                    0x00019FFE
14493 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT                                     11
14494 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK                                      0x00001800U
14495
14496 /*Oscillator Mode Write-Data Delay Line Select*/
14497 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL
14498 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
14499 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK
14500 #define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL                                           0x00019FFE
14501 #define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT                                            9
14502 #define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK                                             0x00000600U
14503
14504 /*Reserved. Caution, do not write to this register field.*/
14505 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL
14506 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
14507 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK
14508 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL                                      0x00019FFE
14509 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT                                       7
14510 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK                                        0x00000180U
14511
14512 /*Oscillator Mode Write-Leveling Delay Line Select*/
14513 #undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL
14514 #undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
14515 #undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK
14516 #define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL                                            0x00019FFE
14517 #define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT                                             5
14518 #define DDR_PHY_DX8SL0OSC_OSCWDL_MASK                                              0x00000060U
14519
14520 /*Oscillator Mode Division*/
14521 #undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL
14522 #undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
14523 #undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK
14524 #define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL                                            0x00019FFE
14525 #define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT                                             1
14526 #define DDR_PHY_DX8SL0OSC_OSCDIV_MASK                                              0x0000001EU
14527
14528 /*Oscillator Enable*/
14529 #undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL
14530 #undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
14531 #undef DDR_PHY_DX8SL0OSC_OSCEN_MASK
14532 #define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL                                             0x00019FFE
14533 #define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT                                              0
14534 #define DDR_PHY_DX8SL0OSC_OSCEN_MASK                                               0x00000001U
14535
14536 /*Reserved. Return zeroes on reads.*/
14537 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL
14538 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
14539 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK
14540 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
14541 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT                                  25
14542 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
14543
14544 /*Read Path Rise-to-Rise Mode*/
14545 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL
14546 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
14547 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK
14548 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL                                        0x01264000
14549 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT                                         24
14550 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK                                          0x01000000U
14551
14552 /*Reserved. Return zeroes on reads.*/
14553 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL
14554 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
14555 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK
14556 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
14557 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT                                  22
14558 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
14559
14560 /*Write Path Rise-to-Rise Mode*/
14561 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL
14562 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
14563 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK
14564 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL                                        0x01264000
14565 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT                                         21
14566 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK                                          0x00200000U
14567
14568 /*DQS Gate Extension*/
14569 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL
14570 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
14571 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK
14572 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL                                          0x01264000
14573 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT                                           19
14574 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK                                            0x00180000U
14575
14576 /*Low Power PLL Power Down*/
14577 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL
14578 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
14579 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK
14580 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
14581 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT                                         18
14582 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK                                          0x00040000U
14583
14584 /*Low Power I/O Power Down*/
14585 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL
14586 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
14587 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK
14588 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL                                         0x01264000
14589 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT                                          17
14590 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK                                           0x00020000U
14591
14592 /*Reserved. Return zeroes on reads.*/
14593 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL
14594 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
14595 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK
14596 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
14597 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT                                  15
14598 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
14599
14600 /*QS Counter Enable*/
14601 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL
14602 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
14603 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK
14604 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
14605 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT                                         14
14606 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK                                          0x00004000U
14607
14608 /*Unused DQ I/O Mode*/
14609 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL
14610 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
14611 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK
14612 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL                                         0x01264000
14613 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT                                          13
14614 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK                                           0x00002000U
14615
14616 /*Reserved. Return zeroes on reads.*/
14617 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL
14618 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
14619 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK
14620 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
14621 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT                                  10
14622 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
14623
14624 /*Data Slew Rate*/
14625 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL
14626 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
14627 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK
14628 #define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL                                           0x01264000
14629 #define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT                                            8
14630 #define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK                                             0x00000300U
14631
14632 /*DQS_N Resistor*/
14633 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL
14634 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
14635 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK
14636 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL                                        0x01264000
14637 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT                                         4
14638 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK                                          0x000000F0U
14639
14640 /*DQS Resistor*/
14641 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL
14642 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
14643 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK
14644 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL                                         0x01264000
14645 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT                                          0
14646 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK                                           0x0000000FU
14647
14648 /*Reserved. Return zeroes on reads.*/
14649 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL
14650 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
14651 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK
14652 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
14653 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT                                  24
14654 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
14655
14656 /*Configurable Read Data Enable*/
14657 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL
14658 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
14659 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK
14660 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL                                          0x00141800
14661 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT                                           23
14662 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK                                            0x00800000U
14663
14664 /*OX Extension during Post-amble*/
14665 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL
14666 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
14667 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK
14668 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL                                         0x00141800
14669 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT                                          20
14670 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK                                           0x00700000U
14671
14672 /*OE Extension during Pre-amble*/
14673 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL
14674 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
14675 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK
14676 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL                                         0x00141800
14677 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT                                          18
14678 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK                                           0x000C0000U
14679
14680 /*Reserved. Return zeroes on reads.*/
14681 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL
14682 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
14683 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK
14684 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
14685 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT                                     17
14686 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK                                      0x00020000U
14687
14688 /*I/O Assisted Gate Select*/
14689 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL
14690 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
14691 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK
14692 #define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL                                           0x00141800
14693 #define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT                                            16
14694 #define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK                                             0x00010000U
14695
14696 /*I/O Loopback Select*/
14697 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL
14698 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
14699 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK
14700 #define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL                                           0x00141800
14701 #define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT                                            15
14702 #define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK                                             0x00008000U
14703
14704 /*Reserved. Return zeroes on reads.*/
14705 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL
14706 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
14707 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK
14708 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
14709 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT                                  13
14710 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
14711
14712 /*Low Power Wakeup Threshold*/
14713 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL
14714 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
14715 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK
14716 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
14717 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
14718 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
14719
14720 /*Read Data Bus Inversion Enable*/
14721 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL
14722 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
14723 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK
14724 #define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL                                           0x00141800
14725 #define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT                                            8
14726 #define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK                                             0x00000100U
14727
14728 /*Write Data Bus Inversion Enable*/
14729 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL
14730 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
14731 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK
14732 #define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL                                           0x00141800
14733 #define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT                                            7
14734 #define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK                                             0x00000080U
14735
14736 /*PUB Read FIFO Bypass*/
14737 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL
14738 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
14739 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK
14740 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL                                         0x00141800
14741 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT                                          6
14742 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK                                           0x00000040U
14743
14744 /*DATX8 Receive FIFO Read Mode*/
14745 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL
14746 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
14747 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK
14748 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL                                         0x00141800
14749 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT                                          4
14750 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK                                           0x00000030U
14751
14752 /*Disables the Read FIFO Reset*/
14753 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL
14754 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
14755 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK
14756 #define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL                                         0x00141800
14757 #define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT                                          3
14758 #define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK                                           0x00000008U
14759
14760 /*Read DQS Gate I/O Loopback*/
14761 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL
14762 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
14763 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK
14764 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL                                         0x00141800
14765 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT                                          1
14766 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK                                           0x00000006U
14767
14768 /*Reserved. Return zeroes on reads.*/
14769 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL
14770 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
14771 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK
14772 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
14773 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT                                      0
14774 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK                                       0x00000001U
14775
14776 /*Reserved. Return zeroes on reads.*/
14777 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL
14778 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
14779 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK
14780 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL                                      0x00000000
14781 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT                                       31
14782 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK                                        0x80000000U
14783
14784 /*PVREF_DAC REFSEL range select*/
14785 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL
14786 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
14787 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK
14788 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL                                       0x00000000
14789 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT                                        28
14790 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK                                         0x70000000U
14791
14792 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
14793 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL
14794 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
14795 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK
14796 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL                                        0x00000000
14797 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT                                         25
14798 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK                                          0x0E000000U
14799
14800 /*DX IO Mode*/
14801 #undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL
14802 #undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
14803 #undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK
14804 #define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL                                            0x00000000
14805 #define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT                                             22
14806 #define DDR_PHY_DX8SL0IOCR_DXIOM_MASK                                              0x01C00000U
14807
14808 /*DX IO Transmitter Mode*/
14809 #undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL
14810 #undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
14811 #undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK
14812 #define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL                                            0x00000000
14813 #define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT                                             11
14814 #define DDR_PHY_DX8SL0IOCR_DXTXM_MASK                                              0x003FF800U
14815
14816 /*DX IO Receiver Mode*/
14817 #undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL
14818 #undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
14819 #undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK
14820 #define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL                                            0x00000000
14821 #define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT                                             0
14822 #define DDR_PHY_DX8SL0IOCR_DXRXM_MASK                                              0x000007FFU
14823
14824 /*Reserved. Return zeroes on reads.*/
14825 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL
14826 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
14827 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK
14828 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL                                    0x00019FFE
14829 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT                                     30
14830 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK                                      0xC0000000U
14831
14832 /*Enable Clock Gating for DX ddr_clk*/
14833 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL
14834 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
14835 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK
14836 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL                                       0x00019FFE
14837 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT                                        28
14838 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK                                         0x30000000U
14839
14840 /*Enable Clock Gating for DX ctl_rd_clk*/
14841 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL
14842 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
14843 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK
14844 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL                                      0x00019FFE
14845 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT                                       26
14846 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK                                        0x0C000000U
14847
14848 /*Enable Clock Gating for DX ctl_clk*/
14849 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL
14850 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
14851 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK
14852 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL                                      0x00019FFE
14853 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT                                       24
14854 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK                                        0x03000000U
14855
14856 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
14857 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL
14858 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
14859 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK
14860 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL                                          0x00019FFE
14861 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT                                           22
14862 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK                                            0x00C00000U
14863
14864 /*Loopback Mode*/
14865 #undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL
14866 #undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
14867 #undef DDR_PHY_DX8SL1OSC_LBMODE_MASK
14868 #define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL                                            0x00019FFE
14869 #define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT                                             21
14870 #define DDR_PHY_DX8SL1OSC_LBMODE_MASK                                              0x00200000U
14871
14872 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
14873 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL
14874 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
14875 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK
14876 #define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL                                           0x00019FFE
14877 #define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT                                            20
14878 #define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK                                             0x00100000U
14879
14880 /*Loopback DQS Gating*/
14881 #undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL
14882 #undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
14883 #undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK
14884 #define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL                                            0x00019FFE
14885 #define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT                                             18
14886 #define DDR_PHY_DX8SL1OSC_LBGDQS_MASK                                              0x000C0000U
14887
14888 /*Loopback DQS Shift*/
14889 #undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL
14890 #undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
14891 #undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK
14892 #define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL                                            0x00019FFE
14893 #define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT                                             17
14894 #define DDR_PHY_DX8SL1OSC_LBDQSS_MASK                                              0x00020000U
14895
14896 /*PHY High-Speed Reset*/
14897 #undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL
14898 #undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
14899 #undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK
14900 #define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL                                           0x00019FFE
14901 #define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT                                            16
14902 #define DDR_PHY_DX8SL1OSC_PHYHRST_MASK                                             0x00010000U
14903
14904 /*PHY FIFO Reset*/
14905 #undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL
14906 #undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
14907 #undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK
14908 #define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL                                           0x00019FFE
14909 #define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT                                            15
14910 #define DDR_PHY_DX8SL1OSC_PHYFRST_MASK                                             0x00008000U
14911
14912 /*Delay Line Test Start*/
14913 #undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL
14914 #undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT
14915 #undef DDR_PHY_DX8SL1OSC_DLTST_MASK
14916 #define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL                                             0x00019FFE
14917 #define DDR_PHY_DX8SL1OSC_DLTST_SHIFT                                              14
14918 #define DDR_PHY_DX8SL1OSC_DLTST_MASK                                               0x00004000U
14919
14920 /*Delay Line Test Mode*/
14921 #undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL
14922 #undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
14923 #undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK
14924 #define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL                                           0x00019FFE
14925 #define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT                                            13
14926 #define DDR_PHY_DX8SL1OSC_DLTMODE_MASK                                             0x00002000U
14927
14928 /*Reserved. Caution, do not write to this register field.*/
14929 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL
14930 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
14931 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK
14932 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL                                    0x00019FFE
14933 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT                                     11
14934 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK                                      0x00001800U
14935
14936 /*Oscillator Mode Write-Data Delay Line Select*/
14937 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL
14938 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
14939 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK
14940 #define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL                                           0x00019FFE
14941 #define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT                                            9
14942 #define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK                                             0x00000600U
14943
14944 /*Reserved. Caution, do not write to this register field.*/
14945 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL
14946 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
14947 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK
14948 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL                                      0x00019FFE
14949 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT                                       7
14950 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK                                        0x00000180U
14951
14952 /*Oscillator Mode Write-Leveling Delay Line Select*/
14953 #undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL
14954 #undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
14955 #undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK
14956 #define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL                                            0x00019FFE
14957 #define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT                                             5
14958 #define DDR_PHY_DX8SL1OSC_OSCWDL_MASK                                              0x00000060U
14959
14960 /*Oscillator Mode Division*/
14961 #undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL
14962 #undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
14963 #undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK
14964 #define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL                                            0x00019FFE
14965 #define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT                                             1
14966 #define DDR_PHY_DX8SL1OSC_OSCDIV_MASK                                              0x0000001EU
14967
14968 /*Oscillator Enable*/
14969 #undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL
14970 #undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
14971 #undef DDR_PHY_DX8SL1OSC_OSCEN_MASK
14972 #define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL                                             0x00019FFE
14973 #define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT                                              0
14974 #define DDR_PHY_DX8SL1OSC_OSCEN_MASK                                               0x00000001U
14975
14976 /*Reserved. Return zeroes on reads.*/
14977 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL
14978 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
14979 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK
14980 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
14981 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT                                  25
14982 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
14983
14984 /*Read Path Rise-to-Rise Mode*/
14985 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL
14986 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
14987 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK
14988 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL                                        0x01264000
14989 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT                                         24
14990 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK                                          0x01000000U
14991
14992 /*Reserved. Return zeroes on reads.*/
14993 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL
14994 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
14995 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK
14996 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
14997 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT                                  22
14998 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
14999
15000 /*Write Path Rise-to-Rise Mode*/
15001 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL
15002 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
15003 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK
15004 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL                                        0x01264000
15005 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT                                         21
15006 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK                                          0x00200000U
15007
15008 /*DQS Gate Extension*/
15009 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL
15010 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
15011 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK
15012 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL                                          0x01264000
15013 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT                                           19
15014 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK                                            0x00180000U
15015
15016 /*Low Power PLL Power Down*/
15017 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL
15018 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
15019 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK
15020 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
15021 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT                                         18
15022 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK                                          0x00040000U
15023
15024 /*Low Power I/O Power Down*/
15025 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL
15026 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
15027 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK
15028 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL                                         0x01264000
15029 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT                                          17
15030 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK                                           0x00020000U
15031
15032 /*Reserved. Return zeroes on reads.*/
15033 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL
15034 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
15035 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK
15036 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
15037 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT                                  15
15038 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
15039
15040 /*QS Counter Enable*/
15041 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL
15042 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
15043 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK
15044 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
15045 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT                                         14
15046 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK                                          0x00004000U
15047
15048 /*Unused DQ I/O Mode*/
15049 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL
15050 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
15051 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK
15052 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL                                         0x01264000
15053 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT                                          13
15054 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK                                           0x00002000U
15055
15056 /*Reserved. Return zeroes on reads.*/
15057 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL
15058 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
15059 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK
15060 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
15061 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT                                  10
15062 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
15063
15064 /*Data Slew Rate*/
15065 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL
15066 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
15067 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK
15068 #define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL                                           0x01264000
15069 #define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT                                            8
15070 #define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK                                             0x00000300U
15071
15072 /*DQS_N Resistor*/
15073 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL
15074 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
15075 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK
15076 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL                                        0x01264000
15077 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT                                         4
15078 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK                                          0x000000F0U
15079
15080 /*DQS Resistor*/
15081 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL
15082 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
15083 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK
15084 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL                                         0x01264000
15085 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT                                          0
15086 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK                                           0x0000000FU
15087
15088 /*Reserved. Return zeroes on reads.*/
15089 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL
15090 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
15091 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK
15092 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
15093 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT                                  24
15094 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
15095
15096 /*Configurable Read Data Enable*/
15097 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL
15098 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
15099 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK
15100 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL                                          0x00141800
15101 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT                                           23
15102 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK                                            0x00800000U
15103
15104 /*OX Extension during Post-amble*/
15105 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL
15106 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
15107 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK
15108 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL                                         0x00141800
15109 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT                                          20
15110 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK                                           0x00700000U
15111
15112 /*OE Extension during Pre-amble*/
15113 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL
15114 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
15115 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK
15116 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL                                         0x00141800
15117 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT                                          18
15118 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK                                           0x000C0000U
15119
15120 /*Reserved. Return zeroes on reads.*/
15121 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL
15122 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
15123 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK
15124 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
15125 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT                                     17
15126 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK                                      0x00020000U
15127
15128 /*I/O Assisted Gate Select*/
15129 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL
15130 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
15131 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK
15132 #define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL                                           0x00141800
15133 #define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT                                            16
15134 #define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK                                             0x00010000U
15135
15136 /*I/O Loopback Select*/
15137 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL
15138 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
15139 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK
15140 #define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL                                           0x00141800
15141 #define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT                                            15
15142 #define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK                                             0x00008000U
15143
15144 /*Reserved. Return zeroes on reads.*/
15145 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL
15146 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
15147 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK
15148 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
15149 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT                                  13
15150 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
15151
15152 /*Low Power Wakeup Threshold*/
15153 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL
15154 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
15155 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK
15156 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
15157 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
15158 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
15159
15160 /*Read Data Bus Inversion Enable*/
15161 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL
15162 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
15163 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK
15164 #define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL                                           0x00141800
15165 #define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT                                            8
15166 #define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK                                             0x00000100U
15167
15168 /*Write Data Bus Inversion Enable*/
15169 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL
15170 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
15171 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK
15172 #define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL                                           0x00141800
15173 #define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT                                            7
15174 #define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK                                             0x00000080U
15175
15176 /*PUB Read FIFO Bypass*/
15177 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL
15178 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
15179 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK
15180 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL                                         0x00141800
15181 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT                                          6
15182 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK                                           0x00000040U
15183
15184 /*DATX8 Receive FIFO Read Mode*/
15185 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL
15186 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
15187 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK
15188 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL                                         0x00141800
15189 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT                                          4
15190 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK                                           0x00000030U
15191
15192 /*Disables the Read FIFO Reset*/
15193 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL
15194 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
15195 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK
15196 #define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL                                         0x00141800
15197 #define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT                                          3
15198 #define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK                                           0x00000008U
15199
15200 /*Read DQS Gate I/O Loopback*/
15201 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL
15202 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
15203 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK
15204 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL                                         0x00141800
15205 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT                                          1
15206 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK                                           0x00000006U
15207
15208 /*Reserved. Return zeroes on reads.*/
15209 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL
15210 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
15211 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK
15212 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
15213 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT                                      0
15214 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK                                       0x00000001U
15215
15216 /*Reserved. Return zeroes on reads.*/
15217 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL
15218 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
15219 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK
15220 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL                                      0x00000000
15221 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT                                       31
15222 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK                                        0x80000000U
15223
15224 /*PVREF_DAC REFSEL range select*/
15225 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL
15226 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
15227 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK
15228 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL                                       0x00000000
15229 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT                                        28
15230 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK                                         0x70000000U
15231
15232 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
15233 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL
15234 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
15235 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK
15236 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL                                        0x00000000
15237 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT                                         25
15238 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK                                          0x0E000000U
15239
15240 /*DX IO Mode*/
15241 #undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL
15242 #undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
15243 #undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK
15244 #define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL                                            0x00000000
15245 #define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT                                             22
15246 #define DDR_PHY_DX8SL1IOCR_DXIOM_MASK                                              0x01C00000U
15247
15248 /*DX IO Transmitter Mode*/
15249 #undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL
15250 #undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
15251 #undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK
15252 #define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL                                            0x00000000
15253 #define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT                                             11
15254 #define DDR_PHY_DX8SL1IOCR_DXTXM_MASK                                              0x003FF800U
15255
15256 /*DX IO Receiver Mode*/
15257 #undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL
15258 #undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
15259 #undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK
15260 #define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL                                            0x00000000
15261 #define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT                                             0
15262 #define DDR_PHY_DX8SL1IOCR_DXRXM_MASK                                              0x000007FFU
15263
15264 /*Reserved. Return zeroes on reads.*/
15265 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL
15266 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
15267 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK
15268 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL                                    0x00019FFE
15269 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT                                     30
15270 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK                                      0xC0000000U
15271
15272 /*Enable Clock Gating for DX ddr_clk*/
15273 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL
15274 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
15275 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK
15276 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL                                       0x00019FFE
15277 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT                                        28
15278 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK                                         0x30000000U
15279
15280 /*Enable Clock Gating for DX ctl_rd_clk*/
15281 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL
15282 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
15283 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK
15284 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL                                      0x00019FFE
15285 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT                                       26
15286 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK                                        0x0C000000U
15287
15288 /*Enable Clock Gating for DX ctl_clk*/
15289 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL
15290 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
15291 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK
15292 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL                                      0x00019FFE
15293 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT                                       24
15294 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK                                        0x03000000U
15295
15296 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
15297 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL
15298 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
15299 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK
15300 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL                                          0x00019FFE
15301 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT                                           22
15302 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK                                            0x00C00000U
15303
15304 /*Loopback Mode*/
15305 #undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL
15306 #undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
15307 #undef DDR_PHY_DX8SL2OSC_LBMODE_MASK
15308 #define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL                                            0x00019FFE
15309 #define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT                                             21
15310 #define DDR_PHY_DX8SL2OSC_LBMODE_MASK                                              0x00200000U
15311
15312 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
15313 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL
15314 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
15315 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK
15316 #define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL                                           0x00019FFE
15317 #define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT                                            20
15318 #define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK                                             0x00100000U
15319
15320 /*Loopback DQS Gating*/
15321 #undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL
15322 #undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
15323 #undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK
15324 #define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL                                            0x00019FFE
15325 #define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT                                             18
15326 #define DDR_PHY_DX8SL2OSC_LBGDQS_MASK                                              0x000C0000U
15327
15328 /*Loopback DQS Shift*/
15329 #undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL
15330 #undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
15331 #undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK
15332 #define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL                                            0x00019FFE
15333 #define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT                                             17
15334 #define DDR_PHY_DX8SL2OSC_LBDQSS_MASK                                              0x00020000U
15335
15336 /*PHY High-Speed Reset*/
15337 #undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL
15338 #undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
15339 #undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK
15340 #define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL                                           0x00019FFE
15341 #define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT                                            16
15342 #define DDR_PHY_DX8SL2OSC_PHYHRST_MASK                                             0x00010000U
15343
15344 /*PHY FIFO Reset*/
15345 #undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL
15346 #undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
15347 #undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK
15348 #define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL                                           0x00019FFE
15349 #define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT                                            15
15350 #define DDR_PHY_DX8SL2OSC_PHYFRST_MASK                                             0x00008000U
15351
15352 /*Delay Line Test Start*/
15353 #undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL
15354 #undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT
15355 #undef DDR_PHY_DX8SL2OSC_DLTST_MASK
15356 #define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL                                             0x00019FFE
15357 #define DDR_PHY_DX8SL2OSC_DLTST_SHIFT                                              14
15358 #define DDR_PHY_DX8SL2OSC_DLTST_MASK                                               0x00004000U
15359
15360 /*Delay Line Test Mode*/
15361 #undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL
15362 #undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
15363 #undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK
15364 #define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL                                           0x00019FFE
15365 #define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT                                            13
15366 #define DDR_PHY_DX8SL2OSC_DLTMODE_MASK                                             0x00002000U
15367
15368 /*Reserved. Caution, do not write to this register field.*/
15369 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL
15370 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
15371 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK
15372 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL                                    0x00019FFE
15373 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT                                     11
15374 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK                                      0x00001800U
15375
15376 /*Oscillator Mode Write-Data Delay Line Select*/
15377 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL
15378 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
15379 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK
15380 #define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL                                           0x00019FFE
15381 #define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT                                            9
15382 #define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK                                             0x00000600U
15383
15384 /*Reserved. Caution, do not write to this register field.*/
15385 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL
15386 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
15387 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK
15388 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL                                      0x00019FFE
15389 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT                                       7
15390 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK                                        0x00000180U
15391
15392 /*Oscillator Mode Write-Leveling Delay Line Select*/
15393 #undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL
15394 #undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
15395 #undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK
15396 #define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL                                            0x00019FFE
15397 #define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT                                             5
15398 #define DDR_PHY_DX8SL2OSC_OSCWDL_MASK                                              0x00000060U
15399
15400 /*Oscillator Mode Division*/
15401 #undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL
15402 #undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
15403 #undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK
15404 #define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL                                            0x00019FFE
15405 #define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT                                             1
15406 #define DDR_PHY_DX8SL2OSC_OSCDIV_MASK                                              0x0000001EU
15407
15408 /*Oscillator Enable*/
15409 #undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL
15410 #undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
15411 #undef DDR_PHY_DX8SL2OSC_OSCEN_MASK
15412 #define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL                                             0x00019FFE
15413 #define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT                                              0
15414 #define DDR_PHY_DX8SL2OSC_OSCEN_MASK                                               0x00000001U
15415
15416 /*Reserved. Return zeroes on reads.*/
15417 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL
15418 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
15419 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK
15420 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
15421 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT                                  25
15422 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
15423
15424 /*Read Path Rise-to-Rise Mode*/
15425 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL
15426 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
15427 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK
15428 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL                                        0x01264000
15429 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT                                         24
15430 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK                                          0x01000000U
15431
15432 /*Reserved. Return zeroes on reads.*/
15433 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL
15434 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
15435 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK
15436 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
15437 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT                                  22
15438 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
15439
15440 /*Write Path Rise-to-Rise Mode*/
15441 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL
15442 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
15443 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK
15444 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL                                        0x01264000
15445 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT                                         21
15446 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK                                          0x00200000U
15447
15448 /*DQS Gate Extension*/
15449 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL
15450 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
15451 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK
15452 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL                                          0x01264000
15453 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT                                           19
15454 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK                                            0x00180000U
15455
15456 /*Low Power PLL Power Down*/
15457 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL
15458 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
15459 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK
15460 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
15461 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT                                         18
15462 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK                                          0x00040000U
15463
15464 /*Low Power I/O Power Down*/
15465 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL
15466 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
15467 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK
15468 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL                                         0x01264000
15469 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT                                          17
15470 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK                                           0x00020000U
15471
15472 /*Reserved. Return zeroes on reads.*/
15473 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL
15474 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
15475 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK
15476 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
15477 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT                                  15
15478 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
15479
15480 /*QS Counter Enable*/
15481 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL
15482 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
15483 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK
15484 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
15485 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT                                         14
15486 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK                                          0x00004000U
15487
15488 /*Unused DQ I/O Mode*/
15489 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL
15490 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
15491 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK
15492 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL                                         0x01264000
15493 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT                                          13
15494 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK                                           0x00002000U
15495
15496 /*Reserved. Return zeroes on reads.*/
15497 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL
15498 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
15499 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK
15500 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
15501 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT                                  10
15502 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
15503
15504 /*Data Slew Rate*/
15505 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL
15506 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
15507 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK
15508 #define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL                                           0x01264000
15509 #define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT                                            8
15510 #define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK                                             0x00000300U
15511
15512 /*DQS_N Resistor*/
15513 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL
15514 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
15515 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK
15516 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL                                        0x01264000
15517 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT                                         4
15518 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK                                          0x000000F0U
15519
15520 /*DQS Resistor*/
15521 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL
15522 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
15523 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK
15524 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL                                         0x01264000
15525 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT                                          0
15526 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK                                           0x0000000FU
15527
15528 /*Reserved. Return zeroes on reads.*/
15529 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL
15530 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
15531 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK
15532 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
15533 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT                                  24
15534 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
15535
15536 /*Configurable Read Data Enable*/
15537 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL
15538 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
15539 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK
15540 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL                                          0x00141800
15541 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT                                           23
15542 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK                                            0x00800000U
15543
15544 /*OX Extension during Post-amble*/
15545 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL
15546 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
15547 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK
15548 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL                                         0x00141800
15549 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT                                          20
15550 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK                                           0x00700000U
15551
15552 /*OE Extension during Pre-amble*/
15553 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL
15554 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
15555 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK
15556 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL                                         0x00141800
15557 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT                                          18
15558 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK                                           0x000C0000U
15559
15560 /*Reserved. Return zeroes on reads.*/
15561 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL
15562 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
15563 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK
15564 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
15565 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT                                     17
15566 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK                                      0x00020000U
15567
15568 /*I/O Assisted Gate Select*/
15569 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL
15570 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
15571 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK
15572 #define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL                                           0x00141800
15573 #define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT                                            16
15574 #define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK                                             0x00010000U
15575
15576 /*I/O Loopback Select*/
15577 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL
15578 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
15579 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK
15580 #define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL                                           0x00141800
15581 #define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT                                            15
15582 #define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK                                             0x00008000U
15583
15584 /*Reserved. Return zeroes on reads.*/
15585 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL
15586 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
15587 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK
15588 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
15589 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT                                  13
15590 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
15591
15592 /*Low Power Wakeup Threshold*/
15593 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL
15594 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
15595 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK
15596 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
15597 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
15598 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
15599
15600 /*Read Data Bus Inversion Enable*/
15601 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL
15602 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
15603 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK
15604 #define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL                                           0x00141800
15605 #define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT                                            8
15606 #define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK                                             0x00000100U
15607
15608 /*Write Data Bus Inversion Enable*/
15609 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL
15610 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
15611 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK
15612 #define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL                                           0x00141800
15613 #define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT                                            7
15614 #define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK                                             0x00000080U
15615
15616 /*PUB Read FIFO Bypass*/
15617 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL
15618 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
15619 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK
15620 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL                                         0x00141800
15621 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT                                          6
15622 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK                                           0x00000040U
15623
15624 /*DATX8 Receive FIFO Read Mode*/
15625 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL
15626 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
15627 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK
15628 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL                                         0x00141800
15629 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT                                          4
15630 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK                                           0x00000030U
15631
15632 /*Disables the Read FIFO Reset*/
15633 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL
15634 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
15635 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK
15636 #define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL                                         0x00141800
15637 #define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT                                          3
15638 #define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK                                           0x00000008U
15639
15640 /*Read DQS Gate I/O Loopback*/
15641 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL
15642 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
15643 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK
15644 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL                                         0x00141800
15645 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT                                          1
15646 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK                                           0x00000006U
15647
15648 /*Reserved. Return zeroes on reads.*/
15649 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL
15650 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
15651 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK
15652 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
15653 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT                                      0
15654 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK                                       0x00000001U
15655
15656 /*Reserved. Return zeroes on reads.*/
15657 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL
15658 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
15659 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK
15660 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL                                      0x00000000
15661 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT                                       31
15662 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK                                        0x80000000U
15663
15664 /*PVREF_DAC REFSEL range select*/
15665 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL
15666 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
15667 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK
15668 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL                                       0x00000000
15669 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT                                        28
15670 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK                                         0x70000000U
15671
15672 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
15673 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL
15674 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
15675 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK
15676 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL                                        0x00000000
15677 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT                                         25
15678 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK                                          0x0E000000U
15679
15680 /*DX IO Mode*/
15681 #undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL
15682 #undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
15683 #undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK
15684 #define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL                                            0x00000000
15685 #define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT                                             22
15686 #define DDR_PHY_DX8SL2IOCR_DXIOM_MASK                                              0x01C00000U
15687
15688 /*DX IO Transmitter Mode*/
15689 #undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL
15690 #undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
15691 #undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK
15692 #define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL                                            0x00000000
15693 #define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT                                             11
15694 #define DDR_PHY_DX8SL2IOCR_DXTXM_MASK                                              0x003FF800U
15695
15696 /*DX IO Receiver Mode*/
15697 #undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL
15698 #undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
15699 #undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK
15700 #define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL                                            0x00000000
15701 #define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT                                             0
15702 #define DDR_PHY_DX8SL2IOCR_DXRXM_MASK                                              0x000007FFU
15703
15704 /*Reserved. Return zeroes on reads.*/
15705 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL
15706 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
15707 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK
15708 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL                                    0x00019FFE
15709 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT                                     30
15710 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK                                      0xC0000000U
15711
15712 /*Enable Clock Gating for DX ddr_clk*/
15713 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL
15714 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
15715 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK
15716 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL                                       0x00019FFE
15717 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT                                        28
15718 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK                                         0x30000000U
15719
15720 /*Enable Clock Gating for DX ctl_rd_clk*/
15721 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL
15722 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
15723 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK
15724 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL                                      0x00019FFE
15725 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT                                       26
15726 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK                                        0x0C000000U
15727
15728 /*Enable Clock Gating for DX ctl_clk*/
15729 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL
15730 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
15731 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK
15732 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL                                      0x00019FFE
15733 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT                                       24
15734 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK                                        0x03000000U
15735
15736 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
15737 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL
15738 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
15739 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK
15740 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL                                          0x00019FFE
15741 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT                                           22
15742 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK                                            0x00C00000U
15743
15744 /*Loopback Mode*/
15745 #undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL
15746 #undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
15747 #undef DDR_PHY_DX8SL3OSC_LBMODE_MASK
15748 #define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL                                            0x00019FFE
15749 #define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT                                             21
15750 #define DDR_PHY_DX8SL3OSC_LBMODE_MASK                                              0x00200000U
15751
15752 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
15753 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL
15754 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
15755 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK
15756 #define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL                                           0x00019FFE
15757 #define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT                                            20
15758 #define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK                                             0x00100000U
15759
15760 /*Loopback DQS Gating*/
15761 #undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL
15762 #undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
15763 #undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK
15764 #define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL                                            0x00019FFE
15765 #define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT                                             18
15766 #define DDR_PHY_DX8SL3OSC_LBGDQS_MASK                                              0x000C0000U
15767
15768 /*Loopback DQS Shift*/
15769 #undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL
15770 #undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
15771 #undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK
15772 #define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL                                            0x00019FFE
15773 #define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT                                             17
15774 #define DDR_PHY_DX8SL3OSC_LBDQSS_MASK                                              0x00020000U
15775
15776 /*PHY High-Speed Reset*/
15777 #undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL
15778 #undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
15779 #undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK
15780 #define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL                                           0x00019FFE
15781 #define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT                                            16
15782 #define DDR_PHY_DX8SL3OSC_PHYHRST_MASK                                             0x00010000U
15783
15784 /*PHY FIFO Reset*/
15785 #undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL
15786 #undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
15787 #undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK
15788 #define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL                                           0x00019FFE
15789 #define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT                                            15
15790 #define DDR_PHY_DX8SL3OSC_PHYFRST_MASK                                             0x00008000U
15791
15792 /*Delay Line Test Start*/
15793 #undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL
15794 #undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT
15795 #undef DDR_PHY_DX8SL3OSC_DLTST_MASK
15796 #define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL                                             0x00019FFE
15797 #define DDR_PHY_DX8SL3OSC_DLTST_SHIFT                                              14
15798 #define DDR_PHY_DX8SL3OSC_DLTST_MASK                                               0x00004000U
15799
15800 /*Delay Line Test Mode*/
15801 #undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL
15802 #undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
15803 #undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK
15804 #define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL                                           0x00019FFE
15805 #define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT                                            13
15806 #define DDR_PHY_DX8SL3OSC_DLTMODE_MASK                                             0x00002000U
15807
15808 /*Reserved. Caution, do not write to this register field.*/
15809 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL
15810 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
15811 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK
15812 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL                                    0x00019FFE
15813 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT                                     11
15814 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK                                      0x00001800U
15815
15816 /*Oscillator Mode Write-Data Delay Line Select*/
15817 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL
15818 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
15819 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK
15820 #define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL                                           0x00019FFE
15821 #define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT                                            9
15822 #define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK                                             0x00000600U
15823
15824 /*Reserved. Caution, do not write to this register field.*/
15825 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL
15826 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
15827 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK
15828 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL                                      0x00019FFE
15829 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT                                       7
15830 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK                                        0x00000180U
15831
15832 /*Oscillator Mode Write-Leveling Delay Line Select*/
15833 #undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL
15834 #undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
15835 #undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK
15836 #define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL                                            0x00019FFE
15837 #define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT                                             5
15838 #define DDR_PHY_DX8SL3OSC_OSCWDL_MASK                                              0x00000060U
15839
15840 /*Oscillator Mode Division*/
15841 #undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL
15842 #undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
15843 #undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK
15844 #define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL                                            0x00019FFE
15845 #define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT                                             1
15846 #define DDR_PHY_DX8SL3OSC_OSCDIV_MASK                                              0x0000001EU
15847
15848 /*Oscillator Enable*/
15849 #undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL
15850 #undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
15851 #undef DDR_PHY_DX8SL3OSC_OSCEN_MASK
15852 #define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL                                             0x00019FFE
15853 #define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT                                              0
15854 #define DDR_PHY_DX8SL3OSC_OSCEN_MASK                                               0x00000001U
15855
15856 /*Reserved. Return zeroes on reads.*/
15857 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL
15858 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
15859 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK
15860 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
15861 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT                                  25
15862 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
15863
15864 /*Read Path Rise-to-Rise Mode*/
15865 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL
15866 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
15867 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK
15868 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL                                        0x01264000
15869 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT                                         24
15870 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK                                          0x01000000U
15871
15872 /*Reserved. Return zeroes on reads.*/
15873 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL
15874 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
15875 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK
15876 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
15877 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT                                  22
15878 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
15879
15880 /*Write Path Rise-to-Rise Mode*/
15881 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL
15882 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
15883 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK
15884 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL                                        0x01264000
15885 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT                                         21
15886 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK                                          0x00200000U
15887
15888 /*DQS Gate Extension*/
15889 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL
15890 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
15891 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK
15892 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL                                          0x01264000
15893 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT                                           19
15894 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK                                            0x00180000U
15895
15896 /*Low Power PLL Power Down*/
15897 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL
15898 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
15899 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK
15900 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
15901 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT                                         18
15902 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK                                          0x00040000U
15903
15904 /*Low Power I/O Power Down*/
15905 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL
15906 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
15907 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK
15908 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL                                         0x01264000
15909 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT                                          17
15910 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK                                           0x00020000U
15911
15912 /*Reserved. Return zeroes on reads.*/
15913 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL
15914 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
15915 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK
15916 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
15917 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT                                  15
15918 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
15919
15920 /*QS Counter Enable*/
15921 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL
15922 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
15923 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK
15924 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
15925 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT                                         14
15926 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK                                          0x00004000U
15927
15928 /*Unused DQ I/O Mode*/
15929 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL
15930 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
15931 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK
15932 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL                                         0x01264000
15933 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT                                          13
15934 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK                                           0x00002000U
15935
15936 /*Reserved. Return zeroes on reads.*/
15937 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL
15938 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
15939 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK
15940 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
15941 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT                                  10
15942 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
15943
15944 /*Data Slew Rate*/
15945 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL
15946 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
15947 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK
15948 #define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL                                           0x01264000
15949 #define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT                                            8
15950 #define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK                                             0x00000300U
15951
15952 /*DQS_N Resistor*/
15953 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL
15954 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
15955 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK
15956 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL                                        0x01264000
15957 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT                                         4
15958 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK                                          0x000000F0U
15959
15960 /*DQS Resistor*/
15961 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL
15962 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
15963 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK
15964 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL                                         0x01264000
15965 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT                                          0
15966 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK                                           0x0000000FU
15967
15968 /*Reserved. Return zeroes on reads.*/
15969 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL
15970 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
15971 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK
15972 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
15973 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT                                  24
15974 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
15975
15976 /*Configurable Read Data Enable*/
15977 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL
15978 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
15979 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK
15980 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL                                          0x00141800
15981 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT                                           23
15982 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK                                            0x00800000U
15983
15984 /*OX Extension during Post-amble*/
15985 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL
15986 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
15987 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK
15988 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL                                         0x00141800
15989 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT                                          20
15990 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK                                           0x00700000U
15991
15992 /*OE Extension during Pre-amble*/
15993 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL
15994 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
15995 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK
15996 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL                                         0x00141800
15997 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT                                          18
15998 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK                                           0x000C0000U
15999
16000 /*Reserved. Return zeroes on reads.*/
16001 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL
16002 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
16003 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK
16004 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
16005 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT                                     17
16006 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK                                      0x00020000U
16007
16008 /*I/O Assisted Gate Select*/
16009 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL
16010 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
16011 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK
16012 #define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL                                           0x00141800
16013 #define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT                                            16
16014 #define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK                                             0x00010000U
16015
16016 /*I/O Loopback Select*/
16017 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL
16018 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
16019 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK
16020 #define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL                                           0x00141800
16021 #define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT                                            15
16022 #define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK                                             0x00008000U
16023
16024 /*Reserved. Return zeroes on reads.*/
16025 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL
16026 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
16027 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK
16028 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
16029 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT                                  13
16030 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
16031
16032 /*Low Power Wakeup Threshold*/
16033 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL
16034 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
16035 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK
16036 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
16037 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
16038 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
16039
16040 /*Read Data Bus Inversion Enable*/
16041 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL
16042 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
16043 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK
16044 #define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL                                           0x00141800
16045 #define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT                                            8
16046 #define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK                                             0x00000100U
16047
16048 /*Write Data Bus Inversion Enable*/
16049 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL
16050 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
16051 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK
16052 #define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL                                           0x00141800
16053 #define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT                                            7
16054 #define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK                                             0x00000080U
16055
16056 /*PUB Read FIFO Bypass*/
16057 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL
16058 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
16059 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK
16060 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL                                         0x00141800
16061 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT                                          6
16062 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK                                           0x00000040U
16063
16064 /*DATX8 Receive FIFO Read Mode*/
16065 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL
16066 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
16067 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK
16068 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL                                         0x00141800
16069 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT                                          4
16070 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK                                           0x00000030U
16071
16072 /*Disables the Read FIFO Reset*/
16073 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL
16074 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
16075 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK
16076 #define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL                                         0x00141800
16077 #define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT                                          3
16078 #define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK                                           0x00000008U
16079
16080 /*Read DQS Gate I/O Loopback*/
16081 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL
16082 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
16083 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK
16084 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL                                         0x00141800
16085 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT                                          1
16086 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK                                           0x00000006U
16087
16088 /*Reserved. Return zeroes on reads.*/
16089 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL
16090 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
16091 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK
16092 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
16093 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT                                      0
16094 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK                                       0x00000001U
16095
16096 /*Reserved. Return zeroes on reads.*/
16097 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL
16098 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
16099 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK
16100 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL                                      0x00000000
16101 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT                                       31
16102 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK                                        0x80000000U
16103
16104 /*PVREF_DAC REFSEL range select*/
16105 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL
16106 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
16107 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK
16108 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL                                       0x00000000
16109 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT                                        28
16110 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK                                         0x70000000U
16111
16112 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
16113 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL
16114 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
16115 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK
16116 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL                                        0x00000000
16117 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT                                         25
16118 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK                                          0x0E000000U
16119
16120 /*DX IO Mode*/
16121 #undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL
16122 #undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
16123 #undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK
16124 #define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL                                            0x00000000
16125 #define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT                                             22
16126 #define DDR_PHY_DX8SL3IOCR_DXIOM_MASK                                              0x01C00000U
16127
16128 /*DX IO Transmitter Mode*/
16129 #undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL
16130 #undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
16131 #undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK
16132 #define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL                                            0x00000000
16133 #define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT                                             11
16134 #define DDR_PHY_DX8SL3IOCR_DXTXM_MASK                                              0x003FF800U
16135
16136 /*DX IO Receiver Mode*/
16137 #undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL
16138 #undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
16139 #undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK
16140 #define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL                                            0x00000000
16141 #define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT                                             0
16142 #define DDR_PHY_DX8SL3IOCR_DXRXM_MASK                                              0x000007FFU
16143
16144 /*Reserved. Return zeroes on reads.*/
16145 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL
16146 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
16147 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK
16148 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL                                    0x00019FFE
16149 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT                                     30
16150 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK                                      0xC0000000U
16151
16152 /*Enable Clock Gating for DX ddr_clk*/
16153 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL
16154 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
16155 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK
16156 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL                                       0x00019FFE
16157 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT                                        28
16158 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK                                         0x30000000U
16159
16160 /*Enable Clock Gating for DX ctl_rd_clk*/
16161 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL
16162 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
16163 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK
16164 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL                                      0x00019FFE
16165 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT                                       26
16166 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK                                        0x0C000000U
16167
16168 /*Enable Clock Gating for DX ctl_clk*/
16169 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL
16170 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
16171 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK
16172 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL                                      0x00019FFE
16173 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT                                       24
16174 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK                                        0x03000000U
16175
16176 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
16177 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL
16178 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
16179 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK
16180 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL                                          0x00019FFE
16181 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT                                           22
16182 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK                                            0x00C00000U
16183
16184 /*Loopback Mode*/
16185 #undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL
16186 #undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
16187 #undef DDR_PHY_DX8SL4OSC_LBMODE_MASK
16188 #define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL                                            0x00019FFE
16189 #define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT                                             21
16190 #define DDR_PHY_DX8SL4OSC_LBMODE_MASK                                              0x00200000U
16191
16192 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
16193 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL
16194 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
16195 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK
16196 #define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL                                           0x00019FFE
16197 #define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT                                            20
16198 #define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK                                             0x00100000U
16199
16200 /*Loopback DQS Gating*/
16201 #undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL
16202 #undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
16203 #undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK
16204 #define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL                                            0x00019FFE
16205 #define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT                                             18
16206 #define DDR_PHY_DX8SL4OSC_LBGDQS_MASK                                              0x000C0000U
16207
16208 /*Loopback DQS Shift*/
16209 #undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL
16210 #undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
16211 #undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK
16212 #define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL                                            0x00019FFE
16213 #define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT                                             17
16214 #define DDR_PHY_DX8SL4OSC_LBDQSS_MASK                                              0x00020000U
16215
16216 /*PHY High-Speed Reset*/
16217 #undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL
16218 #undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
16219 #undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK
16220 #define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL                                           0x00019FFE
16221 #define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT                                            16
16222 #define DDR_PHY_DX8SL4OSC_PHYHRST_MASK                                             0x00010000U
16223
16224 /*PHY FIFO Reset*/
16225 #undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL
16226 #undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
16227 #undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK
16228 #define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL                                           0x00019FFE
16229 #define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT                                            15
16230 #define DDR_PHY_DX8SL4OSC_PHYFRST_MASK                                             0x00008000U
16231
16232 /*Delay Line Test Start*/
16233 #undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL
16234 #undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT
16235 #undef DDR_PHY_DX8SL4OSC_DLTST_MASK
16236 #define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL                                             0x00019FFE
16237 #define DDR_PHY_DX8SL4OSC_DLTST_SHIFT                                              14
16238 #define DDR_PHY_DX8SL4OSC_DLTST_MASK                                               0x00004000U
16239
16240 /*Delay Line Test Mode*/
16241 #undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL
16242 #undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
16243 #undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK
16244 #define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL                                           0x00019FFE
16245 #define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT                                            13
16246 #define DDR_PHY_DX8SL4OSC_DLTMODE_MASK                                             0x00002000U
16247
16248 /*Reserved. Caution, do not write to this register field.*/
16249 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL
16250 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
16251 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK
16252 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL                                    0x00019FFE
16253 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT                                     11
16254 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK                                      0x00001800U
16255
16256 /*Oscillator Mode Write-Data Delay Line Select*/
16257 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL
16258 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
16259 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK
16260 #define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL                                           0x00019FFE
16261 #define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT                                            9
16262 #define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK                                             0x00000600U
16263
16264 /*Reserved. Caution, do not write to this register field.*/
16265 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL
16266 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
16267 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK
16268 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL                                      0x00019FFE
16269 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT                                       7
16270 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK                                        0x00000180U
16271
16272 /*Oscillator Mode Write-Leveling Delay Line Select*/
16273 #undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL
16274 #undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
16275 #undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK
16276 #define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL                                            0x00019FFE
16277 #define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT                                             5
16278 #define DDR_PHY_DX8SL4OSC_OSCWDL_MASK                                              0x00000060U
16279
16280 /*Oscillator Mode Division*/
16281 #undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL
16282 #undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
16283 #undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK
16284 #define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL                                            0x00019FFE
16285 #define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT                                             1
16286 #define DDR_PHY_DX8SL4OSC_OSCDIV_MASK                                              0x0000001EU
16287
16288 /*Oscillator Enable*/
16289 #undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL
16290 #undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
16291 #undef DDR_PHY_DX8SL4OSC_OSCEN_MASK
16292 #define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL                                             0x00019FFE
16293 #define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT                                              0
16294 #define DDR_PHY_DX8SL4OSC_OSCEN_MASK                                               0x00000001U
16295
16296 /*Reserved. Return zeroes on reads.*/
16297 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL
16298 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
16299 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK
16300 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
16301 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT                                  25
16302 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
16303
16304 /*Read Path Rise-to-Rise Mode*/
16305 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL
16306 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
16307 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK
16308 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL                                        0x01264000
16309 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT                                         24
16310 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK                                          0x01000000U
16311
16312 /*Reserved. Return zeroes on reads.*/
16313 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL
16314 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
16315 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK
16316 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
16317 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT                                  22
16318 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
16319
16320 /*Write Path Rise-to-Rise Mode*/
16321 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL
16322 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
16323 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK
16324 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL                                        0x01264000
16325 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT                                         21
16326 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK                                          0x00200000U
16327
16328 /*DQS Gate Extension*/
16329 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL
16330 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
16331 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK
16332 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL                                          0x01264000
16333 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT                                           19
16334 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK                                            0x00180000U
16335
16336 /*Low Power PLL Power Down*/
16337 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL
16338 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
16339 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK
16340 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
16341 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT                                         18
16342 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK                                          0x00040000U
16343
16344 /*Low Power I/O Power Down*/
16345 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL
16346 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
16347 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK
16348 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL                                         0x01264000
16349 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT                                          17
16350 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK                                           0x00020000U
16351
16352 /*Reserved. Return zeroes on reads.*/
16353 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL
16354 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
16355 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK
16356 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
16357 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT                                  15
16358 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
16359
16360 /*QS Counter Enable*/
16361 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL
16362 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
16363 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK
16364 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
16365 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT                                         14
16366 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK                                          0x00004000U
16367
16368 /*Unused DQ I/O Mode*/
16369 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL
16370 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
16371 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK
16372 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL                                         0x01264000
16373 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT                                          13
16374 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK                                           0x00002000U
16375
16376 /*Reserved. Return zeroes on reads.*/
16377 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL
16378 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
16379 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK
16380 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
16381 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT                                  10
16382 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
16383
16384 /*Data Slew Rate*/
16385 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL
16386 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
16387 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK
16388 #define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL                                           0x01264000
16389 #define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT                                            8
16390 #define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK                                             0x00000300U
16391
16392 /*DQS_N Resistor*/
16393 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL
16394 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
16395 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK
16396 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL                                        0x01264000
16397 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT                                         4
16398 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK                                          0x000000F0U
16399
16400 /*DQS Resistor*/
16401 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL
16402 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
16403 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK
16404 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL                                         0x01264000
16405 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT                                          0
16406 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK                                           0x0000000FU
16407
16408 /*Reserved. Return zeroes on reads.*/
16409 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL
16410 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
16411 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK
16412 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
16413 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT                                  24
16414 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
16415
16416 /*Configurable Read Data Enable*/
16417 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL
16418 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
16419 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK
16420 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL                                          0x00141800
16421 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT                                           23
16422 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK                                            0x00800000U
16423
16424 /*OX Extension during Post-amble*/
16425 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL
16426 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
16427 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK
16428 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL                                         0x00141800
16429 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT                                          20
16430 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK                                           0x00700000U
16431
16432 /*OE Extension during Pre-amble*/
16433 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL
16434 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
16435 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK
16436 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL                                         0x00141800
16437 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT                                          18
16438 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK                                           0x000C0000U
16439
16440 /*Reserved. Return zeroes on reads.*/
16441 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL
16442 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
16443 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK
16444 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
16445 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT                                     17
16446 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK                                      0x00020000U
16447
16448 /*I/O Assisted Gate Select*/
16449 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL
16450 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
16451 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK
16452 #define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL                                           0x00141800
16453 #define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT                                            16
16454 #define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK                                             0x00010000U
16455
16456 /*I/O Loopback Select*/
16457 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL
16458 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
16459 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK
16460 #define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL                                           0x00141800
16461 #define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT                                            15
16462 #define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK                                             0x00008000U
16463
16464 /*Reserved. Return zeroes on reads.*/
16465 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL
16466 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
16467 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK
16468 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
16469 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT                                  13
16470 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
16471
16472 /*Low Power Wakeup Threshold*/
16473 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL
16474 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
16475 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK
16476 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
16477 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
16478 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
16479
16480 /*Read Data Bus Inversion Enable*/
16481 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL
16482 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
16483 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK
16484 #define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL                                           0x00141800
16485 #define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT                                            8
16486 #define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK                                             0x00000100U
16487
16488 /*Write Data Bus Inversion Enable*/
16489 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL
16490 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
16491 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK
16492 #define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL                                           0x00141800
16493 #define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT                                            7
16494 #define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK                                             0x00000080U
16495
16496 /*PUB Read FIFO Bypass*/
16497 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL
16498 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
16499 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK
16500 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL                                         0x00141800
16501 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT                                          6
16502 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK                                           0x00000040U
16503
16504 /*DATX8 Receive FIFO Read Mode*/
16505 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL
16506 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
16507 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK
16508 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL                                         0x00141800
16509 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT                                          4
16510 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK                                           0x00000030U
16511
16512 /*Disables the Read FIFO Reset*/
16513 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL
16514 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
16515 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK
16516 #define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL                                         0x00141800
16517 #define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT                                          3
16518 #define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK                                           0x00000008U
16519
16520 /*Read DQS Gate I/O Loopback*/
16521 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL
16522 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
16523 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK
16524 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL                                         0x00141800
16525 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT                                          1
16526 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK                                           0x00000006U
16527
16528 /*Reserved. Return zeroes on reads.*/
16529 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL
16530 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
16531 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK
16532 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
16533 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT                                      0
16534 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK                                       0x00000001U
16535
16536 /*Reserved. Return zeroes on reads.*/
16537 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL
16538 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
16539 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK
16540 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL                                      0x00000000
16541 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT                                       31
16542 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK                                        0x80000000U
16543
16544 /*PVREF_DAC REFSEL range select*/
16545 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL
16546 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
16547 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK
16548 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL                                       0x00000000
16549 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT                                        28
16550 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK                                         0x70000000U
16551
16552 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
16553 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL
16554 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
16555 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK
16556 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL                                        0x00000000
16557 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT                                         25
16558 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK                                          0x0E000000U
16559
16560 /*DX IO Mode*/
16561 #undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL
16562 #undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
16563 #undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK
16564 #define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL                                            0x00000000
16565 #define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT                                             22
16566 #define DDR_PHY_DX8SL4IOCR_DXIOM_MASK                                              0x01C00000U
16567
16568 /*DX IO Transmitter Mode*/
16569 #undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL
16570 #undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
16571 #undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK
16572 #define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL                                            0x00000000
16573 #define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT                                             11
16574 #define DDR_PHY_DX8SL4IOCR_DXTXM_MASK                                              0x003FF800U
16575
16576 /*DX IO Receiver Mode*/
16577 #undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL
16578 #undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
16579 #undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK
16580 #define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL                                            0x00000000
16581 #define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT                                             0
16582 #define DDR_PHY_DX8SL4IOCR_DXRXM_MASK                                              0x000007FFU
16583
16584 /*Reserved. Return zeroes on reads.*/
16585 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL
16586 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
16587 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK
16588 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL                                 0x00000000
16589 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT                                  25
16590 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
16591
16592 /*Read Path Rise-to-Rise Mode*/
16593 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL
16594 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
16595 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK
16596 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL                                        0x00000000
16597 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT                                         24
16598 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK                                          0x01000000U
16599
16600 /*Reserved. Return zeroes on reads.*/
16601 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL
16602 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
16603 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK
16604 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL                                 0x00000000
16605 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT                                  22
16606 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
16607
16608 /*Write Path Rise-to-Rise Mode*/
16609 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL
16610 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
16611 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK
16612 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL                                        0x00000000
16613 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT                                         21
16614 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK                                          0x00200000U
16615
16616 /*DQS Gate Extension*/
16617 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL
16618 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
16619 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK
16620 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL                                          0x00000000
16621 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT                                           19
16622 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK                                            0x00180000U
16623
16624 /*Low Power PLL Power Down*/
16625 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL
16626 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
16627 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK
16628 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL                                        0x00000000
16629 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT                                         18
16630 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK                                          0x00040000U
16631
16632 /*Low Power I/O Power Down*/
16633 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL
16634 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
16635 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK
16636 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL                                         0x00000000
16637 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT                                          17
16638 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK                                           0x00020000U
16639
16640 /*Reserved. Return zeroes on reads.*/
16641 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL
16642 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
16643 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK
16644 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL                                 0x00000000
16645 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT                                  15
16646 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK                                   0x00018000U
16647
16648 /*QS Counter Enable*/
16649 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL
16650 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
16651 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK
16652 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL                                        0x00000000
16653 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT                                         14
16654 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK                                          0x00004000U
16655
16656 /*Unused DQ I/O Mode*/
16657 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL
16658 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
16659 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK
16660 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL                                         0x00000000
16661 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT                                          13
16662 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK                                           0x00002000U
16663
16664 /*Reserved. Return zeroes on reads.*/
16665 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL
16666 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
16667 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK
16668 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL                                 0x00000000
16669 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT                                  10
16670 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
16671
16672 /*Data Slew Rate*/
16673 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL
16674 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
16675 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK
16676 #define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL                                           0x00000000
16677 #define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT                                            8
16678 #define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK                                             0x00000300U
16679
16680 /*DQS# Resistor*/
16681 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL
16682 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
16683 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK
16684 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL                                        0x00000000
16685 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT                                         4
16686 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK                                          0x000000F0U
16687
16688 /*DQS Resistor*/
16689 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL
16690 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
16691 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK
16692 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL                                         0x00000000
16693 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT                                          0
16694 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK                                           0x0000000FU
16695
16696 /*Reserved. Return zeroes on reads.*/
16697 #undef DDR_PHY_PIR_RESERVED_31_DEFVAL
16698 #undef DDR_PHY_PIR_RESERVED_31_SHIFT
16699 #undef DDR_PHY_PIR_RESERVED_31_MASK
16700 #define DDR_PHY_PIR_RESERVED_31_DEFVAL                                             0x00000000
16701 #define DDR_PHY_PIR_RESERVED_31_SHIFT                                              31
16702 #define DDR_PHY_PIR_RESERVED_31_MASK                                               0x80000000U
16703
16704 /*Impedance Calibration Bypass*/
16705 #undef DDR_PHY_PIR_ZCALBYP_DEFVAL
16706 #undef DDR_PHY_PIR_ZCALBYP_SHIFT
16707 #undef DDR_PHY_PIR_ZCALBYP_MASK
16708 #define DDR_PHY_PIR_ZCALBYP_DEFVAL                                                 0x00000000
16709 #define DDR_PHY_PIR_ZCALBYP_SHIFT                                                  30
16710 #define DDR_PHY_PIR_ZCALBYP_MASK                                                   0x40000000U
16711
16712 /*Digital Delay Line (DDL) Calibration Pause*/
16713 #undef DDR_PHY_PIR_DCALPSE_DEFVAL
16714 #undef DDR_PHY_PIR_DCALPSE_SHIFT
16715 #undef DDR_PHY_PIR_DCALPSE_MASK
16716 #define DDR_PHY_PIR_DCALPSE_DEFVAL                                                 0x00000000
16717 #define DDR_PHY_PIR_DCALPSE_SHIFT                                                  29
16718 #define DDR_PHY_PIR_DCALPSE_MASK                                                   0x20000000U
16719
16720 /*Reserved. Return zeroes on reads.*/
16721 #undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL
16722 #undef DDR_PHY_PIR_RESERVED_28_21_SHIFT
16723 #undef DDR_PHY_PIR_RESERVED_28_21_MASK
16724 #define DDR_PHY_PIR_RESERVED_28_21_DEFVAL                                          0x00000000
16725 #define DDR_PHY_PIR_RESERVED_28_21_SHIFT                                           21
16726 #define DDR_PHY_PIR_RESERVED_28_21_MASK                                            0x1FE00000U
16727
16728 /*Write DQS2DQ Training*/
16729 #undef DDR_PHY_PIR_DQS2DQ_DEFVAL
16730 #undef DDR_PHY_PIR_DQS2DQ_SHIFT
16731 #undef DDR_PHY_PIR_DQS2DQ_MASK
16732 #define DDR_PHY_PIR_DQS2DQ_DEFVAL                                                  0x00000000
16733 #define DDR_PHY_PIR_DQS2DQ_SHIFT                                                   20
16734 #define DDR_PHY_PIR_DQS2DQ_MASK                                                    0x00100000U
16735
16736 /*RDIMM Initialization*/
16737 #undef DDR_PHY_PIR_RDIMMINIT_DEFVAL
16738 #undef DDR_PHY_PIR_RDIMMINIT_SHIFT
16739 #undef DDR_PHY_PIR_RDIMMINIT_MASK
16740 #define DDR_PHY_PIR_RDIMMINIT_DEFVAL                                               0x00000000
16741 #define DDR_PHY_PIR_RDIMMINIT_SHIFT                                                19
16742 #define DDR_PHY_PIR_RDIMMINIT_MASK                                                 0x00080000U
16743
16744 /*Controller DRAM Initialization*/
16745 #undef DDR_PHY_PIR_CTLDINIT_DEFVAL
16746 #undef DDR_PHY_PIR_CTLDINIT_SHIFT
16747 #undef DDR_PHY_PIR_CTLDINIT_MASK
16748 #define DDR_PHY_PIR_CTLDINIT_DEFVAL                                                0x00000000
16749 #define DDR_PHY_PIR_CTLDINIT_SHIFT                                                 18
16750 #define DDR_PHY_PIR_CTLDINIT_MASK                                                  0x00040000U
16751
16752 /*VREF Training*/
16753 #undef DDR_PHY_PIR_VREF_DEFVAL
16754 #undef DDR_PHY_PIR_VREF_SHIFT
16755 #undef DDR_PHY_PIR_VREF_MASK
16756 #define DDR_PHY_PIR_VREF_DEFVAL                                                    0x00000000
16757 #define DDR_PHY_PIR_VREF_SHIFT                                                     17
16758 #define DDR_PHY_PIR_VREF_MASK                                                      0x00020000U
16759
16760 /*Static Read Training*/
16761 #undef DDR_PHY_PIR_SRD_DEFVAL
16762 #undef DDR_PHY_PIR_SRD_SHIFT
16763 #undef DDR_PHY_PIR_SRD_MASK
16764 #define DDR_PHY_PIR_SRD_DEFVAL                                                     0x00000000
16765 #define DDR_PHY_PIR_SRD_SHIFT                                                      16
16766 #define DDR_PHY_PIR_SRD_MASK                                                       0x00010000U
16767
16768 /*Write Data Eye Training*/
16769 #undef DDR_PHY_PIR_WREYE_DEFVAL
16770 #undef DDR_PHY_PIR_WREYE_SHIFT
16771 #undef DDR_PHY_PIR_WREYE_MASK
16772 #define DDR_PHY_PIR_WREYE_DEFVAL                                                   0x00000000
16773 #define DDR_PHY_PIR_WREYE_SHIFT                                                    15
16774 #define DDR_PHY_PIR_WREYE_MASK                                                     0x00008000U
16775
16776 /*Read Data Eye Training*/
16777 #undef DDR_PHY_PIR_RDEYE_DEFVAL
16778 #undef DDR_PHY_PIR_RDEYE_SHIFT
16779 #undef DDR_PHY_PIR_RDEYE_MASK
16780 #define DDR_PHY_PIR_RDEYE_DEFVAL                                                   0x00000000
16781 #define DDR_PHY_PIR_RDEYE_SHIFT                                                    14
16782 #define DDR_PHY_PIR_RDEYE_MASK                                                     0x00004000U
16783
16784 /*Write Data Bit Deskew*/
16785 #undef DDR_PHY_PIR_WRDSKW_DEFVAL
16786 #undef DDR_PHY_PIR_WRDSKW_SHIFT
16787 #undef DDR_PHY_PIR_WRDSKW_MASK
16788 #define DDR_PHY_PIR_WRDSKW_DEFVAL                                                  0x00000000
16789 #define DDR_PHY_PIR_WRDSKW_SHIFT                                                   13
16790 #define DDR_PHY_PIR_WRDSKW_MASK                                                    0x00002000U
16791
16792 /*Read Data Bit Deskew*/
16793 #undef DDR_PHY_PIR_RDDSKW_DEFVAL
16794 #undef DDR_PHY_PIR_RDDSKW_SHIFT
16795 #undef DDR_PHY_PIR_RDDSKW_MASK
16796 #define DDR_PHY_PIR_RDDSKW_DEFVAL                                                  0x00000000
16797 #define DDR_PHY_PIR_RDDSKW_SHIFT                                                   12
16798 #define DDR_PHY_PIR_RDDSKW_MASK                                                    0x00001000U
16799
16800 /*Write Leveling Adjust*/
16801 #undef DDR_PHY_PIR_WLADJ_DEFVAL
16802 #undef DDR_PHY_PIR_WLADJ_SHIFT
16803 #undef DDR_PHY_PIR_WLADJ_MASK
16804 #define DDR_PHY_PIR_WLADJ_DEFVAL                                                   0x00000000
16805 #define DDR_PHY_PIR_WLADJ_SHIFT                                                    11
16806 #define DDR_PHY_PIR_WLADJ_MASK                                                     0x00000800U
16807
16808 /*Read DQS Gate Training*/
16809 #undef DDR_PHY_PIR_QSGATE_DEFVAL
16810 #undef DDR_PHY_PIR_QSGATE_SHIFT
16811 #undef DDR_PHY_PIR_QSGATE_MASK
16812 #define DDR_PHY_PIR_QSGATE_DEFVAL                                                  0x00000000
16813 #define DDR_PHY_PIR_QSGATE_SHIFT                                                   10
16814 #define DDR_PHY_PIR_QSGATE_MASK                                                    0x00000400U
16815
16816 /*Write Leveling*/
16817 #undef DDR_PHY_PIR_WL_DEFVAL
16818 #undef DDR_PHY_PIR_WL_SHIFT
16819 #undef DDR_PHY_PIR_WL_MASK
16820 #define DDR_PHY_PIR_WL_DEFVAL                                                      0x00000000
16821 #define DDR_PHY_PIR_WL_SHIFT                                                       9
16822 #define DDR_PHY_PIR_WL_MASK                                                        0x00000200U
16823
16824 /*DRAM Initialization*/
16825 #undef DDR_PHY_PIR_DRAMINIT_DEFVAL
16826 #undef DDR_PHY_PIR_DRAMINIT_SHIFT
16827 #undef DDR_PHY_PIR_DRAMINIT_MASK
16828 #define DDR_PHY_PIR_DRAMINIT_DEFVAL                                                0x00000000
16829 #define DDR_PHY_PIR_DRAMINIT_SHIFT                                                 8
16830 #define DDR_PHY_PIR_DRAMINIT_MASK                                                  0x00000100U
16831
16832 /*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/
16833 #undef DDR_PHY_PIR_DRAMRST_DEFVAL
16834 #undef DDR_PHY_PIR_DRAMRST_SHIFT
16835 #undef DDR_PHY_PIR_DRAMRST_MASK
16836 #define DDR_PHY_PIR_DRAMRST_DEFVAL                                                 0x00000000
16837 #define DDR_PHY_PIR_DRAMRST_SHIFT                                                  7
16838 #define DDR_PHY_PIR_DRAMRST_MASK                                                   0x00000080U
16839
16840 /*PHY Reset*/
16841 #undef DDR_PHY_PIR_PHYRST_DEFVAL
16842 #undef DDR_PHY_PIR_PHYRST_SHIFT
16843 #undef DDR_PHY_PIR_PHYRST_MASK
16844 #define DDR_PHY_PIR_PHYRST_DEFVAL                                                  0x00000000
16845 #define DDR_PHY_PIR_PHYRST_SHIFT                                                   6
16846 #define DDR_PHY_PIR_PHYRST_MASK                                                    0x00000040U
16847
16848 /*Digital Delay Line (DDL) Calibration*/
16849 #undef DDR_PHY_PIR_DCAL_DEFVAL
16850 #undef DDR_PHY_PIR_DCAL_SHIFT
16851 #undef DDR_PHY_PIR_DCAL_MASK
16852 #define DDR_PHY_PIR_DCAL_DEFVAL                                                    0x00000000
16853 #define DDR_PHY_PIR_DCAL_SHIFT                                                     5
16854 #define DDR_PHY_PIR_DCAL_MASK                                                      0x00000020U
16855
16856 /*PLL Initialiazation*/
16857 #undef DDR_PHY_PIR_PLLINIT_DEFVAL
16858 #undef DDR_PHY_PIR_PLLINIT_SHIFT
16859 #undef DDR_PHY_PIR_PLLINIT_MASK
16860 #define DDR_PHY_PIR_PLLINIT_DEFVAL                                                 0x00000000
16861 #define DDR_PHY_PIR_PLLINIT_SHIFT                                                  4
16862 #define DDR_PHY_PIR_PLLINIT_MASK                                                   0x00000010U
16863
16864 /*Reserved. Return zeroes on reads.*/
16865 #undef DDR_PHY_PIR_RESERVED_3_DEFVAL
16866 #undef DDR_PHY_PIR_RESERVED_3_SHIFT
16867 #undef DDR_PHY_PIR_RESERVED_3_MASK
16868 #define DDR_PHY_PIR_RESERVED_3_DEFVAL                                              0x00000000
16869 #define DDR_PHY_PIR_RESERVED_3_SHIFT                                               3
16870 #define DDR_PHY_PIR_RESERVED_3_MASK                                                0x00000008U
16871
16872 /*CA Training*/
16873 #undef DDR_PHY_PIR_CA_DEFVAL
16874 #undef DDR_PHY_PIR_CA_SHIFT
16875 #undef DDR_PHY_PIR_CA_MASK
16876 #define DDR_PHY_PIR_CA_DEFVAL                                                      0x00000000
16877 #define DDR_PHY_PIR_CA_SHIFT                                                       2
16878 #define DDR_PHY_PIR_CA_MASK                                                        0x00000004U
16879
16880 /*Impedance Calibration*/
16881 #undef DDR_PHY_PIR_ZCAL_DEFVAL
16882 #undef DDR_PHY_PIR_ZCAL_SHIFT
16883 #undef DDR_PHY_PIR_ZCAL_MASK
16884 #define DDR_PHY_PIR_ZCAL_DEFVAL                                                    0x00000000
16885 #define DDR_PHY_PIR_ZCAL_SHIFT                                                     1
16886 #define DDR_PHY_PIR_ZCAL_MASK                                                      0x00000002U
16887
16888 /*Initialization Trigger*/
16889 #undef DDR_PHY_PIR_INIT_DEFVAL
16890 #undef DDR_PHY_PIR_INIT_SHIFT
16891 #undef DDR_PHY_PIR_INIT_MASK
16892 #define DDR_PHY_PIR_INIT_DEFVAL                                                    0x00000000
16893 #define DDR_PHY_PIR_INIT_SHIFT                                                     0
16894 #define DDR_PHY_PIR_INIT_MASK                                                      0x00000001U
16895 #undef IOU_SLCR_MIO_PIN_0_OFFSET
16896 #define IOU_SLCR_MIO_PIN_0_OFFSET                                                  0XFF180000
16897 #undef IOU_SLCR_MIO_PIN_1_OFFSET
16898 #define IOU_SLCR_MIO_PIN_1_OFFSET                                                  0XFF180004
16899 #undef IOU_SLCR_MIO_PIN_2_OFFSET
16900 #define IOU_SLCR_MIO_PIN_2_OFFSET                                                  0XFF180008
16901 #undef IOU_SLCR_MIO_PIN_3_OFFSET
16902 #define IOU_SLCR_MIO_PIN_3_OFFSET                                                  0XFF18000C
16903 #undef IOU_SLCR_MIO_PIN_4_OFFSET
16904 #define IOU_SLCR_MIO_PIN_4_OFFSET                                                  0XFF180010
16905 #undef IOU_SLCR_MIO_PIN_5_OFFSET
16906 #define IOU_SLCR_MIO_PIN_5_OFFSET                                                  0XFF180014
16907 #undef IOU_SLCR_MIO_PIN_6_OFFSET
16908 #define IOU_SLCR_MIO_PIN_6_OFFSET                                                  0XFF180018
16909 #undef IOU_SLCR_MIO_PIN_7_OFFSET
16910 #define IOU_SLCR_MIO_PIN_7_OFFSET                                                  0XFF18001C
16911 #undef IOU_SLCR_MIO_PIN_8_OFFSET
16912 #define IOU_SLCR_MIO_PIN_8_OFFSET                                                  0XFF180020
16913 #undef IOU_SLCR_MIO_PIN_9_OFFSET
16914 #define IOU_SLCR_MIO_PIN_9_OFFSET                                                  0XFF180024
16915 #undef IOU_SLCR_MIO_PIN_10_OFFSET
16916 #define IOU_SLCR_MIO_PIN_10_OFFSET                                                 0XFF180028
16917 #undef IOU_SLCR_MIO_PIN_11_OFFSET
16918 #define IOU_SLCR_MIO_PIN_11_OFFSET                                                 0XFF18002C
16919 #undef IOU_SLCR_MIO_PIN_12_OFFSET
16920 #define IOU_SLCR_MIO_PIN_12_OFFSET                                                 0XFF180030
16921 #undef IOU_SLCR_MIO_PIN_13_OFFSET
16922 #define IOU_SLCR_MIO_PIN_13_OFFSET                                                 0XFF180034
16923 #undef IOU_SLCR_MIO_PIN_14_OFFSET
16924 #define IOU_SLCR_MIO_PIN_14_OFFSET                                                 0XFF180038
16925 #undef IOU_SLCR_MIO_PIN_15_OFFSET
16926 #define IOU_SLCR_MIO_PIN_15_OFFSET                                                 0XFF18003C
16927 #undef IOU_SLCR_MIO_PIN_16_OFFSET
16928 #define IOU_SLCR_MIO_PIN_16_OFFSET                                                 0XFF180040
16929 #undef IOU_SLCR_MIO_PIN_17_OFFSET
16930 #define IOU_SLCR_MIO_PIN_17_OFFSET                                                 0XFF180044
16931 #undef IOU_SLCR_MIO_PIN_18_OFFSET
16932 #define IOU_SLCR_MIO_PIN_18_OFFSET                                                 0XFF180048
16933 #undef IOU_SLCR_MIO_PIN_19_OFFSET
16934 #define IOU_SLCR_MIO_PIN_19_OFFSET                                                 0XFF18004C
16935 #undef IOU_SLCR_MIO_PIN_20_OFFSET
16936 #define IOU_SLCR_MIO_PIN_20_OFFSET                                                 0XFF180050
16937 #undef IOU_SLCR_MIO_PIN_21_OFFSET
16938 #define IOU_SLCR_MIO_PIN_21_OFFSET                                                 0XFF180054
16939 #undef IOU_SLCR_MIO_PIN_22_OFFSET
16940 #define IOU_SLCR_MIO_PIN_22_OFFSET                                                 0XFF180058
16941 #undef IOU_SLCR_MIO_PIN_23_OFFSET
16942 #define IOU_SLCR_MIO_PIN_23_OFFSET                                                 0XFF18005C
16943 #undef IOU_SLCR_MIO_PIN_24_OFFSET
16944 #define IOU_SLCR_MIO_PIN_24_OFFSET                                                 0XFF180060
16945 #undef IOU_SLCR_MIO_PIN_25_OFFSET
16946 #define IOU_SLCR_MIO_PIN_25_OFFSET                                                 0XFF180064
16947 #undef IOU_SLCR_MIO_PIN_26_OFFSET
16948 #define IOU_SLCR_MIO_PIN_26_OFFSET                                                 0XFF180068
16949 #undef IOU_SLCR_MIO_PIN_27_OFFSET
16950 #define IOU_SLCR_MIO_PIN_27_OFFSET                                                 0XFF18006C
16951 #undef IOU_SLCR_MIO_PIN_28_OFFSET
16952 #define IOU_SLCR_MIO_PIN_28_OFFSET                                                 0XFF180070
16953 #undef IOU_SLCR_MIO_PIN_29_OFFSET
16954 #define IOU_SLCR_MIO_PIN_29_OFFSET                                                 0XFF180074
16955 #undef IOU_SLCR_MIO_PIN_30_OFFSET
16956 #define IOU_SLCR_MIO_PIN_30_OFFSET                                                 0XFF180078
16957 #undef IOU_SLCR_MIO_PIN_31_OFFSET
16958 #define IOU_SLCR_MIO_PIN_31_OFFSET                                                 0XFF18007C
16959 #undef IOU_SLCR_MIO_PIN_32_OFFSET
16960 #define IOU_SLCR_MIO_PIN_32_OFFSET                                                 0XFF180080
16961 #undef IOU_SLCR_MIO_PIN_33_OFFSET
16962 #define IOU_SLCR_MIO_PIN_33_OFFSET                                                 0XFF180084
16963 #undef IOU_SLCR_MIO_PIN_34_OFFSET
16964 #define IOU_SLCR_MIO_PIN_34_OFFSET                                                 0XFF180088
16965 #undef IOU_SLCR_MIO_PIN_35_OFFSET
16966 #define IOU_SLCR_MIO_PIN_35_OFFSET                                                 0XFF18008C
16967 #undef IOU_SLCR_MIO_PIN_36_OFFSET
16968 #define IOU_SLCR_MIO_PIN_36_OFFSET                                                 0XFF180090
16969 #undef IOU_SLCR_MIO_PIN_37_OFFSET
16970 #define IOU_SLCR_MIO_PIN_37_OFFSET                                                 0XFF180094
16971 #undef IOU_SLCR_MIO_PIN_38_OFFSET
16972 #define IOU_SLCR_MIO_PIN_38_OFFSET                                                 0XFF180098
16973 #undef IOU_SLCR_MIO_PIN_39_OFFSET
16974 #define IOU_SLCR_MIO_PIN_39_OFFSET                                                 0XFF18009C
16975 #undef IOU_SLCR_MIO_PIN_40_OFFSET
16976 #define IOU_SLCR_MIO_PIN_40_OFFSET                                                 0XFF1800A0
16977 #undef IOU_SLCR_MIO_PIN_41_OFFSET
16978 #define IOU_SLCR_MIO_PIN_41_OFFSET                                                 0XFF1800A4
16979 #undef IOU_SLCR_MIO_PIN_42_OFFSET
16980 #define IOU_SLCR_MIO_PIN_42_OFFSET                                                 0XFF1800A8
16981 #undef IOU_SLCR_MIO_PIN_43_OFFSET
16982 #define IOU_SLCR_MIO_PIN_43_OFFSET                                                 0XFF1800AC
16983 #undef IOU_SLCR_MIO_PIN_44_OFFSET
16984 #define IOU_SLCR_MIO_PIN_44_OFFSET                                                 0XFF1800B0
16985 #undef IOU_SLCR_MIO_PIN_45_OFFSET
16986 #define IOU_SLCR_MIO_PIN_45_OFFSET                                                 0XFF1800B4
16987 #undef IOU_SLCR_MIO_PIN_46_OFFSET
16988 #define IOU_SLCR_MIO_PIN_46_OFFSET                                                 0XFF1800B8
16989 #undef IOU_SLCR_MIO_PIN_47_OFFSET
16990 #define IOU_SLCR_MIO_PIN_47_OFFSET                                                 0XFF1800BC
16991 #undef IOU_SLCR_MIO_PIN_48_OFFSET
16992 #define IOU_SLCR_MIO_PIN_48_OFFSET                                                 0XFF1800C0
16993 #undef IOU_SLCR_MIO_PIN_49_OFFSET
16994 #define IOU_SLCR_MIO_PIN_49_OFFSET                                                 0XFF1800C4
16995 #undef IOU_SLCR_MIO_PIN_50_OFFSET
16996 #define IOU_SLCR_MIO_PIN_50_OFFSET                                                 0XFF1800C8
16997 #undef IOU_SLCR_MIO_PIN_51_OFFSET
16998 #define IOU_SLCR_MIO_PIN_51_OFFSET                                                 0XFF1800CC
16999 #undef IOU_SLCR_MIO_PIN_52_OFFSET
17000 #define IOU_SLCR_MIO_PIN_52_OFFSET                                                 0XFF1800D0
17001 #undef IOU_SLCR_MIO_PIN_53_OFFSET
17002 #define IOU_SLCR_MIO_PIN_53_OFFSET                                                 0XFF1800D4
17003 #undef IOU_SLCR_MIO_PIN_54_OFFSET
17004 #define IOU_SLCR_MIO_PIN_54_OFFSET                                                 0XFF1800D8
17005 #undef IOU_SLCR_MIO_PIN_55_OFFSET
17006 #define IOU_SLCR_MIO_PIN_55_OFFSET                                                 0XFF1800DC
17007 #undef IOU_SLCR_MIO_PIN_56_OFFSET
17008 #define IOU_SLCR_MIO_PIN_56_OFFSET                                                 0XFF1800E0
17009 #undef IOU_SLCR_MIO_PIN_57_OFFSET
17010 #define IOU_SLCR_MIO_PIN_57_OFFSET                                                 0XFF1800E4
17011 #undef IOU_SLCR_MIO_PIN_58_OFFSET
17012 #define IOU_SLCR_MIO_PIN_58_OFFSET                                                 0XFF1800E8
17013 #undef IOU_SLCR_MIO_PIN_59_OFFSET
17014 #define IOU_SLCR_MIO_PIN_59_OFFSET                                                 0XFF1800EC
17015 #undef IOU_SLCR_MIO_PIN_60_OFFSET
17016 #define IOU_SLCR_MIO_PIN_60_OFFSET                                                 0XFF1800F0
17017 #undef IOU_SLCR_MIO_PIN_61_OFFSET
17018 #define IOU_SLCR_MIO_PIN_61_OFFSET                                                 0XFF1800F4
17019 #undef IOU_SLCR_MIO_PIN_62_OFFSET
17020 #define IOU_SLCR_MIO_PIN_62_OFFSET                                                 0XFF1800F8
17021 #undef IOU_SLCR_MIO_PIN_63_OFFSET
17022 #define IOU_SLCR_MIO_PIN_63_OFFSET                                                 0XFF1800FC
17023 #undef IOU_SLCR_MIO_PIN_64_OFFSET
17024 #define IOU_SLCR_MIO_PIN_64_OFFSET                                                 0XFF180100
17025 #undef IOU_SLCR_MIO_PIN_65_OFFSET
17026 #define IOU_SLCR_MIO_PIN_65_OFFSET                                                 0XFF180104
17027 #undef IOU_SLCR_MIO_PIN_66_OFFSET
17028 #define IOU_SLCR_MIO_PIN_66_OFFSET                                                 0XFF180108
17029 #undef IOU_SLCR_MIO_PIN_67_OFFSET
17030 #define IOU_SLCR_MIO_PIN_67_OFFSET                                                 0XFF18010C
17031 #undef IOU_SLCR_MIO_PIN_68_OFFSET
17032 #define IOU_SLCR_MIO_PIN_68_OFFSET                                                 0XFF180110
17033 #undef IOU_SLCR_MIO_PIN_69_OFFSET
17034 #define IOU_SLCR_MIO_PIN_69_OFFSET                                                 0XFF180114
17035 #undef IOU_SLCR_MIO_PIN_70_OFFSET
17036 #define IOU_SLCR_MIO_PIN_70_OFFSET                                                 0XFF180118
17037 #undef IOU_SLCR_MIO_PIN_71_OFFSET
17038 #define IOU_SLCR_MIO_PIN_71_OFFSET                                                 0XFF18011C
17039 #undef IOU_SLCR_MIO_PIN_72_OFFSET
17040 #define IOU_SLCR_MIO_PIN_72_OFFSET                                                 0XFF180120
17041 #undef IOU_SLCR_MIO_PIN_73_OFFSET
17042 #define IOU_SLCR_MIO_PIN_73_OFFSET                                                 0XFF180124
17043 #undef IOU_SLCR_MIO_PIN_74_OFFSET
17044 #define IOU_SLCR_MIO_PIN_74_OFFSET                                                 0XFF180128
17045 #undef IOU_SLCR_MIO_PIN_75_OFFSET
17046 #define IOU_SLCR_MIO_PIN_75_OFFSET                                                 0XFF18012C
17047 #undef IOU_SLCR_MIO_PIN_76_OFFSET
17048 #define IOU_SLCR_MIO_PIN_76_OFFSET                                                 0XFF180130
17049 #undef IOU_SLCR_MIO_PIN_77_OFFSET
17050 #define IOU_SLCR_MIO_PIN_77_OFFSET                                                 0XFF180134
17051 #undef IOU_SLCR_MIO_MST_TRI0_OFFSET
17052 #define IOU_SLCR_MIO_MST_TRI0_OFFSET                                               0XFF180204
17053 #undef IOU_SLCR_MIO_MST_TRI1_OFFSET
17054 #define IOU_SLCR_MIO_MST_TRI1_OFFSET                                               0XFF180208
17055 #undef IOU_SLCR_MIO_MST_TRI2_OFFSET
17056 #define IOU_SLCR_MIO_MST_TRI2_OFFSET                                               0XFF18020C
17057 #undef IOU_SLCR_BANK0_CTRL0_OFFSET
17058 #define IOU_SLCR_BANK0_CTRL0_OFFSET                                                0XFF180138
17059 #undef IOU_SLCR_BANK0_CTRL1_OFFSET
17060 #define IOU_SLCR_BANK0_CTRL1_OFFSET                                                0XFF18013C
17061 #undef IOU_SLCR_BANK0_CTRL3_OFFSET
17062 #define IOU_SLCR_BANK0_CTRL3_OFFSET                                                0XFF180140
17063 #undef IOU_SLCR_BANK0_CTRL4_OFFSET
17064 #define IOU_SLCR_BANK0_CTRL4_OFFSET                                                0XFF180144
17065 #undef IOU_SLCR_BANK0_CTRL5_OFFSET
17066 #define IOU_SLCR_BANK0_CTRL5_OFFSET                                                0XFF180148
17067 #undef IOU_SLCR_BANK0_CTRL6_OFFSET
17068 #define IOU_SLCR_BANK0_CTRL6_OFFSET                                                0XFF18014C
17069 #undef IOU_SLCR_BANK1_CTRL0_OFFSET
17070 #define IOU_SLCR_BANK1_CTRL0_OFFSET                                                0XFF180154
17071 #undef IOU_SLCR_BANK1_CTRL1_OFFSET
17072 #define IOU_SLCR_BANK1_CTRL1_OFFSET                                                0XFF180158
17073 #undef IOU_SLCR_BANK1_CTRL3_OFFSET
17074 #define IOU_SLCR_BANK1_CTRL3_OFFSET                                                0XFF18015C
17075 #undef IOU_SLCR_BANK1_CTRL4_OFFSET
17076 #define IOU_SLCR_BANK1_CTRL4_OFFSET                                                0XFF180160
17077 #undef IOU_SLCR_BANK1_CTRL5_OFFSET
17078 #define IOU_SLCR_BANK1_CTRL5_OFFSET                                                0XFF180164
17079 #undef IOU_SLCR_BANK1_CTRL6_OFFSET
17080 #define IOU_SLCR_BANK1_CTRL6_OFFSET                                                0XFF180168
17081 #undef IOU_SLCR_BANK2_CTRL0_OFFSET
17082 #define IOU_SLCR_BANK2_CTRL0_OFFSET                                                0XFF180170
17083 #undef IOU_SLCR_BANK2_CTRL1_OFFSET
17084 #define IOU_SLCR_BANK2_CTRL1_OFFSET                                                0XFF180174
17085 #undef IOU_SLCR_BANK2_CTRL3_OFFSET
17086 #define IOU_SLCR_BANK2_CTRL3_OFFSET                                                0XFF180178
17087 #undef IOU_SLCR_BANK2_CTRL4_OFFSET
17088 #define IOU_SLCR_BANK2_CTRL4_OFFSET                                                0XFF18017C
17089 #undef IOU_SLCR_BANK2_CTRL5_OFFSET
17090 #define IOU_SLCR_BANK2_CTRL5_OFFSET                                                0XFF180180
17091 #undef IOU_SLCR_BANK2_CTRL6_OFFSET
17092 #define IOU_SLCR_BANK2_CTRL6_OFFSET                                                0XFF180184
17093 #undef IOU_SLCR_MIO_LOOPBACK_OFFSET
17094 #define IOU_SLCR_MIO_LOOPBACK_OFFSET                                               0XFF180200
17095
17096 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/
17097 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL
17098 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
17099 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK
17100 #define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL                                           0x00000000
17101 #define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT                                            1
17102 #define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK                                             0x00000002U
17103
17104 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17105 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL
17106 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
17107 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK
17108 #define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL                                           0x00000000
17109 #define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT                                            2
17110 #define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK                                             0x00000004U
17111
17112 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
17113                 t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/
17114 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL
17115 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
17116 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK
17117 #define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL                                           0x00000000
17118 #define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT                                            3
17119 #define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK                                             0x00000018U
17120
17121 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
17122                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
17123                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
17124                 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
17125                 lk- (Trace Port Clock)*/
17126 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL
17127 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
17128 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK
17129 #define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL                                           0x00000000
17130 #define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT                                            5
17131 #define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK                                             0x000000E0U
17132
17133 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
17134                 us)*/
17135 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL
17136 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
17137 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK
17138 #define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL                                           0x00000000
17139 #define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT                                            1
17140 #define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK                                             0x00000002U
17141
17142 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17143 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL
17144 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
17145 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK
17146 #define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL                                           0x00000000
17147 #define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT                                            2
17148 #define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK                                             0x00000004U
17149
17150 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
17151                 t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/
17152 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL
17153 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
17154 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK
17155 #define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL                                           0x00000000
17156 #define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT                                            3
17157 #define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK                                             0x00000018U
17158
17159 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
17160                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
17161                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
17162                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
17163                 Signal)*/
17164 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL
17165 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
17166 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK
17167 #define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL                                           0x00000000
17168 #define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT                                            5
17169 #define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK                                             0x000000E0U
17170
17171 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/
17172 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL
17173 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
17174 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK
17175 #define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL                                           0x00000000
17176 #define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT                                            1
17177 #define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK                                             0x00000002U
17178
17179 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17180 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL
17181 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
17182 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK
17183 #define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL                                           0x00000000
17184 #define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT                                            2
17185 #define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK                                             0x00000004U
17186
17187 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
17188                 t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/
17189 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL
17190 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
17191 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK
17192 #define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL                                           0x00000000
17193 #define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT                                            3
17194 #define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK                                             0x00000018U
17195
17196 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
17197                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
17198                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
17199                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
17200 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL
17201 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
17202 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK
17203 #define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL                                           0x00000000
17204 #define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT                                            5
17205 #define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK                                             0x000000E0U
17206
17207 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/
17208 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL
17209 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
17210 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK
17211 #define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL                                           0x00000000
17212 #define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT                                            1
17213 #define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK                                             0x00000002U
17214
17215 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17216 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL
17217 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
17218 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK
17219 #define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL                                           0x00000000
17220 #define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT                                            2
17221 #define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK                                             0x00000004U
17222
17223 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
17224                 t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/
17225 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL
17226 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
17227 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK
17228 #define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL                                           0x00000000
17229 #define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT                                            3
17230 #define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK                                             0x00000018U
17231
17232 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
17233                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
17234                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
17235                 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
17236                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
17237 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL
17238 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
17239 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK
17240 #define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL                                           0x00000000
17241 #define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT                                            5
17242 #define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK                                             0x000000E0U
17243
17244 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
17245                 us)*/
17246 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL
17247 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
17248 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK
17249 #define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL                                           0x00000000
17250 #define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT                                            1
17251 #define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK                                             0x00000002U
17252
17253 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17254 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL
17255 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
17256 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK
17257 #define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL                                           0x00000000
17258 #define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT                                            2
17259 #define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK                                             0x00000004U
17260
17261 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
17262                 t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/
17263 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL
17264 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
17265 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK
17266 #define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL                                           0x00000000
17267 #define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT                                            3
17268 #define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK                                             0x00000018U
17269
17270 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
17271                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
17272                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
17273                 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
17274                 utput, tracedq[2]- (Trace Port Databus)*/
17275 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL
17276 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
17277 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK
17278 #define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL                                           0x00000000
17279 #define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT                                            5
17280 #define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK                                             0x000000E0U
17281
17282 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/
17283 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL
17284 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
17285 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK
17286 #define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL                                           0x00000000
17287 #define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT                                            1
17288 #define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK                                             0x00000002U
17289
17290 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17291 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL
17292 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
17293 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK
17294 #define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL                                           0x00000000
17295 #define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT                                            2
17296 #define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK                                             0x00000004U
17297
17298 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
17299                 t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/
17300 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL
17301 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
17302 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK
17303 #define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL                                           0x00000000
17304 #define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT                                            3
17305 #define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK                                             0x00000018U
17306
17307 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
17308                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
17309                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
17310                 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
17311                  trace, Output, tracedq[3]- (Trace Port Databus)*/
17312 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL
17313 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
17314 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK
17315 #define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL                                           0x00000000
17316 #define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT                                            5
17317 #define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK                                             0x000000E0U
17318
17319 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/
17320 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL
17321 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
17322 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK
17323 #define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL                                           0x00000000
17324 #define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT                                            1
17325 #define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK                                             0x00000002U
17326
17327 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17328 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL
17329 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
17330 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK
17331 #define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL                                           0x00000000
17332 #define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT                                            2
17333 #define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK                                             0x00000004U
17334
17335 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
17336                 t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/
17337 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL
17338 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
17339 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK
17340 #define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL                                           0x00000000
17341 #define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT                                            3
17342 #define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK                                             0x00000018U
17343
17344 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
17345                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
17346                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
17347                 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
17348                 Output, tracedq[4]- (Trace Port Databus)*/
17349 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL
17350 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
17351 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK
17352 #define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL                                           0x00000000
17353 #define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT                                            5
17354 #define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK                                             0x000000E0U
17355
17356 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/
17357 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL
17358 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
17359 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK
17360 #define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL                                           0x00000000
17361 #define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT                                            1
17362 #define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK                                             0x00000002U
17363
17364 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17365 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL
17366 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
17367 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK
17368 #define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL                                           0x00000000
17369 #define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT                                            2
17370 #define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK                                             0x00000004U
17371
17372 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
17373                 t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/
17374 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL
17375 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
17376 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK
17377 #define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL                                           0x00000000
17378 #define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT                                            3
17379 #define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK                                             0x00000018U
17380
17381 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
17382                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
17383                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
17384                 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output,
17385                 racedq[5]- (Trace Port Databus)*/
17386 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL
17387 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
17388 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK
17389 #define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL                                           0x00000000
17390 #define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT                                            5
17391 #define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK                                             0x000000E0U
17392
17393 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
17394                 [0]- (QSPI Upper Databus)*/
17395 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL
17396 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
17397 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK
17398 #define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL                                           0x00000000
17399 #define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT                                            1
17400 #define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK                                             0x00000002U
17401
17402 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17403 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL
17404 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
17405 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK
17406 #define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL                                           0x00000000
17407 #define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT                                            2
17408 #define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK                                             0x00000004U
17409
17410 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
17411                 t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/
17412 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL
17413 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
17414 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK
17415 #define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL                                           0x00000000
17416 #define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT                                            3
17417 #define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK                                             0x00000018U
17418
17419 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
17420                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
17421                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
17422                 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
17423                 ce Port Databus)*/
17424 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL
17425 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
17426 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK
17427 #define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL                                           0x00000000
17428 #define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT                                            5
17429 #define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK                                             0x000000E0U
17430
17431 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
17432                 [1]- (QSPI Upper Databus)*/
17433 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL
17434 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
17435 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK
17436 #define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL                                           0x00000000
17437 #define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT                                            1
17438 #define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK                                             0x00000002U
17439
17440 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
17441 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL
17442 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
17443 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK
17444 #define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL                                           0x00000000
17445 #define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT                                            2
17446 #define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK                                             0x00000004U
17447
17448 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
17449                 t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/
17450 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL
17451 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
17452 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK
17453 #define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL                                           0x00000000
17454 #define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT                                            3
17455 #define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK                                             0x00000018U
17456
17457 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
17458                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
17459                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
17460                 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
17461                 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
17462 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL
17463 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
17464 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK
17465 #define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL                                           0x00000000
17466 #define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT                                            5
17467 #define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK                                             0x000000E0U
17468
17469 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
17470                 [2]- (QSPI Upper Databus)*/
17471 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL
17472 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
17473 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK
17474 #define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL                                          0x00000000
17475 #define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT                                           1
17476 #define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK                                            0x00000002U
17477
17478 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
17479 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL
17480 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
17481 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK
17482 #define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL                                          0x00000000
17483 #define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT                                           2
17484 #define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK                                            0x00000004U
17485
17486 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
17487                 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/
17488 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL
17489 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
17490 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK
17491 #define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL                                          0x00000000
17492 #define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT                                           3
17493 #define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK                                            0x00000018U
17494
17495 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
17496                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17497                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
17498                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
17499                 t, tracedq[8]- (Trace Port Databus)*/
17500 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL
17501 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
17502 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK
17503 #define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL                                          0x00000000
17504 #define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT                                           5
17505 #define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK                                            0x000000E0U
17506
17507 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
17508                 [3]- (QSPI Upper Databus)*/
17509 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL
17510 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
17511 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK
17512 #define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL                                          0x00000000
17513 #define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT                                           1
17514 #define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK                                            0x00000002U
17515
17516 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
17517 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL
17518 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
17519 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK
17520 #define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL                                          0x00000000
17521 #define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT                                           2
17522 #define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK                                            0x00000004U
17523
17524 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
17525                 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/
17526 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL
17527 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
17528 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK
17529 #define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL                                          0x00000000
17530 #define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT                                           3
17531 #define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK                                            0x00000018U
17532
17533 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
17534                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17535                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
17536                 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
17537                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
17538 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL
17539 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
17540 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK
17541 #define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL                                          0x00000000
17542 #define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT                                           5
17543 #define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK                                            0x000000E0U
17544
17545 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/
17546 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL
17547 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
17548 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK
17549 #define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL                                          0x00000000
17550 #define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT                                           1
17551 #define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK                                            0x00000002U
17552
17553 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
17554                 */
17555 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL
17556 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
17557 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK
17558 #define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL                                          0x00000000
17559 #define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT                                           2
17560 #define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK                                            0x00000004U
17561
17562 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
17563                 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/
17564 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL
17565 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
17566 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK
17567 #define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL                                          0x00000000
17568 #define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT                                           3
17569 #define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK                                            0x00000018U
17570
17571 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
17572                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17573                 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
17574                 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
17575                 dq[10]- (Trace Port Databus)*/
17576 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL
17577 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
17578 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK
17579 #define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL                                          0x00000000
17580 #define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT                                           5
17581 #define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK                                            0x000000E0U
17582
17583 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17584 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL
17585 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
17586 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK
17587 #define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL                                          0x00000000
17588 #define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT                                           1
17589 #define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK                                            0x00000002U
17590
17591 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/
17592 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL
17593 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
17594 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK
17595 #define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL                                          0x00000000
17596 #define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT                                           2
17597 #define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK                                            0x00000004U
17598
17599 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
17600                 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
17601                  3= Not Used*/
17602 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL
17603 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
17604 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK
17605 #define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL                                          0x00000000
17606 #define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT                                           3
17607 #define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK                                            0x00000018U
17608
17609 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
17610                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17611                 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
17612                 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
17613                 bus)*/
17614 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL
17615 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
17616 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK
17617 #define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL                                          0x00000000
17618 #define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT                                           5
17619 #define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK                                            0x000000E0U
17620
17621 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17622 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL
17623 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
17624 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK
17625 #define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL                                          0x00000000
17626 #define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT                                           1
17627 #define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK                                            0x00000002U
17628
17629 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/
17630 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL
17631 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
17632 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK
17633 #define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL                                          0x00000000
17634 #define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT                                           2
17635 #define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK                                            0x00000004U
17636
17637 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
17638                 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
17639                  3= Not Used*/
17640 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL
17641 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
17642 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK
17643 #define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL                                          0x00000000
17644 #define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT                                           3
17645 #define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK                                            0x00000018U
17646
17647 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
17648                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17649                 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
17650                 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/
17651 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL
17652 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
17653 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK
17654 #define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL                                          0x00000000
17655 #define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT                                           5
17656 #define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK                                            0x000000E0U
17657
17658 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17659 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL
17660 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
17661 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK
17662 #define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL                                          0x00000000
17663 #define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT                                           1
17664 #define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK                                            0x00000002U
17665
17666 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/
17667 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL
17668 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
17669 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK
17670 #define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL                                          0x00000000
17671 #define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT                                           2
17672 #define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK                                            0x00000004U
17673
17674 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
17675                 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
17676                  3= Not Used*/
17677 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL
17678 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
17679 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK
17680 #define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL                                          0x00000000
17681 #define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT                                           3
17682 #define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK                                            0x00000018U
17683
17684 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
17685                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17686                 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
17687                 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
17688                 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
17689 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL
17690 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
17691 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK
17692 #define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL                                          0x00000000
17693 #define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT                                           5
17694 #define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK                                            0x000000E0U
17695
17696 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17697 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL
17698 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
17699 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK
17700 #define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL                                          0x00000000
17701 #define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT                                           1
17702 #define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK                                            0x00000002U
17703
17704 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND
17705                 ata Bus)*/
17706 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL
17707 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
17708 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK
17709 #define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL                                          0x00000000
17710 #define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT                                           2
17711 #define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK                                            0x00000004U
17712
17713 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
17714                 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
17715                  3= Not Used*/
17716 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL
17717 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
17718 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK
17719 #define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL                                          0x00000000
17720 #define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT                                           3
17721 #define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK                                            0x00000018U
17722
17723 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
17724                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17725                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
17726                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
17727                  Output, tracedq[14]- (Trace Port Databus)*/
17728 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL
17729 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
17730 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK
17731 #define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL                                          0x00000000
17732 #define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT                                           5
17733 #define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK                                            0x000000E0U
17734
17735 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17736 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL
17737 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
17738 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK
17739 #define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL                                          0x00000000
17740 #define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT                                           1
17741 #define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK                                            0x00000002U
17742
17743 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND
17744                 ata Bus)*/
17745 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL
17746 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
17747 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK
17748 #define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL                                          0x00000000
17749 #define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT                                           2
17750 #define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK                                            0x00000004U
17751
17752 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
17753                 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
17754                  3= Not Used*/
17755 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL
17756 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
17757 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK
17758 #define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL                                          0x00000000
17759 #define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT                                           3
17760 #define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK                                            0x00000018U
17761
17762 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
17763                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17764                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
17765                 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
17766                 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
17767 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL
17768 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
17769 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK
17770 #define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL                                          0x00000000
17771 #define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT                                           5
17772 #define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK                                            0x000000E0U
17773
17774 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17775 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL
17776 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
17777 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK
17778 #define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL                                          0x00000000
17779 #define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT                                           1
17780 #define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK                                            0x00000002U
17781
17782 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND
17783                 ata Bus)*/
17784 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL
17785 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
17786 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK
17787 #define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL                                          0x00000000
17788 #define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT                                           2
17789 #define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK                                            0x00000004U
17790
17791 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
17792                 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
17793                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17794 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL
17795 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
17796 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK
17797 #define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL                                          0x00000000
17798 #define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT                                           3
17799 #define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK                                            0x00000018U
17800
17801 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
17802                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17803                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
17804                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
17805 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL
17806 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
17807 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK
17808 #define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL                                          0x00000000
17809 #define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT                                           5
17810 #define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK                                            0x000000E0U
17811
17812 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17813 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL
17814 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
17815 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK
17816 #define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL                                          0x00000000
17817 #define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT                                           1
17818 #define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK                                            0x00000002U
17819
17820 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND
17821                 ata Bus)*/
17822 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL
17823 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
17824 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK
17825 #define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL                                          0x00000000
17826 #define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT                                           2
17827 #define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK                                            0x00000004U
17828
17829 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
17830                 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
17831                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17832 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL
17833 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
17834 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK
17835 #define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL                                          0x00000000
17836 #define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT                                           3
17837 #define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK                                            0x00000018U
17838
17839 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
17840                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17841                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
17842                  ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
17843 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL
17844 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
17845 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK
17846 #define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL                                          0x00000000
17847 #define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT                                           5
17848 #define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK                                            0x000000E0U
17849
17850 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17851 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL
17852 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
17853 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK
17854 #define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL                                          0x00000000
17855 #define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT                                           1
17856 #define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK                                            0x00000002U
17857
17858 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND
17859                 ata Bus)*/
17860 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL
17861 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
17862 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK
17863 #define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL                                          0x00000000
17864 #define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT                                           2
17865 #define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK                                            0x00000004U
17866
17867 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
17868                 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
17869                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17870 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL
17871 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
17872 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK
17873 #define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL                                          0x00000000
17874 #define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT                                           3
17875 #define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK                                            0x00000018U
17876
17877 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
17878                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17879                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
17880                 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
17881 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL
17882 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
17883 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK
17884 #define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL                                          0x00000000
17885 #define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT                                           5
17886 #define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK                                            0x000000E0U
17887
17888 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17889 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL
17890 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
17891 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK
17892 #define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL                                          0x00000000
17893 #define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT                                           1
17894 #define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK                                            0x00000002U
17895
17896 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND
17897                 ata Bus)*/
17898 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL
17899 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
17900 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK
17901 #define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL                                          0x00000000
17902 #define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT                                           2
17903 #define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK                                            0x00000004U
17904
17905 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
17906                  Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port)
17907                 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17908 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL
17909 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
17910 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK
17911 #define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL                                          0x00000000
17912 #define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT                                           3
17913 #define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK                                            0x00000018U
17914
17915 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
17916                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17917                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
17918                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd-
17919                 UART receiver serial input) 7= Not Used*/
17920 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL
17921 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
17922 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK
17923 #define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL                                          0x00000000
17924 #define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT                                           5
17925 #define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK                                            0x000000E0U
17926
17927 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17928 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL
17929 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
17930 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK
17931 #define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL                                          0x00000000
17932 #define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT                                           1
17933 #define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK                                            0x00000002U
17934
17935 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/
17936 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL
17937 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
17938 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK
17939 #define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL                                          0x00000000
17940 #define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT                                           2
17941 #define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK                                            0x00000004U
17942
17943 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
17944                 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17945 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL
17946 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
17947 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK
17948 #define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL                                          0x00000000
17949 #define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT                                           3
17950 #define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK                                            0x00000018U
17951
17952 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
17953                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17954                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
17955                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
17956                 sed*/
17957 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL
17958 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
17959 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK
17960 #define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL                                          0x00000000
17961 #define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT                                           5
17962 #define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK                                            0x000000E0U
17963
17964 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17965 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL
17966 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
17967 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK
17968 #define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL                                          0x00000000
17969 #define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT                                           1
17970 #define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK                                            0x00000002U
17971
17972 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND
17973                 ata Bus)*/
17974 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL
17975 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
17976 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK
17977 #define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL                                          0x00000000
17978 #define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT                                           2
17979 #define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK                                            0x00000004U
17980
17981 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
17982                 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
17983                 */
17984 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL
17985 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
17986 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK
17987 #define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL                                          0x00000000
17988 #define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT                                           3
17989 #define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK                                            0x00000018U
17990
17991 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
17992                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17993                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
17994                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
17995                 tput) 7= Not Used*/
17996 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL
17997 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
17998 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK
17999 #define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL                                          0x00000000
18000 #define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT                                           5
18001 #define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK                                            0x000000E0U
18002
18003 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
18004 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL
18005 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
18006 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK
18007 #define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL                                          0x00000000
18008 #define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT                                           1
18009 #define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK                                            0x00000002U
18010
18011 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND
18012                 ata Bus)*/
18013 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL
18014 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
18015 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK
18016 #define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL                                          0x00000000
18017 #define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT                                           2
18018 #define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK                                            0x00000004U
18019
18020 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
18021                 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
18022                  Tamper)*/
18023 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL
18024 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
18025 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK
18026 #define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL                                          0x00000000
18027 #define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT                                           3
18028 #define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK                                            0x00000018U
18029
18030 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
18031                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18032                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
18033                 Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
18034 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL
18035 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
18036 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK
18037 #define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL                                          0x00000000
18038 #define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT                                           5
18039 #define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK                                            0x000000E0U
18040
18041 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
18042 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL
18043 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
18044 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK
18045 #define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL                                          0x00000000
18046 #define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT                                           1
18047 #define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK                                            0x00000002U
18048
18049 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/
18050 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL
18051 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
18052 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK
18053 #define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL                                          0x00000000
18054 #define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT                                           2
18055 #define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK                                            0x00000004U
18056
18057 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
18058                 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
18059                 U Ext Tamper)*/
18060 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL
18061 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
18062 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK
18063 #define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL                                          0x00000000
18064 #define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT                                           3
18065 #define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK                                            0x00000018U
18066
18067 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
18068                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18069                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform
18070                 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
18071 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL
18072 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
18073 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK
18074 #define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL                                          0x00000000
18075 #define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT                                           5
18076 #define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK                                            0x000000E0U
18077
18078 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/
18079 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL
18080 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
18081 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK
18082 #define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL                                          0x00000000
18083 #define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT                                           1
18084 #define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK                                            0x00000002U
18085
18086 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
18087 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL
18088 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
18089 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK
18090 #define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL                                          0x00000000
18091 #define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT                                           2
18092 #define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK                                            0x00000004U
18093
18094 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
18095                 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
18096 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL
18097 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
18098 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK
18099 #define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL                                          0x00000000
18100 #define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT                                           3
18101 #define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK                                            0x00000018U
18102
18103 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
18104                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
18105                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
18106                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
18107                 Trace Port Databus)*/
18108 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL
18109 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
18110 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK
18111 #define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL                                          0x00000000
18112 #define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT                                           5
18113 #define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK                                            0x000000E0U
18114
18115 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/
18116 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL
18117 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
18118 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK
18119 #define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL                                          0x00000000
18120 #define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT                                           1
18121 #define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK                                            0x00000002U
18122
18123 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
18124 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL
18125 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
18126 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK
18127 #define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL                                          0x00000000
18128 #define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT                                           2
18129 #define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK                                            0x00000004U
18130
18131 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
18132                 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
18133                 t, dp_aux_data_out- (Dp Aux Data)*/
18134 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL
18135 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
18136 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK
18137 #define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL                                          0x00000000
18138 #define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT                                           3
18139 #define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK                                            0x00000018U
18140
18141 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
18142                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
18143                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
18144                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
18145                 atabus)*/
18146 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL
18147 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
18148 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK
18149 #define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL                                          0x00000000
18150 #define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT                                           5
18151 #define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK                                            0x000000E0U
18152
18153 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/
18154 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL
18155 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
18156 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK
18157 #define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL                                          0x00000000
18158 #define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT                                           1
18159 #define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK                                            0x00000002U
18160
18161 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
18162 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL
18163 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
18164 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK
18165 #define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL                                          0x00000000
18166 #define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT                                           2
18167 #define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK                                            0x00000004U
18168
18169 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
18170                 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
18171 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL
18172 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
18173 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK
18174 #define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL                                          0x00000000
18175 #define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT                                           3
18176 #define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK                                            0x00000018U
18177
18178 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
18179                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
18180                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
18181                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
18182 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL
18183 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
18184 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK
18185 #define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL                                          0x00000000
18186 #define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT                                           5
18187 #define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK                                            0x000000E0U
18188
18189 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/
18190 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL
18191 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
18192 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK
18193 #define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL                                          0x00000000
18194 #define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT                                           1
18195 #define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK                                            0x00000002U
18196
18197 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18198 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL
18199 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
18200 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK
18201 #define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL                                          0x00000000
18202 #define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT                                           2
18203 #define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK                                            0x00000004U
18204
18205 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
18206                 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
18207                 t, dp_aux_data_out- (Dp Aux Data)*/
18208 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL
18209 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
18210 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK
18211 #define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL                                          0x00000000
18212 #define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT                                           3
18213 #define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK                                            0x00000018U
18214
18215 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
18216                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
18217                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
18218                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
18219                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
18220 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL
18221 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
18222 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK
18223 #define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL                                          0x00000000
18224 #define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT                                           5
18225 #define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK                                            0x000000E0U
18226
18227 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/
18228 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL
18229 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
18230 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK
18231 #define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL                                          0x00000000
18232 #define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT                                           1
18233 #define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK                                            0x00000002U
18234
18235 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18236 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL
18237 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
18238 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK
18239 #define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL                                          0x00000000
18240 #define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT                                           2
18241 #define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK                                            0x00000004U
18242
18243 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
18244                 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
18245 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL
18246 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
18247 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK
18248 #define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL                                          0x00000000
18249 #define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT                                           3
18250 #define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK                                            0x00000018U
18251
18252 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
18253                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
18254                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
18255                  (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
18256                  tracedq[8]- (Trace Port Databus)*/
18257 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL
18258 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
18259 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK
18260 #define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL                                          0x00000000
18261 #define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT                                           5
18262 #define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK                                            0x000000E0U
18263
18264 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/
18265 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL
18266 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
18267 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK
18268 #define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL                                          0x00000000
18269 #define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT                                           1
18270 #define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK                                            0x00000002U
18271
18272 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18273 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL
18274 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
18275 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK
18276 #define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL                                          0x00000000
18277 #define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT                                           2
18278 #define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK                                            0x00000004U
18279
18280 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
18281                 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
18282 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL
18283 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
18284 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK
18285 #define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL                                          0x00000000
18286 #define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT                                           3
18287 #define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK                                            0x00000018U
18288
18289 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
18290                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
18291                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
18292                 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
18293                 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
18294 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL
18295 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
18296 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK
18297 #define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL                                          0x00000000
18298 #define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT                                           5
18299 #define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK                                            0x000000E0U
18300
18301 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/
18302 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL
18303 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
18304 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK
18305 #define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL                                          0x00000000
18306 #define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT                                           1
18307 #define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK                                            0x00000002U
18308
18309 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
18310                 */
18311 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL
18312 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
18313 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK
18314 #define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL                                          0x00000000
18315 #define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT                                           2
18316 #define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK                                            0x00000004U
18317
18318 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
18319                 an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
18320 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL
18321 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
18322 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK
18323 #define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL                                          0x00000000
18324 #define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT                                           3
18325 #define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK                                            0x00000018U
18326
18327 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
18328                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
18329                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
18330                 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
18331                 race, Output, tracedq[10]- (Trace Port Databus)*/
18332 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL
18333 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
18334 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK
18335 #define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL                                          0x00000000
18336 #define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT                                           5
18337 #define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK                                            0x000000E0U
18338
18339 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/
18340 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL
18341 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
18342 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK
18343 #define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL                                          0x00000000
18344 #define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT                                           1
18345 #define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK                                            0x00000002U
18346
18347 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18348 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL
18349 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
18350 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK
18351 #define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL                                          0x00000000
18352 #define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT                                           2
18353 #define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK                                            0x00000004U
18354
18355 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
18356                 an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
18357 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL
18358 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
18359 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK
18360 #define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL                                          0x00000000
18361 #define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT                                           3
18362 #define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK                                            0x00000018U
18363
18364 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
18365                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
18366                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
18367                 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
18368                 [11]- (Trace Port Databus)*/
18369 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL
18370 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
18371 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK
18372 #define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL                                          0x00000000
18373 #define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT                                           5
18374 #define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK                                            0x000000E0U
18375
18376 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/
18377 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL
18378 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
18379 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK
18380 #define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL                                          0x00000000
18381 #define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT                                           1
18382 #define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK                                            0x00000002U
18383
18384 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18385 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL
18386 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
18387 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK
18388 #define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL                                          0x00000000
18389 #define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT                                           2
18390 #define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK                                            0x00000004U
18391
18392 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
18393                 an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
18394                 ut, dp_aux_data_out- (Dp Aux Data)*/
18395 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL
18396 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
18397 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK
18398 #define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL                                          0x00000000
18399 #define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT                                           3
18400 #define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK                                            0x00000018U
18401
18402 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
18403                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
18404                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
18405                  Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
18406                 rt Databus)*/
18407 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL
18408 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
18409 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK
18410 #define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL                                          0x00000000
18411 #define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT                                           5
18412 #define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK                                            0x000000E0U
18413
18414 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/
18415 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL
18416 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
18417 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK
18418 #define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL                                          0x00000000
18419 #define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT                                           1
18420 #define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK                                            0x00000002U
18421
18422 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18423 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL
18424 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
18425 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK
18426 #define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL                                          0x00000000
18427 #define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT                                           2
18428 #define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK                                            0x00000004U
18429
18430 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
18431                 an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
18432 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL
18433 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
18434 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK
18435 #define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL                                          0x00000000
18436 #define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT                                           3
18437 #define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK                                            0x00000018U
18438
18439 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
18440                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
18441                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
18442                 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
18443                 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
18444 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL
18445 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
18446 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK
18447 #define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL                                          0x00000000
18448 #define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT                                           5
18449 #define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK                                            0x000000E0U
18450
18451 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/
18452 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL
18453 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
18454 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK
18455 #define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL                                          0x00000000
18456 #define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT                                           1
18457 #define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK                                            0x00000002U
18458
18459 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18460 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL
18461 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
18462 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK
18463 #define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL                                          0x00000000
18464 #define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT                                           2
18465 #define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK                                            0x00000004U
18466
18467 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
18468                 an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
18469                 ut, dp_aux_data_out- (Dp Aux Data)*/
18470 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL
18471 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
18472 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK
18473 #define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL                                          0x00000000
18474 #define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT                                           3
18475 #define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK                                            0x00000018U
18476
18477 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
18478                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18479                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
18480                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
18481                  Output, tracedq[14]- (Trace Port Databus)*/
18482 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL
18483 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
18484 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK
18485 #define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL                                          0x00000000
18486 #define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT                                           5
18487 #define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK                                            0x000000E0U
18488
18489 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/
18490 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL
18491 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
18492 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK
18493 #define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL                                          0x00000000
18494 #define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT                                           1
18495 #define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK                                            0x00000002U
18496
18497 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18498 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL
18499 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
18500 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK
18501 #define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL                                          0x00000000
18502 #define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT                                           2
18503 #define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK                                            0x00000004U
18504
18505 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
18506                 an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
18507 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL
18508 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
18509 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK
18510 #define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL                                          0x00000000
18511 #define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT                                           3
18512 #define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK                                            0x00000018U
18513
18514 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
18515                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18516                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
18517                 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
18518                 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
18519 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL
18520 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
18521 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK
18522 #define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL                                          0x00000000
18523 #define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT                                           5
18524 #define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK                                            0x000000E0U
18525
18526 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/
18527 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL
18528 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
18529 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK
18530 #define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL                                          0x00000000
18531 #define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT                                           1
18532 #define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK                                            0x00000002U
18533
18534 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18535 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL
18536 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
18537 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK
18538 #define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL                                          0x00000000
18539 #define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT                                           2
18540 #define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK                                            0x00000004U
18541
18542 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
18543 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL
18544 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
18545 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK
18546 #define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL                                          0x00000000
18547 #define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT                                           3
18548 #define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK                                            0x00000018U
18549
18550 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
18551                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18552                 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
18553                 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
18554                 (Trace Port Clock)*/
18555 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL
18556 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
18557 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK
18558 #define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL                                          0x00000000
18559 #define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT                                           5
18560 #define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK                                            0x000000E0U
18561
18562 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/
18563 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL
18564 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
18565 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK
18566 #define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL                                          0x00000000
18567 #define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT                                           1
18568 #define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK                                            0x00000002U
18569
18570 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18571 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL
18572 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
18573 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK
18574 #define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL                                          0x00000000
18575 #define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT                                           2
18576 #define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK                                            0x00000004U
18577
18578 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
18579                 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/
18580 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL
18581 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
18582 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK
18583 #define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL                                          0x00000000
18584 #define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT                                           3
18585 #define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK                                            0x00000018U
18586
18587 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
18588                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18589                 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
18590                 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
18591                 Control Signal)*/
18592 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL
18593 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
18594 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK
18595 #define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL                                          0x00000000
18596 #define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT                                           5
18597 #define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK                                            0x000000E0U
18598
18599 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/
18600 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL
18601 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
18602 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK
18603 #define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL                                          0x00000000
18604 #define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT                                           1
18605 #define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK                                            0x00000002U
18606
18607 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18608 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL
18609 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
18610 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK
18611 #define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL                                          0x00000000
18612 #define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT                                           2
18613 #define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK                                            0x00000004U
18614
18615 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
18616                  Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/
18617 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL
18618 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
18619 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK
18620 #define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL                                          0x00000000
18621 #define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT                                           3
18622 #define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK                                            0x00000018U
18623
18624 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
18625                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18626                 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
18627                 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
18628 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL
18629 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
18630 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK
18631 #define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL                                          0x00000000
18632 #define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT                                           5
18633 #define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK                                            0x000000E0U
18634
18635 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/
18636 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL
18637 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
18638 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK
18639 #define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL                                          0x00000000
18640 #define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT                                           1
18641 #define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK                                            0x00000002U
18642
18643 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18644 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL
18645 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
18646 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK
18647 #define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL                                          0x00000000
18648 #define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT                                           2
18649 #define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK                                            0x00000004U
18650
18651 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
18652                 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/
18653 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL
18654 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
18655 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK
18656 #define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL                                          0x00000000
18657 #define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT                                           3
18658 #define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK                                            0x00000018U
18659
18660 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
18661                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18662                 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
18663                 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
18664                 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
18665 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL
18666 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
18667 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK
18668 #define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL                                          0x00000000
18669 #define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT                                           5
18670 #define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK                                            0x000000E0U
18671
18672 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/
18673 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL
18674 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
18675 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK
18676 #define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL                                          0x00000000
18677 #define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT                                           1
18678 #define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK                                            0x00000002U
18679
18680 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18681 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL
18682 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
18683 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK
18684 #define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL                                          0x00000000
18685 #define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT                                           2
18686 #define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK                                            0x00000004U
18687
18688 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
18689                 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/
18690 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL
18691 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
18692 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK
18693 #define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL                                          0x00000000
18694 #define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT                                           3
18695 #define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK                                            0x00000018U
18696
18697 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
18698                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18699                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
18700                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
18701                 t, tracedq[2]- (Trace Port Databus)*/
18702 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL
18703 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
18704 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK
18705 #define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL                                          0x00000000
18706 #define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT                                           5
18707 #define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK                                            0x000000E0U
18708
18709 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/
18710 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL
18711 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
18712 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK
18713 #define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL                                          0x00000000
18714 #define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT                                           1
18715 #define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK                                            0x00000002U
18716
18717 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18718 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL
18719 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
18720 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK
18721 #define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL                                          0x00000000
18722 #define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT                                           2
18723 #define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK                                            0x00000004U
18724
18725 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
18726                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
18727 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL
18728 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
18729 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK
18730 #define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL                                          0x00000000
18731 #define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT                                           3
18732 #define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK                                            0x00000018U
18733
18734 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
18735                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18736                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
18737                 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
18738                 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/
18739 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL
18740 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
18741 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK
18742 #define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL                                          0x00000000
18743 #define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT                                           5
18744 #define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK                                            0x000000E0U
18745
18746 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/
18747 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL
18748 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
18749 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK
18750 #define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL                                          0x00000000
18751 #define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT                                           1
18752 #define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK                                            0x00000002U
18753
18754 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18755 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL
18756 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
18757 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK
18758 #define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL                                          0x00000000
18759 #define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT                                           2
18760 #define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK                                            0x00000004U
18761
18762 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
18763                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
18764 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL
18765 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
18766 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK
18767 #define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL                                          0x00000000
18768 #define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT                                           3
18769 #define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK                                            0x00000018U
18770
18771 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
18772                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18773                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
18774                 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
18775                  Not Used*/
18776 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL
18777 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
18778 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK
18779 #define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL                                          0x00000000
18780 #define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT                                           5
18781 #define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK                                            0x000000E0U
18782
18783 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/
18784 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL
18785 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
18786 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK
18787 #define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL                                          0x00000000
18788 #define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT                                           1
18789 #define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK                                            0x00000002U
18790
18791 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18792 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL
18793 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
18794 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK
18795 #define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL                                          0x00000000
18796 #define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT                                           2
18797 #define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK                                            0x00000004U
18798
18799 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
18800                 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
18801 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL
18802 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
18803 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK
18804 #define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL                                          0x00000000
18805 #define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT                                           3
18806 #define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK                                            0x00000018U
18807
18808 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
18809                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18810                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
18811                 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
18812 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL
18813 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
18814 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK
18815 #define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL                                          0x00000000
18816 #define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT                                           5
18817 #define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK                                            0x000000E0U
18818
18819 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/
18820 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL
18821 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
18822 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK
18823 #define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL                                          0x00000000
18824 #define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT                                           1
18825 #define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK                                            0x00000002U
18826
18827 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18828 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL
18829 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
18830 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK
18831 #define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL                                          0x00000000
18832 #define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT                                           2
18833 #define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK                                            0x00000004U
18834
18835 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
18836                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
18837 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL
18838 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
18839 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK
18840 #define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL                                          0x00000000
18841 #define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT                                           3
18842 #define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK                                            0x00000018U
18843
18844 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
18845                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18846                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
18847                 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
18848 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL
18849 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
18850 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK
18851 #define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL                                          0x00000000
18852 #define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT                                           5
18853 #define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK                                            0x000000E0U
18854
18855 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/
18856 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL
18857 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
18858 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK
18859 #define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL                                          0x00000000
18860 #define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT                                           1
18861 #define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK                                            0x00000002U
18862
18863 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18864 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL
18865 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
18866 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK
18867 #define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL                                          0x00000000
18868 #define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT                                           2
18869 #define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK                                            0x00000004U
18870
18871 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
18872                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
18873 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL
18874 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
18875 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK
18876 #define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL                                          0x00000000
18877 #define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT                                           3
18878 #define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK                                            0x00000018U
18879
18880 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
18881                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18882                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
18883                 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
18884                  (UART transmitter serial output) 7= Not Used*/
18885 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL
18886 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
18887 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK
18888 #define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL                                          0x00000000
18889 #define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT                                           5
18890 #define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK                                            0x000000E0U
18891
18892 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/
18893 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL
18894 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
18895 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK
18896 #define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL                                          0x00000000
18897 #define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT                                           1
18898 #define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK                                            0x00000002U
18899
18900 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18901 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL
18902 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
18903 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK
18904 #define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL                                          0x00000000
18905 #define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT                                           2
18906 #define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK                                            0x00000004U
18907
18908 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
18909                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
18910 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL
18911 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
18912 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK
18913 #define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL                                          0x00000000
18914 #define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT                                           3
18915 #define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK                                            0x00000018U
18916
18917 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
18918                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18919                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
18920                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
18921                 ed*/
18922 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL
18923 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
18924 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK
18925 #define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL                                          0x00000000
18926 #define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT                                           5
18927 #define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK                                            0x000000E0U
18928
18929 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/
18930 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL
18931 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
18932 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK
18933 #define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL                                          0x00000000
18934 #define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT                                           1
18935 #define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK                                            0x00000002U
18936
18937 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18938 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL
18939 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
18940 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK
18941 #define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL                                          0x00000000
18942 #define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT                                           2
18943 #define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK                                            0x00000004U
18944
18945 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
18946                 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
18947 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL
18948 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
18949 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK
18950 #define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL                                          0x00000000
18951 #define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT                                           3
18952 #define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK                                            0x00000018U
18953
18954 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
18955                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18956                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
18957                 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
18958                 7= Not Used*/
18959 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL
18960 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
18961 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK
18962 #define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL                                          0x00000000
18963 #define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT                                           5
18964 #define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK                                            0x000000E0U
18965
18966 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
18967 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL
18968 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
18969 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK
18970 #define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL                                          0x00000000
18971 #define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT                                           1
18972 #define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK                                            0x00000002U
18973
18974 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18975 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL
18976 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
18977 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK
18978 #define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL                                          0x00000000
18979 #define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT                                           2
18980 #define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK                                            0x00000004U
18981
18982 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
18983                 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
18984 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL
18985 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
18986 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK
18987 #define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL                                          0x00000000
18988 #define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT                                           3
18989 #define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK                                            0x00000018U
18990
18991 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
18992                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18993                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
18994                 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
18995 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL
18996 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
18997 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK
18998 #define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL                                          0x00000000
18999 #define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT                                           5
19000 #define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK                                            0x000000E0U
19001
19002 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
19003 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL
19004 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
19005 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK
19006 #define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL                                          0x00000000
19007 #define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT                                           1
19008 #define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK                                            0x00000002U
19009
19010 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
19011 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL
19012 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
19013 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK
19014 #define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL                                          0x00000000
19015 #define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT                                           2
19016 #define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK                                            0x00000004U
19017
19018 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/
19019 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL
19020 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
19021 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK
19022 #define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL                                          0x00000000
19023 #define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT                                           3
19024 #define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK                                            0x00000018U
19025
19026 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
19027                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19028                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
19029                 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
19030                 serial output) 7= Not Used*/
19031 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL
19032 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
19033 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK
19034 #define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL                                          0x00000000
19035 #define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT                                           5
19036 #define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK                                            0x000000E0U
19037
19038 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/
19039 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL
19040 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
19041 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK
19042 #define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL                                          0x00000000
19043 #define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT                                           1
19044 #define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK                                            0x00000002U
19045
19046 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/
19047 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL
19048 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
19049 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK
19050 #define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL                                          0x00000000
19051 #define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT                                           2
19052 #define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK                                            0x00000004U
19053
19054 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19055 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL
19056 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
19057 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK
19058 #define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL                                          0x00000000
19059 #define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT                                           3
19060 #define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK                                            0x00000018U
19061
19062 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
19063                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
19064                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
19065                 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
19066                 lk- (Trace Port Clock)*/
19067 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL
19068 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
19069 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK
19070 #define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL                                          0x00000000
19071 #define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT                                           5
19072 #define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK                                            0x000000E0U
19073
19074 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/
19075 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL
19076 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
19077 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK
19078 #define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL                                          0x00000000
19079 #define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT                                           1
19080 #define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK                                            0x00000002U
19081
19082 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/
19083 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL
19084 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
19085 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK
19086 #define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL                                          0x00000000
19087 #define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT                                           2
19088 #define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK                                            0x00000004U
19089
19090 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19091 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL
19092 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
19093 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK
19094 #define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL                                          0x00000000
19095 #define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT                                           3
19096 #define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK                                            0x00000018U
19097
19098 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
19099                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
19100                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
19101                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
19102                 Signal)*/
19103 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL
19104 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
19105 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK
19106 #define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL                                          0x00000000
19107 #define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT                                           5
19108 #define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK                                            0x000000E0U
19109
19110 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/
19111 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL
19112 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
19113 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK
19114 #define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL                                          0x00000000
19115 #define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT                                           1
19116 #define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK                                            0x00000002U
19117
19118 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19119                 ata[2]- (ULPI data bus)*/
19120 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL
19121 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
19122 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK
19123 #define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL                                          0x00000000
19124 #define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT                                           2
19125 #define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK                                            0x00000004U
19126
19127 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19128 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL
19129 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
19130 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK
19131 #define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL                                          0x00000000
19132 #define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT                                           3
19133 #define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK                                            0x00000018U
19134
19135 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
19136                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
19137                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
19138                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
19139 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL
19140 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
19141 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK
19142 #define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL                                          0x00000000
19143 #define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT                                           5
19144 #define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK                                            0x000000E0U
19145
19146 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/
19147 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL
19148 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
19149 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK
19150 #define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL                                          0x00000000
19151 #define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT                                           1
19152 #define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK                                            0x00000002U
19153
19154 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/
19155 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL
19156 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
19157 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK
19158 #define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL                                          0x00000000
19159 #define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT                                           2
19160 #define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK                                            0x00000004U
19161
19162 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19163 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL
19164 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
19165 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK
19166 #define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL                                          0x00000000
19167 #define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT                                           3
19168 #define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK                                            0x00000018U
19169
19170 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
19171                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
19172                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
19173                 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
19174                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
19175 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL
19176 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
19177 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK
19178 #define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL                                          0x00000000
19179 #define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT                                           5
19180 #define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK                                            0x000000E0U
19181
19182 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/
19183 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL
19184 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
19185 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK
19186 #define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL                                          0x00000000
19187 #define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT                                           1
19188 #define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK                                            0x00000002U
19189
19190 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19191                 ata[0]- (ULPI data bus)*/
19192 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL
19193 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
19194 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK
19195 #define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL                                          0x00000000
19196 #define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT                                           2
19197 #define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK                                            0x00000004U
19198
19199 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19200 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL
19201 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
19202 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK
19203 #define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL                                          0x00000000
19204 #define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT                                           3
19205 #define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK                                            0x00000018U
19206
19207 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
19208                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
19209                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
19210                 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
19211                 utput, tracedq[2]- (Trace Port Databus)*/
19212 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL
19213 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
19214 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK
19215 #define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL                                          0x00000000
19216 #define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT                                           5
19217 #define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK                                            0x000000E0U
19218
19219 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/
19220 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL
19221 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
19222 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK
19223 #define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL                                          0x00000000
19224 #define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT                                           1
19225 #define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK                                            0x00000002U
19226
19227 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19228                 ata[1]- (ULPI data bus)*/
19229 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL
19230 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
19231 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK
19232 #define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL                                          0x00000000
19233 #define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT                                           2
19234 #define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK                                            0x00000004U
19235
19236 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19237 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL
19238 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
19239 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK
19240 #define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL                                          0x00000000
19241 #define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT                                           3
19242 #define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK                                            0x00000018U
19243
19244 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
19245                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
19246                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
19247                 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
19248                  trace, Output, tracedq[3]- (Trace Port Databus)*/
19249 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL
19250 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
19251 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK
19252 #define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL                                          0x00000000
19253 #define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT                                           5
19254 #define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK                                            0x000000E0U
19255
19256 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/
19257 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL
19258 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
19259 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK
19260 #define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL                                          0x00000000
19261 #define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT                                           1
19262 #define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK                                            0x00000002U
19263
19264 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/
19265 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL
19266 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
19267 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK
19268 #define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL                                          0x00000000
19269 #define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT                                           2
19270 #define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK                                            0x00000004U
19271
19272 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19273 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL
19274 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
19275 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK
19276 #define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL                                          0x00000000
19277 #define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT                                           3
19278 #define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK                                            0x00000018U
19279
19280 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
19281                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
19282                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
19283                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
19284                 Trace Port Databus)*/
19285 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL
19286 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
19287 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK
19288 #define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL                                          0x00000000
19289 #define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT                                           5
19290 #define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK                                            0x000000E0U
19291
19292 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/
19293 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL
19294 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
19295 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK
19296 #define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL                                          0x00000000
19297 #define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT                                           1
19298 #define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK                                            0x00000002U
19299
19300 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19301                 ata[3]- (ULPI data bus)*/
19302 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL
19303 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
19304 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK
19305 #define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL                                          0x00000000
19306 #define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT                                           2
19307 #define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK                                            0x00000004U
19308
19309 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19310 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL
19311 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
19312 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK
19313 #define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL                                          0x00000000
19314 #define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT                                           3
19315 #define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK                                            0x00000018U
19316
19317 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
19318                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
19319                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
19320                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
19321                 atabus)*/
19322 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL
19323 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
19324 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK
19325 #define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL                                          0x00000000
19326 #define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT                                           5
19327 #define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK                                            0x000000E0U
19328
19329 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/
19330 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL
19331 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
19332 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK
19333 #define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL                                          0x00000000
19334 #define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT                                           1
19335 #define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK                                            0x00000002U
19336
19337 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19338                 ata[4]- (ULPI data bus)*/
19339 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL
19340 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
19341 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK
19342 #define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL                                          0x00000000
19343 #define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT                                           2
19344 #define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK                                            0x00000004U
19345
19346 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19347 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL
19348 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
19349 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK
19350 #define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL                                          0x00000000
19351 #define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT                                           3
19352 #define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK                                            0x00000018U
19353
19354 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
19355                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
19356                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
19357                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
19358 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL
19359 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
19360 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK
19361 #define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL                                          0x00000000
19362 #define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT                                           5
19363 #define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK                                            0x000000E0U
19364
19365 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/
19366 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL
19367 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
19368 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK
19369 #define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL                                          0x00000000
19370 #define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT                                           1
19371 #define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK                                            0x00000002U
19372
19373 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19374                 ata[5]- (ULPI data bus)*/
19375 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL
19376 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
19377 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK
19378 #define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL                                          0x00000000
19379 #define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT                                           2
19380 #define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK                                            0x00000004U
19381
19382 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19383 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL
19384 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
19385 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK
19386 #define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL                                          0x00000000
19387 #define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT                                           3
19388 #define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK                                            0x00000018U
19389
19390 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
19391                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
19392                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
19393                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
19394                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
19395 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL
19396 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
19397 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK
19398 #define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL                                          0x00000000
19399 #define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT                                           5
19400 #define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK                                            0x000000E0U
19401
19402 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/
19403 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL
19404 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
19405 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK
19406 #define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL                                          0x00000000
19407 #define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT                                           1
19408 #define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK                                            0x00000002U
19409
19410 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19411                 ata[6]- (ULPI data bus)*/
19412 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL
19413 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
19414 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK
19415 #define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL                                          0x00000000
19416 #define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT                                           2
19417 #define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK                                            0x00000004U
19418
19419 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19420 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL
19421 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
19422 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK
19423 #define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL                                          0x00000000
19424 #define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT                                           3
19425 #define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK                                            0x00000018U
19426
19427 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
19428                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19429                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
19430                 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
19431                 t, tracedq[8]- (Trace Port Databus)*/
19432 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL
19433 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
19434 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK
19435 #define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL                                          0x00000000
19436 #define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT                                           5
19437 #define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK                                            0x000000E0U
19438
19439 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/
19440 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL
19441 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
19442 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK
19443 #define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL                                          0x00000000
19444 #define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT                                           1
19445 #define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK                                            0x00000002U
19446
19447 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19448                 ata[7]- (ULPI data bus)*/
19449 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL
19450 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
19451 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK
19452 #define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL                                          0x00000000
19453 #define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT                                           2
19454 #define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK                                            0x00000004U
19455
19456 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19457 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL
19458 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
19459 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK
19460 #define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL                                          0x00000000
19461 #define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT                                           3
19462 #define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK                                            0x00000018U
19463
19464 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
19465                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19466                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
19467                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
19468                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
19469 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL
19470 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
19471 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK
19472 #define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL                                          0x00000000
19473 #define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT                                           5
19474 #define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK                                            0x000000E0U
19475
19476 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/
19477 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL
19478 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
19479 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK
19480 #define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL                                          0x00000000
19481 #define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT                                           1
19482 #define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK                                            0x00000002U
19483
19484 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/
19485 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL
19486 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
19487 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK
19488 #define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL                                          0x00000000
19489 #define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT                                           2
19490 #define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK                                            0x00000004U
19491
19492 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
19493 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL
19494 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
19495 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK
19496 #define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL                                          0x00000000
19497 #define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT                                           3
19498 #define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK                                            0x00000018U
19499
19500 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
19501                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19502                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
19503                 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
19504                  trace, Output, tracedq[10]- (Trace Port Databus)*/
19505 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL
19506 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
19507 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK
19508 #define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL                                          0x00000000
19509 #define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT                                           5
19510 #define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK                                            0x000000E0U
19511
19512 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/
19513 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL
19514 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
19515 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK
19516 #define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL                                          0x00000000
19517 #define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT                                           1
19518 #define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK                                            0x00000002U
19519
19520 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/
19521 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL
19522 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
19523 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK
19524 #define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL                                          0x00000000
19525 #define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT                                           2
19526 #define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK                                            0x00000004U
19527
19528 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/
19529 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL
19530 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
19531 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK
19532 #define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL                                          0x00000000
19533 #define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT                                           3
19534 #define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK                                            0x00000018U
19535
19536 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
19537                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19538                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
19539                 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
19540                 dq[11]- (Trace Port Databus)*/
19541 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL
19542 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
19543 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK
19544 #define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL                                          0x00000000
19545 #define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT                                           5
19546 #define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK                                            0x000000E0U
19547
19548 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/
19549 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL
19550 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
19551 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK
19552 #define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL                                          0x00000000
19553 #define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT                                           1
19554 #define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK                                            0x00000002U
19555
19556 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19557                 ata[2]- (ULPI data bus)*/
19558 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL
19559 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
19560 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK
19561 #define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL                                          0x00000000
19562 #define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT                                           2
19563 #define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK                                            0x00000004U
19564
19565 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
19566                  Indicator) 2= Not Used 3= Not Used*/
19567 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL
19568 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
19569 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK
19570 #define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL                                          0x00000000
19571 #define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT                                           3
19572 #define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK                                            0x00000018U
19573
19574 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
19575                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19576                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
19577                 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
19578                 Port Databus)*/
19579 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL
19580 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
19581 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK
19582 #define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL                                          0x00000000
19583 #define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT                                           5
19584 #define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK                                            0x000000E0U
19585
19586 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/
19587 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL
19588 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
19589 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK
19590 #define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL                                          0x00000000
19591 #define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT                                           1
19592 #define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK                                            0x00000002U
19593
19594 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/
19595 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL
19596 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
19597 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK
19598 #define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL                                          0x00000000
19599 #define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT                                           2
19600 #define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK                                            0x00000004U
19601
19602 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
19603                 bit Data bus) 2= Not Used 3= Not Used*/
19604 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL
19605 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
19606 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK
19607 #define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL                                          0x00000000
19608 #define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT                                           3
19609 #define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK                                            0x00000018U
19610
19611 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
19612                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19613                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
19614                 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
19615                  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
19616 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL
19617 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
19618 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK
19619 #define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL                                          0x00000000
19620 #define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT                                           5
19621 #define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK                                            0x000000E0U
19622
19623 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/
19624 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL
19625 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
19626 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK
19627 #define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL                                          0x00000000
19628 #define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT                                           1
19629 #define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK                                            0x00000002U
19630
19631 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19632                 ata[0]- (ULPI data bus)*/
19633 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL
19634 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
19635 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK
19636 #define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL                                          0x00000000
19637 #define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT                                           2
19638 #define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK                                            0x00000004U
19639
19640 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
19641                 bit Data bus) 2= Not Used 3= Not Used*/
19642 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL
19643 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
19644 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK
19645 #define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL                                          0x00000000
19646 #define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT                                           3
19647 #define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK                                            0x00000018U
19648
19649 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
19650                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19651                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
19652                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
19653                  Output, tracedq[14]- (Trace Port Databus)*/
19654 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL
19655 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
19656 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK
19657 #define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL                                          0x00000000
19658 #define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT                                           5
19659 #define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK                                            0x000000E0U
19660
19661 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/
19662 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL
19663 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
19664 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK
19665 #define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL                                          0x00000000
19666 #define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT                                           1
19667 #define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK                                            0x00000002U
19668
19669 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19670                 ata[1]- (ULPI data bus)*/
19671 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL
19672 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
19673 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK
19674 #define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL                                          0x00000000
19675 #define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT                                           2
19676 #define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK                                            0x00000004U
19677
19678 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
19679                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
19680 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL
19681 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
19682 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK
19683 #define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL                                          0x00000000
19684 #define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT                                           3
19685 #define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK                                            0x00000018U
19686
19687 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
19688                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19689                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
19690                 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
19691                 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
19692 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL
19693 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
19694 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK
19695 #define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL                                          0x00000000
19696 #define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT                                           5
19697 #define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK                                            0x000000E0U
19698
19699 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/
19700 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL
19701 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
19702 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK
19703 #define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL                                          0x00000000
19704 #define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT                                           1
19705 #define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK                                            0x00000002U
19706
19707 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/
19708 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL
19709 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
19710 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK
19711 #define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL                                          0x00000000
19712 #define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT                                           2
19713 #define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK                                            0x00000004U
19714
19715 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
19716                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
19717 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL
19718 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
19719 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK
19720 #define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL                                          0x00000000
19721 #define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT                                           3
19722 #define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK                                            0x00000018U
19723
19724 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
19725                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19726                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
19727                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
19728                 sed*/
19729 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL
19730 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
19731 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK
19732 #define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL                                          0x00000000
19733 #define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT                                           5
19734 #define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK                                            0x000000E0U
19735
19736 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/
19737 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL
19738 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
19739 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK
19740 #define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL                                          0x00000000
19741 #define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT                                           1
19742 #define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK                                            0x00000002U
19743
19744 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19745                 ata[3]- (ULPI data bus)*/
19746 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL
19747 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
19748 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK
19749 #define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL                                          0x00000000
19750 #define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT                                           2
19751 #define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK                                            0x00000004U
19752
19753 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
19754                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
19755 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL
19756 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
19757 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK
19758 #define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL                                          0x00000000
19759 #define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT                                           3
19760 #define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK                                            0x00000018U
19761
19762 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
19763                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19764                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
19765                  ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
19766 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL
19767 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
19768 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK
19769 #define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL                                          0x00000000
19770 #define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT                                           5
19771 #define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK                                            0x000000E0U
19772
19773 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/
19774 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL
19775 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
19776 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK
19777 #define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL                                          0x00000000
19778 #define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT                                           1
19779 #define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK                                            0x00000002U
19780
19781 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19782                 ata[4]- (ULPI data bus)*/
19783 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL
19784 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
19785 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK
19786 #define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL                                          0x00000000
19787 #define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT                                           2
19788 #define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK                                            0x00000004U
19789
19790 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
19791                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
19792 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL
19793 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
19794 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK
19795 #define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL                                          0x00000000
19796 #define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT                                           3
19797 #define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK                                            0x00000018U
19798
19799 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
19800                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19801                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
19802                 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
19803 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL
19804 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
19805 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK
19806 #define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL                                          0x00000000
19807 #define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT                                           5
19808 #define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK                                            0x000000E0U
19809
19810 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/
19811 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL
19812 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
19813 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK
19814 #define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL                                          0x00000000
19815 #define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT                                           1
19816 #define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK                                            0x00000002U
19817
19818 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19819                 ata[5]- (ULPI data bus)*/
19820 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL
19821 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
19822 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK
19823 #define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL                                          0x00000000
19824 #define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT                                           2
19825 #define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK                                            0x00000004U
19826
19827 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
19828                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
19829 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL
19830 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
19831 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK
19832 #define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL                                          0x00000000
19833 #define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT                                           3
19834 #define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK                                            0x00000018U
19835
19836 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
19837                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19838                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
19839                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
19840 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL
19841 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
19842 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK
19843 #define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL                                          0x00000000
19844 #define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT                                           5
19845 #define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK                                            0x000000E0U
19846
19847 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/
19848 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL
19849 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
19850 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK
19851 #define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL                                          0x00000000
19852 #define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT                                           1
19853 #define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK                                            0x00000002U
19854
19855 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19856                 ata[6]- (ULPI data bus)*/
19857 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL
19858 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
19859 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK
19860 #define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL                                          0x00000000
19861 #define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT                                           2
19862 #define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK                                            0x00000004U
19863
19864 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
19865                 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
19866 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL
19867 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
19868 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK
19869 #define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL                                          0x00000000
19870 #define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT                                           3
19871 #define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK                                            0x00000018U
19872
19873 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
19874                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19875                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
19876                 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
19877 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL
19878 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
19879 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK
19880 #define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL                                          0x00000000
19881 #define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT                                           5
19882 #define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK                                            0x000000E0U
19883
19884 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/
19885 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL
19886 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
19887 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK
19888 #define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL                                          0x00000000
19889 #define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT                                           1
19890 #define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK                                            0x00000002U
19891
19892 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19893                 ata[7]- (ULPI data bus)*/
19894 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL
19895 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
19896 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK
19897 #define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL                                          0x00000000
19898 #define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT                                           2
19899 #define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK                                            0x00000004U
19900
19901 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
19902                 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
19903 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL
19904 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
19905 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK
19906 #define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL                                          0x00000000
19907 #define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT                                           3
19908 #define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK                                            0x00000018U
19909
19910 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
19911                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19912                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
19913                 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
19914 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL
19915 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
19916 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK
19917 #define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL                                          0x00000000
19918 #define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT                                           5
19919 #define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK                                            0x000000E0U
19920
19921 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
19922 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL
19923 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
19924 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK
19925 #define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL                                          0x00000000
19926 #define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT                                           1
19927 #define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK                                            0x00000002U
19928
19929 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
19930 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL
19931 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
19932 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK
19933 #define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL                                          0x00000000
19934 #define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT                                           2
19935 #define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK                                            0x00000004U
19936
19937 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
19938                 _clk_out- (SDSDIO clock) 3= Not Used*/
19939 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL
19940 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
19941 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK
19942 #define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL                                          0x00000000
19943 #define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT                                           3
19944 #define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK                                            0x00000018U
19945
19946 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
19947                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19948                 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
19949                  6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/
19950 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL
19951 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
19952 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK
19953 #define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL                                          0x00000000
19954 #define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT                                           5
19955 #define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK                                            0x000000E0U
19956
19957 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
19958 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL
19959 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
19960 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK
19961 #define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL                                          0x00000000
19962 #define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT                                           1
19963 #define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK                                            0x00000002U
19964
19965 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
19966 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL
19967 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
19968 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK
19969 #define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL                                          0x00000000
19970 #define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT                                           2
19971 #define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK                                            0x00000004U
19972
19973 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
19974 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL
19975 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
19976 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK
19977 #define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL                                          0x00000000
19978 #define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT                                           3
19979 #define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK                                            0x00000018U
19980
19981 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
19982                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19983                 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
19984                 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
19985                 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/
19986 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL
19987 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
19988 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK
19989 #define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL                                          0x00000000
19990 #define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT                                           5
19991 #define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK                                            0x000000E0U
19992
19993 /*Master Tri-state Enable for pin 0, active high*/
19994 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL
19995 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
19996 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK
19997 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL                                    0xFFFFFFFF
19998 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT                                     0
19999 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK                                      0x00000001U
20000
20001 /*Master Tri-state Enable for pin 1, active high*/
20002 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL
20003 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
20004 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK
20005 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL                                    0xFFFFFFFF
20006 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT                                     1
20007 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK                                      0x00000002U
20008
20009 /*Master Tri-state Enable for pin 2, active high*/
20010 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL
20011 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
20012 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK
20013 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL                                    0xFFFFFFFF
20014 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT                                     2
20015 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK                                      0x00000004U
20016
20017 /*Master Tri-state Enable for pin 3, active high*/
20018 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL
20019 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
20020 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK
20021 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL                                    0xFFFFFFFF
20022 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT                                     3
20023 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK                                      0x00000008U
20024
20025 /*Master Tri-state Enable for pin 4, active high*/
20026 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL
20027 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
20028 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK
20029 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL                                    0xFFFFFFFF
20030 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT                                     4
20031 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK                                      0x00000010U
20032
20033 /*Master Tri-state Enable for pin 5, active high*/
20034 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL
20035 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
20036 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK
20037 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL                                    0xFFFFFFFF
20038 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT                                     5
20039 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK                                      0x00000020U
20040
20041 /*Master Tri-state Enable for pin 6, active high*/
20042 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL
20043 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
20044 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK
20045 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL                                    0xFFFFFFFF
20046 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT                                     6
20047 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK                                      0x00000040U
20048
20049 /*Master Tri-state Enable for pin 7, active high*/
20050 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL
20051 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
20052 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK
20053 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL                                    0xFFFFFFFF
20054 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT                                     7
20055 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK                                      0x00000080U
20056
20057 /*Master Tri-state Enable for pin 8, active high*/
20058 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL
20059 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
20060 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK
20061 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL                                    0xFFFFFFFF
20062 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT                                     8
20063 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK                                      0x00000100U
20064
20065 /*Master Tri-state Enable for pin 9, active high*/
20066 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL
20067 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
20068 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK
20069 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL                                    0xFFFFFFFF
20070 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT                                     9
20071 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK                                      0x00000200U
20072
20073 /*Master Tri-state Enable for pin 10, active high*/
20074 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL
20075 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
20076 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK
20077 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL                                    0xFFFFFFFF
20078 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT                                     10
20079 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK                                      0x00000400U
20080
20081 /*Master Tri-state Enable for pin 11, active high*/
20082 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL
20083 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
20084 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK
20085 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL                                    0xFFFFFFFF
20086 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT                                     11
20087 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK                                      0x00000800U
20088
20089 /*Master Tri-state Enable for pin 12, active high*/
20090 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL
20091 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
20092 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK
20093 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL                                    0xFFFFFFFF
20094 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT                                     12
20095 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK                                      0x00001000U
20096
20097 /*Master Tri-state Enable for pin 13, active high*/
20098 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL
20099 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
20100 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK
20101 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL                                    0xFFFFFFFF
20102 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT                                     13
20103 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK                                      0x00002000U
20104
20105 /*Master Tri-state Enable for pin 14, active high*/
20106 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL
20107 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
20108 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK
20109 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL                                    0xFFFFFFFF
20110 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT                                     14
20111 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK                                      0x00004000U
20112
20113 /*Master Tri-state Enable for pin 15, active high*/
20114 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL
20115 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
20116 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK
20117 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL                                    0xFFFFFFFF
20118 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT                                     15
20119 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK                                      0x00008000U
20120
20121 /*Master Tri-state Enable for pin 16, active high*/
20122 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL
20123 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
20124 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK
20125 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL                                    0xFFFFFFFF
20126 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT                                     16
20127 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK                                      0x00010000U
20128
20129 /*Master Tri-state Enable for pin 17, active high*/
20130 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL
20131 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
20132 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK
20133 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL                                    0xFFFFFFFF
20134 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT                                     17
20135 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK                                      0x00020000U
20136
20137 /*Master Tri-state Enable for pin 18, active high*/
20138 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL
20139 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
20140 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK
20141 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL                                    0xFFFFFFFF
20142 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT                                     18
20143 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK                                      0x00040000U
20144
20145 /*Master Tri-state Enable for pin 19, active high*/
20146 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL
20147 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
20148 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK
20149 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL                                    0xFFFFFFFF
20150 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT                                     19
20151 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK                                      0x00080000U
20152
20153 /*Master Tri-state Enable for pin 20, active high*/
20154 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL
20155 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
20156 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK
20157 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL                                    0xFFFFFFFF
20158 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT                                     20
20159 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK                                      0x00100000U
20160
20161 /*Master Tri-state Enable for pin 21, active high*/
20162 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL
20163 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
20164 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK
20165 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL                                    0xFFFFFFFF
20166 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT                                     21
20167 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK                                      0x00200000U
20168
20169 /*Master Tri-state Enable for pin 22, active high*/
20170 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL
20171 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
20172 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK
20173 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL                                    0xFFFFFFFF
20174 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT                                     22
20175 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK                                      0x00400000U
20176
20177 /*Master Tri-state Enable for pin 23, active high*/
20178 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL
20179 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
20180 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK
20181 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL                                    0xFFFFFFFF
20182 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT                                     23
20183 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK                                      0x00800000U
20184
20185 /*Master Tri-state Enable for pin 24, active high*/
20186 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL
20187 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
20188 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK
20189 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL                                    0xFFFFFFFF
20190 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT                                     24
20191 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK                                      0x01000000U
20192
20193 /*Master Tri-state Enable for pin 25, active high*/
20194 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL
20195 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
20196 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK
20197 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL                                    0xFFFFFFFF
20198 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT                                     25
20199 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK                                      0x02000000U
20200
20201 /*Master Tri-state Enable for pin 26, active high*/
20202 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL
20203 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
20204 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK
20205 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL                                    0xFFFFFFFF
20206 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT                                     26
20207 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK                                      0x04000000U
20208
20209 /*Master Tri-state Enable for pin 27, active high*/
20210 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL
20211 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
20212 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK
20213 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL                                    0xFFFFFFFF
20214 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT                                     27
20215 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK                                      0x08000000U
20216
20217 /*Master Tri-state Enable for pin 28, active high*/
20218 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL
20219 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
20220 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK
20221 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL                                    0xFFFFFFFF
20222 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT                                     28
20223 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK                                      0x10000000U
20224
20225 /*Master Tri-state Enable for pin 29, active high*/
20226 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL
20227 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
20228 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK
20229 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL                                    0xFFFFFFFF
20230 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT                                     29
20231 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK                                      0x20000000U
20232
20233 /*Master Tri-state Enable for pin 30, active high*/
20234 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL
20235 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
20236 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK
20237 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL                                    0xFFFFFFFF
20238 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT                                     30
20239 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK                                      0x40000000U
20240
20241 /*Master Tri-state Enable for pin 31, active high*/
20242 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL
20243 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
20244 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK
20245 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL                                    0xFFFFFFFF
20246 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT                                     31
20247 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK                                      0x80000000U
20248
20249 /*Master Tri-state Enable for pin 32, active high*/
20250 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL
20251 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
20252 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK
20253 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL                                    0xFFFFFFFF
20254 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT                                     0
20255 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK                                      0x00000001U
20256
20257 /*Master Tri-state Enable for pin 33, active high*/
20258 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL
20259 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
20260 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK
20261 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL                                    0xFFFFFFFF
20262 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT                                     1
20263 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK                                      0x00000002U
20264
20265 /*Master Tri-state Enable for pin 34, active high*/
20266 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL
20267 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
20268 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK
20269 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL                                    0xFFFFFFFF
20270 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT                                     2
20271 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK                                      0x00000004U
20272
20273 /*Master Tri-state Enable for pin 35, active high*/
20274 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL
20275 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
20276 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK
20277 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL                                    0xFFFFFFFF
20278 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT                                     3
20279 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK                                      0x00000008U
20280
20281 /*Master Tri-state Enable for pin 36, active high*/
20282 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL
20283 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
20284 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK
20285 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL                                    0xFFFFFFFF
20286 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT                                     4
20287 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK                                      0x00000010U
20288
20289 /*Master Tri-state Enable for pin 37, active high*/
20290 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL
20291 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
20292 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK
20293 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL                                    0xFFFFFFFF
20294 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT                                     5
20295 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK                                      0x00000020U
20296
20297 /*Master Tri-state Enable for pin 38, active high*/
20298 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL
20299 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
20300 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK
20301 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL                                    0xFFFFFFFF
20302 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT                                     6
20303 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK                                      0x00000040U
20304
20305 /*Master Tri-state Enable for pin 39, active high*/
20306 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL
20307 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
20308 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK
20309 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL                                    0xFFFFFFFF
20310 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT                                     7
20311 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK                                      0x00000080U
20312
20313 /*Master Tri-state Enable for pin 40, active high*/
20314 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL
20315 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
20316 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK
20317 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL                                    0xFFFFFFFF
20318 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT                                     8
20319 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK                                      0x00000100U
20320
20321 /*Master Tri-state Enable for pin 41, active high*/
20322 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL
20323 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
20324 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK
20325 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL                                    0xFFFFFFFF
20326 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT                                     9
20327 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK                                      0x00000200U
20328
20329 /*Master Tri-state Enable for pin 42, active high*/
20330 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL
20331 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
20332 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK
20333 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL                                    0xFFFFFFFF
20334 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT                                     10
20335 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK                                      0x00000400U
20336
20337 /*Master Tri-state Enable for pin 43, active high*/
20338 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL
20339 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
20340 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK
20341 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL                                    0xFFFFFFFF
20342 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT                                     11
20343 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK                                      0x00000800U
20344
20345 /*Master Tri-state Enable for pin 44, active high*/
20346 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL
20347 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
20348 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK
20349 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL                                    0xFFFFFFFF
20350 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT                                     12
20351 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK                                      0x00001000U
20352
20353 /*Master Tri-state Enable for pin 45, active high*/
20354 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL
20355 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
20356 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK
20357 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL                                    0xFFFFFFFF
20358 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT                                     13
20359 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK                                      0x00002000U
20360
20361 /*Master Tri-state Enable for pin 46, active high*/
20362 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL
20363 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
20364 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK
20365 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL                                    0xFFFFFFFF
20366 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT                                     14
20367 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK                                      0x00004000U
20368
20369 /*Master Tri-state Enable for pin 47, active high*/
20370 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL
20371 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
20372 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK
20373 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL                                    0xFFFFFFFF
20374 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT                                     15
20375 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK                                      0x00008000U
20376
20377 /*Master Tri-state Enable for pin 48, active high*/
20378 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL
20379 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
20380 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK
20381 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL                                    0xFFFFFFFF
20382 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT                                     16
20383 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK                                      0x00010000U
20384
20385 /*Master Tri-state Enable for pin 49, active high*/
20386 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL
20387 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
20388 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK
20389 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL                                    0xFFFFFFFF
20390 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT                                     17
20391 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK                                      0x00020000U
20392
20393 /*Master Tri-state Enable for pin 50, active high*/
20394 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL
20395 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
20396 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK
20397 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL                                    0xFFFFFFFF
20398 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT                                     18
20399 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK                                      0x00040000U
20400
20401 /*Master Tri-state Enable for pin 51, active high*/
20402 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL
20403 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
20404 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK
20405 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL                                    0xFFFFFFFF
20406 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT                                     19
20407 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK                                      0x00080000U
20408
20409 /*Master Tri-state Enable for pin 52, active high*/
20410 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL
20411 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
20412 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK
20413 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL                                    0xFFFFFFFF
20414 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT                                     20
20415 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK                                      0x00100000U
20416
20417 /*Master Tri-state Enable for pin 53, active high*/
20418 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL
20419 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
20420 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK
20421 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL                                    0xFFFFFFFF
20422 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT                                     21
20423 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK                                      0x00200000U
20424
20425 /*Master Tri-state Enable for pin 54, active high*/
20426 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL
20427 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
20428 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK
20429 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL                                    0xFFFFFFFF
20430 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT                                     22
20431 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK                                      0x00400000U
20432
20433 /*Master Tri-state Enable for pin 55, active high*/
20434 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL
20435 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
20436 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK
20437 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL                                    0xFFFFFFFF
20438 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT                                     23
20439 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK                                      0x00800000U
20440
20441 /*Master Tri-state Enable for pin 56, active high*/
20442 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL
20443 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
20444 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK
20445 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL                                    0xFFFFFFFF
20446 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT                                     24
20447 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK                                      0x01000000U
20448
20449 /*Master Tri-state Enable for pin 57, active high*/
20450 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL
20451 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
20452 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK
20453 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL                                    0xFFFFFFFF
20454 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT                                     25
20455 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK                                      0x02000000U
20456
20457 /*Master Tri-state Enable for pin 58, active high*/
20458 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL
20459 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
20460 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK
20461 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL                                    0xFFFFFFFF
20462 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT                                     26
20463 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK                                      0x04000000U
20464
20465 /*Master Tri-state Enable for pin 59, active high*/
20466 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL
20467 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
20468 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK
20469 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL                                    0xFFFFFFFF
20470 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT                                     27
20471 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK                                      0x08000000U
20472
20473 /*Master Tri-state Enable for pin 60, active high*/
20474 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL
20475 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
20476 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK
20477 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL                                    0xFFFFFFFF
20478 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT                                     28
20479 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK                                      0x10000000U
20480
20481 /*Master Tri-state Enable for pin 61, active high*/
20482 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL
20483 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
20484 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK
20485 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL                                    0xFFFFFFFF
20486 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT                                     29
20487 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK                                      0x20000000U
20488
20489 /*Master Tri-state Enable for pin 62, active high*/
20490 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL
20491 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
20492 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK
20493 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL                                    0xFFFFFFFF
20494 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT                                     30
20495 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK                                      0x40000000U
20496
20497 /*Master Tri-state Enable for pin 63, active high*/
20498 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL
20499 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
20500 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK
20501 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL                                    0xFFFFFFFF
20502 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT                                     31
20503 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK                                      0x80000000U
20504
20505 /*Master Tri-state Enable for pin 64, active high*/
20506 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL
20507 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
20508 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK
20509 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL                                    0x00003FFF
20510 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT                                     0
20511 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK                                      0x00000001U
20512
20513 /*Master Tri-state Enable for pin 65, active high*/
20514 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL
20515 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
20516 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK
20517 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL                                    0x00003FFF
20518 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT                                     1
20519 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK                                      0x00000002U
20520
20521 /*Master Tri-state Enable for pin 66, active high*/
20522 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL
20523 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
20524 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK
20525 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL                                    0x00003FFF
20526 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT                                     2
20527 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK                                      0x00000004U
20528
20529 /*Master Tri-state Enable for pin 67, active high*/
20530 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL
20531 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
20532 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK
20533 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL                                    0x00003FFF
20534 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT                                     3
20535 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK                                      0x00000008U
20536
20537 /*Master Tri-state Enable for pin 68, active high*/
20538 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL
20539 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
20540 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK
20541 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL                                    0x00003FFF
20542 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT                                     4
20543 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK                                      0x00000010U
20544
20545 /*Master Tri-state Enable for pin 69, active high*/
20546 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL
20547 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
20548 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK
20549 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL                                    0x00003FFF
20550 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT                                     5
20551 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK                                      0x00000020U
20552
20553 /*Master Tri-state Enable for pin 70, active high*/
20554 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL
20555 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
20556 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK
20557 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL                                    0x00003FFF
20558 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT                                     6
20559 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK                                      0x00000040U
20560
20561 /*Master Tri-state Enable for pin 71, active high*/
20562 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL
20563 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
20564 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK
20565 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL                                    0x00003FFF
20566 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT                                     7
20567 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK                                      0x00000080U
20568
20569 /*Master Tri-state Enable for pin 72, active high*/
20570 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL
20571 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
20572 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK
20573 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL                                    0x00003FFF
20574 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT                                     8
20575 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK                                      0x00000100U
20576
20577 /*Master Tri-state Enable for pin 73, active high*/
20578 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL
20579 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
20580 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK
20581 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL                                    0x00003FFF
20582 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT                                     9
20583 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK                                      0x00000200U
20584
20585 /*Master Tri-state Enable for pin 74, active high*/
20586 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL
20587 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
20588 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK
20589 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL                                    0x00003FFF
20590 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT                                     10
20591 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK                                      0x00000400U
20592
20593 /*Master Tri-state Enable for pin 75, active high*/
20594 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL
20595 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
20596 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK
20597 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL                                    0x00003FFF
20598 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT                                     11
20599 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK                                      0x00000800U
20600
20601 /*Master Tri-state Enable for pin 76, active high*/
20602 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL
20603 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
20604 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK
20605 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL                                    0x00003FFF
20606 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT                                     12
20607 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK                                      0x00001000U
20608
20609 /*Master Tri-state Enable for pin 77, active high*/
20610 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL
20611 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
20612 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK
20613 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL                                    0x00003FFF
20614 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT                                     13
20615 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK                                      0x00002000U
20616
20617 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20618 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
20619 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
20620 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK
20621 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
20622 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
20623 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
20624
20625 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20626 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
20627 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
20628 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK
20629 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
20630 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
20631 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
20632
20633 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20634 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
20635 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
20636 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK
20637 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
20638 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
20639 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
20640
20641 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20642 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
20643 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
20644 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK
20645 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
20646 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
20647 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
20648
20649 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20650 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
20651 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
20652 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK
20653 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
20654 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
20655 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
20656
20657 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20658 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
20659 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
20660 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK
20661 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
20662 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
20663 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
20664
20665 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20666 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
20667 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
20668 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK
20669 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
20670 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
20671 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
20672
20673 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20674 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
20675 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
20676 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK
20677 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
20678 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
20679 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
20680
20681 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20682 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
20683 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
20684 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK
20685 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
20686 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
20687 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
20688
20689 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20690 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
20691 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
20692 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK
20693 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
20694 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
20695 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
20696
20697 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20698 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
20699 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
20700 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK
20701 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
20702 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
20703 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
20704
20705 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20706 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
20707 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
20708 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK
20709 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
20710 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
20711 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
20712
20713 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20714 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
20715 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
20716 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK
20717 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
20718 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
20719 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
20720
20721 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20722 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
20723 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
20724 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK
20725 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
20726 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
20727 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
20728
20729 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20730 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
20731 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
20732 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK
20733 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
20734 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
20735 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
20736
20737 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20738 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
20739 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
20740 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK
20741 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
20742 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
20743 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
20744
20745 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20746 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
20747 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
20748 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK
20749 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
20750 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
20751 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
20752
20753 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20754 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
20755 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
20756 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK
20757 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
20758 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
20759 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
20760
20761 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20762 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
20763 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
20764 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK
20765 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
20766 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
20767 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
20768
20769 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20770 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
20771 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
20772 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK
20773 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
20774 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
20775 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
20776
20777 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20778 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
20779 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
20780 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK
20781 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
20782 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
20783 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
20784
20785 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20786 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
20787 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
20788 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK
20789 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
20790 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
20791 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
20792
20793 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20794 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
20795 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
20796 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK
20797 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
20798 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
20799 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
20800
20801 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20802 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
20803 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
20804 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK
20805 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
20806 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
20807 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
20808
20809 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20810 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
20811 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
20812 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK
20813 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
20814 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
20815 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
20816
20817 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20818 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
20819 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
20820 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK
20821 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
20822 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
20823 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
20824
20825 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20826 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
20827 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
20828 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK
20829 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
20830 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
20831 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
20832
20833 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20834 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
20835 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
20836 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK
20837 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
20838 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
20839 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
20840
20841 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20842 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
20843 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
20844 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK
20845 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
20846 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
20847 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
20848
20849 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20850 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
20851 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
20852 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK
20853 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
20854 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
20855 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
20856
20857 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20858 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
20859 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
20860 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK
20861 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
20862 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
20863 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
20864
20865 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20866 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
20867 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
20868 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK
20869 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
20870 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
20871 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
20872
20873 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20874 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
20875 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
20876 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK
20877 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
20878 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
20879 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
20880
20881 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20882 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
20883 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
20884 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK
20885 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
20886 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
20887 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
20888
20889 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20890 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
20891 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
20892 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK
20893 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
20894 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
20895 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
20896
20897 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20898 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
20899 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
20900 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK
20901 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
20902 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
20903 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
20904
20905 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20906 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
20907 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
20908 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK
20909 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
20910 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
20911 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
20912
20913 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20914 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
20915 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
20916 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK
20917 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
20918 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
20919 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
20920
20921 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20922 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
20923 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
20924 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK
20925 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
20926 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
20927 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
20928
20929 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20930 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
20931 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
20932 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK
20933 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
20934 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
20935 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
20936
20937 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20938 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
20939 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
20940 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK
20941 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
20942 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
20943 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
20944
20945 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20946 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
20947 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
20948 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK
20949 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
20950 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
20951 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
20952
20953 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20954 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
20955 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
20956 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK
20957 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
20958 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
20959 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
20960
20961 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20962 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
20963 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
20964 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK
20965 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
20966 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
20967 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
20968
20969 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20970 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
20971 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
20972 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK
20973 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
20974 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
20975 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
20976
20977 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20978 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
20979 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
20980 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK
20981 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
20982 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
20983 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
20984
20985 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20986 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
20987 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
20988 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK
20989 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
20990 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
20991 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
20992
20993 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20994 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
20995 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
20996 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK
20997 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
20998 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
20999 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
21000
21001 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21002 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
21003 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
21004 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK
21005 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
21006 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
21007 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
21008
21009 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21010 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
21011 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
21012 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK
21013 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
21014 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
21015 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
21016
21017 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21018 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
21019 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
21020 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK
21021 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
21022 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
21023 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
21024
21025 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21026 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
21027 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
21028 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK
21029 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
21030 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
21031 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
21032
21033 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21034 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
21035 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
21036 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
21037 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
21038 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
21039 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
21040
21041 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21042 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
21043 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
21044 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
21045 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
21046 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
21047 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
21048
21049 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21050 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
21051 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
21052 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
21053 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
21054 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
21055 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
21056
21057 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21058 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
21059 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
21060 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
21061 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
21062 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
21063 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
21064
21065 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21066 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
21067 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
21068 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
21069 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
21070 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
21071 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
21072
21073 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21074 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
21075 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
21076 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
21077 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
21078 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
21079 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
21080
21081 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21082 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
21083 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
21084 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
21085 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
21086 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
21087 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
21088
21089 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21090 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
21091 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
21092 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
21093 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
21094 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
21095 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
21096
21097 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21098 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
21099 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
21100 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
21101 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
21102 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
21103 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
21104
21105 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21106 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
21107 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
21108 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
21109 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
21110 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
21111 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
21112
21113 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21114 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
21115 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
21116 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
21117 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
21118 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
21119 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
21120
21121 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21122 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
21123 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
21124 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
21125 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
21126 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
21127 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
21128
21129 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21130 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
21131 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
21132 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
21133 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
21134 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
21135 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
21136
21137 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21138 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
21139 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
21140 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
21141 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
21142 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
21143 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
21144
21145 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21146 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
21147 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
21148 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
21149 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
21150 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
21151 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
21152
21153 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21154 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
21155 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
21156 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
21157 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
21158 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
21159 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
21160
21161 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21162 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
21163 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
21164 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
21165 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
21166 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
21167 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
21168
21169 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21170 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
21171 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
21172 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
21173 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
21174 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
21175 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
21176
21177 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21178 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
21179 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
21180 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
21181 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
21182 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
21183 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
21184
21185 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21186 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
21187 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
21188 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
21189 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
21190 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
21191 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
21192
21193 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21194 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
21195 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
21196 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
21197 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
21198 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
21199 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
21200
21201 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21202 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
21203 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
21204 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
21205 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
21206 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
21207 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
21208
21209 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21210 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
21211 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
21212 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
21213 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
21214 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
21215 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
21216
21217 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21218 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
21219 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
21220 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
21221 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
21222 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
21223 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
21224
21225 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21226 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
21227 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
21228 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
21229 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
21230 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
21231 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
21232
21233 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21234 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
21235 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
21236 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
21237 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
21238 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
21239 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
21240
21241 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21242 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
21243 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
21244 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
21245 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
21246 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
21247 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
21248
21249 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21250 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
21251 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
21252 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
21253 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
21254 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
21255 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
21256
21257 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21258 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
21259 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
21260 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
21261 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
21262 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
21263 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
21264
21265 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21266 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
21267 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
21268 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
21269 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
21270 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
21271 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
21272
21273 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21274 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
21275 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
21276 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
21277 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
21278 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
21279 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
21280
21281 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21282 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
21283 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
21284 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
21285 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
21286 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
21287 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
21288
21289 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21290 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
21291 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
21292 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
21293 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
21294 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
21295 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
21296
21297 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21298 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
21299 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
21300 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
21301 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
21302 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
21303 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
21304
21305 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21306 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
21307 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
21308 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
21309 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
21310 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
21311 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
21312
21313 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21314 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
21315 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
21316 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
21317 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
21318 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
21319 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
21320
21321 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21322 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
21323 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
21324 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
21325 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
21326 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
21327 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
21328
21329 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21330 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
21331 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
21332 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
21333 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
21334 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
21335 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
21336
21337 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21338 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
21339 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
21340 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
21341 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
21342 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
21343 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
21344
21345 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21346 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
21347 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
21348 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
21349 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
21350 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
21351 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
21352
21353 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21354 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
21355 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
21356 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
21357 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
21358 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
21359 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
21360
21361 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21362 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
21363 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
21364 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
21365 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
21366 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
21367 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
21368
21369 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21370 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
21371 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
21372 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
21373 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
21374 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
21375 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
21376
21377 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21378 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
21379 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
21380 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
21381 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
21382 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
21383 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
21384
21385 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21386 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
21387 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
21388 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
21389 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
21390 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
21391 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
21392
21393 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21394 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
21395 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
21396 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
21397 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
21398 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
21399 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
21400
21401 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21402 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
21403 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
21404 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
21405 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
21406 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
21407 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
21408
21409 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21410 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
21411 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
21412 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
21413 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
21414 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
21415 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
21416
21417 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21418 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
21419 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
21420 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
21421 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
21422 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
21423 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
21424
21425 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21426 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
21427 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
21428 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
21429 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
21430 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
21431 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
21432
21433 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21434 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
21435 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
21436 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
21437 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
21438 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
21439 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
21440
21441 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21442 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
21443 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
21444 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
21445 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
21446 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
21447 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
21448
21449 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21450 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
21451 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
21452 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK
21453 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
21454 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
21455 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
21456
21457 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21458 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
21459 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
21460 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK
21461 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
21462 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
21463 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
21464
21465 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21466 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
21467 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
21468 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK
21469 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
21470 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
21471 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
21472
21473 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21474 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
21475 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
21476 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK
21477 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
21478 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
21479 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
21480
21481 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21482 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
21483 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
21484 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK
21485 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
21486 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
21487 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
21488
21489 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21490 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
21491 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
21492 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK
21493 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
21494 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
21495 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
21496
21497 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21498 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
21499 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
21500 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK
21501 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
21502 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
21503 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
21504
21505 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21506 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
21507 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
21508 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK
21509 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
21510 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
21511 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
21512
21513 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21514 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
21515 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
21516 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK
21517 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
21518 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
21519 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
21520
21521 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21522 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
21523 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
21524 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK
21525 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
21526 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
21527 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
21528
21529 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21530 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
21531 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
21532 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK
21533 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
21534 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
21535 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
21536
21537 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21538 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
21539 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
21540 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK
21541 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
21542 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
21543 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
21544
21545 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21546 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
21547 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
21548 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK
21549 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
21550 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
21551 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
21552
21553 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21554 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
21555 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
21556 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK
21557 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
21558 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
21559 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
21560
21561 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21562 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
21563 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
21564 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK
21565 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
21566 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
21567 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
21568
21569 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21570 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
21571 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
21572 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK
21573 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
21574 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
21575 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
21576
21577 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21578 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
21579 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
21580 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK
21581 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
21582 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
21583 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
21584
21585 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21586 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
21587 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
21588 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK
21589 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
21590 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
21591 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
21592
21593 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21594 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
21595 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
21596 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK
21597 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
21598 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
21599 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
21600
21601 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21602 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
21603 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
21604 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK
21605 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
21606 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
21607 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
21608
21609 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21610 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
21611 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
21612 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK
21613 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
21614 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
21615 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
21616
21617 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21618 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
21619 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
21620 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK
21621 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
21622 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
21623 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
21624
21625 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21626 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
21627 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
21628 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK
21629 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
21630 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
21631 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
21632
21633 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21634 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
21635 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
21636 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK
21637 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
21638 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
21639 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
21640
21641 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21642 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
21643 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
21644 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK
21645 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
21646 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
21647 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
21648
21649 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21650 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
21651 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
21652 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK
21653 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
21654 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
21655 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
21656
21657 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21658 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
21659 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
21660 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
21661 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
21662 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
21663 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
21664
21665 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21666 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
21667 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
21668 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
21669 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
21670 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
21671 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
21672
21673 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21674 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
21675 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
21676 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
21677 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
21678 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
21679 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
21680
21681 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21682 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
21683 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
21684 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
21685 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
21686 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
21687 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
21688
21689 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21690 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
21691 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
21692 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
21693 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
21694 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
21695 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
21696
21697 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21698 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
21699 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
21700 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
21701 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
21702 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
21703 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
21704
21705 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21706 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
21707 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
21708 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
21709 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
21710 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
21711 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
21712
21713 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21714 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
21715 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
21716 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
21717 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
21718 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
21719 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
21720
21721 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21722 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
21723 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
21724 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
21725 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
21726 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
21727 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
21728
21729 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21730 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
21731 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
21732 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
21733 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
21734 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
21735 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
21736
21737 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21738 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
21739 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
21740 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
21741 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
21742 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
21743 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
21744
21745 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21746 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
21747 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
21748 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
21749 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
21750 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
21751 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
21752
21753 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21754 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
21755 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
21756 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
21757 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
21758 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
21759 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
21760
21761 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21762 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
21763 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
21764 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
21765 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
21766 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
21767 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
21768
21769 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21770 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
21771 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
21772 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
21773 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
21774 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
21775 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
21776
21777 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21778 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
21779 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
21780 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
21781 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
21782 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
21783 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
21784
21785 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21786 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
21787 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
21788 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
21789 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
21790 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
21791 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
21792
21793 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21794 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
21795 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
21796 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
21797 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
21798 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
21799 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
21800
21801 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21802 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
21803 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
21804 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
21805 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
21806 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
21807 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
21808
21809 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21810 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
21811 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
21812 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
21813 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
21814 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
21815 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
21816
21817 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21818 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
21819 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
21820 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
21821 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
21822 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
21823 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
21824
21825 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21826 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
21827 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
21828 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
21829 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
21830 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
21831 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
21832
21833 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21834 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
21835 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
21836 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
21837 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
21838 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
21839 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
21840
21841 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21842 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
21843 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
21844 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
21845 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
21846 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
21847 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
21848
21849 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21850 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
21851 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
21852 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
21853 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
21854 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
21855 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
21856
21857 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21858 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
21859 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
21860 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
21861 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
21862 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
21863 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
21864
21865 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21866 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
21867 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
21868 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK
21869 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
21870 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
21871 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
21872
21873 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21874 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
21875 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
21876 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK
21877 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
21878 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
21879 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
21880
21881 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21882 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
21883 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
21884 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK
21885 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
21886 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
21887 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
21888
21889 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21890 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
21891 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
21892 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK
21893 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
21894 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
21895 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
21896
21897 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21898 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
21899 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
21900 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK
21901 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
21902 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
21903 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
21904
21905 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21906 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
21907 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
21908 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK
21909 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
21910 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
21911 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
21912
21913 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21914 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
21915 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
21916 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK
21917 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
21918 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
21919 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
21920
21921 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21922 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
21923 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
21924 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK
21925 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
21926 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
21927 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
21928
21929 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21930 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
21931 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
21932 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK
21933 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
21934 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
21935 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
21936
21937 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21938 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
21939 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
21940 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK
21941 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
21942 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
21943 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
21944
21945 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21946 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
21947 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
21948 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK
21949 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
21950 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
21951 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
21952
21953 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21954 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
21955 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
21956 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK
21957 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
21958 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
21959 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
21960
21961 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21962 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
21963 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
21964 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK
21965 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
21966 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
21967 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
21968
21969 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21970 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
21971 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
21972 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK
21973 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
21974 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
21975 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
21976
21977 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21978 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
21979 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
21980 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK
21981 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
21982 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
21983 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
21984
21985 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21986 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
21987 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
21988 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK
21989 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
21990 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
21991 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
21992
21993 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21994 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
21995 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
21996 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK
21997 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
21998 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
21999 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
22000
22001 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22002 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
22003 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
22004 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK
22005 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
22006 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
22007 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
22008
22009 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22010 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
22011 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
22012 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK
22013 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
22014 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
22015 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
22016
22017 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22018 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
22019 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
22020 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK
22021 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
22022 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
22023 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
22024
22025 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22026 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
22027 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
22028 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK
22029 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
22030 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
22031 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
22032
22033 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22034 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
22035 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
22036 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK
22037 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
22038 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
22039 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
22040
22041 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22042 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
22043 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
22044 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK
22045 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
22046 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
22047 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
22048
22049 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22050 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
22051 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
22052 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK
22053 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
22054 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
22055 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
22056
22057 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22058 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
22059 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
22060 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK
22061 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
22062 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
22063 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
22064
22065 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22066 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
22067 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
22068 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK
22069 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
22070 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
22071 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
22072
22073 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22074 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
22075 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
22076 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK
22077 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
22078 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
22079 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
22080
22081 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22082 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
22083 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
22084 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK
22085 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
22086 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
22087 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
22088
22089 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22090 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
22091 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
22092 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK
22093 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
22094 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
22095 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
22096
22097 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22098 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
22099 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
22100 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK
22101 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
22102 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
22103 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
22104
22105 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22106 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
22107 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
22108 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK
22109 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
22110 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
22111 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
22112
22113 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22114 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
22115 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
22116 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK
22117 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
22118 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
22119 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
22120
22121 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22122 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
22123 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
22124 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK
22125 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
22126 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
22127 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
22128
22129 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22130 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
22131 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
22132 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK
22133 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
22134 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
22135 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
22136
22137 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22138 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
22139 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
22140 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK
22141 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
22142 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
22143 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
22144
22145 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22146 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
22147 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
22148 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK
22149 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
22150 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
22151 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
22152
22153 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22154 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
22155 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
22156 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK
22157 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
22158 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
22159 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
22160
22161 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22162 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
22163 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
22164 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK
22165 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
22166 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
22167 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
22168
22169 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22170 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
22171 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
22172 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK
22173 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
22174 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
22175 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
22176
22177 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22178 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
22179 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
22180 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK
22181 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
22182 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
22183 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
22184
22185 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22186 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
22187 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
22188 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK
22189 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
22190 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
22191 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
22192
22193 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22194 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
22195 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
22196 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK
22197 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
22198 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
22199 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
22200
22201 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22202 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
22203 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
22204 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK
22205 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
22206 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
22207 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
22208
22209 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22210 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
22211 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
22212 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK
22213 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
22214 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
22215 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
22216
22217 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22218 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
22219 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
22220 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK
22221 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
22222 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
22223 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
22224
22225 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22226 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
22227 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
22228 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK
22229 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
22230 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
22231 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
22232
22233 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22234 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
22235 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
22236 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK
22237 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
22238 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
22239 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
22240
22241 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22242 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
22243 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
22244 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK
22245 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
22246 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
22247 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
22248
22249 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22250 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
22251 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
22252 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK
22253 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
22254 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
22255 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
22256
22257 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22258 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
22259 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
22260 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK
22261 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
22262 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
22263 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
22264
22265 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22266 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
22267 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
22268 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK
22269 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
22270 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
22271 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
22272
22273 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22274 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
22275 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
22276 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK
22277 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
22278 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
22279 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
22280
22281 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22282 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
22283 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
22284 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
22285 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
22286 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
22287 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
22288
22289 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22290 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
22291 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
22292 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
22293 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
22294 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
22295 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
22296
22297 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22298 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
22299 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
22300 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
22301 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
22302 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
22303 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
22304
22305 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22306 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
22307 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
22308 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
22309 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
22310 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
22311 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
22312
22313 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22314 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
22315 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
22316 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
22317 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
22318 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
22319 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
22320
22321 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22322 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
22323 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
22324 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
22325 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
22326 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
22327 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
22328
22329 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22330 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
22331 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
22332 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
22333 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
22334 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
22335 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
22336
22337 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22338 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
22339 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
22340 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
22341 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
22342 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
22343 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
22344
22345 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22346 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
22347 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
22348 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
22349 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
22350 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
22351 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
22352
22353 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22354 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
22355 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
22356 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
22357 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
22358 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
22359 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
22360
22361 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22362 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
22363 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
22364 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
22365 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
22366 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
22367 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
22368
22369 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22370 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
22371 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
22372 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
22373 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
22374 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
22375 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
22376
22377 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22378 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
22379 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
22380 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
22381 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
22382 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
22383 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
22384
22385 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22386 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
22387 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
22388 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
22389 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
22390 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
22391 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
22392
22393 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22394 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
22395 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
22396 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
22397 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
22398 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
22399 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
22400
22401 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22402 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
22403 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
22404 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
22405 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
22406 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
22407 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
22408
22409 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22410 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
22411 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
22412 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
22413 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
22414 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
22415 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
22416
22417 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22418 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
22419 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
22420 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
22421 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
22422 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
22423 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
22424
22425 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22426 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
22427 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
22428 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
22429 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
22430 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
22431 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
22432
22433 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22434 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
22435 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
22436 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
22437 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
22438 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
22439 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
22440
22441 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22442 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
22443 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
22444 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
22445 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
22446 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
22447 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
22448
22449 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22450 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
22451 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
22452 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
22453 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
22454 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
22455 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
22456
22457 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22458 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
22459 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
22460 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
22461 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
22462 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
22463 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
22464
22465 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22466 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
22467 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
22468 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
22469 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
22470 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
22471 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
22472
22473 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22474 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
22475 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
22476 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
22477 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
22478 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
22479 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
22480
22481 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22482 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
22483 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
22484 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
22485 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
22486 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
22487 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
22488
22489 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22490 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
22491 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
22492 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
22493 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
22494 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
22495 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
22496
22497 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22498 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
22499 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
22500 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
22501 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
22502 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
22503 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
22504
22505 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22506 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
22507 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
22508 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
22509 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
22510 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
22511 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
22512
22513 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22514 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
22515 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
22516 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
22517 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
22518 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
22519 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
22520
22521 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22522 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
22523 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
22524 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
22525 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
22526 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
22527 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
22528
22529 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22530 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
22531 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
22532 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
22533 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
22534 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
22535 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
22536
22537 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22538 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
22539 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
22540 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
22541 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
22542 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
22543 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
22544
22545 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22546 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
22547 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
22548 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
22549 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
22550 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
22551 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
22552
22553 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22554 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
22555 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
22556 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
22557 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
22558 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
22559 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
22560
22561 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22562 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
22563 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
22564 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
22565 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
22566 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
22567 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
22568
22569 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22570 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
22571 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
22572 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
22573 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
22574 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
22575 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
22576
22577 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22578 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
22579 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
22580 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
22581 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
22582 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
22583 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
22584
22585 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22586 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
22587 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
22588 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
22589 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
22590 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
22591 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
22592
22593 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22594 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
22595 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
22596 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
22597 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
22598 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
22599 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
22600
22601 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22602 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
22603 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
22604 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
22605 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
22606 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
22607 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
22608
22609 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22610 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
22611 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
22612 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
22613 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
22614 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
22615 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
22616
22617 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22618 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
22619 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
22620 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
22621 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
22622 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
22623 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
22624
22625 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22626 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
22627 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
22628 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
22629 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
22630 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
22631 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
22632
22633 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22634 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
22635 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
22636 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
22637 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
22638 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
22639 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
22640
22641 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22642 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
22643 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
22644 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
22645 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
22646 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
22647 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
22648
22649 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22650 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
22651 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
22652 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
22653 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
22654 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
22655 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
22656
22657 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22658 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
22659 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
22660 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
22661 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
22662 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
22663 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
22664
22665 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22666 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
22667 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
22668 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
22669 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
22670 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
22671 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
22672
22673 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22674 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
22675 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
22676 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
22677 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
22678 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
22679 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
22680
22681 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22682 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
22683 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
22684 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
22685 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
22686 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
22687 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
22688
22689 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22690 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
22691 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
22692 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
22693 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
22694 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
22695 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
22696
22697 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22698 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
22699 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
22700 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK
22701 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
22702 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               12
22703 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00001000U
22704
22705 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22706 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
22707 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
22708 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK
22709 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
22710 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               13
22711 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00002000U
22712
22713 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22714 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
22715 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
22716 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK
22717 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
22718 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               14
22719 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00004000U
22720
22721 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22722 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
22723 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
22724 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK
22725 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
22726 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               15
22727 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00008000U
22728
22729 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22730 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
22731 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
22732 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK
22733 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
22734 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               16
22735 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00010000U
22736
22737 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22738 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
22739 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
22740 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK
22741 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
22742 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               17
22743 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00020000U
22744
22745 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22746 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
22747 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
22748 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK
22749 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
22750 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               18
22751 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00040000U
22752
22753 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22754 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
22755 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
22756 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK
22757 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
22758 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               19
22759 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00080000U
22760
22761 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22762 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
22763 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
22764 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK
22765 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
22766 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               20
22767 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00100000U
22768
22769 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22770 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
22771 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
22772 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK
22773 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
22774 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               21
22775 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00200000U
22776
22777 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22778 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
22779 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
22780 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK
22781 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
22782 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              22
22783 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00400000U
22784
22785 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22786 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
22787 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
22788 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK
22789 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
22790 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              23
22791 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00800000U
22792
22793 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22794 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
22795 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
22796 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK
22797 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
22798 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              24
22799 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x01000000U
22800
22801 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22802 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
22803 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
22804 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK
22805 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
22806 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              25
22807 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x02000000U
22808
22809 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22810 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
22811 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
22812 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK
22813 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
22814 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              0
22815 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00000001U
22816
22817 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22818 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
22819 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
22820 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK
22821 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
22822 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              1
22823 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00000002U
22824
22825 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22826 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
22827 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
22828 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK
22829 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
22830 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              2
22831 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00000004U
22832
22833 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22834 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
22835 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
22836 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK
22837 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
22838 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              3
22839 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00000008U
22840
22841 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22842 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
22843 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
22844 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK
22845 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
22846 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              4
22847 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00000010U
22848
22849 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22850 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
22851 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
22852 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK
22853 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
22854 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              5
22855 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00000020U
22856
22857 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22858 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
22859 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
22860 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK
22861 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
22862 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              6
22863 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00000040U
22864
22865 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22866 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
22867 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
22868 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK
22869 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
22870 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              7
22871 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00000080U
22872
22873 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22874 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
22875 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
22876 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK
22877 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
22878 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              8
22879 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00000100U
22880
22881 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22882 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
22883 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
22884 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK
22885 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
22886 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              9
22887 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00000200U
22888
22889 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22890 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
22891 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
22892 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK
22893 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
22894 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              10
22895 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x00000400U
22896
22897 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22898 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
22899 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
22900 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK
22901 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
22902 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              11
22903 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x00000800U
22904
22905 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22906 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
22907 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
22908 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
22909 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
22910 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
22911 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
22912
22913 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22914 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
22915 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
22916 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
22917 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
22918 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
22919 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
22920
22921 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22922 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
22923 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
22924 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
22925 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
22926 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
22927 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
22928
22929 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22930 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
22931 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
22932 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
22933 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
22934 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
22935 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
22936
22937 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22938 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
22939 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
22940 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
22941 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
22942 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
22943 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
22944
22945 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22946 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
22947 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
22948 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
22949 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
22950 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
22951 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
22952
22953 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22954 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
22955 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
22956 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
22957 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
22958 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
22959 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
22960
22961 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22962 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
22963 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
22964 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
22965 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
22966 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
22967 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
22968
22969 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22970 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
22971 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
22972 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
22973 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
22974 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
22975 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
22976
22977 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22978 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
22979 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
22980 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
22981 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
22982 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
22983 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
22984
22985 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22986 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
22987 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
22988 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
22989 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
22990 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
22991 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
22992
22993 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22994 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
22995 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
22996 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
22997 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
22998 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
22999 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
23000
23001 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23002 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
23003 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
23004 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
23005 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
23006 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
23007 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
23008
23009 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23010 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
23011 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
23012 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
23013 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
23014 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
23015 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
23016
23017 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23018 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
23019 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
23020 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
23021 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
23022 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
23023 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
23024
23025 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23026 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
23027 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
23028 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
23029 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
23030 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
23031 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
23032
23033 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23034 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
23035 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
23036 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
23037 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
23038 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
23039 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
23040
23041 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23042 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
23043 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
23044 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
23045 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
23046 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
23047 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
23048
23049 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23050 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
23051 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
23052 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
23053 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
23054 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
23055 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
23056
23057 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23058 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
23059 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
23060 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
23061 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
23062 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
23063 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
23064
23065 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23066 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
23067 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
23068 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
23069 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
23070 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
23071 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
23072
23073 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23074 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
23075 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
23076 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
23077 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
23078 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
23079 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
23080
23081 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23082 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
23083 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
23084 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
23085 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
23086 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
23087 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
23088
23089 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23090 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
23091 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
23092 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
23093 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
23094 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
23095 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
23096
23097 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23098 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
23099 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
23100 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
23101 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
23102 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
23103 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
23104
23105 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23106 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
23107 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
23108 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
23109 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
23110 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
23111 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
23112
23113 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23114 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
23115 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
23116 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK
23117 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
23118 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
23119 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
23120
23121 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23122 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
23123 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
23124 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK
23125 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
23126 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
23127 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
23128
23129 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23130 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
23131 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
23132 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK
23133 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
23134 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
23135 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
23136
23137 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23138 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
23139 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
23140 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK
23141 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
23142 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
23143 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
23144
23145 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23146 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
23147 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
23148 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK
23149 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
23150 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
23151 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
23152
23153 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23154 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
23155 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
23156 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK
23157 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
23158 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
23159 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
23160
23161 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23162 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
23163 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
23164 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK
23165 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
23166 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
23167 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
23168
23169 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23170 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
23171 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
23172 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK
23173 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
23174 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
23175 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
23176
23177 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23178 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
23179 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
23180 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK
23181 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
23182 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
23183 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
23184
23185 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23186 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
23187 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
23188 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK
23189 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
23190 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
23191 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
23192
23193 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23194 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
23195 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
23196 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK
23197 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
23198 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
23199 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
23200
23201 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23202 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
23203 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
23204 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK
23205 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
23206 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
23207 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
23208
23209 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23210 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
23211 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
23212 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK
23213 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
23214 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
23215 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
23216
23217 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23218 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
23219 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
23220 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK
23221 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
23222 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
23223 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
23224
23225 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23226 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
23227 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
23228 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK
23229 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
23230 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
23231 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
23232
23233 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23234 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
23235 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
23236 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK
23237 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
23238 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
23239 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
23240
23241 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23242 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
23243 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
23244 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK
23245 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
23246 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
23247 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
23248
23249 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23250 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
23251 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
23252 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK
23253 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
23254 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
23255 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
23256
23257 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23258 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
23259 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
23260 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK
23261 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
23262 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
23263 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
23264
23265 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23266 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
23267 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
23268 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK
23269 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
23270 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
23271 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
23272
23273 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23274 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
23275 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
23276 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK
23277 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
23278 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
23279 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
23280
23281 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23282 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
23283 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
23284 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK
23285 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
23286 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
23287 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
23288
23289 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23290 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
23291 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
23292 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK
23293 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
23294 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
23295 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
23296
23297 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23298 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
23299 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
23300 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK
23301 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
23302 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
23303 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
23304
23305 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23306 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
23307 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
23308 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK
23309 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
23310 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
23311 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
23312
23313 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23314 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
23315 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
23316 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK
23317 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
23318 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
23319 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
23320
23321 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23322 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
23323 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
23324 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK
23325 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
23326 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
23327 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
23328
23329 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23330 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
23331 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
23332 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK
23333 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
23334 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
23335 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
23336
23337 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23338 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
23339 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
23340 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK
23341 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
23342 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
23343 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
23344
23345 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23346 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
23347 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
23348 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK
23349 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
23350 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
23351 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
23352
23353 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23354 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
23355 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
23356 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK
23357 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
23358 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
23359 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
23360
23361 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23362 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
23363 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
23364 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK
23365 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
23366 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
23367 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
23368
23369 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23370 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
23371 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
23372 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK
23373 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
23374 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
23375 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
23376
23377 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23378 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
23379 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
23380 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK
23381 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
23382 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
23383 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
23384
23385 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23386 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
23387 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
23388 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK
23389 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
23390 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
23391 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
23392
23393 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23394 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
23395 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
23396 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK
23397 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
23398 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
23399 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
23400
23401 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23402 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
23403 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
23404 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK
23405 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
23406 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
23407 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
23408
23409 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23410 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
23411 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
23412 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK
23413 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
23414 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
23415 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
23416
23417 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23418 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
23419 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
23420 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK
23421 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
23422 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
23423 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
23424
23425 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23426 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
23427 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
23428 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK
23429 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
23430 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
23431 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
23432
23433 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23434 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
23435 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
23436 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK
23437 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
23438 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
23439 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
23440
23441 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23442 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
23443 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
23444 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK
23445 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
23446 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
23447 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
23448
23449 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23450 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
23451 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
23452 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK
23453 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
23454 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
23455 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
23456
23457 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23458 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
23459 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
23460 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK
23461 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
23462 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
23463 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
23464
23465 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23466 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
23467 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
23468 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK
23469 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
23470 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
23471 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
23472
23473 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23474 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
23475 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
23476 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK
23477 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
23478 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
23479 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
23480
23481 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23482 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
23483 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
23484 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK
23485 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
23486 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
23487 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
23488
23489 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23490 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
23491 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
23492 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK
23493 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
23494 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
23495 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
23496
23497 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23498 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
23499 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
23500 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK
23501 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
23502 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
23503 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
23504
23505 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23506 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
23507 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
23508 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK
23509 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
23510 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
23511 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
23512
23513 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23514 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
23515 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
23516 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK
23517 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
23518 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
23519 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
23520
23521 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23522 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
23523 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
23524 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK
23525 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
23526 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
23527 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
23528
23529 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23530 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
23531 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
23532 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
23533 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
23534 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
23535 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
23536
23537 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23538 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
23539 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
23540 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
23541 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
23542 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
23543 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
23544
23545 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23546 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
23547 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
23548 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
23549 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
23550 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
23551 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
23552
23553 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23554 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
23555 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
23556 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
23557 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
23558 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
23559 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
23560
23561 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23562 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
23563 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
23564 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
23565 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
23566 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
23567 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
23568
23569 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23570 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
23571 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
23572 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
23573 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
23574 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
23575 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
23576
23577 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23578 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
23579 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
23580 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
23581 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
23582 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
23583 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
23584
23585 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23586 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
23587 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
23588 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
23589 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
23590 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
23591 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
23592
23593 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23594 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
23595 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
23596 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
23597 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
23598 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
23599 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
23600
23601 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23602 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
23603 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
23604 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
23605 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
23606 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
23607 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
23608
23609 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23610 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
23611 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
23612 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
23613 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
23614 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
23615 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
23616
23617 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23618 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
23619 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
23620 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
23621 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
23622 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
23623 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
23624
23625 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23626 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
23627 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
23628 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
23629 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
23630 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
23631 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
23632
23633 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23634 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
23635 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
23636 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
23637 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
23638 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
23639 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
23640
23641 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23642 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
23643 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
23644 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
23645 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
23646 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
23647 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
23648
23649 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23650 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
23651 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
23652 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
23653 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
23654 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
23655 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
23656
23657 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23658 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
23659 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
23660 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
23661 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
23662 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
23663 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
23664
23665 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23666 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
23667 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
23668 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
23669 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
23670 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
23671 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
23672
23673 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23674 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
23675 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
23676 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
23677 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
23678 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
23679 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
23680
23681 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23682 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
23683 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
23684 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
23685 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
23686 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
23687 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
23688
23689 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23690 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
23691 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
23692 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
23693 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
23694 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
23695 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
23696
23697 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23698 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
23699 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
23700 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
23701 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
23702 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
23703 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
23704
23705 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23706 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
23707 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
23708 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
23709 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
23710 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
23711 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
23712
23713 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23714 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
23715 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
23716 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
23717 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
23718 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
23719 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
23720
23721 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23722 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
23723 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
23724 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
23725 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
23726 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
23727 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
23728
23729 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23730 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
23731 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
23732 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
23733 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
23734 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
23735 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
23736
23737 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23738 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
23739 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
23740 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
23741 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
23742 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
23743 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
23744
23745 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23746 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
23747 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
23748 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
23749 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
23750 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
23751 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
23752
23753 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23754 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
23755 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
23756 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
23757 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
23758 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
23759 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
23760
23761 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23762 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
23763 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
23764 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
23765 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
23766 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
23767 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
23768
23769 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23770 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
23771 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
23772 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
23773 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
23774 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
23775 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
23776
23777 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23778 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
23779 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
23780 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
23781 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
23782 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
23783 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
23784
23785 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23786 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
23787 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
23788 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
23789 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
23790 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
23791 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
23792
23793 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23794 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
23795 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
23796 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
23797 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
23798 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
23799 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
23800
23801 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23802 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
23803 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
23804 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
23805 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
23806 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
23807 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
23808
23809 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23810 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
23811 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
23812 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
23813 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
23814 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
23815 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
23816
23817 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23818 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
23819 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
23820 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
23821 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
23822 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
23823 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
23824
23825 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23826 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
23827 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
23828 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
23829 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
23830 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
23831 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
23832
23833 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23834 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
23835 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
23836 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
23837 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
23838 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
23839 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
23840
23841 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23842 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
23843 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
23844 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
23845 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
23846 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
23847 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
23848
23849 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23850 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
23851 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
23852 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
23853 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
23854 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
23855 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
23856
23857 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23858 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
23859 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
23860 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
23861 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
23862 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
23863 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
23864
23865 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23866 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
23867 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
23868 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
23869 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
23870 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
23871 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
23872
23873 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23874 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
23875 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
23876 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
23877 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
23878 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
23879 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
23880
23881 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23882 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
23883 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
23884 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
23885 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
23886 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
23887 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
23888
23889 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23890 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
23891 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
23892 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
23893 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
23894 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
23895 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
23896
23897 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23898 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
23899 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
23900 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
23901 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
23902 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
23903 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
23904
23905 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23906 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
23907 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
23908 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
23909 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
23910 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
23911 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
23912
23913 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23914 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
23915 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
23916 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
23917 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
23918 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
23919 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
23920
23921 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23922 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
23923 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
23924 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
23925 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
23926 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
23927 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
23928
23929 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23930 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
23931 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
23932 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
23933 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
23934 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
23935 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
23936
23937 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23938 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
23939 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
23940 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
23941 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
23942 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
23943 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
23944
23945 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23946 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
23947 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
23948 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK
23949 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
23950 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
23951 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
23952
23953 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23954 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
23955 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
23956 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK
23957 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
23958 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
23959 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
23960
23961 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23962 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
23963 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
23964 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK
23965 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
23966 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
23967 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
23968
23969 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23970 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
23971 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
23972 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK
23973 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
23974 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
23975 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
23976
23977 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23978 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
23979 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
23980 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK
23981 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
23982 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
23983 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
23984
23985 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23986 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
23987 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
23988 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK
23989 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
23990 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
23991 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
23992
23993 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23994 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
23995 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
23996 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK
23997 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
23998 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
23999 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
24000
24001 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24002 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
24003 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
24004 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK
24005 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
24006 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
24007 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
24008
24009 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24010 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
24011 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
24012 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK
24013 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
24014 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
24015 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
24016
24017 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24018 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
24019 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
24020 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK
24021 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
24022 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
24023 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
24024
24025 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24026 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
24027 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
24028 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK
24029 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
24030 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
24031 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
24032
24033 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24034 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
24035 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
24036 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK
24037 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
24038 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
24039 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
24040
24041 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24042 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
24043 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
24044 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK
24045 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
24046 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
24047 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
24048
24049 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24050 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
24051 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
24052 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK
24053 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
24054 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
24055 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
24056
24057 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24058 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
24059 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
24060 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK
24061 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
24062 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
24063 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
24064
24065 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24066 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
24067 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
24068 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK
24069 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
24070 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
24071 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
24072
24073 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24074 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
24075 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
24076 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK
24077 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
24078 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
24079 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
24080
24081 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24082 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
24083 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
24084 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK
24085 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
24086 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
24087 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
24088
24089 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24090 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
24091 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
24092 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK
24093 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
24094 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
24095 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
24096
24097 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24098 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
24099 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
24100 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK
24101 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
24102 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
24103 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
24104
24105 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24106 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
24107 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
24108 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK
24109 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
24110 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
24111 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
24112
24113 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24114 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
24115 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
24116 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK
24117 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
24118 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
24119 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
24120
24121 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24122 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
24123 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
24124 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK
24125 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
24126 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
24127 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
24128
24129 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24130 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
24131 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
24132 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK
24133 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
24134 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
24135 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
24136
24137 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24138 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
24139 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
24140 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK
24141 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
24142 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
24143 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
24144
24145 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24146 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
24147 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
24148 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK
24149 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
24150 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
24151 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
24152
24153 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24154 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
24155 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
24156 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
24157 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
24158 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
24159 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
24160
24161 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24162 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
24163 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
24164 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
24165 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
24166 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
24167 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
24168
24169 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24170 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
24171 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
24172 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
24173 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
24174 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
24175 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
24176
24177 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24178 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
24179 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
24180 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
24181 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
24182 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
24183 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
24184
24185 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24186 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
24187 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
24188 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
24189 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
24190 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
24191 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
24192
24193 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24194 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
24195 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
24196 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
24197 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
24198 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
24199 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
24200
24201 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24202 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
24203 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
24204 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
24205 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
24206 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
24207 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
24208
24209 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24210 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
24211 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
24212 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
24213 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
24214 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
24215 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
24216
24217 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24218 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
24219 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
24220 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
24221 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
24222 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
24223 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
24224
24225 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24226 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
24227 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
24228 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
24229 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
24230 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
24231 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
24232
24233 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24234 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
24235 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
24236 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
24237 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
24238 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
24239 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
24240
24241 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24242 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
24243 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
24244 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
24245 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
24246 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
24247 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
24248
24249 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24250 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
24251 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
24252 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
24253 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
24254 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
24255 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
24256
24257 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24258 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
24259 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
24260 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
24261 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
24262 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
24263 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
24264
24265 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24266 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
24267 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
24268 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
24269 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
24270 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
24271 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
24272
24273 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24274 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
24275 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
24276 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
24277 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
24278 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
24279 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
24280
24281 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24282 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
24283 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
24284 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
24285 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
24286 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
24287 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
24288
24289 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24290 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
24291 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
24292 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
24293 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
24294 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
24295 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
24296
24297 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24298 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
24299 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
24300 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
24301 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
24302 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
24303 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
24304
24305 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24306 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
24307 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
24308 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
24309 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
24310 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
24311 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
24312
24313 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24314 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
24315 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
24316 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
24317 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
24318 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
24319 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
24320
24321 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24322 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
24323 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
24324 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
24325 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
24326 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
24327 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
24328
24329 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24330 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
24331 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
24332 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
24333 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
24334 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
24335 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
24336
24337 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24338 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
24339 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
24340 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
24341 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
24342 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
24343 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
24344
24345 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24346 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
24347 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
24348 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
24349 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
24350 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
24351 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
24352
24353 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24354 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
24355 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
24356 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
24357 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
24358 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
24359 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
24360
24361 /*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
24362                 ts to I2C 0 inputs.*/
24363 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL
24364 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
24365 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK
24366 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL                                0x00000000
24367 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT                                 3
24368 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK                                  0x00000008U
24369
24370 /*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
24371                 .*/
24372 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL
24373 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
24374 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK
24375 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL                                0x00000000
24376 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT                                 2
24377 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK                                  0x00000004U
24378
24379 /*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
24380                 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/
24381 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL
24382 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
24383 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK
24384 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL                                  0x00000000
24385 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT                                   1
24386 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK                                    0x00000002U
24387
24388 /*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
24389                 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/
24390 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL
24391 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
24392 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK
24393 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL                                0x00000000
24394 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT                                 0
24395 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK                                  0x00000001U
24396 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24397 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
24398 #undef CRL_APB_RST_LPD_IOU0_OFFSET
24399 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
24400 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24401 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
24402 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET
24403 #define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET                                          0XFF180390
24404 #undef CRL_APB_RST_LPD_TOP_OFFSET
24405 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
24406 #undef CRF_APB_RST_FPD_TOP_OFFSET
24407 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
24408 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24409 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
24410 #undef IOU_SLCR_CTRL_REG_SD_OFFSET
24411 #define IOU_SLCR_CTRL_REG_SD_OFFSET                                                0XFF180310
24412 #undef IOU_SLCR_SD_CONFIG_REG2_OFFSET
24413 #define IOU_SLCR_SD_CONFIG_REG2_OFFSET                                             0XFF180320
24414 #undef IOU_SLCR_SD_CONFIG_REG1_OFFSET
24415 #define IOU_SLCR_SD_CONFIG_REG1_OFFSET                                             0XFF18031C
24416 #undef IOU_SLCR_SD_CONFIG_REG3_OFFSET
24417 #define IOU_SLCR_SD_CONFIG_REG3_OFFSET                                             0XFF180324
24418 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24419 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
24420 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24421 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
24422 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24423 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
24424 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24425 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
24426 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24427 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
24428 #undef TPIU_LAR_OFFSET
24429 #define TPIU_LAR_OFFSET                                                            0XFE980FB0
24430 #undef TPIU_CURRENT_PORT_SIZE_OFFSET
24431 #define TPIU_CURRENT_PORT_SIZE_OFFSET                                              0XFE980004
24432 #undef TPIU_LAR_OFFSET
24433 #define TPIU_LAR_OFFSET                                                            0XFE980FB0
24434 #undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET
24435 #define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF000034
24436 #undef UART0_BAUD_RATE_GEN_REG0_OFFSET
24437 #define UART0_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF000018
24438 #undef UART0_CONTROL_REG0_OFFSET
24439 #define UART0_CONTROL_REG0_OFFSET                                                  0XFF000000
24440 #undef UART0_MODE_REG0_OFFSET
24441 #define UART0_MODE_REG0_OFFSET                                                     0XFF000004
24442 #undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET
24443 #define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF010034
24444 #undef UART1_BAUD_RATE_GEN_REG0_OFFSET
24445 #define UART1_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF010018
24446 #undef UART1_CONTROL_REG0_OFFSET
24447 #define UART1_CONTROL_REG0_OFFSET                                                  0XFF010000
24448 #undef UART1_MODE_REG0_OFFSET
24449 #define UART1_MODE_REG0_OFFSET                                                     0XFF010004
24450 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET
24451 #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
24452 #undef CSU_TAMPER_STATUS_OFFSET
24453 #define CSU_TAMPER_STATUS_OFFSET                                                   0XFFCA5000
24454 #undef APU_ACE_CTRL_OFFSET
24455 #define APU_ACE_CTRL_OFFSET                                                        0XFD5C0060
24456 #undef RTC_CONTROL_OFFSET
24457 #define RTC_CONTROL_OFFSET                                                         0XFFA60040
24458 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET
24459 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET                               0XFF260020
24460 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET
24461 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET                                 0XFF260000
24462
24463 /*Block level reset*/
24464 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL
24465 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
24466 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK
24467 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL                                0x0017FFFF
24468 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT                                 20
24469 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK                                  0x00100000U
24470
24471 /*GEM 3 reset*/
24472 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
24473 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
24474 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
24475 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
24476 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
24477 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
24478
24479 /*Block level reset*/
24480 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL
24481 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
24482 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK
24483 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL                                     0x0017FFFF
24484 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT                                      0
24485 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK                                       0x00000001U
24486
24487 /*0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI*/
24488 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL
24489 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
24490 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK
24491 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL                                 0x00000007
24492 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT                                  2
24493 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK                                   0x00000004U
24494
24495 /*USB 0 reset for control registers*/
24496 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
24497 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
24498 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
24499 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
24500 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
24501 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
24502
24503 /*USB 0 sleep circuit reset*/
24504 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
24505 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
24506 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
24507 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
24508 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
24509 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
24510
24511 /*USB 0 reset*/
24512 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
24513 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
24514 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
24515 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
24516 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
24517 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
24518
24519 /*Display Port block level reset (includes DPDMA)*/
24520 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
24521 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
24522 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
24523 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
24524 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
24525 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
24526
24527 /*FPD WDT reset*/
24528 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL
24529 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
24530 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK
24531 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL                                      0x000F9FFE
24532 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT                                       15
24533 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK                                        0x00008000U
24534
24535 /*GDMA block level reset*/
24536 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL
24537 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
24538 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK
24539 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL                                      0x000F9FFE
24540 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT                                       6
24541 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK                                        0x00000040U
24542
24543 /*Pixel Processor (submodule of GPU) block level reset*/
24544 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL
24545 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
24546 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK
24547 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL                                   0x000F9FFE
24548 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT                                    4
24549 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK                                     0x00000010U
24550
24551 /*Pixel Processor (submodule of GPU) block level reset*/
24552 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL
24553 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
24554 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK
24555 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL                                   0x000F9FFE
24556 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT                                    5
24557 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK                                     0x00000020U
24558
24559 /*GPU block level reset*/
24560 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL
24561 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
24562 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK
24563 #define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL                                       0x000F9FFE
24564 #define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT                                        3
24565 #define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK                                         0x00000008U
24566
24567 /*GT block level reset*/
24568 #undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL
24569 #undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
24570 #undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK
24571 #define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL                                        0x000F9FFE
24572 #define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT                                         2
24573 #define CRF_APB_RST_FPD_TOP_GT_RESET_MASK                                          0x00000004U
24574
24575 /*Sata block level reset*/
24576 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
24577 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
24578 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
24579 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
24580 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
24581 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
24582
24583 /*Block level reset*/
24584 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL
24585 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
24586 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK
24587 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL                                    0x0017FFFF
24588 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT                                     6
24589 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK                                      0x00000040U
24590
24591 /*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/
24592 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL
24593 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
24594 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK
24595 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL                                   0x00000000
24596 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT                                    15
24597 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK                                     0x00008000U
24598
24599 /*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
24600                 t 11 - Reserved*/
24601 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL
24602 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
24603 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK
24604 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL                                0x0FFC0FFC
24605 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT                                 28
24606 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK                                  0x30000000U
24607
24608 /*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
24609 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL
24610 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
24611 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK
24612 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL                                    0x0FFC0FFC
24613 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT                                     25
24614 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK                                      0x02000000U
24615
24616 /*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
24617 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL
24618 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
24619 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK
24620 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL                                    0x0FFC0FFC
24621 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT                                     24
24622 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK                                      0x01000000U
24623
24624 /*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
24625 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL
24626 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
24627 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK
24628 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL                                    0x0FFC0FFC
24629 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT                                     23
24630 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK                                      0x00800000U
24631
24632 /*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/
24633 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL
24634 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
24635 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK
24636 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL                                 0x32403240
24637 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT                                  23
24638 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK                                   0x7F800000U
24639
24640 /*This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
24641                 rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
24642                 s Fh - Ch = Reserved*/
24643 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL
24644 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
24645 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK
24646 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL                               0x06070607
24647 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT                                22
24648 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK                                 0x03C00000U
24649
24650 /*Block level reset*/
24651 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL
24652 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
24653 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK
24654 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL                                     0x0017FFFF
24655 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT                                      8
24656 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK                                       0x00000100U
24657
24658 /*Block level reset*/
24659 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL
24660 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
24661 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK
24662 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL                                     0x0017FFFF
24663 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT                                      9
24664 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK                                       0x00000200U
24665
24666 /*Block level reset*/
24667 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL
24668 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
24669 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK
24670 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL                                     0x0017FFFF
24671 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT                                      10
24672 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK                                       0x00000400U
24673
24674 /*Block level reset*/
24675 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL
24676 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
24677 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK
24678 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL                                     0x0017FFFF
24679 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT                                      15
24680 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK                                       0x00008000U
24681
24682 /*Block level reset*/
24683 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL
24684 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
24685 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK
24686 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL                                     0x0017FFFF
24687 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT                                      11
24688 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK                                       0x00000800U
24689
24690 /*Block level reset*/
24691 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL
24692 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
24693 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK
24694 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL                                     0x0017FFFF
24695 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT                                      12
24696 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK                                       0x00001000U
24697
24698 /*Block level reset*/
24699 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL
24700 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
24701 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK
24702 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL                                     0x0017FFFF
24703 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT                                      13
24704 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK                                       0x00002000U
24705
24706 /*Block level reset*/
24707 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL
24708 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
24709 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK
24710 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL                                     0x0017FFFF
24711 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT                                      14
24712 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK                                       0x00004000U
24713
24714 /*Block level reset*/
24715 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL
24716 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
24717 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK
24718 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL                                    0x0017FFFF
24719 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT                                     1
24720 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK                                      0x00000002U
24721
24722 /*Block level reset*/
24723 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL
24724 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
24725 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK
24726 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL                                    0x0017FFFF
24727 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT                                     2
24728 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK                                      0x00000004U
24729
24730 /*A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the a
24731                 fect of removing write access.*/
24732 #undef TPIU_LAR_ACCESS_W_DEFVAL
24733 #undef TPIU_LAR_ACCESS_W_SHIFT
24734 #undef TPIU_LAR_ACCESS_W_MASK
24735 #define TPIU_LAR_ACCESS_W_DEFVAL
24736 #define TPIU_LAR_ACCESS_W_SHIFT                                                    0
24737 #define TPIU_LAR_ACCESS_W_MASK                                                     0xFFFFFFFFU
24738
24739 /*Indicates whether the current port size of the TPIU is 32 bits.*/
24740 #undef TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_DEFVAL
24741 #undef TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_SHIFT
24742 #undef TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_MASK
24743 #define TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_DEFVAL                                 0x00000001
24744 #define TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_SHIFT                                  31
24745 #define TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_MASK                                   0x80000000U
24746
24747 /*A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the a
24748                 fect of removing write access.*/
24749 #undef TPIU_LAR_ACCESS_W_DEFVAL
24750 #undef TPIU_LAR_ACCESS_W_SHIFT
24751 #undef TPIU_LAR_ACCESS_W_MASK
24752 #define TPIU_LAR_ACCESS_W_DEFVAL
24753 #define TPIU_LAR_ACCESS_W_SHIFT                                                    0
24754 #define TPIU_LAR_ACCESS_W_MASK                                                     0xFFFFFFFFU
24755
24756 /*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
24757 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
24758 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
24759 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
24760 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
24761 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
24762 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
24763
24764 /*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
24765 #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL
24766 #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
24767 #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK
24768 #define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
24769 #define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
24770 #define UART0_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
24771
24772 /*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
24773                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
24774 #undef UART0_CONTROL_REG0_STPBRK_DEFVAL
24775 #undef UART0_CONTROL_REG0_STPBRK_SHIFT
24776 #undef UART0_CONTROL_REG0_STPBRK_MASK
24777 #define UART0_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
24778 #define UART0_CONTROL_REG0_STPBRK_SHIFT                                            8
24779 #define UART0_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
24780
24781 /*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
24782                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
24783 #undef UART0_CONTROL_REG0_STTBRK_DEFVAL
24784 #undef UART0_CONTROL_REG0_STTBRK_SHIFT
24785 #undef UART0_CONTROL_REG0_STTBRK_MASK
24786 #define UART0_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
24787 #define UART0_CONTROL_REG0_STTBRK_SHIFT                                            7
24788 #define UART0_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
24789
24790 /*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
24791                 pleted.*/
24792 #undef UART0_CONTROL_REG0_RSTTO_DEFVAL
24793 #undef UART0_CONTROL_REG0_RSTTO_SHIFT
24794 #undef UART0_CONTROL_REG0_RSTTO_MASK
24795 #define UART0_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
24796 #define UART0_CONTROL_REG0_RSTTO_SHIFT                                             6
24797 #define UART0_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
24798
24799 /*Transmit disable: 0: enable transmitter 1: disable transmitter*/
24800 #undef UART0_CONTROL_REG0_TXDIS_DEFVAL
24801 #undef UART0_CONTROL_REG0_TXDIS_SHIFT
24802 #undef UART0_CONTROL_REG0_TXDIS_MASK
24803 #define UART0_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
24804 #define UART0_CONTROL_REG0_TXDIS_SHIFT                                             5
24805 #define UART0_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
24806
24807 /*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
24808 #undef UART0_CONTROL_REG0_TXEN_DEFVAL
24809 #undef UART0_CONTROL_REG0_TXEN_SHIFT
24810 #undef UART0_CONTROL_REG0_TXEN_MASK
24811 #define UART0_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
24812 #define UART0_CONTROL_REG0_TXEN_SHIFT                                              4
24813 #define UART0_CONTROL_REG0_TXEN_MASK                                               0x00000010U
24814
24815 /*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
24816 #undef UART0_CONTROL_REG0_RXDIS_DEFVAL
24817 #undef UART0_CONTROL_REG0_RXDIS_SHIFT
24818 #undef UART0_CONTROL_REG0_RXDIS_MASK
24819 #define UART0_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
24820 #define UART0_CONTROL_REG0_RXDIS_SHIFT                                             3
24821 #define UART0_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
24822
24823 /*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
24824 #undef UART0_CONTROL_REG0_RXEN_DEFVAL
24825 #undef UART0_CONTROL_REG0_RXEN_SHIFT
24826 #undef UART0_CONTROL_REG0_RXEN_MASK
24827 #define UART0_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
24828 #define UART0_CONTROL_REG0_RXEN_SHIFT                                              2
24829 #define UART0_CONTROL_REG0_RXEN_MASK                                               0x00000004U
24830
24831 /*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
24832                  bit is self clearing once the reset has completed.*/
24833 #undef UART0_CONTROL_REG0_TXRES_DEFVAL
24834 #undef UART0_CONTROL_REG0_TXRES_SHIFT
24835 #undef UART0_CONTROL_REG0_TXRES_MASK
24836 #define UART0_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
24837 #define UART0_CONTROL_REG0_TXRES_SHIFT                                             1
24838 #define UART0_CONTROL_REG0_TXRES_MASK                                              0x00000002U
24839
24840 /*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
24841                 is self clearing once the reset has completed.*/
24842 #undef UART0_CONTROL_REG0_RXRES_DEFVAL
24843 #undef UART0_CONTROL_REG0_RXRES_SHIFT
24844 #undef UART0_CONTROL_REG0_RXRES_MASK
24845 #define UART0_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
24846 #define UART0_CONTROL_REG0_RXRES_SHIFT                                             0
24847 #define UART0_CONTROL_REG0_RXRES_MASK                                              0x00000001U
24848
24849 /*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
24850 #undef UART0_MODE_REG0_CHMODE_DEFVAL
24851 #undef UART0_MODE_REG0_CHMODE_SHIFT
24852 #undef UART0_MODE_REG0_CHMODE_MASK
24853 #define UART0_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
24854 #define UART0_MODE_REG0_CHMODE_SHIFT                                               8
24855 #define UART0_MODE_REG0_CHMODE_MASK                                                0x00000300U
24856
24857 /*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
24858                 stop bits 10: 2 stop bits 11: reserved*/
24859 #undef UART0_MODE_REG0_NBSTOP_DEFVAL
24860 #undef UART0_MODE_REG0_NBSTOP_SHIFT
24861 #undef UART0_MODE_REG0_NBSTOP_MASK
24862 #define UART0_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
24863 #define UART0_MODE_REG0_NBSTOP_SHIFT                                               6
24864 #define UART0_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
24865
24866 /*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
24867                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
24868 #undef UART0_MODE_REG0_PAR_DEFVAL
24869 #undef UART0_MODE_REG0_PAR_SHIFT
24870 #undef UART0_MODE_REG0_PAR_MASK
24871 #define UART0_MODE_REG0_PAR_DEFVAL                                                 0x00000000
24872 #define UART0_MODE_REG0_PAR_SHIFT                                                  3
24873 #define UART0_MODE_REG0_PAR_MASK                                                   0x00000038U
24874
24875 /*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
24876 #undef UART0_MODE_REG0_CHRL_DEFVAL
24877 #undef UART0_MODE_REG0_CHRL_SHIFT
24878 #undef UART0_MODE_REG0_CHRL_MASK
24879 #define UART0_MODE_REG0_CHRL_DEFVAL                                                0x00000000
24880 #define UART0_MODE_REG0_CHRL_SHIFT                                                 1
24881 #define UART0_MODE_REG0_CHRL_MASK                                                  0x00000006U
24882
24883 /*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
24884                 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
24885 #undef UART0_MODE_REG0_CLKS_DEFVAL
24886 #undef UART0_MODE_REG0_CLKS_SHIFT
24887 #undef UART0_MODE_REG0_CLKS_MASK
24888 #define UART0_MODE_REG0_CLKS_DEFVAL                                                0x00000000
24889 #define UART0_MODE_REG0_CLKS_SHIFT                                                 0
24890 #define UART0_MODE_REG0_CLKS_MASK                                                  0x00000001U
24891
24892 /*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
24893 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
24894 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
24895 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
24896 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
24897 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
24898 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
24899
24900 /*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
24901 #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL
24902 #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
24903 #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK
24904 #define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
24905 #define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
24906 #define UART1_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
24907
24908 /*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
24909                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
24910 #undef UART1_CONTROL_REG0_STPBRK_DEFVAL
24911 #undef UART1_CONTROL_REG0_STPBRK_SHIFT
24912 #undef UART1_CONTROL_REG0_STPBRK_MASK
24913 #define UART1_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
24914 #define UART1_CONTROL_REG0_STPBRK_SHIFT                                            8
24915 #define UART1_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
24916
24917 /*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
24918                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
24919 #undef UART1_CONTROL_REG0_STTBRK_DEFVAL
24920 #undef UART1_CONTROL_REG0_STTBRK_SHIFT
24921 #undef UART1_CONTROL_REG0_STTBRK_MASK
24922 #define UART1_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
24923 #define UART1_CONTROL_REG0_STTBRK_SHIFT                                            7
24924 #define UART1_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
24925
24926 /*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
24927                 pleted.*/
24928 #undef UART1_CONTROL_REG0_RSTTO_DEFVAL
24929 #undef UART1_CONTROL_REG0_RSTTO_SHIFT
24930 #undef UART1_CONTROL_REG0_RSTTO_MASK
24931 #define UART1_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
24932 #define UART1_CONTROL_REG0_RSTTO_SHIFT                                             6
24933 #define UART1_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
24934
24935 /*Transmit disable: 0: enable transmitter 1: disable transmitter*/
24936 #undef UART1_CONTROL_REG0_TXDIS_DEFVAL
24937 #undef UART1_CONTROL_REG0_TXDIS_SHIFT
24938 #undef UART1_CONTROL_REG0_TXDIS_MASK
24939 #define UART1_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
24940 #define UART1_CONTROL_REG0_TXDIS_SHIFT                                             5
24941 #define UART1_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
24942
24943 /*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
24944 #undef UART1_CONTROL_REG0_TXEN_DEFVAL
24945 #undef UART1_CONTROL_REG0_TXEN_SHIFT
24946 #undef UART1_CONTROL_REG0_TXEN_MASK
24947 #define UART1_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
24948 #define UART1_CONTROL_REG0_TXEN_SHIFT                                              4
24949 #define UART1_CONTROL_REG0_TXEN_MASK                                               0x00000010U
24950
24951 /*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
24952 #undef UART1_CONTROL_REG0_RXDIS_DEFVAL
24953 #undef UART1_CONTROL_REG0_RXDIS_SHIFT
24954 #undef UART1_CONTROL_REG0_RXDIS_MASK
24955 #define UART1_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
24956 #define UART1_CONTROL_REG0_RXDIS_SHIFT                                             3
24957 #define UART1_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
24958
24959 /*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
24960 #undef UART1_CONTROL_REG0_RXEN_DEFVAL
24961 #undef UART1_CONTROL_REG0_RXEN_SHIFT
24962 #undef UART1_CONTROL_REG0_RXEN_MASK
24963 #define UART1_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
24964 #define UART1_CONTROL_REG0_RXEN_SHIFT                                              2
24965 #define UART1_CONTROL_REG0_RXEN_MASK                                               0x00000004U
24966
24967 /*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
24968                  bit is self clearing once the reset has completed.*/
24969 #undef UART1_CONTROL_REG0_TXRES_DEFVAL
24970 #undef UART1_CONTROL_REG0_TXRES_SHIFT
24971 #undef UART1_CONTROL_REG0_TXRES_MASK
24972 #define UART1_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
24973 #define UART1_CONTROL_REG0_TXRES_SHIFT                                             1
24974 #define UART1_CONTROL_REG0_TXRES_MASK                                              0x00000002U
24975
24976 /*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
24977                 is self clearing once the reset has completed.*/
24978 #undef UART1_CONTROL_REG0_RXRES_DEFVAL
24979 #undef UART1_CONTROL_REG0_RXRES_SHIFT
24980 #undef UART1_CONTROL_REG0_RXRES_MASK
24981 #define UART1_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
24982 #define UART1_CONTROL_REG0_RXRES_SHIFT                                             0
24983 #define UART1_CONTROL_REG0_RXRES_MASK                                              0x00000001U
24984
24985 /*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
24986 #undef UART1_MODE_REG0_CHMODE_DEFVAL
24987 #undef UART1_MODE_REG0_CHMODE_SHIFT
24988 #undef UART1_MODE_REG0_CHMODE_MASK
24989 #define UART1_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
24990 #define UART1_MODE_REG0_CHMODE_SHIFT                                               8
24991 #define UART1_MODE_REG0_CHMODE_MASK                                                0x00000300U
24992
24993 /*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
24994                 stop bits 10: 2 stop bits 11: reserved*/
24995 #undef UART1_MODE_REG0_NBSTOP_DEFVAL
24996 #undef UART1_MODE_REG0_NBSTOP_SHIFT
24997 #undef UART1_MODE_REG0_NBSTOP_MASK
24998 #define UART1_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
24999 #define UART1_MODE_REG0_NBSTOP_SHIFT                                               6
25000 #define UART1_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
25001
25002 /*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
25003                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
25004 #undef UART1_MODE_REG0_PAR_DEFVAL
25005 #undef UART1_MODE_REG0_PAR_SHIFT
25006 #undef UART1_MODE_REG0_PAR_MASK
25007 #define UART1_MODE_REG0_PAR_DEFVAL                                                 0x00000000
25008 #define UART1_MODE_REG0_PAR_SHIFT                                                  3
25009 #define UART1_MODE_REG0_PAR_MASK                                                   0x00000038U
25010
25011 /*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
25012 #undef UART1_MODE_REG0_CHRL_DEFVAL
25013 #undef UART1_MODE_REG0_CHRL_SHIFT
25014 #undef UART1_MODE_REG0_CHRL_MASK
25015 #define UART1_MODE_REG0_CHRL_DEFVAL                                                0x00000000
25016 #define UART1_MODE_REG0_CHRL_SHIFT                                                 1
25017 #define UART1_MODE_REG0_CHRL_MASK                                                  0x00000006U
25018
25019 /*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
25020                 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
25021 #undef UART1_MODE_REG0_CLKS_DEFVAL
25022 #undef UART1_MODE_REG0_CLKS_SHIFT
25023 #undef UART1_MODE_REG0_CLKS_MASK
25024 #define UART1_MODE_REG0_CLKS_DEFVAL                                                0x00000000
25025 #define UART1_MODE_REG0_CLKS_SHIFT                                                 0
25026 #define UART1_MODE_REG0_CLKS_MASK                                                  0x00000001U
25027
25028 /*TrustZone Classification for ADMA*/
25029 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
25030 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
25031 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK
25032 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
25033 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                                         0
25034 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                                          0x000000FFU
25035
25036 /*CSU regsiter*/
25037 #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL
25038 #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT
25039 #undef CSU_TAMPER_STATUS_TAMPER_0_MASK
25040 #define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL                                          0x00000000
25041 #define CSU_TAMPER_STATUS_TAMPER_0_SHIFT                                           0
25042 #define CSU_TAMPER_STATUS_TAMPER_0_MASK                                            0x00000001U
25043
25044 /*External MIO*/
25045 #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL
25046 #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT
25047 #undef CSU_TAMPER_STATUS_TAMPER_1_MASK
25048 #define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL                                          0x00000000
25049 #define CSU_TAMPER_STATUS_TAMPER_1_SHIFT                                           1
25050 #define CSU_TAMPER_STATUS_TAMPER_1_MASK                                            0x00000002U
25051
25052 /*JTAG toggle detect*/
25053 #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL
25054 #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT
25055 #undef CSU_TAMPER_STATUS_TAMPER_2_MASK
25056 #define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL                                          0x00000000
25057 #define CSU_TAMPER_STATUS_TAMPER_2_SHIFT                                           2
25058 #define CSU_TAMPER_STATUS_TAMPER_2_MASK                                            0x00000004U
25059
25060 /*PL SEU error*/
25061 #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL
25062 #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT
25063 #undef CSU_TAMPER_STATUS_TAMPER_3_MASK
25064 #define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL                                          0x00000000
25065 #define CSU_TAMPER_STATUS_TAMPER_3_SHIFT                                           3
25066 #define CSU_TAMPER_STATUS_TAMPER_3_MASK                                            0x00000008U
25067
25068 /*AMS over temperature alarm for LPD*/
25069 #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL
25070 #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT
25071 #undef CSU_TAMPER_STATUS_TAMPER_4_MASK
25072 #define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL                                          0x00000000
25073 #define CSU_TAMPER_STATUS_TAMPER_4_SHIFT                                           4
25074 #define CSU_TAMPER_STATUS_TAMPER_4_MASK                                            0x00000010U
25075
25076 /*AMS over temperature alarm for APU*/
25077 #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL
25078 #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT
25079 #undef CSU_TAMPER_STATUS_TAMPER_5_MASK
25080 #define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL                                          0x00000000
25081 #define CSU_TAMPER_STATUS_TAMPER_5_SHIFT                                           5
25082 #define CSU_TAMPER_STATUS_TAMPER_5_MASK                                            0x00000020U
25083
25084 /*AMS voltage alarm for VCCPINT_FPD*/
25085 #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL
25086 #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT
25087 #undef CSU_TAMPER_STATUS_TAMPER_6_MASK
25088 #define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL                                          0x00000000
25089 #define CSU_TAMPER_STATUS_TAMPER_6_SHIFT                                           6
25090 #define CSU_TAMPER_STATUS_TAMPER_6_MASK                                            0x00000040U
25091
25092 /*AMS voltage alarm for VCCPINT_LPD*/
25093 #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL
25094 #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT
25095 #undef CSU_TAMPER_STATUS_TAMPER_7_MASK
25096 #define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL                                          0x00000000
25097 #define CSU_TAMPER_STATUS_TAMPER_7_SHIFT                                           7
25098 #define CSU_TAMPER_STATUS_TAMPER_7_MASK                                            0x00000080U
25099
25100 /*AMS voltage alarm for VCCPAUX*/
25101 #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL
25102 #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT
25103 #undef CSU_TAMPER_STATUS_TAMPER_8_MASK
25104 #define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL                                          0x00000000
25105 #define CSU_TAMPER_STATUS_TAMPER_8_SHIFT                                           8
25106 #define CSU_TAMPER_STATUS_TAMPER_8_MASK                                            0x00000100U
25107
25108 /*AMS voltage alarm for DDRPHY*/
25109 #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL
25110 #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT
25111 #undef CSU_TAMPER_STATUS_TAMPER_9_MASK
25112 #define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL                                          0x00000000
25113 #define CSU_TAMPER_STATUS_TAMPER_9_SHIFT                                           9
25114 #define CSU_TAMPER_STATUS_TAMPER_9_MASK                                            0x00000200U
25115
25116 /*AMS voltage alarm for PSIO bank 0/1/2*/
25117 #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL
25118 #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT
25119 #undef CSU_TAMPER_STATUS_TAMPER_10_MASK
25120 #define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL                                         0x00000000
25121 #define CSU_TAMPER_STATUS_TAMPER_10_SHIFT                                          10
25122 #define CSU_TAMPER_STATUS_TAMPER_10_MASK                                           0x00000400U
25123
25124 /*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/
25125 #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL
25126 #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT
25127 #undef CSU_TAMPER_STATUS_TAMPER_11_MASK
25128 #define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL                                         0x00000000
25129 #define CSU_TAMPER_STATUS_TAMPER_11_SHIFT                                          11
25130 #define CSU_TAMPER_STATUS_TAMPER_11_MASK                                           0x00000800U
25131
25132 /*AMS voltaage alarm for GT*/
25133 #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL
25134 #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT
25135 #undef CSU_TAMPER_STATUS_TAMPER_12_MASK
25136 #define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL                                         0x00000000
25137 #define CSU_TAMPER_STATUS_TAMPER_12_SHIFT                                          12
25138 #define CSU_TAMPER_STATUS_TAMPER_12_MASK                                           0x00001000U
25139
25140 /*Set ACE outgoing AWQOS value*/
25141 #undef APU_ACE_CTRL_AWQOS_DEFVAL
25142 #undef APU_ACE_CTRL_AWQOS_SHIFT
25143 #undef APU_ACE_CTRL_AWQOS_MASK
25144 #define APU_ACE_CTRL_AWQOS_DEFVAL                                                  0x000F000F
25145 #define APU_ACE_CTRL_AWQOS_SHIFT                                                   16
25146 #define APU_ACE_CTRL_AWQOS_MASK                                                    0x000F0000U
25147
25148 /*Set ACE outgoing ARQOS value*/
25149 #undef APU_ACE_CTRL_ARQOS_DEFVAL
25150 #undef APU_ACE_CTRL_ARQOS_SHIFT
25151 #undef APU_ACE_CTRL_ARQOS_MASK
25152 #define APU_ACE_CTRL_ARQOS_DEFVAL                                                  0x000F000F
25153 #define APU_ACE_CTRL_ARQOS_SHIFT                                                   0
25154 #define APU_ACE_CTRL_ARQOS_MASK                                                    0x0000000FU
25155
25156 /*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from
25157                 he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
25158                 pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
25159                 g a 0 to this bit.*/
25160 #undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL
25161 #undef RTC_CONTROL_BATTERY_DISABLE_SHIFT
25162 #undef RTC_CONTROL_BATTERY_DISABLE_MASK
25163 #define RTC_CONTROL_BATTERY_DISABLE_DEFVAL                                         0x01000000
25164 #define RTC_CONTROL_BATTERY_DISABLE_SHIFT                                          31
25165 #define RTC_CONTROL_BATTERY_DISABLE_MASK                                           0x80000000U
25166
25167 /*Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.*/
25168 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
25169 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
25170 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK
25171 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
25172 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT                           0
25173 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK                            0xFFFFFFFFU
25174
25175 /*Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.*/
25176 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL
25177 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
25178 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK
25179 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL                              0x00000000
25180 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT                               0
25181 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK                                0x00000001U
25182 #undef LPD_XPPU_CFG_MASTER_ID00_OFFSET
25183 #define LPD_XPPU_CFG_MASTER_ID00_OFFSET                                            0XFF980100
25184 #undef LPD_XPPU_CFG_MASTER_ID01_OFFSET
25185 #define LPD_XPPU_CFG_MASTER_ID01_OFFSET                                            0XFF980104
25186 #undef LPD_XPPU_CFG_MASTER_ID02_OFFSET
25187 #define LPD_XPPU_CFG_MASTER_ID02_OFFSET                                            0XFF980108
25188 #undef LPD_XPPU_CFG_MASTER_ID03_OFFSET
25189 #define LPD_XPPU_CFG_MASTER_ID03_OFFSET                                            0XFF98010C
25190 #undef LPD_XPPU_CFG_MASTER_ID04_OFFSET
25191 #define LPD_XPPU_CFG_MASTER_ID04_OFFSET                                            0XFF980110
25192 #undef LPD_XPPU_CFG_MASTER_ID05_OFFSET
25193 #define LPD_XPPU_CFG_MASTER_ID05_OFFSET                                            0XFF980114
25194 #undef LPD_XPPU_CFG_MASTER_ID06_OFFSET
25195 #define LPD_XPPU_CFG_MASTER_ID06_OFFSET                                            0XFF980118
25196 #undef LPD_XPPU_CFG_MASTER_ID07_OFFSET
25197 #define LPD_XPPU_CFG_MASTER_ID07_OFFSET                                            0XFF98011C
25198 #undef LPD_XPPU_CFG_MASTER_ID19_OFFSET
25199 #define LPD_XPPU_CFG_MASTER_ID19_OFFSET                                            0XFF98014C
25200 #undef LPD_XPPU_CFG_APERPERM_048_OFFSET
25201 #define LPD_XPPU_CFG_APERPERM_048_OFFSET                                           0XFF9810C0
25202 #undef LPD_XPPU_CFG_APERPERM_049_OFFSET
25203 #define LPD_XPPU_CFG_APERPERM_049_OFFSET                                           0XFF9810C4
25204 #undef LPD_XPPU_CFG_APERPERM_050_OFFSET
25205 #define LPD_XPPU_CFG_APERPERM_050_OFFSET                                           0XFF9810C8
25206 #undef LPD_XPPU_CFG_APERPERM_051_OFFSET
25207 #define LPD_XPPU_CFG_APERPERM_051_OFFSET                                           0XFF9810CC
25208 #undef LPD_XPPU_CFG_APERPERM_256_OFFSET
25209 #define LPD_XPPU_CFG_APERPERM_256_OFFSET                                           0XFF981400
25210 #undef LPD_XPPU_CFG_APERPERM_257_OFFSET
25211 #define LPD_XPPU_CFG_APERPERM_257_OFFSET                                           0XFF981404
25212 #undef LPD_XPPU_CFG_APERPERM_258_OFFSET
25213 #define LPD_XPPU_CFG_APERPERM_258_OFFSET                                           0XFF981408
25214 #undef LPD_XPPU_CFG_APERPERM_259_OFFSET
25215 #define LPD_XPPU_CFG_APERPERM_259_OFFSET                                           0XFF98140C
25216 #undef LPD_XPPU_CFG_APERPERM_260_OFFSET
25217 #define LPD_XPPU_CFG_APERPERM_260_OFFSET                                           0XFF981410
25218 #undef LPD_XPPU_CFG_APERPERM_261_OFFSET
25219 #define LPD_XPPU_CFG_APERPERM_261_OFFSET                                           0XFF981414
25220 #undef LPD_XPPU_CFG_APERPERM_262_OFFSET
25221 #define LPD_XPPU_CFG_APERPERM_262_OFFSET                                           0XFF981418
25222 #undef LPD_XPPU_CFG_APERPERM_263_OFFSET
25223 #define LPD_XPPU_CFG_APERPERM_263_OFFSET                                           0XFF98141C
25224 #undef LPD_XPPU_CFG_APERPERM_264_OFFSET
25225 #define LPD_XPPU_CFG_APERPERM_264_OFFSET                                           0XFF981420
25226 #undef LPD_XPPU_CFG_APERPERM_265_OFFSET
25227 #define LPD_XPPU_CFG_APERPERM_265_OFFSET                                           0XFF981424
25228 #undef LPD_XPPU_CFG_APERPERM_266_OFFSET
25229 #define LPD_XPPU_CFG_APERPERM_266_OFFSET                                           0XFF981428
25230 #undef LPD_XPPU_CFG_APERPERM_267_OFFSET
25231 #define LPD_XPPU_CFG_APERPERM_267_OFFSET                                           0XFF98142C
25232 #undef LPD_XPPU_CFG_APERPERM_268_OFFSET
25233 #define LPD_XPPU_CFG_APERPERM_268_OFFSET                                           0XFF981430
25234 #undef LPD_XPPU_CFG_APERPERM_269_OFFSET
25235 #define LPD_XPPU_CFG_APERPERM_269_OFFSET                                           0XFF981434
25236 #undef LPD_XPPU_CFG_APERPERM_270_OFFSET
25237 #define LPD_XPPU_CFG_APERPERM_270_OFFSET                                           0XFF981438
25238 #undef LPD_XPPU_CFG_APERPERM_271_OFFSET
25239 #define LPD_XPPU_CFG_APERPERM_271_OFFSET                                           0XFF98143C
25240 #undef LPD_XPPU_CFG_APERPERM_272_OFFSET
25241 #define LPD_XPPU_CFG_APERPERM_272_OFFSET                                           0XFF981440
25242 #undef LPD_XPPU_CFG_APERPERM_273_OFFSET
25243 #define LPD_XPPU_CFG_APERPERM_273_OFFSET                                           0XFF981444
25244 #undef LPD_XPPU_CFG_APERPERM_274_OFFSET
25245 #define LPD_XPPU_CFG_APERPERM_274_OFFSET                                           0XFF981448
25246 #undef LPD_XPPU_CFG_APERPERM_275_OFFSET
25247 #define LPD_XPPU_CFG_APERPERM_275_OFFSET                                           0XFF98144C
25248 #undef LPD_XPPU_CFG_APERPERM_276_OFFSET
25249 #define LPD_XPPU_CFG_APERPERM_276_OFFSET                                           0XFF981450
25250 #undef LPD_XPPU_CFG_APERPERM_277_OFFSET
25251 #define LPD_XPPU_CFG_APERPERM_277_OFFSET                                           0XFF981454
25252 #undef LPD_XPPU_CFG_APERPERM_278_OFFSET
25253 #define LPD_XPPU_CFG_APERPERM_278_OFFSET                                           0XFF981458
25254 #undef LPD_XPPU_CFG_APERPERM_279_OFFSET
25255 #define LPD_XPPU_CFG_APERPERM_279_OFFSET                                           0XFF98145C
25256 #undef LPD_XPPU_CFG_APERPERM_280_OFFSET
25257 #define LPD_XPPU_CFG_APERPERM_280_OFFSET                                           0XFF981460
25258 #undef LPD_XPPU_CFG_APERPERM_281_OFFSET
25259 #define LPD_XPPU_CFG_APERPERM_281_OFFSET                                           0XFF981464
25260 #undef LPD_XPPU_CFG_APERPERM_282_OFFSET
25261 #define LPD_XPPU_CFG_APERPERM_282_OFFSET                                           0XFF981468
25262 #undef LPD_XPPU_CFG_APERPERM_283_OFFSET
25263 #define LPD_XPPU_CFG_APERPERM_283_OFFSET                                           0XFF98146C
25264 #undef LPD_XPPU_CFG_APERPERM_284_OFFSET
25265 #define LPD_XPPU_CFG_APERPERM_284_OFFSET                                           0XFF981470
25266 #undef LPD_XPPU_CFG_APERPERM_285_OFFSET
25267 #define LPD_XPPU_CFG_APERPERM_285_OFFSET                                           0XFF981474
25268 #undef LPD_XPPU_CFG_APERPERM_286_OFFSET
25269 #define LPD_XPPU_CFG_APERPERM_286_OFFSET                                           0XFF981478
25270 #undef LPD_XPPU_CFG_APERPERM_287_OFFSET
25271 #define LPD_XPPU_CFG_APERPERM_287_OFFSET                                           0XFF98147C
25272 #undef LPD_XPPU_CFG_APERPERM_288_OFFSET
25273 #define LPD_XPPU_CFG_APERPERM_288_OFFSET                                           0XFF981480
25274 #undef LPD_XPPU_CFG_APERPERM_289_OFFSET
25275 #define LPD_XPPU_CFG_APERPERM_289_OFFSET                                           0XFF981484
25276 #undef LPD_XPPU_CFG_APERPERM_290_OFFSET
25277 #define LPD_XPPU_CFG_APERPERM_290_OFFSET                                           0XFF981488
25278 #undef LPD_XPPU_CFG_APERPERM_291_OFFSET
25279 #define LPD_XPPU_CFG_APERPERM_291_OFFSET                                           0XFF98148C
25280 #undef LPD_XPPU_CFG_APERPERM_292_OFFSET
25281 #define LPD_XPPU_CFG_APERPERM_292_OFFSET                                           0XFF981490
25282 #undef LPD_XPPU_CFG_APERPERM_293_OFFSET
25283 #define LPD_XPPU_CFG_APERPERM_293_OFFSET                                           0XFF981494
25284 #undef LPD_XPPU_CFG_APERPERM_294_OFFSET
25285 #define LPD_XPPU_CFG_APERPERM_294_OFFSET                                           0XFF981498
25286 #undef LPD_XPPU_CFG_APERPERM_295_OFFSET
25287 #define LPD_XPPU_CFG_APERPERM_295_OFFSET                                           0XFF98149C
25288 #undef LPD_XPPU_CFG_APERPERM_296_OFFSET
25289 #define LPD_XPPU_CFG_APERPERM_296_OFFSET                                           0XFF9814A0
25290 #undef LPD_XPPU_CFG_APERPERM_297_OFFSET
25291 #define LPD_XPPU_CFG_APERPERM_297_OFFSET                                           0XFF9814A4
25292 #undef LPD_XPPU_CFG_APERPERM_298_OFFSET
25293 #define LPD_XPPU_CFG_APERPERM_298_OFFSET                                           0XFF9814A8
25294 #undef LPD_XPPU_CFG_APERPERM_299_OFFSET
25295 #define LPD_XPPU_CFG_APERPERM_299_OFFSET                                           0XFF9814AC
25296 #undef LPD_XPPU_CFG_APERPERM_300_OFFSET
25297 #define LPD_XPPU_CFG_APERPERM_300_OFFSET                                           0XFF9814B0
25298 #undef LPD_XPPU_CFG_APERPERM_301_OFFSET
25299 #define LPD_XPPU_CFG_APERPERM_301_OFFSET                                           0XFF9814B4
25300 #undef LPD_XPPU_CFG_APERPERM_302_OFFSET
25301 #define LPD_XPPU_CFG_APERPERM_302_OFFSET                                           0XFF9814B8
25302 #undef LPD_XPPU_CFG_APERPERM_303_OFFSET
25303 #define LPD_XPPU_CFG_APERPERM_303_OFFSET                                           0XFF9814BC
25304 #undef LPD_XPPU_CFG_APERPERM_304_OFFSET
25305 #define LPD_XPPU_CFG_APERPERM_304_OFFSET                                           0XFF9814C0
25306 #undef LPD_XPPU_CFG_APERPERM_305_OFFSET
25307 #define LPD_XPPU_CFG_APERPERM_305_OFFSET                                           0XFF9814C4
25308 #undef LPD_XPPU_CFG_APERPERM_306_OFFSET
25309 #define LPD_XPPU_CFG_APERPERM_306_OFFSET                                           0XFF9814C8
25310 #undef LPD_XPPU_CFG_APERPERM_307_OFFSET
25311 #define LPD_XPPU_CFG_APERPERM_307_OFFSET                                           0XFF9814CC
25312 #undef LPD_XPPU_CFG_APERPERM_308_OFFSET
25313 #define LPD_XPPU_CFG_APERPERM_308_OFFSET                                           0XFF9814D0
25314 #undef LPD_XPPU_CFG_APERPERM_309_OFFSET
25315 #define LPD_XPPU_CFG_APERPERM_309_OFFSET                                           0XFF9814D4
25316 #undef LPD_XPPU_CFG_APERPERM_318_OFFSET
25317 #define LPD_XPPU_CFG_APERPERM_318_OFFSET                                           0XFF9814F8
25318 #undef LPD_XPPU_CFG_APERPERM_319_OFFSET
25319 #define LPD_XPPU_CFG_APERPERM_319_OFFSET                                           0XFF9814FC
25320 #undef LPD_XPPU_CFG_APERPERM_320_OFFSET
25321 #define LPD_XPPU_CFG_APERPERM_320_OFFSET                                           0XFF981500
25322 #undef LPD_XPPU_CFG_APERPERM_321_OFFSET
25323 #define LPD_XPPU_CFG_APERPERM_321_OFFSET                                           0XFF981504
25324 #undef LPD_XPPU_CFG_APERPERM_322_OFFSET
25325 #define LPD_XPPU_CFG_APERPERM_322_OFFSET                                           0XFF981508
25326 #undef LPD_XPPU_CFG_APERPERM_323_OFFSET
25327 #define LPD_XPPU_CFG_APERPERM_323_OFFSET                                           0XFF98150C
25328 #undef LPD_XPPU_CFG_APERPERM_324_OFFSET
25329 #define LPD_XPPU_CFG_APERPERM_324_OFFSET                                           0XFF981510
25330 #undef LPD_XPPU_CFG_APERPERM_325_OFFSET
25331 #define LPD_XPPU_CFG_APERPERM_325_OFFSET                                           0XFF981514
25332 #undef LPD_XPPU_CFG_APERPERM_334_OFFSET
25333 #define LPD_XPPU_CFG_APERPERM_334_OFFSET                                           0XFF981538
25334 #undef LPD_XPPU_CFG_APERPERM_335_OFFSET
25335 #define LPD_XPPU_CFG_APERPERM_335_OFFSET                                           0XFF98153C
25336 #undef LPD_XPPU_CFG_APERPERM_336_OFFSET
25337 #define LPD_XPPU_CFG_APERPERM_336_OFFSET                                           0XFF981540
25338 #undef LPD_XPPU_CFG_APERPERM_337_OFFSET
25339 #define LPD_XPPU_CFG_APERPERM_337_OFFSET                                           0XFF981544
25340 #undef LPD_XPPU_CFG_APERPERM_338_OFFSET
25341 #define LPD_XPPU_CFG_APERPERM_338_OFFSET                                           0XFF981548
25342 #undef LPD_XPPU_CFG_APERPERM_339_OFFSET
25343 #define LPD_XPPU_CFG_APERPERM_339_OFFSET                                           0XFF98154C
25344 #undef LPD_XPPU_CFG_APERPERM_340_OFFSET
25345 #define LPD_XPPU_CFG_APERPERM_340_OFFSET                                           0XFF981550
25346 #undef LPD_XPPU_CFG_APERPERM_341_OFFSET
25347 #define LPD_XPPU_CFG_APERPERM_341_OFFSET                                           0XFF981554
25348 #undef LPD_XPPU_CFG_APERPERM_350_OFFSET
25349 #define LPD_XPPU_CFG_APERPERM_350_OFFSET                                           0XFF981578
25350 #undef LPD_XPPU_CFG_APERPERM_351_OFFSET
25351 #define LPD_XPPU_CFG_APERPERM_351_OFFSET                                           0XFF98157C
25352 #undef LPD_XPPU_CFG_APERPERM_352_OFFSET
25353 #define LPD_XPPU_CFG_APERPERM_352_OFFSET                                           0XFF981580
25354 #undef LPD_XPPU_CFG_APERPERM_353_OFFSET
25355 #define LPD_XPPU_CFG_APERPERM_353_OFFSET                                           0XFF981584
25356 #undef LPD_XPPU_CFG_APERPERM_354_OFFSET
25357 #define LPD_XPPU_CFG_APERPERM_354_OFFSET                                           0XFF981588
25358 #undef LPD_XPPU_CFG_APERPERM_355_OFFSET
25359 #define LPD_XPPU_CFG_APERPERM_355_OFFSET                                           0XFF98158C
25360 #undef LPD_XPPU_CFG_APERPERM_356_OFFSET
25361 #define LPD_XPPU_CFG_APERPERM_356_OFFSET                                           0XFF981590
25362 #undef LPD_XPPU_CFG_APERPERM_357_OFFSET
25363 #define LPD_XPPU_CFG_APERPERM_357_OFFSET                                           0XFF981594
25364 #undef LPD_XPPU_CFG_APERPERM_366_OFFSET
25365 #define LPD_XPPU_CFG_APERPERM_366_OFFSET                                           0XFF9815B8
25366 #undef LPD_XPPU_CFG_APERPERM_367_OFFSET
25367 #define LPD_XPPU_CFG_APERPERM_367_OFFSET                                           0XFF9815BC
25368 #undef LPD_XPPU_CFG_APERPERM_368_OFFSET
25369 #define LPD_XPPU_CFG_APERPERM_368_OFFSET                                           0XFF9815C0
25370 #undef LPD_XPPU_CFG_APERPERM_369_OFFSET
25371 #define LPD_XPPU_CFG_APERPERM_369_OFFSET                                           0XFF9815C4
25372 #undef LPD_XPPU_CFG_APERPERM_370_OFFSET
25373 #define LPD_XPPU_CFG_APERPERM_370_OFFSET                                           0XFF9815C8
25374 #undef LPD_XPPU_CFG_APERPERM_371_OFFSET
25375 #define LPD_XPPU_CFG_APERPERM_371_OFFSET                                           0XFF9815CC
25376 #undef LPD_XPPU_CFG_APERPERM_372_OFFSET
25377 #define LPD_XPPU_CFG_APERPERM_372_OFFSET                                           0XFF9815D0
25378 #undef LPD_XPPU_CFG_APERPERM_373_OFFSET
25379 #define LPD_XPPU_CFG_APERPERM_373_OFFSET                                           0XFF9815D4
25380 #undef LPD_XPPU_CFG_APERPERM_374_OFFSET
25381 #define LPD_XPPU_CFG_APERPERM_374_OFFSET                                           0XFF9815D8
25382 #undef LPD_XPPU_CFG_APERPERM_375_OFFSET
25383 #define LPD_XPPU_CFG_APERPERM_375_OFFSET                                           0XFF9815DC
25384 #undef LPD_XPPU_CFG_APERPERM_376_OFFSET
25385 #define LPD_XPPU_CFG_APERPERM_376_OFFSET                                           0XFF9815E0
25386 #undef LPD_XPPU_CFG_APERPERM_377_OFFSET
25387 #define LPD_XPPU_CFG_APERPERM_377_OFFSET                                           0XFF9815E4
25388 #undef LPD_XPPU_CFG_APERPERM_378_OFFSET
25389 #define LPD_XPPU_CFG_APERPERM_378_OFFSET                                           0XFF9815E8
25390 #undef LPD_XPPU_CFG_APERPERM_379_OFFSET
25391 #define LPD_XPPU_CFG_APERPERM_379_OFFSET                                           0XFF9815EC
25392 #undef LPD_XPPU_CFG_APERPERM_380_OFFSET
25393 #define LPD_XPPU_CFG_APERPERM_380_OFFSET                                           0XFF9815F0
25394 #undef LPD_XPPU_CFG_APERPERM_381_OFFSET
25395 #define LPD_XPPU_CFG_APERPERM_381_OFFSET                                           0XFF9815F4
25396 #undef LPD_XPPU_CFG_APERPERM_382_OFFSET
25397 #define LPD_XPPU_CFG_APERPERM_382_OFFSET                                           0XFF9815F8
25398 #undef LPD_XPPU_CFG_APERPERM_383_OFFSET
25399 #define LPD_XPPU_CFG_APERPERM_383_OFFSET                                           0XFF9815FC
25400 #undef LPD_XPPU_SINK_ERR_CTRL_OFFSET
25401 #define LPD_XPPU_SINK_ERR_CTRL_OFFSET                                              0XFF9CFFEC
25402 #undef LPD_XPPU_CFG_CTRL_OFFSET
25403 #define LPD_XPPU_CFG_CTRL_OFFSET                                                   0XFF980000
25404 #undef LPD_XPPU_CFG_IEN_OFFSET
25405 #define LPD_XPPU_CFG_IEN_OFFSET                                                    0XFF980018
25406
25407 /*If set, only read transactions are allowed for the masters matching this register*/
25408 #undef LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL
25409 #undef LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT
25410 #undef LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK
25411 #define LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL                                       0x83FF0040
25412 #define LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT                                        30
25413 #define LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK                                         0x40000000U
25414
25415 /*Mask to be applied before comparing*/
25416 #undef LPD_XPPU_CFG_MASTER_ID00_MIDM_DEFVAL
25417 #undef LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT
25418 #undef LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK
25419 #define LPD_XPPU_CFG_MASTER_ID00_MIDM_DEFVAL                                       0x83FF0040
25420 #define LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT                                        16
25421 #define LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK                                         0x03FF0000U
25422
25423 /*Predefined Master ID for PMU*/
25424 #undef LPD_XPPU_CFG_MASTER_ID00_MID_DEFVAL
25425 #undef LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT
25426 #undef LPD_XPPU_CFG_MASTER_ID00_MID_MASK
25427 #define LPD_XPPU_CFG_MASTER_ID00_MID_DEFVAL                                        0x83FF0040
25428 #define LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT                                         0
25429 #define LPD_XPPU_CFG_MASTER_ID00_MID_MASK                                          0x000003FFU
25430
25431 /*If set, only read transactions are allowed for the masters matching this register*/
25432 #undef LPD_XPPU_CFG_MASTER_ID01_MIDR_DEFVAL
25433 #undef LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT
25434 #undef LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK
25435 #define LPD_XPPU_CFG_MASTER_ID01_MIDR_DEFVAL                                       0x03F00000
25436 #define LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT                                        30
25437 #define LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK                                         0x40000000U
25438
25439 /*Mask to be applied before comparing*/
25440 #undef LPD_XPPU_CFG_MASTER_ID01_MIDM_DEFVAL
25441 #undef LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT
25442 #undef LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK
25443 #define LPD_XPPU_CFG_MASTER_ID01_MIDM_DEFVAL                                       0x03F00000
25444 #define LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT                                        16
25445 #define LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK                                         0x03FF0000U
25446
25447 /*Predefined Master ID for RPU0*/
25448 #undef LPD_XPPU_CFG_MASTER_ID01_MID_DEFVAL
25449 #undef LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT
25450 #undef LPD_XPPU_CFG_MASTER_ID01_MID_MASK
25451 #define LPD_XPPU_CFG_MASTER_ID01_MID_DEFVAL                                        0x03F00000
25452 #define LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT                                         0
25453 #define LPD_XPPU_CFG_MASTER_ID01_MID_MASK                                          0x000003FFU
25454
25455 /*If set, only read transactions are allowed for the masters matching this register*/
25456 #undef LPD_XPPU_CFG_MASTER_ID02_MIDR_DEFVAL
25457 #undef LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT
25458 #undef LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK
25459 #define LPD_XPPU_CFG_MASTER_ID02_MIDR_DEFVAL                                       0x83F00010
25460 #define LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT                                        30
25461 #define LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK                                         0x40000000U
25462
25463 /*Mask to be applied before comparing*/
25464 #undef LPD_XPPU_CFG_MASTER_ID02_MIDM_DEFVAL
25465 #undef LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT
25466 #undef LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK
25467 #define LPD_XPPU_CFG_MASTER_ID02_MIDM_DEFVAL                                       0x83F00010
25468 #define LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT                                        16
25469 #define LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK                                         0x03FF0000U
25470
25471 /*Predefined Master ID for RPU1*/
25472 #undef LPD_XPPU_CFG_MASTER_ID02_MID_DEFVAL
25473 #undef LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT
25474 #undef LPD_XPPU_CFG_MASTER_ID02_MID_MASK
25475 #define LPD_XPPU_CFG_MASTER_ID02_MID_DEFVAL                                        0x83F00010
25476 #define LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT                                         0
25477 #define LPD_XPPU_CFG_MASTER_ID02_MID_MASK                                          0x000003FFU
25478
25479 /*If set, only read transactions are allowed for the masters matching this register*/
25480 #undef LPD_XPPU_CFG_MASTER_ID03_MIDR_DEFVAL
25481 #undef LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT
25482 #undef LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK
25483 #define LPD_XPPU_CFG_MASTER_ID03_MIDR_DEFVAL                                       0x83C00080
25484 #define LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT                                        30
25485 #define LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK                                         0x40000000U
25486
25487 /*Mask to be applied before comparing*/
25488 #undef LPD_XPPU_CFG_MASTER_ID03_MIDM_DEFVAL
25489 #undef LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT
25490 #undef LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK
25491 #define LPD_XPPU_CFG_MASTER_ID03_MIDM_DEFVAL                                       0x83C00080
25492 #define LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT                                        16
25493 #define LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK                                         0x03FF0000U
25494
25495 /*Predefined Master ID for APU*/
25496 #undef LPD_XPPU_CFG_MASTER_ID03_MID_DEFVAL
25497 #undef LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT
25498 #undef LPD_XPPU_CFG_MASTER_ID03_MID_MASK
25499 #define LPD_XPPU_CFG_MASTER_ID03_MID_DEFVAL                                        0x83C00080
25500 #define LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT                                         0
25501 #define LPD_XPPU_CFG_MASTER_ID03_MID_MASK                                          0x000003FFU
25502
25503 /*If set, only read transactions are allowed for the masters matching this register*/
25504 #undef LPD_XPPU_CFG_MASTER_ID04_MIDR_DEFVAL
25505 #undef LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT
25506 #undef LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK
25507 #define LPD_XPPU_CFG_MASTER_ID04_MIDR_DEFVAL                                       0x83C30080
25508 #define LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT                                        30
25509 #define LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK                                         0x40000000U
25510
25511 /*Mask to be applied before comparing*/
25512 #undef LPD_XPPU_CFG_MASTER_ID04_MIDM_DEFVAL
25513 #undef LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT
25514 #undef LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK
25515 #define LPD_XPPU_CFG_MASTER_ID04_MIDM_DEFVAL                                       0x83C30080
25516 #define LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT                                        16
25517 #define LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK                                         0x03FF0000U
25518
25519 /*Predefined Master ID for A53 Core 0*/
25520 #undef LPD_XPPU_CFG_MASTER_ID04_MID_DEFVAL
25521 #undef LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT
25522 #undef LPD_XPPU_CFG_MASTER_ID04_MID_MASK
25523 #define LPD_XPPU_CFG_MASTER_ID04_MID_DEFVAL                                        0x83C30080
25524 #define LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT                                         0
25525 #define LPD_XPPU_CFG_MASTER_ID04_MID_MASK                                          0x000003FFU
25526
25527 /*If set, only read transactions are allowed for the masters matching this register*/
25528 #undef LPD_XPPU_CFG_MASTER_ID05_MIDR_DEFVAL
25529 #undef LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT
25530 #undef LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK
25531 #define LPD_XPPU_CFG_MASTER_ID05_MIDR_DEFVAL                                       0x03C30081
25532 #define LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT                                        30
25533 #define LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK                                         0x40000000U
25534
25535 /*Mask to be applied before comparing*/
25536 #undef LPD_XPPU_CFG_MASTER_ID05_MIDM_DEFVAL
25537 #undef LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT
25538 #undef LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK
25539 #define LPD_XPPU_CFG_MASTER_ID05_MIDM_DEFVAL                                       0x03C30081
25540 #define LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT                                        16
25541 #define LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK                                         0x03FF0000U
25542
25543 /*Predefined Master ID for A53 Core 1*/
25544 #undef LPD_XPPU_CFG_MASTER_ID05_MID_DEFVAL
25545 #undef LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT
25546 #undef LPD_XPPU_CFG_MASTER_ID05_MID_MASK
25547 #define LPD_XPPU_CFG_MASTER_ID05_MID_DEFVAL                                        0x03C30081
25548 #define LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT                                         0
25549 #define LPD_XPPU_CFG_MASTER_ID05_MID_MASK                                          0x000003FFU
25550
25551 /*If set, only read transactions are allowed for the masters matching this register*/
25552 #undef LPD_XPPU_CFG_MASTER_ID06_MIDR_DEFVAL
25553 #undef LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT
25554 #undef LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK
25555 #define LPD_XPPU_CFG_MASTER_ID06_MIDR_DEFVAL                                       0x03C30082
25556 #define LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT                                        30
25557 #define LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK                                         0x40000000U
25558
25559 /*Mask to be applied before comparing*/
25560 #undef LPD_XPPU_CFG_MASTER_ID06_MIDM_DEFVAL
25561 #undef LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT
25562 #undef LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK
25563 #define LPD_XPPU_CFG_MASTER_ID06_MIDM_DEFVAL                                       0x03C30082
25564 #define LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT                                        16
25565 #define LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK                                         0x03FF0000U
25566
25567 /*Predefined Master ID for A53 Core 2*/
25568 #undef LPD_XPPU_CFG_MASTER_ID06_MID_DEFVAL
25569 #undef LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT
25570 #undef LPD_XPPU_CFG_MASTER_ID06_MID_MASK
25571 #define LPD_XPPU_CFG_MASTER_ID06_MID_DEFVAL                                        0x03C30082
25572 #define LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT                                         0
25573 #define LPD_XPPU_CFG_MASTER_ID06_MID_MASK                                          0x000003FFU
25574
25575 /*If set, only read transactions are allowed for the masters matching this register*/
25576 #undef LPD_XPPU_CFG_MASTER_ID07_MIDR_DEFVAL
25577 #undef LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT
25578 #undef LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK
25579 #define LPD_XPPU_CFG_MASTER_ID07_MIDR_DEFVAL                                       0x83C30083
25580 #define LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT                                        30
25581 #define LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK                                         0x40000000U
25582
25583 /*Mask to be applied before comparing*/
25584 #undef LPD_XPPU_CFG_MASTER_ID07_MIDM_DEFVAL
25585 #undef LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT
25586 #undef LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK
25587 #define LPD_XPPU_CFG_MASTER_ID07_MIDM_DEFVAL                                       0x83C30083
25588 #define LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT                                        16
25589 #define LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK                                         0x03FF0000U
25590
25591 /*Predefined Master ID for A53 Core 3*/
25592 #undef LPD_XPPU_CFG_MASTER_ID07_MID_DEFVAL
25593 #undef LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT
25594 #undef LPD_XPPU_CFG_MASTER_ID07_MID_MASK
25595 #define LPD_XPPU_CFG_MASTER_ID07_MID_DEFVAL                                        0x83C30083
25596 #define LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT                                         0
25597 #define LPD_XPPU_CFG_MASTER_ID07_MID_MASK                                          0x000003FFU
25598
25599 /*If set, only read transactions are allowed for the masters matching this register*/
25600 #undef LPD_XPPU_CFG_MASTER_ID19_MIDR_DEFVAL
25601 #undef LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT
25602 #undef LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK
25603 #define LPD_XPPU_CFG_MASTER_ID19_MIDR_DEFVAL                                       0x00000000
25604 #define LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT                                        30
25605 #define LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK                                         0x40000000U
25606
25607 /*Mask to be applied before comparing*/
25608 #undef LPD_XPPU_CFG_MASTER_ID19_MIDM_DEFVAL
25609 #undef LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT
25610 #undef LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK
25611 #define LPD_XPPU_CFG_MASTER_ID19_MIDM_DEFVAL                                       0x00000000
25612 #define LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT                                        16
25613 #define LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK                                         0x03FF0000U
25614
25615 /*Programmable Master ID*/
25616 #undef LPD_XPPU_CFG_MASTER_ID19_MID_DEFVAL
25617 #undef LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT
25618 #undef LPD_XPPU_CFG_MASTER_ID19_MID_MASK
25619 #define LPD_XPPU_CFG_MASTER_ID19_MID_DEFVAL                                        0x00000000
25620 #define LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT                                         0
25621 #define LPD_XPPU_CFG_MASTER_ID19_MID_MASK                                          0x000003FFU
25622
25623 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25624                 h.*/
25625 #undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_DEFVAL
25626 #undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT
25627 #undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK
25628 #define LPD_XPPU_CFG_APERPERM_048_PERMISSION_DEFVAL                                0x00000000
25629 #define LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT                                 0
25630 #define LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK                                  0x000FFFFFU
25631
25632 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25633 #undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_DEFVAL
25634 #undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT
25635 #undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK
25636 #define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_DEFVAL                                 0x00000000
25637 #define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT                                  27
25638 #define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK                                   0x08000000U
25639
25640 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25641                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25642 #undef LPD_XPPU_CFG_APERPERM_048_PARITY_DEFVAL
25643 #undef LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT
25644 #undef LPD_XPPU_CFG_APERPERM_048_PARITY_MASK
25645 #define LPD_XPPU_CFG_APERPERM_048_PARITY_DEFVAL                                    0x00000000
25646 #define LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT                                     28
25647 #define LPD_XPPU_CFG_APERPERM_048_PARITY_MASK                                      0xF0000000U
25648
25649 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25650                 h.*/
25651 #undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_DEFVAL
25652 #undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT
25653 #undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK
25654 #define LPD_XPPU_CFG_APERPERM_049_PERMISSION_DEFVAL                                0x00000000
25655 #define LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT                                 0
25656 #define LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK                                  0x000FFFFFU
25657
25658 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25659 #undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_DEFVAL
25660 #undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT
25661 #undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK
25662 #define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_DEFVAL                                 0x00000000
25663 #define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT                                  27
25664 #define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK                                   0x08000000U
25665
25666 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25667                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25668 #undef LPD_XPPU_CFG_APERPERM_049_PARITY_DEFVAL
25669 #undef LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT
25670 #undef LPD_XPPU_CFG_APERPERM_049_PARITY_MASK
25671 #define LPD_XPPU_CFG_APERPERM_049_PARITY_DEFVAL                                    0x00000000
25672 #define LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT                                     28
25673 #define LPD_XPPU_CFG_APERPERM_049_PARITY_MASK                                      0xF0000000U
25674
25675 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25676                 h.*/
25677 #undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_DEFVAL
25678 #undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT
25679 #undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK
25680 #define LPD_XPPU_CFG_APERPERM_050_PERMISSION_DEFVAL                                0x00000000
25681 #define LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT                                 0
25682 #define LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK                                  0x000FFFFFU
25683
25684 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25685 #undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_DEFVAL
25686 #undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT
25687 #undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK
25688 #define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_DEFVAL                                 0x00000000
25689 #define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT                                  27
25690 #define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK                                   0x08000000U
25691
25692 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25693                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25694 #undef LPD_XPPU_CFG_APERPERM_050_PARITY_DEFVAL
25695 #undef LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT
25696 #undef LPD_XPPU_CFG_APERPERM_050_PARITY_MASK
25697 #define LPD_XPPU_CFG_APERPERM_050_PARITY_DEFVAL                                    0x00000000
25698 #define LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT                                     28
25699 #define LPD_XPPU_CFG_APERPERM_050_PARITY_MASK                                      0xF0000000U
25700
25701 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25702                 h.*/
25703 #undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_DEFVAL
25704 #undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT
25705 #undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK
25706 #define LPD_XPPU_CFG_APERPERM_051_PERMISSION_DEFVAL                                0x00000000
25707 #define LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT                                 0
25708 #define LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK                                  0x000FFFFFU
25709
25710 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25711 #undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_DEFVAL
25712 #undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT
25713 #undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK
25714 #define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_DEFVAL                                 0x00000000
25715 #define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT                                  27
25716 #define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK                                   0x08000000U
25717
25718 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25719                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25720 #undef LPD_XPPU_CFG_APERPERM_051_PARITY_DEFVAL
25721 #undef LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT
25722 #undef LPD_XPPU_CFG_APERPERM_051_PARITY_MASK
25723 #define LPD_XPPU_CFG_APERPERM_051_PARITY_DEFVAL                                    0x00000000
25724 #define LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT                                     28
25725 #define LPD_XPPU_CFG_APERPERM_051_PARITY_MASK                                      0xF0000000U
25726
25727 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25728                 h.*/
25729 #undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_DEFVAL
25730 #undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT
25731 #undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK
25732 #define LPD_XPPU_CFG_APERPERM_256_PERMISSION_DEFVAL                                0x00000000
25733 #define LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT                                 0
25734 #define LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK                                  0x000FFFFFU
25735
25736 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25737 #undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_DEFVAL
25738 #undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT
25739 #undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK
25740 #define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_DEFVAL                                 0x00000000
25741 #define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT                                  27
25742 #define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK                                   0x08000000U
25743
25744 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25745                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25746 #undef LPD_XPPU_CFG_APERPERM_256_PARITY_DEFVAL
25747 #undef LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT
25748 #undef LPD_XPPU_CFG_APERPERM_256_PARITY_MASK
25749 #define LPD_XPPU_CFG_APERPERM_256_PARITY_DEFVAL                                    0x00000000
25750 #define LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT                                     28
25751 #define LPD_XPPU_CFG_APERPERM_256_PARITY_MASK                                      0xF0000000U
25752
25753 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25754                 h.*/
25755 #undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_DEFVAL
25756 #undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT
25757 #undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK
25758 #define LPD_XPPU_CFG_APERPERM_257_PERMISSION_DEFVAL                                0x00000000
25759 #define LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT                                 0
25760 #define LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK                                  0x000FFFFFU
25761
25762 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25763 #undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_DEFVAL
25764 #undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT
25765 #undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK
25766 #define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_DEFVAL                                 0x00000000
25767 #define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT                                  27
25768 #define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK                                   0x08000000U
25769
25770 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25771                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25772 #undef LPD_XPPU_CFG_APERPERM_257_PARITY_DEFVAL
25773 #undef LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT
25774 #undef LPD_XPPU_CFG_APERPERM_257_PARITY_MASK
25775 #define LPD_XPPU_CFG_APERPERM_257_PARITY_DEFVAL                                    0x00000000
25776 #define LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT                                     28
25777 #define LPD_XPPU_CFG_APERPERM_257_PARITY_MASK                                      0xF0000000U
25778
25779 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25780                 h.*/
25781 #undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_DEFVAL
25782 #undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT
25783 #undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK
25784 #define LPD_XPPU_CFG_APERPERM_258_PERMISSION_DEFVAL                                0x00000000
25785 #define LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT                                 0
25786 #define LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK                                  0x000FFFFFU
25787
25788 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25789 #undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_DEFVAL
25790 #undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT
25791 #undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK
25792 #define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_DEFVAL                                 0x00000000
25793 #define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT                                  27
25794 #define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK                                   0x08000000U
25795
25796 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25797                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25798 #undef LPD_XPPU_CFG_APERPERM_258_PARITY_DEFVAL
25799 #undef LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT
25800 #undef LPD_XPPU_CFG_APERPERM_258_PARITY_MASK
25801 #define LPD_XPPU_CFG_APERPERM_258_PARITY_DEFVAL                                    0x00000000
25802 #define LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT                                     28
25803 #define LPD_XPPU_CFG_APERPERM_258_PARITY_MASK                                      0xF0000000U
25804
25805 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25806                 h.*/
25807 #undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_DEFVAL
25808 #undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT
25809 #undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK
25810 #define LPD_XPPU_CFG_APERPERM_259_PERMISSION_DEFVAL                                0x00000000
25811 #define LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT                                 0
25812 #define LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK                                  0x000FFFFFU
25813
25814 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25815 #undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_DEFVAL
25816 #undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT
25817 #undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK
25818 #define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_DEFVAL                                 0x00000000
25819 #define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT                                  27
25820 #define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK                                   0x08000000U
25821
25822 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25823                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25824 #undef LPD_XPPU_CFG_APERPERM_259_PARITY_DEFVAL
25825 #undef LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT
25826 #undef LPD_XPPU_CFG_APERPERM_259_PARITY_MASK
25827 #define LPD_XPPU_CFG_APERPERM_259_PARITY_DEFVAL                                    0x00000000
25828 #define LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT                                     28
25829 #define LPD_XPPU_CFG_APERPERM_259_PARITY_MASK                                      0xF0000000U
25830
25831 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25832                 h.*/
25833 #undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_DEFVAL
25834 #undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT
25835 #undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK
25836 #define LPD_XPPU_CFG_APERPERM_260_PERMISSION_DEFVAL                                0x00000000
25837 #define LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT                                 0
25838 #define LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK                                  0x000FFFFFU
25839
25840 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25841 #undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_DEFVAL
25842 #undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT
25843 #undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK
25844 #define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_DEFVAL                                 0x00000000
25845 #define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT                                  27
25846 #define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK                                   0x08000000U
25847
25848 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25849                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25850 #undef LPD_XPPU_CFG_APERPERM_260_PARITY_DEFVAL
25851 #undef LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT
25852 #undef LPD_XPPU_CFG_APERPERM_260_PARITY_MASK
25853 #define LPD_XPPU_CFG_APERPERM_260_PARITY_DEFVAL                                    0x00000000
25854 #define LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT                                     28
25855 #define LPD_XPPU_CFG_APERPERM_260_PARITY_MASK                                      0xF0000000U
25856
25857 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25858                 h.*/
25859 #undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_DEFVAL
25860 #undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT
25861 #undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK
25862 #define LPD_XPPU_CFG_APERPERM_261_PERMISSION_DEFVAL                                0x00000000
25863 #define LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT                                 0
25864 #define LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK                                  0x000FFFFFU
25865
25866 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25867 #undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_DEFVAL
25868 #undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT
25869 #undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK
25870 #define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_DEFVAL                                 0x00000000
25871 #define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT                                  27
25872 #define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK                                   0x08000000U
25873
25874 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25875                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25876 #undef LPD_XPPU_CFG_APERPERM_261_PARITY_DEFVAL
25877 #undef LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT
25878 #undef LPD_XPPU_CFG_APERPERM_261_PARITY_MASK
25879 #define LPD_XPPU_CFG_APERPERM_261_PARITY_DEFVAL                                    0x00000000
25880 #define LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT                                     28
25881 #define LPD_XPPU_CFG_APERPERM_261_PARITY_MASK                                      0xF0000000U
25882
25883 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25884                 h.*/
25885 #undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_DEFVAL
25886 #undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT
25887 #undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK
25888 #define LPD_XPPU_CFG_APERPERM_262_PERMISSION_DEFVAL                                0x00000000
25889 #define LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT                                 0
25890 #define LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK                                  0x000FFFFFU
25891
25892 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25893 #undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_DEFVAL
25894 #undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT
25895 #undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK
25896 #define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_DEFVAL                                 0x00000000
25897 #define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT                                  27
25898 #define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK                                   0x08000000U
25899
25900 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25901                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25902 #undef LPD_XPPU_CFG_APERPERM_262_PARITY_DEFVAL
25903 #undef LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT
25904 #undef LPD_XPPU_CFG_APERPERM_262_PARITY_MASK
25905 #define LPD_XPPU_CFG_APERPERM_262_PARITY_DEFVAL                                    0x00000000
25906 #define LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT                                     28
25907 #define LPD_XPPU_CFG_APERPERM_262_PARITY_MASK                                      0xF0000000U
25908
25909 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25910                 h.*/
25911 #undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_DEFVAL
25912 #undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT
25913 #undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK
25914 #define LPD_XPPU_CFG_APERPERM_263_PERMISSION_DEFVAL                                0x00000000
25915 #define LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT                                 0
25916 #define LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK                                  0x000FFFFFU
25917
25918 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25919 #undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_DEFVAL
25920 #undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT
25921 #undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK
25922 #define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_DEFVAL                                 0x00000000
25923 #define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT                                  27
25924 #define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK                                   0x08000000U
25925
25926 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25927                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25928 #undef LPD_XPPU_CFG_APERPERM_263_PARITY_DEFVAL
25929 #undef LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT
25930 #undef LPD_XPPU_CFG_APERPERM_263_PARITY_MASK
25931 #define LPD_XPPU_CFG_APERPERM_263_PARITY_DEFVAL                                    0x00000000
25932 #define LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT                                     28
25933 #define LPD_XPPU_CFG_APERPERM_263_PARITY_MASK                                      0xF0000000U
25934
25935 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25936                 h.*/
25937 #undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_DEFVAL
25938 #undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT
25939 #undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK
25940 #define LPD_XPPU_CFG_APERPERM_264_PERMISSION_DEFVAL                                0x00000000
25941 #define LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT                                 0
25942 #define LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK                                  0x000FFFFFU
25943
25944 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25945 #undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_DEFVAL
25946 #undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT
25947 #undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK
25948 #define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_DEFVAL                                 0x00000000
25949 #define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT                                  27
25950 #define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK                                   0x08000000U
25951
25952 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25953                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25954 #undef LPD_XPPU_CFG_APERPERM_264_PARITY_DEFVAL
25955 #undef LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT
25956 #undef LPD_XPPU_CFG_APERPERM_264_PARITY_MASK
25957 #define LPD_XPPU_CFG_APERPERM_264_PARITY_DEFVAL                                    0x00000000
25958 #define LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT                                     28
25959 #define LPD_XPPU_CFG_APERPERM_264_PARITY_MASK                                      0xF0000000U
25960
25961 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25962                 h.*/
25963 #undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_DEFVAL
25964 #undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT
25965 #undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK
25966 #define LPD_XPPU_CFG_APERPERM_265_PERMISSION_DEFVAL                                0x00000000
25967 #define LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT                                 0
25968 #define LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK                                  0x000FFFFFU
25969
25970 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25971 #undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_DEFVAL
25972 #undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT
25973 #undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK
25974 #define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_DEFVAL                                 0x00000000
25975 #define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT                                  27
25976 #define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK                                   0x08000000U
25977
25978 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
25979                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
25980 #undef LPD_XPPU_CFG_APERPERM_265_PARITY_DEFVAL
25981 #undef LPD_XPPU_CFG_APERPERM_265_PARITY_SHIFT
25982 #undef LPD_XPPU_CFG_APERPERM_265_PARITY_MASK
25983 #define LPD_XPPU_CFG_APERPERM_265_PARITY_DEFVAL                                    0x00000000
25984 #define LPD_XPPU_CFG_APERPERM_265_PARITY_SHIFT                                     28
25985 #define LPD_XPPU_CFG_APERPERM_265_PARITY_MASK                                      0xF0000000U
25986
25987 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
25988                 h.*/
25989 #undef LPD_XPPU_CFG_APERPERM_266_PERMISSION_DEFVAL
25990 #undef LPD_XPPU_CFG_APERPERM_266_PERMISSION_SHIFT
25991 #undef LPD_XPPU_CFG_APERPERM_266_PERMISSION_MASK
25992 #define LPD_XPPU_CFG_APERPERM_266_PERMISSION_DEFVAL                                0x00000000
25993 #define LPD_XPPU_CFG_APERPERM_266_PERMISSION_SHIFT                                 0
25994 #define LPD_XPPU_CFG_APERPERM_266_PERMISSION_MASK                                  0x000FFFFFU
25995
25996 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
25997 #undef LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_DEFVAL
25998 #undef LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_SHIFT
25999 #undef LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_MASK
26000 #define LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_DEFVAL                                 0x00000000
26001 #define LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_SHIFT                                  27
26002 #define LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_MASK                                   0x08000000U
26003
26004 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26005                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26006 #undef LPD_XPPU_CFG_APERPERM_266_PARITY_DEFVAL
26007 #undef LPD_XPPU_CFG_APERPERM_266_PARITY_SHIFT
26008 #undef LPD_XPPU_CFG_APERPERM_266_PARITY_MASK
26009 #define LPD_XPPU_CFG_APERPERM_266_PARITY_DEFVAL                                    0x00000000
26010 #define LPD_XPPU_CFG_APERPERM_266_PARITY_SHIFT                                     28
26011 #define LPD_XPPU_CFG_APERPERM_266_PARITY_MASK                                      0xF0000000U
26012
26013 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26014                 h.*/
26015 #undef LPD_XPPU_CFG_APERPERM_267_PERMISSION_DEFVAL
26016 #undef LPD_XPPU_CFG_APERPERM_267_PERMISSION_SHIFT
26017 #undef LPD_XPPU_CFG_APERPERM_267_PERMISSION_MASK
26018 #define LPD_XPPU_CFG_APERPERM_267_PERMISSION_DEFVAL                                0x00000000
26019 #define LPD_XPPU_CFG_APERPERM_267_PERMISSION_SHIFT                                 0
26020 #define LPD_XPPU_CFG_APERPERM_267_PERMISSION_MASK                                  0x000FFFFFU
26021
26022 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26023 #undef LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_DEFVAL
26024 #undef LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_SHIFT
26025 #undef LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_MASK
26026 #define LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_DEFVAL                                 0x00000000
26027 #define LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_SHIFT                                  27
26028 #define LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_MASK                                   0x08000000U
26029
26030 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26031                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26032 #undef LPD_XPPU_CFG_APERPERM_267_PARITY_DEFVAL
26033 #undef LPD_XPPU_CFG_APERPERM_267_PARITY_SHIFT
26034 #undef LPD_XPPU_CFG_APERPERM_267_PARITY_MASK
26035 #define LPD_XPPU_CFG_APERPERM_267_PARITY_DEFVAL                                    0x00000000
26036 #define LPD_XPPU_CFG_APERPERM_267_PARITY_SHIFT                                     28
26037 #define LPD_XPPU_CFG_APERPERM_267_PARITY_MASK                                      0xF0000000U
26038
26039 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26040                 h.*/
26041 #undef LPD_XPPU_CFG_APERPERM_268_PERMISSION_DEFVAL
26042 #undef LPD_XPPU_CFG_APERPERM_268_PERMISSION_SHIFT
26043 #undef LPD_XPPU_CFG_APERPERM_268_PERMISSION_MASK
26044 #define LPD_XPPU_CFG_APERPERM_268_PERMISSION_DEFVAL                                0x00000000
26045 #define LPD_XPPU_CFG_APERPERM_268_PERMISSION_SHIFT                                 0
26046 #define LPD_XPPU_CFG_APERPERM_268_PERMISSION_MASK                                  0x000FFFFFU
26047
26048 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26049 #undef LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_DEFVAL
26050 #undef LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_SHIFT
26051 #undef LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_MASK
26052 #define LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_DEFVAL                                 0x00000000
26053 #define LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_SHIFT                                  27
26054 #define LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_MASK                                   0x08000000U
26055
26056 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26057                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26058 #undef LPD_XPPU_CFG_APERPERM_268_PARITY_DEFVAL
26059 #undef LPD_XPPU_CFG_APERPERM_268_PARITY_SHIFT
26060 #undef LPD_XPPU_CFG_APERPERM_268_PARITY_MASK
26061 #define LPD_XPPU_CFG_APERPERM_268_PARITY_DEFVAL                                    0x00000000
26062 #define LPD_XPPU_CFG_APERPERM_268_PARITY_SHIFT                                     28
26063 #define LPD_XPPU_CFG_APERPERM_268_PARITY_MASK                                      0xF0000000U
26064
26065 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26066                 h.*/
26067 #undef LPD_XPPU_CFG_APERPERM_269_PERMISSION_DEFVAL
26068 #undef LPD_XPPU_CFG_APERPERM_269_PERMISSION_SHIFT
26069 #undef LPD_XPPU_CFG_APERPERM_269_PERMISSION_MASK
26070 #define LPD_XPPU_CFG_APERPERM_269_PERMISSION_DEFVAL                                0x00000000
26071 #define LPD_XPPU_CFG_APERPERM_269_PERMISSION_SHIFT                                 0
26072 #define LPD_XPPU_CFG_APERPERM_269_PERMISSION_MASK                                  0x000FFFFFU
26073
26074 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26075 #undef LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_DEFVAL
26076 #undef LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_SHIFT
26077 #undef LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_MASK
26078 #define LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_DEFVAL                                 0x00000000
26079 #define LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_SHIFT                                  27
26080 #define LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_MASK                                   0x08000000U
26081
26082 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26083                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26084 #undef LPD_XPPU_CFG_APERPERM_269_PARITY_DEFVAL
26085 #undef LPD_XPPU_CFG_APERPERM_269_PARITY_SHIFT
26086 #undef LPD_XPPU_CFG_APERPERM_269_PARITY_MASK
26087 #define LPD_XPPU_CFG_APERPERM_269_PARITY_DEFVAL                                    0x00000000
26088 #define LPD_XPPU_CFG_APERPERM_269_PARITY_SHIFT                                     28
26089 #define LPD_XPPU_CFG_APERPERM_269_PARITY_MASK                                      0xF0000000U
26090
26091 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26092                 h.*/
26093 #undef LPD_XPPU_CFG_APERPERM_270_PERMISSION_DEFVAL
26094 #undef LPD_XPPU_CFG_APERPERM_270_PERMISSION_SHIFT
26095 #undef LPD_XPPU_CFG_APERPERM_270_PERMISSION_MASK
26096 #define LPD_XPPU_CFG_APERPERM_270_PERMISSION_DEFVAL                                0x00000000
26097 #define LPD_XPPU_CFG_APERPERM_270_PERMISSION_SHIFT                                 0
26098 #define LPD_XPPU_CFG_APERPERM_270_PERMISSION_MASK                                  0x000FFFFFU
26099
26100 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26101 #undef LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_DEFVAL
26102 #undef LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_SHIFT
26103 #undef LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_MASK
26104 #define LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_DEFVAL                                 0x00000000
26105 #define LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_SHIFT                                  27
26106 #define LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_MASK                                   0x08000000U
26107
26108 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26109                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26110 #undef LPD_XPPU_CFG_APERPERM_270_PARITY_DEFVAL
26111 #undef LPD_XPPU_CFG_APERPERM_270_PARITY_SHIFT
26112 #undef LPD_XPPU_CFG_APERPERM_270_PARITY_MASK
26113 #define LPD_XPPU_CFG_APERPERM_270_PARITY_DEFVAL                                    0x00000000
26114 #define LPD_XPPU_CFG_APERPERM_270_PARITY_SHIFT                                     28
26115 #define LPD_XPPU_CFG_APERPERM_270_PARITY_MASK                                      0xF0000000U
26116
26117 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26118                 h.*/
26119 #undef LPD_XPPU_CFG_APERPERM_271_PERMISSION_DEFVAL
26120 #undef LPD_XPPU_CFG_APERPERM_271_PERMISSION_SHIFT
26121 #undef LPD_XPPU_CFG_APERPERM_271_PERMISSION_MASK
26122 #define LPD_XPPU_CFG_APERPERM_271_PERMISSION_DEFVAL                                0x00000000
26123 #define LPD_XPPU_CFG_APERPERM_271_PERMISSION_SHIFT                                 0
26124 #define LPD_XPPU_CFG_APERPERM_271_PERMISSION_MASK                                  0x000FFFFFU
26125
26126 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26127 #undef LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_DEFVAL
26128 #undef LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_SHIFT
26129 #undef LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_MASK
26130 #define LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_DEFVAL                                 0x00000000
26131 #define LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_SHIFT                                  27
26132 #define LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_MASK                                   0x08000000U
26133
26134 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26135                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26136 #undef LPD_XPPU_CFG_APERPERM_271_PARITY_DEFVAL
26137 #undef LPD_XPPU_CFG_APERPERM_271_PARITY_SHIFT
26138 #undef LPD_XPPU_CFG_APERPERM_271_PARITY_MASK
26139 #define LPD_XPPU_CFG_APERPERM_271_PARITY_DEFVAL                                    0x00000000
26140 #define LPD_XPPU_CFG_APERPERM_271_PARITY_SHIFT                                     28
26141 #define LPD_XPPU_CFG_APERPERM_271_PARITY_MASK                                      0xF0000000U
26142
26143 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26144                 h.*/
26145 #undef LPD_XPPU_CFG_APERPERM_272_PERMISSION_DEFVAL
26146 #undef LPD_XPPU_CFG_APERPERM_272_PERMISSION_SHIFT
26147 #undef LPD_XPPU_CFG_APERPERM_272_PERMISSION_MASK
26148 #define LPD_XPPU_CFG_APERPERM_272_PERMISSION_DEFVAL                                0x00000000
26149 #define LPD_XPPU_CFG_APERPERM_272_PERMISSION_SHIFT                                 0
26150 #define LPD_XPPU_CFG_APERPERM_272_PERMISSION_MASK                                  0x000FFFFFU
26151
26152 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26153 #undef LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_DEFVAL
26154 #undef LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_SHIFT
26155 #undef LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_MASK
26156 #define LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_DEFVAL                                 0x00000000
26157 #define LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_SHIFT                                  27
26158 #define LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_MASK                                   0x08000000U
26159
26160 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26161                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26162 #undef LPD_XPPU_CFG_APERPERM_272_PARITY_DEFVAL
26163 #undef LPD_XPPU_CFG_APERPERM_272_PARITY_SHIFT
26164 #undef LPD_XPPU_CFG_APERPERM_272_PARITY_MASK
26165 #define LPD_XPPU_CFG_APERPERM_272_PARITY_DEFVAL                                    0x00000000
26166 #define LPD_XPPU_CFG_APERPERM_272_PARITY_SHIFT                                     28
26167 #define LPD_XPPU_CFG_APERPERM_272_PARITY_MASK                                      0xF0000000U
26168
26169 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26170                 h.*/
26171 #undef LPD_XPPU_CFG_APERPERM_273_PERMISSION_DEFVAL
26172 #undef LPD_XPPU_CFG_APERPERM_273_PERMISSION_SHIFT
26173 #undef LPD_XPPU_CFG_APERPERM_273_PERMISSION_MASK
26174 #define LPD_XPPU_CFG_APERPERM_273_PERMISSION_DEFVAL                                0x00000000
26175 #define LPD_XPPU_CFG_APERPERM_273_PERMISSION_SHIFT                                 0
26176 #define LPD_XPPU_CFG_APERPERM_273_PERMISSION_MASK                                  0x000FFFFFU
26177
26178 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26179 #undef LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_DEFVAL
26180 #undef LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_SHIFT
26181 #undef LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_MASK
26182 #define LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_DEFVAL                                 0x00000000
26183 #define LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_SHIFT                                  27
26184 #define LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_MASK                                   0x08000000U
26185
26186 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26187                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26188 #undef LPD_XPPU_CFG_APERPERM_273_PARITY_DEFVAL
26189 #undef LPD_XPPU_CFG_APERPERM_273_PARITY_SHIFT
26190 #undef LPD_XPPU_CFG_APERPERM_273_PARITY_MASK
26191 #define LPD_XPPU_CFG_APERPERM_273_PARITY_DEFVAL                                    0x00000000
26192 #define LPD_XPPU_CFG_APERPERM_273_PARITY_SHIFT                                     28
26193 #define LPD_XPPU_CFG_APERPERM_273_PARITY_MASK                                      0xF0000000U
26194
26195 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26196                 h.*/
26197 #undef LPD_XPPU_CFG_APERPERM_274_PERMISSION_DEFVAL
26198 #undef LPD_XPPU_CFG_APERPERM_274_PERMISSION_SHIFT
26199 #undef LPD_XPPU_CFG_APERPERM_274_PERMISSION_MASK
26200 #define LPD_XPPU_CFG_APERPERM_274_PERMISSION_DEFVAL                                0x00000000
26201 #define LPD_XPPU_CFG_APERPERM_274_PERMISSION_SHIFT                                 0
26202 #define LPD_XPPU_CFG_APERPERM_274_PERMISSION_MASK                                  0x000FFFFFU
26203
26204 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26205 #undef LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_DEFVAL
26206 #undef LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_SHIFT
26207 #undef LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_MASK
26208 #define LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_DEFVAL                                 0x00000000
26209 #define LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_SHIFT                                  27
26210 #define LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_MASK                                   0x08000000U
26211
26212 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26213                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26214 #undef LPD_XPPU_CFG_APERPERM_274_PARITY_DEFVAL
26215 #undef LPD_XPPU_CFG_APERPERM_274_PARITY_SHIFT
26216 #undef LPD_XPPU_CFG_APERPERM_274_PARITY_MASK
26217 #define LPD_XPPU_CFG_APERPERM_274_PARITY_DEFVAL                                    0x00000000
26218 #define LPD_XPPU_CFG_APERPERM_274_PARITY_SHIFT                                     28
26219 #define LPD_XPPU_CFG_APERPERM_274_PARITY_MASK                                      0xF0000000U
26220
26221 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26222                 h.*/
26223 #undef LPD_XPPU_CFG_APERPERM_275_PERMISSION_DEFVAL
26224 #undef LPD_XPPU_CFG_APERPERM_275_PERMISSION_SHIFT
26225 #undef LPD_XPPU_CFG_APERPERM_275_PERMISSION_MASK
26226 #define LPD_XPPU_CFG_APERPERM_275_PERMISSION_DEFVAL                                0x00000000
26227 #define LPD_XPPU_CFG_APERPERM_275_PERMISSION_SHIFT                                 0
26228 #define LPD_XPPU_CFG_APERPERM_275_PERMISSION_MASK                                  0x000FFFFFU
26229
26230 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26231 #undef LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_DEFVAL
26232 #undef LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_SHIFT
26233 #undef LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_MASK
26234 #define LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_DEFVAL                                 0x00000000
26235 #define LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_SHIFT                                  27
26236 #define LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_MASK                                   0x08000000U
26237
26238 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26239                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26240 #undef LPD_XPPU_CFG_APERPERM_275_PARITY_DEFVAL
26241 #undef LPD_XPPU_CFG_APERPERM_275_PARITY_SHIFT
26242 #undef LPD_XPPU_CFG_APERPERM_275_PARITY_MASK
26243 #define LPD_XPPU_CFG_APERPERM_275_PARITY_DEFVAL                                    0x00000000
26244 #define LPD_XPPU_CFG_APERPERM_275_PARITY_SHIFT                                     28
26245 #define LPD_XPPU_CFG_APERPERM_275_PARITY_MASK                                      0xF0000000U
26246
26247 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26248                 h.*/
26249 #undef LPD_XPPU_CFG_APERPERM_276_PERMISSION_DEFVAL
26250 #undef LPD_XPPU_CFG_APERPERM_276_PERMISSION_SHIFT
26251 #undef LPD_XPPU_CFG_APERPERM_276_PERMISSION_MASK
26252 #define LPD_XPPU_CFG_APERPERM_276_PERMISSION_DEFVAL                                0x00000000
26253 #define LPD_XPPU_CFG_APERPERM_276_PERMISSION_SHIFT                                 0
26254 #define LPD_XPPU_CFG_APERPERM_276_PERMISSION_MASK                                  0x000FFFFFU
26255
26256 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26257 #undef LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_DEFVAL
26258 #undef LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_SHIFT
26259 #undef LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_MASK
26260 #define LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_DEFVAL                                 0x00000000
26261 #define LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_SHIFT                                  27
26262 #define LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_MASK                                   0x08000000U
26263
26264 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26265                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26266 #undef LPD_XPPU_CFG_APERPERM_276_PARITY_DEFVAL
26267 #undef LPD_XPPU_CFG_APERPERM_276_PARITY_SHIFT
26268 #undef LPD_XPPU_CFG_APERPERM_276_PARITY_MASK
26269 #define LPD_XPPU_CFG_APERPERM_276_PARITY_DEFVAL                                    0x00000000
26270 #define LPD_XPPU_CFG_APERPERM_276_PARITY_SHIFT                                     28
26271 #define LPD_XPPU_CFG_APERPERM_276_PARITY_MASK                                      0xF0000000U
26272
26273 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26274                 h.*/
26275 #undef LPD_XPPU_CFG_APERPERM_277_PERMISSION_DEFVAL
26276 #undef LPD_XPPU_CFG_APERPERM_277_PERMISSION_SHIFT
26277 #undef LPD_XPPU_CFG_APERPERM_277_PERMISSION_MASK
26278 #define LPD_XPPU_CFG_APERPERM_277_PERMISSION_DEFVAL                                0x00000000
26279 #define LPD_XPPU_CFG_APERPERM_277_PERMISSION_SHIFT                                 0
26280 #define LPD_XPPU_CFG_APERPERM_277_PERMISSION_MASK                                  0x000FFFFFU
26281
26282 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26283 #undef LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_DEFVAL
26284 #undef LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_SHIFT
26285 #undef LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_MASK
26286 #define LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_DEFVAL                                 0x00000000
26287 #define LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_SHIFT                                  27
26288 #define LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_MASK                                   0x08000000U
26289
26290 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26291                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26292 #undef LPD_XPPU_CFG_APERPERM_277_PARITY_DEFVAL
26293 #undef LPD_XPPU_CFG_APERPERM_277_PARITY_SHIFT
26294 #undef LPD_XPPU_CFG_APERPERM_277_PARITY_MASK
26295 #define LPD_XPPU_CFG_APERPERM_277_PARITY_DEFVAL                                    0x00000000
26296 #define LPD_XPPU_CFG_APERPERM_277_PARITY_SHIFT                                     28
26297 #define LPD_XPPU_CFG_APERPERM_277_PARITY_MASK                                      0xF0000000U
26298
26299 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26300                 h.*/
26301 #undef LPD_XPPU_CFG_APERPERM_278_PERMISSION_DEFVAL
26302 #undef LPD_XPPU_CFG_APERPERM_278_PERMISSION_SHIFT
26303 #undef LPD_XPPU_CFG_APERPERM_278_PERMISSION_MASK
26304 #define LPD_XPPU_CFG_APERPERM_278_PERMISSION_DEFVAL                                0x00000000
26305 #define LPD_XPPU_CFG_APERPERM_278_PERMISSION_SHIFT                                 0
26306 #define LPD_XPPU_CFG_APERPERM_278_PERMISSION_MASK                                  0x000FFFFFU
26307
26308 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26309 #undef LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_DEFVAL
26310 #undef LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_SHIFT
26311 #undef LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_MASK
26312 #define LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_DEFVAL                                 0x00000000
26313 #define LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_SHIFT                                  27
26314 #define LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_MASK                                   0x08000000U
26315
26316 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26317                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26318 #undef LPD_XPPU_CFG_APERPERM_278_PARITY_DEFVAL
26319 #undef LPD_XPPU_CFG_APERPERM_278_PARITY_SHIFT
26320 #undef LPD_XPPU_CFG_APERPERM_278_PARITY_MASK
26321 #define LPD_XPPU_CFG_APERPERM_278_PARITY_DEFVAL                                    0x00000000
26322 #define LPD_XPPU_CFG_APERPERM_278_PARITY_SHIFT                                     28
26323 #define LPD_XPPU_CFG_APERPERM_278_PARITY_MASK                                      0xF0000000U
26324
26325 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26326                 h.*/
26327 #undef LPD_XPPU_CFG_APERPERM_279_PERMISSION_DEFVAL
26328 #undef LPD_XPPU_CFG_APERPERM_279_PERMISSION_SHIFT
26329 #undef LPD_XPPU_CFG_APERPERM_279_PERMISSION_MASK
26330 #define LPD_XPPU_CFG_APERPERM_279_PERMISSION_DEFVAL                                0x00000000
26331 #define LPD_XPPU_CFG_APERPERM_279_PERMISSION_SHIFT                                 0
26332 #define LPD_XPPU_CFG_APERPERM_279_PERMISSION_MASK                                  0x000FFFFFU
26333
26334 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26335 #undef LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_DEFVAL
26336 #undef LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_SHIFT
26337 #undef LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_MASK
26338 #define LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_DEFVAL                                 0x00000000
26339 #define LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_SHIFT                                  27
26340 #define LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_MASK                                   0x08000000U
26341
26342 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26343                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26344 #undef LPD_XPPU_CFG_APERPERM_279_PARITY_DEFVAL
26345 #undef LPD_XPPU_CFG_APERPERM_279_PARITY_SHIFT
26346 #undef LPD_XPPU_CFG_APERPERM_279_PARITY_MASK
26347 #define LPD_XPPU_CFG_APERPERM_279_PARITY_DEFVAL                                    0x00000000
26348 #define LPD_XPPU_CFG_APERPERM_279_PARITY_SHIFT                                     28
26349 #define LPD_XPPU_CFG_APERPERM_279_PARITY_MASK                                      0xF0000000U
26350
26351 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26352                 h.*/
26353 #undef LPD_XPPU_CFG_APERPERM_280_PERMISSION_DEFVAL
26354 #undef LPD_XPPU_CFG_APERPERM_280_PERMISSION_SHIFT
26355 #undef LPD_XPPU_CFG_APERPERM_280_PERMISSION_MASK
26356 #define LPD_XPPU_CFG_APERPERM_280_PERMISSION_DEFVAL                                0x00000000
26357 #define LPD_XPPU_CFG_APERPERM_280_PERMISSION_SHIFT                                 0
26358 #define LPD_XPPU_CFG_APERPERM_280_PERMISSION_MASK                                  0x000FFFFFU
26359
26360 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26361 #undef LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_DEFVAL
26362 #undef LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_SHIFT
26363 #undef LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_MASK
26364 #define LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_DEFVAL                                 0x00000000
26365 #define LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_SHIFT                                  27
26366 #define LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_MASK                                   0x08000000U
26367
26368 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26369                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26370 #undef LPD_XPPU_CFG_APERPERM_280_PARITY_DEFVAL
26371 #undef LPD_XPPU_CFG_APERPERM_280_PARITY_SHIFT
26372 #undef LPD_XPPU_CFG_APERPERM_280_PARITY_MASK
26373 #define LPD_XPPU_CFG_APERPERM_280_PARITY_DEFVAL                                    0x00000000
26374 #define LPD_XPPU_CFG_APERPERM_280_PARITY_SHIFT                                     28
26375 #define LPD_XPPU_CFG_APERPERM_280_PARITY_MASK                                      0xF0000000U
26376
26377 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26378                 h.*/
26379 #undef LPD_XPPU_CFG_APERPERM_281_PERMISSION_DEFVAL
26380 #undef LPD_XPPU_CFG_APERPERM_281_PERMISSION_SHIFT
26381 #undef LPD_XPPU_CFG_APERPERM_281_PERMISSION_MASK
26382 #define LPD_XPPU_CFG_APERPERM_281_PERMISSION_DEFVAL                                0x00000000
26383 #define LPD_XPPU_CFG_APERPERM_281_PERMISSION_SHIFT                                 0
26384 #define LPD_XPPU_CFG_APERPERM_281_PERMISSION_MASK                                  0x000FFFFFU
26385
26386 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26387 #undef LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_DEFVAL
26388 #undef LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_SHIFT
26389 #undef LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_MASK
26390 #define LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_DEFVAL                                 0x00000000
26391 #define LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_SHIFT                                  27
26392 #define LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_MASK                                   0x08000000U
26393
26394 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26395                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26396 #undef LPD_XPPU_CFG_APERPERM_281_PARITY_DEFVAL
26397 #undef LPD_XPPU_CFG_APERPERM_281_PARITY_SHIFT
26398 #undef LPD_XPPU_CFG_APERPERM_281_PARITY_MASK
26399 #define LPD_XPPU_CFG_APERPERM_281_PARITY_DEFVAL                                    0x00000000
26400 #define LPD_XPPU_CFG_APERPERM_281_PARITY_SHIFT                                     28
26401 #define LPD_XPPU_CFG_APERPERM_281_PARITY_MASK                                      0xF0000000U
26402
26403 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26404                 h.*/
26405 #undef LPD_XPPU_CFG_APERPERM_282_PERMISSION_DEFVAL
26406 #undef LPD_XPPU_CFG_APERPERM_282_PERMISSION_SHIFT
26407 #undef LPD_XPPU_CFG_APERPERM_282_PERMISSION_MASK
26408 #define LPD_XPPU_CFG_APERPERM_282_PERMISSION_DEFVAL                                0x00000000
26409 #define LPD_XPPU_CFG_APERPERM_282_PERMISSION_SHIFT                                 0
26410 #define LPD_XPPU_CFG_APERPERM_282_PERMISSION_MASK                                  0x000FFFFFU
26411
26412 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26413 #undef LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_DEFVAL
26414 #undef LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_SHIFT
26415 #undef LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_MASK
26416 #define LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_DEFVAL                                 0x00000000
26417 #define LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_SHIFT                                  27
26418 #define LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_MASK                                   0x08000000U
26419
26420 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26421                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26422 #undef LPD_XPPU_CFG_APERPERM_282_PARITY_DEFVAL
26423 #undef LPD_XPPU_CFG_APERPERM_282_PARITY_SHIFT
26424 #undef LPD_XPPU_CFG_APERPERM_282_PARITY_MASK
26425 #define LPD_XPPU_CFG_APERPERM_282_PARITY_DEFVAL                                    0x00000000
26426 #define LPD_XPPU_CFG_APERPERM_282_PARITY_SHIFT                                     28
26427 #define LPD_XPPU_CFG_APERPERM_282_PARITY_MASK                                      0xF0000000U
26428
26429 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26430                 h.*/
26431 #undef LPD_XPPU_CFG_APERPERM_283_PERMISSION_DEFVAL
26432 #undef LPD_XPPU_CFG_APERPERM_283_PERMISSION_SHIFT
26433 #undef LPD_XPPU_CFG_APERPERM_283_PERMISSION_MASK
26434 #define LPD_XPPU_CFG_APERPERM_283_PERMISSION_DEFVAL                                0x00000000
26435 #define LPD_XPPU_CFG_APERPERM_283_PERMISSION_SHIFT                                 0
26436 #define LPD_XPPU_CFG_APERPERM_283_PERMISSION_MASK                                  0x000FFFFFU
26437
26438 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26439 #undef LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_DEFVAL
26440 #undef LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_SHIFT
26441 #undef LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_MASK
26442 #define LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_DEFVAL                                 0x00000000
26443 #define LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_SHIFT                                  27
26444 #define LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_MASK                                   0x08000000U
26445
26446 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26447                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26448 #undef LPD_XPPU_CFG_APERPERM_283_PARITY_DEFVAL
26449 #undef LPD_XPPU_CFG_APERPERM_283_PARITY_SHIFT
26450 #undef LPD_XPPU_CFG_APERPERM_283_PARITY_MASK
26451 #define LPD_XPPU_CFG_APERPERM_283_PARITY_DEFVAL                                    0x00000000
26452 #define LPD_XPPU_CFG_APERPERM_283_PARITY_SHIFT                                     28
26453 #define LPD_XPPU_CFG_APERPERM_283_PARITY_MASK                                      0xF0000000U
26454
26455 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26456                 h.*/
26457 #undef LPD_XPPU_CFG_APERPERM_284_PERMISSION_DEFVAL
26458 #undef LPD_XPPU_CFG_APERPERM_284_PERMISSION_SHIFT
26459 #undef LPD_XPPU_CFG_APERPERM_284_PERMISSION_MASK
26460 #define LPD_XPPU_CFG_APERPERM_284_PERMISSION_DEFVAL                                0x00000000
26461 #define LPD_XPPU_CFG_APERPERM_284_PERMISSION_SHIFT                                 0
26462 #define LPD_XPPU_CFG_APERPERM_284_PERMISSION_MASK                                  0x000FFFFFU
26463
26464 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26465 #undef LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_DEFVAL
26466 #undef LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_SHIFT
26467 #undef LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_MASK
26468 #define LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_DEFVAL                                 0x00000000
26469 #define LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_SHIFT                                  27
26470 #define LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_MASK                                   0x08000000U
26471
26472 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26473                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26474 #undef LPD_XPPU_CFG_APERPERM_284_PARITY_DEFVAL
26475 #undef LPD_XPPU_CFG_APERPERM_284_PARITY_SHIFT
26476 #undef LPD_XPPU_CFG_APERPERM_284_PARITY_MASK
26477 #define LPD_XPPU_CFG_APERPERM_284_PARITY_DEFVAL                                    0x00000000
26478 #define LPD_XPPU_CFG_APERPERM_284_PARITY_SHIFT                                     28
26479 #define LPD_XPPU_CFG_APERPERM_284_PARITY_MASK                                      0xF0000000U
26480
26481 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26482                 h.*/
26483 #undef LPD_XPPU_CFG_APERPERM_285_PERMISSION_DEFVAL
26484 #undef LPD_XPPU_CFG_APERPERM_285_PERMISSION_SHIFT
26485 #undef LPD_XPPU_CFG_APERPERM_285_PERMISSION_MASK
26486 #define LPD_XPPU_CFG_APERPERM_285_PERMISSION_DEFVAL                                0x00000000
26487 #define LPD_XPPU_CFG_APERPERM_285_PERMISSION_SHIFT                                 0
26488 #define LPD_XPPU_CFG_APERPERM_285_PERMISSION_MASK                                  0x000FFFFFU
26489
26490 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26491 #undef LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_DEFVAL
26492 #undef LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_SHIFT
26493 #undef LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_MASK
26494 #define LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_DEFVAL                                 0x00000000
26495 #define LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_SHIFT                                  27
26496 #define LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_MASK                                   0x08000000U
26497
26498 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26499                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26500 #undef LPD_XPPU_CFG_APERPERM_285_PARITY_DEFVAL
26501 #undef LPD_XPPU_CFG_APERPERM_285_PARITY_SHIFT
26502 #undef LPD_XPPU_CFG_APERPERM_285_PARITY_MASK
26503 #define LPD_XPPU_CFG_APERPERM_285_PARITY_DEFVAL                                    0x00000000
26504 #define LPD_XPPU_CFG_APERPERM_285_PARITY_SHIFT                                     28
26505 #define LPD_XPPU_CFG_APERPERM_285_PARITY_MASK                                      0xF0000000U
26506
26507 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26508                 h.*/
26509 #undef LPD_XPPU_CFG_APERPERM_286_PERMISSION_DEFVAL
26510 #undef LPD_XPPU_CFG_APERPERM_286_PERMISSION_SHIFT
26511 #undef LPD_XPPU_CFG_APERPERM_286_PERMISSION_MASK
26512 #define LPD_XPPU_CFG_APERPERM_286_PERMISSION_DEFVAL                                0x00000000
26513 #define LPD_XPPU_CFG_APERPERM_286_PERMISSION_SHIFT                                 0
26514 #define LPD_XPPU_CFG_APERPERM_286_PERMISSION_MASK                                  0x000FFFFFU
26515
26516 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26517 #undef LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_DEFVAL
26518 #undef LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_SHIFT
26519 #undef LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_MASK
26520 #define LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_DEFVAL                                 0x00000000
26521 #define LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_SHIFT                                  27
26522 #define LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_MASK                                   0x08000000U
26523
26524 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26525                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26526 #undef LPD_XPPU_CFG_APERPERM_286_PARITY_DEFVAL
26527 #undef LPD_XPPU_CFG_APERPERM_286_PARITY_SHIFT
26528 #undef LPD_XPPU_CFG_APERPERM_286_PARITY_MASK
26529 #define LPD_XPPU_CFG_APERPERM_286_PARITY_DEFVAL                                    0x00000000
26530 #define LPD_XPPU_CFG_APERPERM_286_PARITY_SHIFT                                     28
26531 #define LPD_XPPU_CFG_APERPERM_286_PARITY_MASK                                      0xF0000000U
26532
26533 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26534                 h.*/
26535 #undef LPD_XPPU_CFG_APERPERM_287_PERMISSION_DEFVAL
26536 #undef LPD_XPPU_CFG_APERPERM_287_PERMISSION_SHIFT
26537 #undef LPD_XPPU_CFG_APERPERM_287_PERMISSION_MASK
26538 #define LPD_XPPU_CFG_APERPERM_287_PERMISSION_DEFVAL                                0x00000000
26539 #define LPD_XPPU_CFG_APERPERM_287_PERMISSION_SHIFT                                 0
26540 #define LPD_XPPU_CFG_APERPERM_287_PERMISSION_MASK                                  0x000FFFFFU
26541
26542 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26543 #undef LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_DEFVAL
26544 #undef LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_SHIFT
26545 #undef LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_MASK
26546 #define LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_DEFVAL                                 0x00000000
26547 #define LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_SHIFT                                  27
26548 #define LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_MASK                                   0x08000000U
26549
26550 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26551                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26552 #undef LPD_XPPU_CFG_APERPERM_287_PARITY_DEFVAL
26553 #undef LPD_XPPU_CFG_APERPERM_287_PARITY_SHIFT
26554 #undef LPD_XPPU_CFG_APERPERM_287_PARITY_MASK
26555 #define LPD_XPPU_CFG_APERPERM_287_PARITY_DEFVAL                                    0x00000000
26556 #define LPD_XPPU_CFG_APERPERM_287_PARITY_SHIFT                                     28
26557 #define LPD_XPPU_CFG_APERPERM_287_PARITY_MASK                                      0xF0000000U
26558
26559 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26560                 h.*/
26561 #undef LPD_XPPU_CFG_APERPERM_288_PERMISSION_DEFVAL
26562 #undef LPD_XPPU_CFG_APERPERM_288_PERMISSION_SHIFT
26563 #undef LPD_XPPU_CFG_APERPERM_288_PERMISSION_MASK
26564 #define LPD_XPPU_CFG_APERPERM_288_PERMISSION_DEFVAL                                0x00000000
26565 #define LPD_XPPU_CFG_APERPERM_288_PERMISSION_SHIFT                                 0
26566 #define LPD_XPPU_CFG_APERPERM_288_PERMISSION_MASK                                  0x000FFFFFU
26567
26568 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26569 #undef LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_DEFVAL
26570 #undef LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_SHIFT
26571 #undef LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_MASK
26572 #define LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_DEFVAL                                 0x00000000
26573 #define LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_SHIFT                                  27
26574 #define LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_MASK                                   0x08000000U
26575
26576 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26577                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26578 #undef LPD_XPPU_CFG_APERPERM_288_PARITY_DEFVAL
26579 #undef LPD_XPPU_CFG_APERPERM_288_PARITY_SHIFT
26580 #undef LPD_XPPU_CFG_APERPERM_288_PARITY_MASK
26581 #define LPD_XPPU_CFG_APERPERM_288_PARITY_DEFVAL                                    0x00000000
26582 #define LPD_XPPU_CFG_APERPERM_288_PARITY_SHIFT                                     28
26583 #define LPD_XPPU_CFG_APERPERM_288_PARITY_MASK                                      0xF0000000U
26584
26585 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26586                 h.*/
26587 #undef LPD_XPPU_CFG_APERPERM_289_PERMISSION_DEFVAL
26588 #undef LPD_XPPU_CFG_APERPERM_289_PERMISSION_SHIFT
26589 #undef LPD_XPPU_CFG_APERPERM_289_PERMISSION_MASK
26590 #define LPD_XPPU_CFG_APERPERM_289_PERMISSION_DEFVAL                                0x00000000
26591 #define LPD_XPPU_CFG_APERPERM_289_PERMISSION_SHIFT                                 0
26592 #define LPD_XPPU_CFG_APERPERM_289_PERMISSION_MASK                                  0x000FFFFFU
26593
26594 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26595 #undef LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_DEFVAL
26596 #undef LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_SHIFT
26597 #undef LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_MASK
26598 #define LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_DEFVAL                                 0x00000000
26599 #define LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_SHIFT                                  27
26600 #define LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_MASK                                   0x08000000U
26601
26602 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26603                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26604 #undef LPD_XPPU_CFG_APERPERM_289_PARITY_DEFVAL
26605 #undef LPD_XPPU_CFG_APERPERM_289_PARITY_SHIFT
26606 #undef LPD_XPPU_CFG_APERPERM_289_PARITY_MASK
26607 #define LPD_XPPU_CFG_APERPERM_289_PARITY_DEFVAL                                    0x00000000
26608 #define LPD_XPPU_CFG_APERPERM_289_PARITY_SHIFT                                     28
26609 #define LPD_XPPU_CFG_APERPERM_289_PARITY_MASK                                      0xF0000000U
26610
26611 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26612                 h.*/
26613 #undef LPD_XPPU_CFG_APERPERM_290_PERMISSION_DEFVAL
26614 #undef LPD_XPPU_CFG_APERPERM_290_PERMISSION_SHIFT
26615 #undef LPD_XPPU_CFG_APERPERM_290_PERMISSION_MASK
26616 #define LPD_XPPU_CFG_APERPERM_290_PERMISSION_DEFVAL                                0x00000000
26617 #define LPD_XPPU_CFG_APERPERM_290_PERMISSION_SHIFT                                 0
26618 #define LPD_XPPU_CFG_APERPERM_290_PERMISSION_MASK                                  0x000FFFFFU
26619
26620 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26621 #undef LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_DEFVAL
26622 #undef LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_SHIFT
26623 #undef LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_MASK
26624 #define LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_DEFVAL                                 0x00000000
26625 #define LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_SHIFT                                  27
26626 #define LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_MASK                                   0x08000000U
26627
26628 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26629                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26630 #undef LPD_XPPU_CFG_APERPERM_290_PARITY_DEFVAL
26631 #undef LPD_XPPU_CFG_APERPERM_290_PARITY_SHIFT
26632 #undef LPD_XPPU_CFG_APERPERM_290_PARITY_MASK
26633 #define LPD_XPPU_CFG_APERPERM_290_PARITY_DEFVAL                                    0x00000000
26634 #define LPD_XPPU_CFG_APERPERM_290_PARITY_SHIFT                                     28
26635 #define LPD_XPPU_CFG_APERPERM_290_PARITY_MASK                                      0xF0000000U
26636
26637 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26638                 h.*/
26639 #undef LPD_XPPU_CFG_APERPERM_291_PERMISSION_DEFVAL
26640 #undef LPD_XPPU_CFG_APERPERM_291_PERMISSION_SHIFT
26641 #undef LPD_XPPU_CFG_APERPERM_291_PERMISSION_MASK
26642 #define LPD_XPPU_CFG_APERPERM_291_PERMISSION_DEFVAL                                0x00000000
26643 #define LPD_XPPU_CFG_APERPERM_291_PERMISSION_SHIFT                                 0
26644 #define LPD_XPPU_CFG_APERPERM_291_PERMISSION_MASK                                  0x000FFFFFU
26645
26646 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26647 #undef LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_DEFVAL
26648 #undef LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_SHIFT
26649 #undef LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_MASK
26650 #define LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_DEFVAL                                 0x00000000
26651 #define LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_SHIFT                                  27
26652 #define LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_MASK                                   0x08000000U
26653
26654 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26655                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26656 #undef LPD_XPPU_CFG_APERPERM_291_PARITY_DEFVAL
26657 #undef LPD_XPPU_CFG_APERPERM_291_PARITY_SHIFT
26658 #undef LPD_XPPU_CFG_APERPERM_291_PARITY_MASK
26659 #define LPD_XPPU_CFG_APERPERM_291_PARITY_DEFVAL                                    0x00000000
26660 #define LPD_XPPU_CFG_APERPERM_291_PARITY_SHIFT                                     28
26661 #define LPD_XPPU_CFG_APERPERM_291_PARITY_MASK                                      0xF0000000U
26662
26663 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26664                 h.*/
26665 #undef LPD_XPPU_CFG_APERPERM_292_PERMISSION_DEFVAL
26666 #undef LPD_XPPU_CFG_APERPERM_292_PERMISSION_SHIFT
26667 #undef LPD_XPPU_CFG_APERPERM_292_PERMISSION_MASK
26668 #define LPD_XPPU_CFG_APERPERM_292_PERMISSION_DEFVAL                                0x00000000
26669 #define LPD_XPPU_CFG_APERPERM_292_PERMISSION_SHIFT                                 0
26670 #define LPD_XPPU_CFG_APERPERM_292_PERMISSION_MASK                                  0x000FFFFFU
26671
26672 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26673 #undef LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_DEFVAL
26674 #undef LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_SHIFT
26675 #undef LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_MASK
26676 #define LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_DEFVAL                                 0x00000000
26677 #define LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_SHIFT                                  27
26678 #define LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_MASK                                   0x08000000U
26679
26680 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26681                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26682 #undef LPD_XPPU_CFG_APERPERM_292_PARITY_DEFVAL
26683 #undef LPD_XPPU_CFG_APERPERM_292_PARITY_SHIFT
26684 #undef LPD_XPPU_CFG_APERPERM_292_PARITY_MASK
26685 #define LPD_XPPU_CFG_APERPERM_292_PARITY_DEFVAL                                    0x00000000
26686 #define LPD_XPPU_CFG_APERPERM_292_PARITY_SHIFT                                     28
26687 #define LPD_XPPU_CFG_APERPERM_292_PARITY_MASK                                      0xF0000000U
26688
26689 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26690                 h.*/
26691 #undef LPD_XPPU_CFG_APERPERM_293_PERMISSION_DEFVAL
26692 #undef LPD_XPPU_CFG_APERPERM_293_PERMISSION_SHIFT
26693 #undef LPD_XPPU_CFG_APERPERM_293_PERMISSION_MASK
26694 #define LPD_XPPU_CFG_APERPERM_293_PERMISSION_DEFVAL                                0x00000000
26695 #define LPD_XPPU_CFG_APERPERM_293_PERMISSION_SHIFT                                 0
26696 #define LPD_XPPU_CFG_APERPERM_293_PERMISSION_MASK                                  0x000FFFFFU
26697
26698 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26699 #undef LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_DEFVAL
26700 #undef LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_SHIFT
26701 #undef LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_MASK
26702 #define LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_DEFVAL                                 0x00000000
26703 #define LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_SHIFT                                  27
26704 #define LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_MASK                                   0x08000000U
26705
26706 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26707                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26708 #undef LPD_XPPU_CFG_APERPERM_293_PARITY_DEFVAL
26709 #undef LPD_XPPU_CFG_APERPERM_293_PARITY_SHIFT
26710 #undef LPD_XPPU_CFG_APERPERM_293_PARITY_MASK
26711 #define LPD_XPPU_CFG_APERPERM_293_PARITY_DEFVAL                                    0x00000000
26712 #define LPD_XPPU_CFG_APERPERM_293_PARITY_SHIFT                                     28
26713 #define LPD_XPPU_CFG_APERPERM_293_PARITY_MASK                                      0xF0000000U
26714
26715 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26716                 h.*/
26717 #undef LPD_XPPU_CFG_APERPERM_294_PERMISSION_DEFVAL
26718 #undef LPD_XPPU_CFG_APERPERM_294_PERMISSION_SHIFT
26719 #undef LPD_XPPU_CFG_APERPERM_294_PERMISSION_MASK
26720 #define LPD_XPPU_CFG_APERPERM_294_PERMISSION_DEFVAL                                0x00000000
26721 #define LPD_XPPU_CFG_APERPERM_294_PERMISSION_SHIFT                                 0
26722 #define LPD_XPPU_CFG_APERPERM_294_PERMISSION_MASK                                  0x000FFFFFU
26723
26724 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26725 #undef LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_DEFVAL
26726 #undef LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_SHIFT
26727 #undef LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_MASK
26728 #define LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_DEFVAL                                 0x00000000
26729 #define LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_SHIFT                                  27
26730 #define LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_MASK                                   0x08000000U
26731
26732 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26733                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26734 #undef LPD_XPPU_CFG_APERPERM_294_PARITY_DEFVAL
26735 #undef LPD_XPPU_CFG_APERPERM_294_PARITY_SHIFT
26736 #undef LPD_XPPU_CFG_APERPERM_294_PARITY_MASK
26737 #define LPD_XPPU_CFG_APERPERM_294_PARITY_DEFVAL                                    0x00000000
26738 #define LPD_XPPU_CFG_APERPERM_294_PARITY_SHIFT                                     28
26739 #define LPD_XPPU_CFG_APERPERM_294_PARITY_MASK                                      0xF0000000U
26740
26741 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26742                 h.*/
26743 #undef LPD_XPPU_CFG_APERPERM_295_PERMISSION_DEFVAL
26744 #undef LPD_XPPU_CFG_APERPERM_295_PERMISSION_SHIFT
26745 #undef LPD_XPPU_CFG_APERPERM_295_PERMISSION_MASK
26746 #define LPD_XPPU_CFG_APERPERM_295_PERMISSION_DEFVAL                                0x00000000
26747 #define LPD_XPPU_CFG_APERPERM_295_PERMISSION_SHIFT                                 0
26748 #define LPD_XPPU_CFG_APERPERM_295_PERMISSION_MASK                                  0x000FFFFFU
26749
26750 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26751 #undef LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_DEFVAL
26752 #undef LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_SHIFT
26753 #undef LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_MASK
26754 #define LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_DEFVAL                                 0x00000000
26755 #define LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_SHIFT                                  27
26756 #define LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_MASK                                   0x08000000U
26757
26758 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26759                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26760 #undef LPD_XPPU_CFG_APERPERM_295_PARITY_DEFVAL
26761 #undef LPD_XPPU_CFG_APERPERM_295_PARITY_SHIFT
26762 #undef LPD_XPPU_CFG_APERPERM_295_PARITY_MASK
26763 #define LPD_XPPU_CFG_APERPERM_295_PARITY_DEFVAL                                    0x00000000
26764 #define LPD_XPPU_CFG_APERPERM_295_PARITY_SHIFT                                     28
26765 #define LPD_XPPU_CFG_APERPERM_295_PARITY_MASK                                      0xF0000000U
26766
26767 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26768                 h.*/
26769 #undef LPD_XPPU_CFG_APERPERM_296_PERMISSION_DEFVAL
26770 #undef LPD_XPPU_CFG_APERPERM_296_PERMISSION_SHIFT
26771 #undef LPD_XPPU_CFG_APERPERM_296_PERMISSION_MASK
26772 #define LPD_XPPU_CFG_APERPERM_296_PERMISSION_DEFVAL                                0x00000000
26773 #define LPD_XPPU_CFG_APERPERM_296_PERMISSION_SHIFT                                 0
26774 #define LPD_XPPU_CFG_APERPERM_296_PERMISSION_MASK                                  0x000FFFFFU
26775
26776 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26777 #undef LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_DEFVAL
26778 #undef LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_SHIFT
26779 #undef LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_MASK
26780 #define LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_DEFVAL                                 0x00000000
26781 #define LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_SHIFT                                  27
26782 #define LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_MASK                                   0x08000000U
26783
26784 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26785                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26786 #undef LPD_XPPU_CFG_APERPERM_296_PARITY_DEFVAL
26787 #undef LPD_XPPU_CFG_APERPERM_296_PARITY_SHIFT
26788 #undef LPD_XPPU_CFG_APERPERM_296_PARITY_MASK
26789 #define LPD_XPPU_CFG_APERPERM_296_PARITY_DEFVAL                                    0x00000000
26790 #define LPD_XPPU_CFG_APERPERM_296_PARITY_SHIFT                                     28
26791 #define LPD_XPPU_CFG_APERPERM_296_PARITY_MASK                                      0xF0000000U
26792
26793 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26794                 h.*/
26795 #undef LPD_XPPU_CFG_APERPERM_297_PERMISSION_DEFVAL
26796 #undef LPD_XPPU_CFG_APERPERM_297_PERMISSION_SHIFT
26797 #undef LPD_XPPU_CFG_APERPERM_297_PERMISSION_MASK
26798 #define LPD_XPPU_CFG_APERPERM_297_PERMISSION_DEFVAL                                0x00000000
26799 #define LPD_XPPU_CFG_APERPERM_297_PERMISSION_SHIFT                                 0
26800 #define LPD_XPPU_CFG_APERPERM_297_PERMISSION_MASK                                  0x000FFFFFU
26801
26802 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26803 #undef LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_DEFVAL
26804 #undef LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_SHIFT
26805 #undef LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_MASK
26806 #define LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_DEFVAL                                 0x00000000
26807 #define LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_SHIFT                                  27
26808 #define LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_MASK                                   0x08000000U
26809
26810 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26811                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26812 #undef LPD_XPPU_CFG_APERPERM_297_PARITY_DEFVAL
26813 #undef LPD_XPPU_CFG_APERPERM_297_PARITY_SHIFT
26814 #undef LPD_XPPU_CFG_APERPERM_297_PARITY_MASK
26815 #define LPD_XPPU_CFG_APERPERM_297_PARITY_DEFVAL                                    0x00000000
26816 #define LPD_XPPU_CFG_APERPERM_297_PARITY_SHIFT                                     28
26817 #define LPD_XPPU_CFG_APERPERM_297_PARITY_MASK                                      0xF0000000U
26818
26819 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26820                 h.*/
26821 #undef LPD_XPPU_CFG_APERPERM_298_PERMISSION_DEFVAL
26822 #undef LPD_XPPU_CFG_APERPERM_298_PERMISSION_SHIFT
26823 #undef LPD_XPPU_CFG_APERPERM_298_PERMISSION_MASK
26824 #define LPD_XPPU_CFG_APERPERM_298_PERMISSION_DEFVAL                                0x00000000
26825 #define LPD_XPPU_CFG_APERPERM_298_PERMISSION_SHIFT                                 0
26826 #define LPD_XPPU_CFG_APERPERM_298_PERMISSION_MASK                                  0x000FFFFFU
26827
26828 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26829 #undef LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_DEFVAL
26830 #undef LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_SHIFT
26831 #undef LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_MASK
26832 #define LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_DEFVAL                                 0x00000000
26833 #define LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_SHIFT                                  27
26834 #define LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_MASK                                   0x08000000U
26835
26836 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26837                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26838 #undef LPD_XPPU_CFG_APERPERM_298_PARITY_DEFVAL
26839 #undef LPD_XPPU_CFG_APERPERM_298_PARITY_SHIFT
26840 #undef LPD_XPPU_CFG_APERPERM_298_PARITY_MASK
26841 #define LPD_XPPU_CFG_APERPERM_298_PARITY_DEFVAL                                    0x00000000
26842 #define LPD_XPPU_CFG_APERPERM_298_PARITY_SHIFT                                     28
26843 #define LPD_XPPU_CFG_APERPERM_298_PARITY_MASK                                      0xF0000000U
26844
26845 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26846                 h.*/
26847 #undef LPD_XPPU_CFG_APERPERM_299_PERMISSION_DEFVAL
26848 #undef LPD_XPPU_CFG_APERPERM_299_PERMISSION_SHIFT
26849 #undef LPD_XPPU_CFG_APERPERM_299_PERMISSION_MASK
26850 #define LPD_XPPU_CFG_APERPERM_299_PERMISSION_DEFVAL                                0x00000000
26851 #define LPD_XPPU_CFG_APERPERM_299_PERMISSION_SHIFT                                 0
26852 #define LPD_XPPU_CFG_APERPERM_299_PERMISSION_MASK                                  0x000FFFFFU
26853
26854 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26855 #undef LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_DEFVAL
26856 #undef LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_SHIFT
26857 #undef LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_MASK
26858 #define LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_DEFVAL                                 0x00000000
26859 #define LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_SHIFT                                  27
26860 #define LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_MASK                                   0x08000000U
26861
26862 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26863                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26864 #undef LPD_XPPU_CFG_APERPERM_299_PARITY_DEFVAL
26865 #undef LPD_XPPU_CFG_APERPERM_299_PARITY_SHIFT
26866 #undef LPD_XPPU_CFG_APERPERM_299_PARITY_MASK
26867 #define LPD_XPPU_CFG_APERPERM_299_PARITY_DEFVAL                                    0x00000000
26868 #define LPD_XPPU_CFG_APERPERM_299_PARITY_SHIFT                                     28
26869 #define LPD_XPPU_CFG_APERPERM_299_PARITY_MASK                                      0xF0000000U
26870
26871 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26872                 h.*/
26873 #undef LPD_XPPU_CFG_APERPERM_300_PERMISSION_DEFVAL
26874 #undef LPD_XPPU_CFG_APERPERM_300_PERMISSION_SHIFT
26875 #undef LPD_XPPU_CFG_APERPERM_300_PERMISSION_MASK
26876 #define LPD_XPPU_CFG_APERPERM_300_PERMISSION_DEFVAL                                0x00000000
26877 #define LPD_XPPU_CFG_APERPERM_300_PERMISSION_SHIFT                                 0
26878 #define LPD_XPPU_CFG_APERPERM_300_PERMISSION_MASK                                  0x000FFFFFU
26879
26880 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26881 #undef LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_DEFVAL
26882 #undef LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_SHIFT
26883 #undef LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_MASK
26884 #define LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_DEFVAL                                 0x00000000
26885 #define LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_SHIFT                                  27
26886 #define LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_MASK                                   0x08000000U
26887
26888 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26889                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26890 #undef LPD_XPPU_CFG_APERPERM_300_PARITY_DEFVAL
26891 #undef LPD_XPPU_CFG_APERPERM_300_PARITY_SHIFT
26892 #undef LPD_XPPU_CFG_APERPERM_300_PARITY_MASK
26893 #define LPD_XPPU_CFG_APERPERM_300_PARITY_DEFVAL                                    0x00000000
26894 #define LPD_XPPU_CFG_APERPERM_300_PARITY_SHIFT                                     28
26895 #define LPD_XPPU_CFG_APERPERM_300_PARITY_MASK                                      0xF0000000U
26896
26897 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26898                 h.*/
26899 #undef LPD_XPPU_CFG_APERPERM_301_PERMISSION_DEFVAL
26900 #undef LPD_XPPU_CFG_APERPERM_301_PERMISSION_SHIFT
26901 #undef LPD_XPPU_CFG_APERPERM_301_PERMISSION_MASK
26902 #define LPD_XPPU_CFG_APERPERM_301_PERMISSION_DEFVAL                                0x00000000
26903 #define LPD_XPPU_CFG_APERPERM_301_PERMISSION_SHIFT                                 0
26904 #define LPD_XPPU_CFG_APERPERM_301_PERMISSION_MASK                                  0x000FFFFFU
26905
26906 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26907 #undef LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_DEFVAL
26908 #undef LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_SHIFT
26909 #undef LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_MASK
26910 #define LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_DEFVAL                                 0x00000000
26911 #define LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_SHIFT                                  27
26912 #define LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_MASK                                   0x08000000U
26913
26914 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26915                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26916 #undef LPD_XPPU_CFG_APERPERM_301_PARITY_DEFVAL
26917 #undef LPD_XPPU_CFG_APERPERM_301_PARITY_SHIFT
26918 #undef LPD_XPPU_CFG_APERPERM_301_PARITY_MASK
26919 #define LPD_XPPU_CFG_APERPERM_301_PARITY_DEFVAL                                    0x00000000
26920 #define LPD_XPPU_CFG_APERPERM_301_PARITY_SHIFT                                     28
26921 #define LPD_XPPU_CFG_APERPERM_301_PARITY_MASK                                      0xF0000000U
26922
26923 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26924                 h.*/
26925 #undef LPD_XPPU_CFG_APERPERM_302_PERMISSION_DEFVAL
26926 #undef LPD_XPPU_CFG_APERPERM_302_PERMISSION_SHIFT
26927 #undef LPD_XPPU_CFG_APERPERM_302_PERMISSION_MASK
26928 #define LPD_XPPU_CFG_APERPERM_302_PERMISSION_DEFVAL                                0x00000000
26929 #define LPD_XPPU_CFG_APERPERM_302_PERMISSION_SHIFT                                 0
26930 #define LPD_XPPU_CFG_APERPERM_302_PERMISSION_MASK                                  0x000FFFFFU
26931
26932 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26933 #undef LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_DEFVAL
26934 #undef LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_SHIFT
26935 #undef LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_MASK
26936 #define LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_DEFVAL                                 0x00000000
26937 #define LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_SHIFT                                  27
26938 #define LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_MASK                                   0x08000000U
26939
26940 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26941                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26942 #undef LPD_XPPU_CFG_APERPERM_302_PARITY_DEFVAL
26943 #undef LPD_XPPU_CFG_APERPERM_302_PARITY_SHIFT
26944 #undef LPD_XPPU_CFG_APERPERM_302_PARITY_MASK
26945 #define LPD_XPPU_CFG_APERPERM_302_PARITY_DEFVAL                                    0x00000000
26946 #define LPD_XPPU_CFG_APERPERM_302_PARITY_SHIFT                                     28
26947 #define LPD_XPPU_CFG_APERPERM_302_PARITY_MASK                                      0xF0000000U
26948
26949 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26950                 h.*/
26951 #undef LPD_XPPU_CFG_APERPERM_303_PERMISSION_DEFVAL
26952 #undef LPD_XPPU_CFG_APERPERM_303_PERMISSION_SHIFT
26953 #undef LPD_XPPU_CFG_APERPERM_303_PERMISSION_MASK
26954 #define LPD_XPPU_CFG_APERPERM_303_PERMISSION_DEFVAL                                0x00000000
26955 #define LPD_XPPU_CFG_APERPERM_303_PERMISSION_SHIFT                                 0
26956 #define LPD_XPPU_CFG_APERPERM_303_PERMISSION_MASK                                  0x000FFFFFU
26957
26958 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26959 #undef LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_DEFVAL
26960 #undef LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_SHIFT
26961 #undef LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_MASK
26962 #define LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_DEFVAL                                 0x00000000
26963 #define LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_SHIFT                                  27
26964 #define LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_MASK                                   0x08000000U
26965
26966 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26967                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26968 #undef LPD_XPPU_CFG_APERPERM_303_PARITY_DEFVAL
26969 #undef LPD_XPPU_CFG_APERPERM_303_PARITY_SHIFT
26970 #undef LPD_XPPU_CFG_APERPERM_303_PARITY_MASK
26971 #define LPD_XPPU_CFG_APERPERM_303_PARITY_DEFVAL                                    0x00000000
26972 #define LPD_XPPU_CFG_APERPERM_303_PARITY_SHIFT                                     28
26973 #define LPD_XPPU_CFG_APERPERM_303_PARITY_MASK                                      0xF0000000U
26974
26975 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
26976                 h.*/
26977 #undef LPD_XPPU_CFG_APERPERM_304_PERMISSION_DEFVAL
26978 #undef LPD_XPPU_CFG_APERPERM_304_PERMISSION_SHIFT
26979 #undef LPD_XPPU_CFG_APERPERM_304_PERMISSION_MASK
26980 #define LPD_XPPU_CFG_APERPERM_304_PERMISSION_DEFVAL                                0x00000000
26981 #define LPD_XPPU_CFG_APERPERM_304_PERMISSION_SHIFT                                 0
26982 #define LPD_XPPU_CFG_APERPERM_304_PERMISSION_MASK                                  0x000FFFFFU
26983
26984 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
26985 #undef LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_DEFVAL
26986 #undef LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_SHIFT
26987 #undef LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_MASK
26988 #define LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_DEFVAL                                 0x00000000
26989 #define LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_SHIFT                                  27
26990 #define LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_MASK                                   0x08000000U
26991
26992 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
26993                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
26994 #undef LPD_XPPU_CFG_APERPERM_304_PARITY_DEFVAL
26995 #undef LPD_XPPU_CFG_APERPERM_304_PARITY_SHIFT
26996 #undef LPD_XPPU_CFG_APERPERM_304_PARITY_MASK
26997 #define LPD_XPPU_CFG_APERPERM_304_PARITY_DEFVAL                                    0x00000000
26998 #define LPD_XPPU_CFG_APERPERM_304_PARITY_SHIFT                                     28
26999 #define LPD_XPPU_CFG_APERPERM_304_PARITY_MASK                                      0xF0000000U
27000
27001 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27002                 h.*/
27003 #undef LPD_XPPU_CFG_APERPERM_305_PERMISSION_DEFVAL
27004 #undef LPD_XPPU_CFG_APERPERM_305_PERMISSION_SHIFT
27005 #undef LPD_XPPU_CFG_APERPERM_305_PERMISSION_MASK
27006 #define LPD_XPPU_CFG_APERPERM_305_PERMISSION_DEFVAL                                0x00000000
27007 #define LPD_XPPU_CFG_APERPERM_305_PERMISSION_SHIFT                                 0
27008 #define LPD_XPPU_CFG_APERPERM_305_PERMISSION_MASK                                  0x000FFFFFU
27009
27010 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27011 #undef LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_DEFVAL
27012 #undef LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_SHIFT
27013 #undef LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_MASK
27014 #define LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_DEFVAL                                 0x00000000
27015 #define LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_SHIFT                                  27
27016 #define LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_MASK                                   0x08000000U
27017
27018 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27019                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27020 #undef LPD_XPPU_CFG_APERPERM_305_PARITY_DEFVAL
27021 #undef LPD_XPPU_CFG_APERPERM_305_PARITY_SHIFT
27022 #undef LPD_XPPU_CFG_APERPERM_305_PARITY_MASK
27023 #define LPD_XPPU_CFG_APERPERM_305_PARITY_DEFVAL                                    0x00000000
27024 #define LPD_XPPU_CFG_APERPERM_305_PARITY_SHIFT                                     28
27025 #define LPD_XPPU_CFG_APERPERM_305_PARITY_MASK                                      0xF0000000U
27026
27027 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27028                 h.*/
27029 #undef LPD_XPPU_CFG_APERPERM_306_PERMISSION_DEFVAL
27030 #undef LPD_XPPU_CFG_APERPERM_306_PERMISSION_SHIFT
27031 #undef LPD_XPPU_CFG_APERPERM_306_PERMISSION_MASK
27032 #define LPD_XPPU_CFG_APERPERM_306_PERMISSION_DEFVAL                                0x00000000
27033 #define LPD_XPPU_CFG_APERPERM_306_PERMISSION_SHIFT                                 0
27034 #define LPD_XPPU_CFG_APERPERM_306_PERMISSION_MASK                                  0x000FFFFFU
27035
27036 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27037 #undef LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_DEFVAL
27038 #undef LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_SHIFT
27039 #undef LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_MASK
27040 #define LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_DEFVAL                                 0x00000000
27041 #define LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_SHIFT                                  27
27042 #define LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_MASK                                   0x08000000U
27043
27044 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27045                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27046 #undef LPD_XPPU_CFG_APERPERM_306_PARITY_DEFVAL
27047 #undef LPD_XPPU_CFG_APERPERM_306_PARITY_SHIFT
27048 #undef LPD_XPPU_CFG_APERPERM_306_PARITY_MASK
27049 #define LPD_XPPU_CFG_APERPERM_306_PARITY_DEFVAL                                    0x00000000
27050 #define LPD_XPPU_CFG_APERPERM_306_PARITY_SHIFT                                     28
27051 #define LPD_XPPU_CFG_APERPERM_306_PARITY_MASK                                      0xF0000000U
27052
27053 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27054                 h.*/
27055 #undef LPD_XPPU_CFG_APERPERM_307_PERMISSION_DEFVAL
27056 #undef LPD_XPPU_CFG_APERPERM_307_PERMISSION_SHIFT
27057 #undef LPD_XPPU_CFG_APERPERM_307_PERMISSION_MASK
27058 #define LPD_XPPU_CFG_APERPERM_307_PERMISSION_DEFVAL                                0x00000000
27059 #define LPD_XPPU_CFG_APERPERM_307_PERMISSION_SHIFT                                 0
27060 #define LPD_XPPU_CFG_APERPERM_307_PERMISSION_MASK                                  0x000FFFFFU
27061
27062 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27063 #undef LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_DEFVAL
27064 #undef LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_SHIFT
27065 #undef LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_MASK
27066 #define LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_DEFVAL                                 0x00000000
27067 #define LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_SHIFT                                  27
27068 #define LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_MASK                                   0x08000000U
27069
27070 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27071                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27072 #undef LPD_XPPU_CFG_APERPERM_307_PARITY_DEFVAL
27073 #undef LPD_XPPU_CFG_APERPERM_307_PARITY_SHIFT
27074 #undef LPD_XPPU_CFG_APERPERM_307_PARITY_MASK
27075 #define LPD_XPPU_CFG_APERPERM_307_PARITY_DEFVAL                                    0x00000000
27076 #define LPD_XPPU_CFG_APERPERM_307_PARITY_SHIFT                                     28
27077 #define LPD_XPPU_CFG_APERPERM_307_PARITY_MASK                                      0xF0000000U
27078
27079 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27080                 h.*/
27081 #undef LPD_XPPU_CFG_APERPERM_308_PERMISSION_DEFVAL
27082 #undef LPD_XPPU_CFG_APERPERM_308_PERMISSION_SHIFT
27083 #undef LPD_XPPU_CFG_APERPERM_308_PERMISSION_MASK
27084 #define LPD_XPPU_CFG_APERPERM_308_PERMISSION_DEFVAL                                0x00000000
27085 #define LPD_XPPU_CFG_APERPERM_308_PERMISSION_SHIFT                                 0
27086 #define LPD_XPPU_CFG_APERPERM_308_PERMISSION_MASK                                  0x000FFFFFU
27087
27088 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27089 #undef LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_DEFVAL
27090 #undef LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_SHIFT
27091 #undef LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_MASK
27092 #define LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_DEFVAL                                 0x00000000
27093 #define LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_SHIFT                                  27
27094 #define LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_MASK                                   0x08000000U
27095
27096 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27097                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27098 #undef LPD_XPPU_CFG_APERPERM_308_PARITY_DEFVAL
27099 #undef LPD_XPPU_CFG_APERPERM_308_PARITY_SHIFT
27100 #undef LPD_XPPU_CFG_APERPERM_308_PARITY_MASK
27101 #define LPD_XPPU_CFG_APERPERM_308_PARITY_DEFVAL                                    0x00000000
27102 #define LPD_XPPU_CFG_APERPERM_308_PARITY_SHIFT                                     28
27103 #define LPD_XPPU_CFG_APERPERM_308_PARITY_MASK                                      0xF0000000U
27104
27105 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27106                 h.*/
27107 #undef LPD_XPPU_CFG_APERPERM_309_PERMISSION_DEFVAL
27108 #undef LPD_XPPU_CFG_APERPERM_309_PERMISSION_SHIFT
27109 #undef LPD_XPPU_CFG_APERPERM_309_PERMISSION_MASK
27110 #define LPD_XPPU_CFG_APERPERM_309_PERMISSION_DEFVAL                                0x00000000
27111 #define LPD_XPPU_CFG_APERPERM_309_PERMISSION_SHIFT                                 0
27112 #define LPD_XPPU_CFG_APERPERM_309_PERMISSION_MASK                                  0x000FFFFFU
27113
27114 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27115 #undef LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_DEFVAL
27116 #undef LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_SHIFT
27117 #undef LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_MASK
27118 #define LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_DEFVAL                                 0x00000000
27119 #define LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_SHIFT                                  27
27120 #define LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_MASK                                   0x08000000U
27121
27122 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27123                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27124 #undef LPD_XPPU_CFG_APERPERM_309_PARITY_DEFVAL
27125 #undef LPD_XPPU_CFG_APERPERM_309_PARITY_SHIFT
27126 #undef LPD_XPPU_CFG_APERPERM_309_PARITY_MASK
27127 #define LPD_XPPU_CFG_APERPERM_309_PARITY_DEFVAL                                    0x00000000
27128 #define LPD_XPPU_CFG_APERPERM_309_PARITY_SHIFT                                     28
27129 #define LPD_XPPU_CFG_APERPERM_309_PARITY_MASK                                      0xF0000000U
27130
27131 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27132                 h.*/
27133 #undef LPD_XPPU_CFG_APERPERM_318_PERMISSION_DEFVAL
27134 #undef LPD_XPPU_CFG_APERPERM_318_PERMISSION_SHIFT
27135 #undef LPD_XPPU_CFG_APERPERM_318_PERMISSION_MASK
27136 #define LPD_XPPU_CFG_APERPERM_318_PERMISSION_DEFVAL                                0x00000000
27137 #define LPD_XPPU_CFG_APERPERM_318_PERMISSION_SHIFT                                 0
27138 #define LPD_XPPU_CFG_APERPERM_318_PERMISSION_MASK                                  0x000FFFFFU
27139
27140 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27141 #undef LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_DEFVAL
27142 #undef LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_SHIFT
27143 #undef LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_MASK
27144 #define LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_DEFVAL                                 0x00000000
27145 #define LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_SHIFT                                  27
27146 #define LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_MASK                                   0x08000000U
27147
27148 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27149                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27150 #undef LPD_XPPU_CFG_APERPERM_318_PARITY_DEFVAL
27151 #undef LPD_XPPU_CFG_APERPERM_318_PARITY_SHIFT
27152 #undef LPD_XPPU_CFG_APERPERM_318_PARITY_MASK
27153 #define LPD_XPPU_CFG_APERPERM_318_PARITY_DEFVAL                                    0x00000000
27154 #define LPD_XPPU_CFG_APERPERM_318_PARITY_SHIFT                                     28
27155 #define LPD_XPPU_CFG_APERPERM_318_PARITY_MASK                                      0xF0000000U
27156
27157 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27158                 h.*/
27159 #undef LPD_XPPU_CFG_APERPERM_319_PERMISSION_DEFVAL
27160 #undef LPD_XPPU_CFG_APERPERM_319_PERMISSION_SHIFT
27161 #undef LPD_XPPU_CFG_APERPERM_319_PERMISSION_MASK
27162 #define LPD_XPPU_CFG_APERPERM_319_PERMISSION_DEFVAL                                0x00000000
27163 #define LPD_XPPU_CFG_APERPERM_319_PERMISSION_SHIFT                                 0
27164 #define LPD_XPPU_CFG_APERPERM_319_PERMISSION_MASK                                  0x000FFFFFU
27165
27166 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27167 #undef LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_DEFVAL
27168 #undef LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_SHIFT
27169 #undef LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_MASK
27170 #define LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_DEFVAL                                 0x00000000
27171 #define LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_SHIFT                                  27
27172 #define LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_MASK                                   0x08000000U
27173
27174 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27175                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27176 #undef LPD_XPPU_CFG_APERPERM_319_PARITY_DEFVAL
27177 #undef LPD_XPPU_CFG_APERPERM_319_PARITY_SHIFT
27178 #undef LPD_XPPU_CFG_APERPERM_319_PARITY_MASK
27179 #define LPD_XPPU_CFG_APERPERM_319_PARITY_DEFVAL                                    0x00000000
27180 #define LPD_XPPU_CFG_APERPERM_319_PARITY_SHIFT                                     28
27181 #define LPD_XPPU_CFG_APERPERM_319_PARITY_MASK                                      0xF0000000U
27182
27183 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27184                 h.*/
27185 #undef LPD_XPPU_CFG_APERPERM_320_PERMISSION_DEFVAL
27186 #undef LPD_XPPU_CFG_APERPERM_320_PERMISSION_SHIFT
27187 #undef LPD_XPPU_CFG_APERPERM_320_PERMISSION_MASK
27188 #define LPD_XPPU_CFG_APERPERM_320_PERMISSION_DEFVAL                                0x00000000
27189 #define LPD_XPPU_CFG_APERPERM_320_PERMISSION_SHIFT                                 0
27190 #define LPD_XPPU_CFG_APERPERM_320_PERMISSION_MASK                                  0x000FFFFFU
27191
27192 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27193 #undef LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_DEFVAL
27194 #undef LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_SHIFT
27195 #undef LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_MASK
27196 #define LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_DEFVAL                                 0x00000000
27197 #define LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_SHIFT                                  27
27198 #define LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_MASK                                   0x08000000U
27199
27200 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27201                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27202 #undef LPD_XPPU_CFG_APERPERM_320_PARITY_DEFVAL
27203 #undef LPD_XPPU_CFG_APERPERM_320_PARITY_SHIFT
27204 #undef LPD_XPPU_CFG_APERPERM_320_PARITY_MASK
27205 #define LPD_XPPU_CFG_APERPERM_320_PARITY_DEFVAL                                    0x00000000
27206 #define LPD_XPPU_CFG_APERPERM_320_PARITY_SHIFT                                     28
27207 #define LPD_XPPU_CFG_APERPERM_320_PARITY_MASK                                      0xF0000000U
27208
27209 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27210                 h.*/
27211 #undef LPD_XPPU_CFG_APERPERM_321_PERMISSION_DEFVAL
27212 #undef LPD_XPPU_CFG_APERPERM_321_PERMISSION_SHIFT
27213 #undef LPD_XPPU_CFG_APERPERM_321_PERMISSION_MASK
27214 #define LPD_XPPU_CFG_APERPERM_321_PERMISSION_DEFVAL                                0x00000000
27215 #define LPD_XPPU_CFG_APERPERM_321_PERMISSION_SHIFT                                 0
27216 #define LPD_XPPU_CFG_APERPERM_321_PERMISSION_MASK                                  0x000FFFFFU
27217
27218 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27219 #undef LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_DEFVAL
27220 #undef LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_SHIFT
27221 #undef LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_MASK
27222 #define LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_DEFVAL                                 0x00000000
27223 #define LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_SHIFT                                  27
27224 #define LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_MASK                                   0x08000000U
27225
27226 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27227                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27228 #undef LPD_XPPU_CFG_APERPERM_321_PARITY_DEFVAL
27229 #undef LPD_XPPU_CFG_APERPERM_321_PARITY_SHIFT
27230 #undef LPD_XPPU_CFG_APERPERM_321_PARITY_MASK
27231 #define LPD_XPPU_CFG_APERPERM_321_PARITY_DEFVAL                                    0x00000000
27232 #define LPD_XPPU_CFG_APERPERM_321_PARITY_SHIFT                                     28
27233 #define LPD_XPPU_CFG_APERPERM_321_PARITY_MASK                                      0xF0000000U
27234
27235 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27236                 h.*/
27237 #undef LPD_XPPU_CFG_APERPERM_322_PERMISSION_DEFVAL
27238 #undef LPD_XPPU_CFG_APERPERM_322_PERMISSION_SHIFT
27239 #undef LPD_XPPU_CFG_APERPERM_322_PERMISSION_MASK
27240 #define LPD_XPPU_CFG_APERPERM_322_PERMISSION_DEFVAL                                0x00000000
27241 #define LPD_XPPU_CFG_APERPERM_322_PERMISSION_SHIFT                                 0
27242 #define LPD_XPPU_CFG_APERPERM_322_PERMISSION_MASK                                  0x000FFFFFU
27243
27244 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27245 #undef LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_DEFVAL
27246 #undef LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_SHIFT
27247 #undef LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_MASK
27248 #define LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_DEFVAL                                 0x00000000
27249 #define LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_SHIFT                                  27
27250 #define LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_MASK                                   0x08000000U
27251
27252 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27253                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27254 #undef LPD_XPPU_CFG_APERPERM_322_PARITY_DEFVAL
27255 #undef LPD_XPPU_CFG_APERPERM_322_PARITY_SHIFT
27256 #undef LPD_XPPU_CFG_APERPERM_322_PARITY_MASK
27257 #define LPD_XPPU_CFG_APERPERM_322_PARITY_DEFVAL                                    0x00000000
27258 #define LPD_XPPU_CFG_APERPERM_322_PARITY_SHIFT                                     28
27259 #define LPD_XPPU_CFG_APERPERM_322_PARITY_MASK                                      0xF0000000U
27260
27261 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27262                 h.*/
27263 #undef LPD_XPPU_CFG_APERPERM_323_PERMISSION_DEFVAL
27264 #undef LPD_XPPU_CFG_APERPERM_323_PERMISSION_SHIFT
27265 #undef LPD_XPPU_CFG_APERPERM_323_PERMISSION_MASK
27266 #define LPD_XPPU_CFG_APERPERM_323_PERMISSION_DEFVAL                                0x00000000
27267 #define LPD_XPPU_CFG_APERPERM_323_PERMISSION_SHIFT                                 0
27268 #define LPD_XPPU_CFG_APERPERM_323_PERMISSION_MASK                                  0x000FFFFFU
27269
27270 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27271 #undef LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_DEFVAL
27272 #undef LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_SHIFT
27273 #undef LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_MASK
27274 #define LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_DEFVAL                                 0x00000000
27275 #define LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_SHIFT                                  27
27276 #define LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_MASK                                   0x08000000U
27277
27278 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27279                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27280 #undef LPD_XPPU_CFG_APERPERM_323_PARITY_DEFVAL
27281 #undef LPD_XPPU_CFG_APERPERM_323_PARITY_SHIFT
27282 #undef LPD_XPPU_CFG_APERPERM_323_PARITY_MASK
27283 #define LPD_XPPU_CFG_APERPERM_323_PARITY_DEFVAL                                    0x00000000
27284 #define LPD_XPPU_CFG_APERPERM_323_PARITY_SHIFT                                     28
27285 #define LPD_XPPU_CFG_APERPERM_323_PARITY_MASK                                      0xF0000000U
27286
27287 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27288                 h.*/
27289 #undef LPD_XPPU_CFG_APERPERM_324_PERMISSION_DEFVAL
27290 #undef LPD_XPPU_CFG_APERPERM_324_PERMISSION_SHIFT
27291 #undef LPD_XPPU_CFG_APERPERM_324_PERMISSION_MASK
27292 #define LPD_XPPU_CFG_APERPERM_324_PERMISSION_DEFVAL                                0x00000000
27293 #define LPD_XPPU_CFG_APERPERM_324_PERMISSION_SHIFT                                 0
27294 #define LPD_XPPU_CFG_APERPERM_324_PERMISSION_MASK                                  0x000FFFFFU
27295
27296 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27297 #undef LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_DEFVAL
27298 #undef LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_SHIFT
27299 #undef LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_MASK
27300 #define LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_DEFVAL                                 0x00000000
27301 #define LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_SHIFT                                  27
27302 #define LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_MASK                                   0x08000000U
27303
27304 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27305                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27306 #undef LPD_XPPU_CFG_APERPERM_324_PARITY_DEFVAL
27307 #undef LPD_XPPU_CFG_APERPERM_324_PARITY_SHIFT
27308 #undef LPD_XPPU_CFG_APERPERM_324_PARITY_MASK
27309 #define LPD_XPPU_CFG_APERPERM_324_PARITY_DEFVAL                                    0x00000000
27310 #define LPD_XPPU_CFG_APERPERM_324_PARITY_SHIFT                                     28
27311 #define LPD_XPPU_CFG_APERPERM_324_PARITY_MASK                                      0xF0000000U
27312
27313 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27314                 h.*/
27315 #undef LPD_XPPU_CFG_APERPERM_325_PERMISSION_DEFVAL
27316 #undef LPD_XPPU_CFG_APERPERM_325_PERMISSION_SHIFT
27317 #undef LPD_XPPU_CFG_APERPERM_325_PERMISSION_MASK
27318 #define LPD_XPPU_CFG_APERPERM_325_PERMISSION_DEFVAL                                0x00000000
27319 #define LPD_XPPU_CFG_APERPERM_325_PERMISSION_SHIFT                                 0
27320 #define LPD_XPPU_CFG_APERPERM_325_PERMISSION_MASK                                  0x000FFFFFU
27321
27322 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27323 #undef LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_DEFVAL
27324 #undef LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_SHIFT
27325 #undef LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_MASK
27326 #define LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_DEFVAL                                 0x00000000
27327 #define LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_SHIFT                                  27
27328 #define LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_MASK                                   0x08000000U
27329
27330 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27331                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27332 #undef LPD_XPPU_CFG_APERPERM_325_PARITY_DEFVAL
27333 #undef LPD_XPPU_CFG_APERPERM_325_PARITY_SHIFT
27334 #undef LPD_XPPU_CFG_APERPERM_325_PARITY_MASK
27335 #define LPD_XPPU_CFG_APERPERM_325_PARITY_DEFVAL                                    0x00000000
27336 #define LPD_XPPU_CFG_APERPERM_325_PARITY_SHIFT                                     28
27337 #define LPD_XPPU_CFG_APERPERM_325_PARITY_MASK                                      0xF0000000U
27338
27339 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27340                 h.*/
27341 #undef LPD_XPPU_CFG_APERPERM_334_PERMISSION_DEFVAL
27342 #undef LPD_XPPU_CFG_APERPERM_334_PERMISSION_SHIFT
27343 #undef LPD_XPPU_CFG_APERPERM_334_PERMISSION_MASK
27344 #define LPD_XPPU_CFG_APERPERM_334_PERMISSION_DEFVAL                                0x00000000
27345 #define LPD_XPPU_CFG_APERPERM_334_PERMISSION_SHIFT                                 0
27346 #define LPD_XPPU_CFG_APERPERM_334_PERMISSION_MASK                                  0x000FFFFFU
27347
27348 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27349 #undef LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_DEFVAL
27350 #undef LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_SHIFT
27351 #undef LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_MASK
27352 #define LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_DEFVAL                                 0x00000000
27353 #define LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_SHIFT                                  27
27354 #define LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_MASK                                   0x08000000U
27355
27356 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27357                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27358 #undef LPD_XPPU_CFG_APERPERM_334_PARITY_DEFVAL
27359 #undef LPD_XPPU_CFG_APERPERM_334_PARITY_SHIFT
27360 #undef LPD_XPPU_CFG_APERPERM_334_PARITY_MASK
27361 #define LPD_XPPU_CFG_APERPERM_334_PARITY_DEFVAL                                    0x00000000
27362 #define LPD_XPPU_CFG_APERPERM_334_PARITY_SHIFT                                     28
27363 #define LPD_XPPU_CFG_APERPERM_334_PARITY_MASK                                      0xF0000000U
27364
27365 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27366                 h.*/
27367 #undef LPD_XPPU_CFG_APERPERM_335_PERMISSION_DEFVAL
27368 #undef LPD_XPPU_CFG_APERPERM_335_PERMISSION_SHIFT
27369 #undef LPD_XPPU_CFG_APERPERM_335_PERMISSION_MASK
27370 #define LPD_XPPU_CFG_APERPERM_335_PERMISSION_DEFVAL                                0x00000000
27371 #define LPD_XPPU_CFG_APERPERM_335_PERMISSION_SHIFT                                 0
27372 #define LPD_XPPU_CFG_APERPERM_335_PERMISSION_MASK                                  0x000FFFFFU
27373
27374 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27375 #undef LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_DEFVAL
27376 #undef LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_SHIFT
27377 #undef LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_MASK
27378 #define LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_DEFVAL                                 0x00000000
27379 #define LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_SHIFT                                  27
27380 #define LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_MASK                                   0x08000000U
27381
27382 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27383                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27384 #undef LPD_XPPU_CFG_APERPERM_335_PARITY_DEFVAL
27385 #undef LPD_XPPU_CFG_APERPERM_335_PARITY_SHIFT
27386 #undef LPD_XPPU_CFG_APERPERM_335_PARITY_MASK
27387 #define LPD_XPPU_CFG_APERPERM_335_PARITY_DEFVAL                                    0x00000000
27388 #define LPD_XPPU_CFG_APERPERM_335_PARITY_SHIFT                                     28
27389 #define LPD_XPPU_CFG_APERPERM_335_PARITY_MASK                                      0xF0000000U
27390
27391 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27392                 h.*/
27393 #undef LPD_XPPU_CFG_APERPERM_336_PERMISSION_DEFVAL
27394 #undef LPD_XPPU_CFG_APERPERM_336_PERMISSION_SHIFT
27395 #undef LPD_XPPU_CFG_APERPERM_336_PERMISSION_MASK
27396 #define LPD_XPPU_CFG_APERPERM_336_PERMISSION_DEFVAL                                0x00000000
27397 #define LPD_XPPU_CFG_APERPERM_336_PERMISSION_SHIFT                                 0
27398 #define LPD_XPPU_CFG_APERPERM_336_PERMISSION_MASK                                  0x000FFFFFU
27399
27400 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27401 #undef LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_DEFVAL
27402 #undef LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_SHIFT
27403 #undef LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_MASK
27404 #define LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_DEFVAL                                 0x00000000
27405 #define LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_SHIFT                                  27
27406 #define LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_MASK                                   0x08000000U
27407
27408 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27409                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27410 #undef LPD_XPPU_CFG_APERPERM_336_PARITY_DEFVAL
27411 #undef LPD_XPPU_CFG_APERPERM_336_PARITY_SHIFT
27412 #undef LPD_XPPU_CFG_APERPERM_336_PARITY_MASK
27413 #define LPD_XPPU_CFG_APERPERM_336_PARITY_DEFVAL                                    0x00000000
27414 #define LPD_XPPU_CFG_APERPERM_336_PARITY_SHIFT                                     28
27415 #define LPD_XPPU_CFG_APERPERM_336_PARITY_MASK                                      0xF0000000U
27416
27417 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27418                 h.*/
27419 #undef LPD_XPPU_CFG_APERPERM_337_PERMISSION_DEFVAL
27420 #undef LPD_XPPU_CFG_APERPERM_337_PERMISSION_SHIFT
27421 #undef LPD_XPPU_CFG_APERPERM_337_PERMISSION_MASK
27422 #define LPD_XPPU_CFG_APERPERM_337_PERMISSION_DEFVAL                                0x00000000
27423 #define LPD_XPPU_CFG_APERPERM_337_PERMISSION_SHIFT                                 0
27424 #define LPD_XPPU_CFG_APERPERM_337_PERMISSION_MASK                                  0x000FFFFFU
27425
27426 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27427 #undef LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_DEFVAL
27428 #undef LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_SHIFT
27429 #undef LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_MASK
27430 #define LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_DEFVAL                                 0x00000000
27431 #define LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_SHIFT                                  27
27432 #define LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_MASK                                   0x08000000U
27433
27434 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27435                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27436 #undef LPD_XPPU_CFG_APERPERM_337_PARITY_DEFVAL
27437 #undef LPD_XPPU_CFG_APERPERM_337_PARITY_SHIFT
27438 #undef LPD_XPPU_CFG_APERPERM_337_PARITY_MASK
27439 #define LPD_XPPU_CFG_APERPERM_337_PARITY_DEFVAL                                    0x00000000
27440 #define LPD_XPPU_CFG_APERPERM_337_PARITY_SHIFT                                     28
27441 #define LPD_XPPU_CFG_APERPERM_337_PARITY_MASK                                      0xF0000000U
27442
27443 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27444                 h.*/
27445 #undef LPD_XPPU_CFG_APERPERM_338_PERMISSION_DEFVAL
27446 #undef LPD_XPPU_CFG_APERPERM_338_PERMISSION_SHIFT
27447 #undef LPD_XPPU_CFG_APERPERM_338_PERMISSION_MASK
27448 #define LPD_XPPU_CFG_APERPERM_338_PERMISSION_DEFVAL                                0x00000000
27449 #define LPD_XPPU_CFG_APERPERM_338_PERMISSION_SHIFT                                 0
27450 #define LPD_XPPU_CFG_APERPERM_338_PERMISSION_MASK                                  0x000FFFFFU
27451
27452 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27453 #undef LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_DEFVAL
27454 #undef LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_SHIFT
27455 #undef LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_MASK
27456 #define LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_DEFVAL                                 0x00000000
27457 #define LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_SHIFT                                  27
27458 #define LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_MASK                                   0x08000000U
27459
27460 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27461                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27462 #undef LPD_XPPU_CFG_APERPERM_338_PARITY_DEFVAL
27463 #undef LPD_XPPU_CFG_APERPERM_338_PARITY_SHIFT
27464 #undef LPD_XPPU_CFG_APERPERM_338_PARITY_MASK
27465 #define LPD_XPPU_CFG_APERPERM_338_PARITY_DEFVAL                                    0x00000000
27466 #define LPD_XPPU_CFG_APERPERM_338_PARITY_SHIFT                                     28
27467 #define LPD_XPPU_CFG_APERPERM_338_PARITY_MASK                                      0xF0000000U
27468
27469 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27470                 h.*/
27471 #undef LPD_XPPU_CFG_APERPERM_339_PERMISSION_DEFVAL
27472 #undef LPD_XPPU_CFG_APERPERM_339_PERMISSION_SHIFT
27473 #undef LPD_XPPU_CFG_APERPERM_339_PERMISSION_MASK
27474 #define LPD_XPPU_CFG_APERPERM_339_PERMISSION_DEFVAL                                0x00000000
27475 #define LPD_XPPU_CFG_APERPERM_339_PERMISSION_SHIFT                                 0
27476 #define LPD_XPPU_CFG_APERPERM_339_PERMISSION_MASK                                  0x000FFFFFU
27477
27478 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27479 #undef LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_DEFVAL
27480 #undef LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_SHIFT
27481 #undef LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_MASK
27482 #define LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_DEFVAL                                 0x00000000
27483 #define LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_SHIFT                                  27
27484 #define LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_MASK                                   0x08000000U
27485
27486 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27487                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27488 #undef LPD_XPPU_CFG_APERPERM_339_PARITY_DEFVAL
27489 #undef LPD_XPPU_CFG_APERPERM_339_PARITY_SHIFT
27490 #undef LPD_XPPU_CFG_APERPERM_339_PARITY_MASK
27491 #define LPD_XPPU_CFG_APERPERM_339_PARITY_DEFVAL                                    0x00000000
27492 #define LPD_XPPU_CFG_APERPERM_339_PARITY_SHIFT                                     28
27493 #define LPD_XPPU_CFG_APERPERM_339_PARITY_MASK                                      0xF0000000U
27494
27495 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27496                 h.*/
27497 #undef LPD_XPPU_CFG_APERPERM_340_PERMISSION_DEFVAL
27498 #undef LPD_XPPU_CFG_APERPERM_340_PERMISSION_SHIFT
27499 #undef LPD_XPPU_CFG_APERPERM_340_PERMISSION_MASK
27500 #define LPD_XPPU_CFG_APERPERM_340_PERMISSION_DEFVAL                                0x00000000
27501 #define LPD_XPPU_CFG_APERPERM_340_PERMISSION_SHIFT                                 0
27502 #define LPD_XPPU_CFG_APERPERM_340_PERMISSION_MASK                                  0x000FFFFFU
27503
27504 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27505 #undef LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_DEFVAL
27506 #undef LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_SHIFT
27507 #undef LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_MASK
27508 #define LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_DEFVAL                                 0x00000000
27509 #define LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_SHIFT                                  27
27510 #define LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_MASK                                   0x08000000U
27511
27512 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27513                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27514 #undef LPD_XPPU_CFG_APERPERM_340_PARITY_DEFVAL
27515 #undef LPD_XPPU_CFG_APERPERM_340_PARITY_SHIFT
27516 #undef LPD_XPPU_CFG_APERPERM_340_PARITY_MASK
27517 #define LPD_XPPU_CFG_APERPERM_340_PARITY_DEFVAL                                    0x00000000
27518 #define LPD_XPPU_CFG_APERPERM_340_PARITY_SHIFT                                     28
27519 #define LPD_XPPU_CFG_APERPERM_340_PARITY_MASK                                      0xF0000000U
27520
27521 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27522                 h.*/
27523 #undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_DEFVAL
27524 #undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT
27525 #undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK
27526 #define LPD_XPPU_CFG_APERPERM_341_PERMISSION_DEFVAL                                0x00000000
27527 #define LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT                                 0
27528 #define LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK                                  0x000FFFFFU
27529
27530 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27531 #undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_DEFVAL
27532 #undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT
27533 #undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK
27534 #define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_DEFVAL                                 0x00000000
27535 #define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT                                  27
27536 #define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK                                   0x08000000U
27537
27538 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27539                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27540 #undef LPD_XPPU_CFG_APERPERM_341_PARITY_DEFVAL
27541 #undef LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT
27542 #undef LPD_XPPU_CFG_APERPERM_341_PARITY_MASK
27543 #define LPD_XPPU_CFG_APERPERM_341_PARITY_DEFVAL                                    0x00000000
27544 #define LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT                                     28
27545 #define LPD_XPPU_CFG_APERPERM_341_PARITY_MASK                                      0xF0000000U
27546
27547 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27548                 h.*/
27549 #undef LPD_XPPU_CFG_APERPERM_350_PERMISSION_DEFVAL
27550 #undef LPD_XPPU_CFG_APERPERM_350_PERMISSION_SHIFT
27551 #undef LPD_XPPU_CFG_APERPERM_350_PERMISSION_MASK
27552 #define LPD_XPPU_CFG_APERPERM_350_PERMISSION_DEFVAL                                0x00000000
27553 #define LPD_XPPU_CFG_APERPERM_350_PERMISSION_SHIFT                                 0
27554 #define LPD_XPPU_CFG_APERPERM_350_PERMISSION_MASK                                  0x000FFFFFU
27555
27556 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27557 #undef LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_DEFVAL
27558 #undef LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_SHIFT
27559 #undef LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_MASK
27560 #define LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_DEFVAL                                 0x00000000
27561 #define LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_SHIFT                                  27
27562 #define LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_MASK                                   0x08000000U
27563
27564 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27565                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27566 #undef LPD_XPPU_CFG_APERPERM_350_PARITY_DEFVAL
27567 #undef LPD_XPPU_CFG_APERPERM_350_PARITY_SHIFT
27568 #undef LPD_XPPU_CFG_APERPERM_350_PARITY_MASK
27569 #define LPD_XPPU_CFG_APERPERM_350_PARITY_DEFVAL                                    0x00000000
27570 #define LPD_XPPU_CFG_APERPERM_350_PARITY_SHIFT                                     28
27571 #define LPD_XPPU_CFG_APERPERM_350_PARITY_MASK                                      0xF0000000U
27572
27573 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27574                 h.*/
27575 #undef LPD_XPPU_CFG_APERPERM_351_PERMISSION_DEFVAL
27576 #undef LPD_XPPU_CFG_APERPERM_351_PERMISSION_SHIFT
27577 #undef LPD_XPPU_CFG_APERPERM_351_PERMISSION_MASK
27578 #define LPD_XPPU_CFG_APERPERM_351_PERMISSION_DEFVAL                                0x00000000
27579 #define LPD_XPPU_CFG_APERPERM_351_PERMISSION_SHIFT                                 0
27580 #define LPD_XPPU_CFG_APERPERM_351_PERMISSION_MASK                                  0x000FFFFFU
27581
27582 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27583 #undef LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_DEFVAL
27584 #undef LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_SHIFT
27585 #undef LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_MASK
27586 #define LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_DEFVAL                                 0x00000000
27587 #define LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_SHIFT                                  27
27588 #define LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_MASK                                   0x08000000U
27589
27590 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27591                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27592 #undef LPD_XPPU_CFG_APERPERM_351_PARITY_DEFVAL
27593 #undef LPD_XPPU_CFG_APERPERM_351_PARITY_SHIFT
27594 #undef LPD_XPPU_CFG_APERPERM_351_PARITY_MASK
27595 #define LPD_XPPU_CFG_APERPERM_351_PARITY_DEFVAL                                    0x00000000
27596 #define LPD_XPPU_CFG_APERPERM_351_PARITY_SHIFT                                     28
27597 #define LPD_XPPU_CFG_APERPERM_351_PARITY_MASK                                      0xF0000000U
27598
27599 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27600                 h.*/
27601 #undef LPD_XPPU_CFG_APERPERM_352_PERMISSION_DEFVAL
27602 #undef LPD_XPPU_CFG_APERPERM_352_PERMISSION_SHIFT
27603 #undef LPD_XPPU_CFG_APERPERM_352_PERMISSION_MASK
27604 #define LPD_XPPU_CFG_APERPERM_352_PERMISSION_DEFVAL                                0x00000000
27605 #define LPD_XPPU_CFG_APERPERM_352_PERMISSION_SHIFT                                 0
27606 #define LPD_XPPU_CFG_APERPERM_352_PERMISSION_MASK                                  0x000FFFFFU
27607
27608 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27609 #undef LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_DEFVAL
27610 #undef LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_SHIFT
27611 #undef LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_MASK
27612 #define LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_DEFVAL                                 0x00000000
27613 #define LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_SHIFT                                  27
27614 #define LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_MASK                                   0x08000000U
27615
27616 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27617                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27618 #undef LPD_XPPU_CFG_APERPERM_352_PARITY_DEFVAL
27619 #undef LPD_XPPU_CFG_APERPERM_352_PARITY_SHIFT
27620 #undef LPD_XPPU_CFG_APERPERM_352_PARITY_MASK
27621 #define LPD_XPPU_CFG_APERPERM_352_PARITY_DEFVAL                                    0x00000000
27622 #define LPD_XPPU_CFG_APERPERM_352_PARITY_SHIFT                                     28
27623 #define LPD_XPPU_CFG_APERPERM_352_PARITY_MASK                                      0xF0000000U
27624
27625 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27626                 h.*/
27627 #undef LPD_XPPU_CFG_APERPERM_353_PERMISSION_DEFVAL
27628 #undef LPD_XPPU_CFG_APERPERM_353_PERMISSION_SHIFT
27629 #undef LPD_XPPU_CFG_APERPERM_353_PERMISSION_MASK
27630 #define LPD_XPPU_CFG_APERPERM_353_PERMISSION_DEFVAL                                0x00000000
27631 #define LPD_XPPU_CFG_APERPERM_353_PERMISSION_SHIFT                                 0
27632 #define LPD_XPPU_CFG_APERPERM_353_PERMISSION_MASK                                  0x000FFFFFU
27633
27634 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27635 #undef LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_DEFVAL
27636 #undef LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_SHIFT
27637 #undef LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_MASK
27638 #define LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_DEFVAL                                 0x00000000
27639 #define LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_SHIFT                                  27
27640 #define LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_MASK                                   0x08000000U
27641
27642 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27643                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27644 #undef LPD_XPPU_CFG_APERPERM_353_PARITY_DEFVAL
27645 #undef LPD_XPPU_CFG_APERPERM_353_PARITY_SHIFT
27646 #undef LPD_XPPU_CFG_APERPERM_353_PARITY_MASK
27647 #define LPD_XPPU_CFG_APERPERM_353_PARITY_DEFVAL                                    0x00000000
27648 #define LPD_XPPU_CFG_APERPERM_353_PARITY_SHIFT                                     28
27649 #define LPD_XPPU_CFG_APERPERM_353_PARITY_MASK                                      0xF0000000U
27650
27651 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27652                 h.*/
27653 #undef LPD_XPPU_CFG_APERPERM_354_PERMISSION_DEFVAL
27654 #undef LPD_XPPU_CFG_APERPERM_354_PERMISSION_SHIFT
27655 #undef LPD_XPPU_CFG_APERPERM_354_PERMISSION_MASK
27656 #define LPD_XPPU_CFG_APERPERM_354_PERMISSION_DEFVAL                                0x00000000
27657 #define LPD_XPPU_CFG_APERPERM_354_PERMISSION_SHIFT                                 0
27658 #define LPD_XPPU_CFG_APERPERM_354_PERMISSION_MASK                                  0x000FFFFFU
27659
27660 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27661 #undef LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_DEFVAL
27662 #undef LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_SHIFT
27663 #undef LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_MASK
27664 #define LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_DEFVAL                                 0x00000000
27665 #define LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_SHIFT                                  27
27666 #define LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_MASK                                   0x08000000U
27667
27668 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27669                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27670 #undef LPD_XPPU_CFG_APERPERM_354_PARITY_DEFVAL
27671 #undef LPD_XPPU_CFG_APERPERM_354_PARITY_SHIFT
27672 #undef LPD_XPPU_CFG_APERPERM_354_PARITY_MASK
27673 #define LPD_XPPU_CFG_APERPERM_354_PARITY_DEFVAL                                    0x00000000
27674 #define LPD_XPPU_CFG_APERPERM_354_PARITY_SHIFT                                     28
27675 #define LPD_XPPU_CFG_APERPERM_354_PARITY_MASK                                      0xF0000000U
27676
27677 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27678                 h.*/
27679 #undef LPD_XPPU_CFG_APERPERM_355_PERMISSION_DEFVAL
27680 #undef LPD_XPPU_CFG_APERPERM_355_PERMISSION_SHIFT
27681 #undef LPD_XPPU_CFG_APERPERM_355_PERMISSION_MASK
27682 #define LPD_XPPU_CFG_APERPERM_355_PERMISSION_DEFVAL                                0x00000000
27683 #define LPD_XPPU_CFG_APERPERM_355_PERMISSION_SHIFT                                 0
27684 #define LPD_XPPU_CFG_APERPERM_355_PERMISSION_MASK                                  0x000FFFFFU
27685
27686 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27687 #undef LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_DEFVAL
27688 #undef LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_SHIFT
27689 #undef LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_MASK
27690 #define LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_DEFVAL                                 0x00000000
27691 #define LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_SHIFT                                  27
27692 #define LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_MASK                                   0x08000000U
27693
27694 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27695                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27696 #undef LPD_XPPU_CFG_APERPERM_355_PARITY_DEFVAL
27697 #undef LPD_XPPU_CFG_APERPERM_355_PARITY_SHIFT
27698 #undef LPD_XPPU_CFG_APERPERM_355_PARITY_MASK
27699 #define LPD_XPPU_CFG_APERPERM_355_PARITY_DEFVAL                                    0x00000000
27700 #define LPD_XPPU_CFG_APERPERM_355_PARITY_SHIFT                                     28
27701 #define LPD_XPPU_CFG_APERPERM_355_PARITY_MASK                                      0xF0000000U
27702
27703 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27704                 h.*/
27705 #undef LPD_XPPU_CFG_APERPERM_356_PERMISSION_DEFVAL
27706 #undef LPD_XPPU_CFG_APERPERM_356_PERMISSION_SHIFT
27707 #undef LPD_XPPU_CFG_APERPERM_356_PERMISSION_MASK
27708 #define LPD_XPPU_CFG_APERPERM_356_PERMISSION_DEFVAL                                0x00000000
27709 #define LPD_XPPU_CFG_APERPERM_356_PERMISSION_SHIFT                                 0
27710 #define LPD_XPPU_CFG_APERPERM_356_PERMISSION_MASK                                  0x000FFFFFU
27711
27712 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27713 #undef LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_DEFVAL
27714 #undef LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_SHIFT
27715 #undef LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_MASK
27716 #define LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_DEFVAL                                 0x00000000
27717 #define LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_SHIFT                                  27
27718 #define LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_MASK                                   0x08000000U
27719
27720 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27721                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27722 #undef LPD_XPPU_CFG_APERPERM_356_PARITY_DEFVAL
27723 #undef LPD_XPPU_CFG_APERPERM_356_PARITY_SHIFT
27724 #undef LPD_XPPU_CFG_APERPERM_356_PARITY_MASK
27725 #define LPD_XPPU_CFG_APERPERM_356_PARITY_DEFVAL                                    0x00000000
27726 #define LPD_XPPU_CFG_APERPERM_356_PARITY_SHIFT                                     28
27727 #define LPD_XPPU_CFG_APERPERM_356_PARITY_MASK                                      0xF0000000U
27728
27729 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27730                 h.*/
27731 #undef LPD_XPPU_CFG_APERPERM_357_PERMISSION_DEFVAL
27732 #undef LPD_XPPU_CFG_APERPERM_357_PERMISSION_SHIFT
27733 #undef LPD_XPPU_CFG_APERPERM_357_PERMISSION_MASK
27734 #define LPD_XPPU_CFG_APERPERM_357_PERMISSION_DEFVAL                                0x00000000
27735 #define LPD_XPPU_CFG_APERPERM_357_PERMISSION_SHIFT                                 0
27736 #define LPD_XPPU_CFG_APERPERM_357_PERMISSION_MASK                                  0x000FFFFFU
27737
27738 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27739 #undef LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_DEFVAL
27740 #undef LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_SHIFT
27741 #undef LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_MASK
27742 #define LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_DEFVAL                                 0x00000000
27743 #define LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_SHIFT                                  27
27744 #define LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_MASK                                   0x08000000U
27745
27746 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27747                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27748 #undef LPD_XPPU_CFG_APERPERM_357_PARITY_DEFVAL
27749 #undef LPD_XPPU_CFG_APERPERM_357_PARITY_SHIFT
27750 #undef LPD_XPPU_CFG_APERPERM_357_PARITY_MASK
27751 #define LPD_XPPU_CFG_APERPERM_357_PARITY_DEFVAL                                    0x00000000
27752 #define LPD_XPPU_CFG_APERPERM_357_PARITY_SHIFT                                     28
27753 #define LPD_XPPU_CFG_APERPERM_357_PARITY_MASK                                      0xF0000000U
27754
27755 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27756                 h.*/
27757 #undef LPD_XPPU_CFG_APERPERM_366_PERMISSION_DEFVAL
27758 #undef LPD_XPPU_CFG_APERPERM_366_PERMISSION_SHIFT
27759 #undef LPD_XPPU_CFG_APERPERM_366_PERMISSION_MASK
27760 #define LPD_XPPU_CFG_APERPERM_366_PERMISSION_DEFVAL                                0x00000000
27761 #define LPD_XPPU_CFG_APERPERM_366_PERMISSION_SHIFT                                 0
27762 #define LPD_XPPU_CFG_APERPERM_366_PERMISSION_MASK                                  0x000FFFFFU
27763
27764 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27765 #undef LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_DEFVAL
27766 #undef LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_SHIFT
27767 #undef LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_MASK
27768 #define LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_DEFVAL                                 0x00000000
27769 #define LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_SHIFT                                  27
27770 #define LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_MASK                                   0x08000000U
27771
27772 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27773                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27774 #undef LPD_XPPU_CFG_APERPERM_366_PARITY_DEFVAL
27775 #undef LPD_XPPU_CFG_APERPERM_366_PARITY_SHIFT
27776 #undef LPD_XPPU_CFG_APERPERM_366_PARITY_MASK
27777 #define LPD_XPPU_CFG_APERPERM_366_PARITY_DEFVAL                                    0x00000000
27778 #define LPD_XPPU_CFG_APERPERM_366_PARITY_SHIFT                                     28
27779 #define LPD_XPPU_CFG_APERPERM_366_PARITY_MASK                                      0xF0000000U
27780
27781 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27782                 h.*/
27783 #undef LPD_XPPU_CFG_APERPERM_367_PERMISSION_DEFVAL
27784 #undef LPD_XPPU_CFG_APERPERM_367_PERMISSION_SHIFT
27785 #undef LPD_XPPU_CFG_APERPERM_367_PERMISSION_MASK
27786 #define LPD_XPPU_CFG_APERPERM_367_PERMISSION_DEFVAL                                0x00000000
27787 #define LPD_XPPU_CFG_APERPERM_367_PERMISSION_SHIFT                                 0
27788 #define LPD_XPPU_CFG_APERPERM_367_PERMISSION_MASK                                  0x000FFFFFU
27789
27790 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27791 #undef LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_DEFVAL
27792 #undef LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_SHIFT
27793 #undef LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_MASK
27794 #define LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_DEFVAL                                 0x00000000
27795 #define LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_SHIFT                                  27
27796 #define LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_MASK                                   0x08000000U
27797
27798 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27799                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27800 #undef LPD_XPPU_CFG_APERPERM_367_PARITY_DEFVAL
27801 #undef LPD_XPPU_CFG_APERPERM_367_PARITY_SHIFT
27802 #undef LPD_XPPU_CFG_APERPERM_367_PARITY_MASK
27803 #define LPD_XPPU_CFG_APERPERM_367_PARITY_DEFVAL                                    0x00000000
27804 #define LPD_XPPU_CFG_APERPERM_367_PARITY_SHIFT                                     28
27805 #define LPD_XPPU_CFG_APERPERM_367_PARITY_MASK                                      0xF0000000U
27806
27807 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27808                 h.*/
27809 #undef LPD_XPPU_CFG_APERPERM_368_PERMISSION_DEFVAL
27810 #undef LPD_XPPU_CFG_APERPERM_368_PERMISSION_SHIFT
27811 #undef LPD_XPPU_CFG_APERPERM_368_PERMISSION_MASK
27812 #define LPD_XPPU_CFG_APERPERM_368_PERMISSION_DEFVAL                                0x00000000
27813 #define LPD_XPPU_CFG_APERPERM_368_PERMISSION_SHIFT                                 0
27814 #define LPD_XPPU_CFG_APERPERM_368_PERMISSION_MASK                                  0x000FFFFFU
27815
27816 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27817 #undef LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_DEFVAL
27818 #undef LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_SHIFT
27819 #undef LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_MASK
27820 #define LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_DEFVAL                                 0x00000000
27821 #define LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_SHIFT                                  27
27822 #define LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_MASK                                   0x08000000U
27823
27824 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27825                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27826 #undef LPD_XPPU_CFG_APERPERM_368_PARITY_DEFVAL
27827 #undef LPD_XPPU_CFG_APERPERM_368_PARITY_SHIFT
27828 #undef LPD_XPPU_CFG_APERPERM_368_PARITY_MASK
27829 #define LPD_XPPU_CFG_APERPERM_368_PARITY_DEFVAL                                    0x00000000
27830 #define LPD_XPPU_CFG_APERPERM_368_PARITY_SHIFT                                     28
27831 #define LPD_XPPU_CFG_APERPERM_368_PARITY_MASK                                      0xF0000000U
27832
27833 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27834                 h.*/
27835 #undef LPD_XPPU_CFG_APERPERM_369_PERMISSION_DEFVAL
27836 #undef LPD_XPPU_CFG_APERPERM_369_PERMISSION_SHIFT
27837 #undef LPD_XPPU_CFG_APERPERM_369_PERMISSION_MASK
27838 #define LPD_XPPU_CFG_APERPERM_369_PERMISSION_DEFVAL                                0x00000000
27839 #define LPD_XPPU_CFG_APERPERM_369_PERMISSION_SHIFT                                 0
27840 #define LPD_XPPU_CFG_APERPERM_369_PERMISSION_MASK                                  0x000FFFFFU
27841
27842 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27843 #undef LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_DEFVAL
27844 #undef LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_SHIFT
27845 #undef LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_MASK
27846 #define LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_DEFVAL                                 0x00000000
27847 #define LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_SHIFT                                  27
27848 #define LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_MASK                                   0x08000000U
27849
27850 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27851                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27852 #undef LPD_XPPU_CFG_APERPERM_369_PARITY_DEFVAL
27853 #undef LPD_XPPU_CFG_APERPERM_369_PARITY_SHIFT
27854 #undef LPD_XPPU_CFG_APERPERM_369_PARITY_MASK
27855 #define LPD_XPPU_CFG_APERPERM_369_PARITY_DEFVAL                                    0x00000000
27856 #define LPD_XPPU_CFG_APERPERM_369_PARITY_SHIFT                                     28
27857 #define LPD_XPPU_CFG_APERPERM_369_PARITY_MASK                                      0xF0000000U
27858
27859 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27860                 h.*/
27861 #undef LPD_XPPU_CFG_APERPERM_370_PERMISSION_DEFVAL
27862 #undef LPD_XPPU_CFG_APERPERM_370_PERMISSION_SHIFT
27863 #undef LPD_XPPU_CFG_APERPERM_370_PERMISSION_MASK
27864 #define LPD_XPPU_CFG_APERPERM_370_PERMISSION_DEFVAL                                0x00000000
27865 #define LPD_XPPU_CFG_APERPERM_370_PERMISSION_SHIFT                                 0
27866 #define LPD_XPPU_CFG_APERPERM_370_PERMISSION_MASK                                  0x000FFFFFU
27867
27868 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27869 #undef LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_DEFVAL
27870 #undef LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_SHIFT
27871 #undef LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_MASK
27872 #define LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_DEFVAL                                 0x00000000
27873 #define LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_SHIFT                                  27
27874 #define LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_MASK                                   0x08000000U
27875
27876 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27877                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27878 #undef LPD_XPPU_CFG_APERPERM_370_PARITY_DEFVAL
27879 #undef LPD_XPPU_CFG_APERPERM_370_PARITY_SHIFT
27880 #undef LPD_XPPU_CFG_APERPERM_370_PARITY_MASK
27881 #define LPD_XPPU_CFG_APERPERM_370_PARITY_DEFVAL                                    0x00000000
27882 #define LPD_XPPU_CFG_APERPERM_370_PARITY_SHIFT                                     28
27883 #define LPD_XPPU_CFG_APERPERM_370_PARITY_MASK                                      0xF0000000U
27884
27885 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27886                 h.*/
27887 #undef LPD_XPPU_CFG_APERPERM_371_PERMISSION_DEFVAL
27888 #undef LPD_XPPU_CFG_APERPERM_371_PERMISSION_SHIFT
27889 #undef LPD_XPPU_CFG_APERPERM_371_PERMISSION_MASK
27890 #define LPD_XPPU_CFG_APERPERM_371_PERMISSION_DEFVAL                                0x00000000
27891 #define LPD_XPPU_CFG_APERPERM_371_PERMISSION_SHIFT                                 0
27892 #define LPD_XPPU_CFG_APERPERM_371_PERMISSION_MASK                                  0x000FFFFFU
27893
27894 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27895 #undef LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_DEFVAL
27896 #undef LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_SHIFT
27897 #undef LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_MASK
27898 #define LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_DEFVAL                                 0x00000000
27899 #define LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_SHIFT                                  27
27900 #define LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_MASK                                   0x08000000U
27901
27902 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27903                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27904 #undef LPD_XPPU_CFG_APERPERM_371_PARITY_DEFVAL
27905 #undef LPD_XPPU_CFG_APERPERM_371_PARITY_SHIFT
27906 #undef LPD_XPPU_CFG_APERPERM_371_PARITY_MASK
27907 #define LPD_XPPU_CFG_APERPERM_371_PARITY_DEFVAL                                    0x00000000
27908 #define LPD_XPPU_CFG_APERPERM_371_PARITY_SHIFT                                     28
27909 #define LPD_XPPU_CFG_APERPERM_371_PARITY_MASK                                      0xF0000000U
27910
27911 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27912                 h.*/
27913 #undef LPD_XPPU_CFG_APERPERM_372_PERMISSION_DEFVAL
27914 #undef LPD_XPPU_CFG_APERPERM_372_PERMISSION_SHIFT
27915 #undef LPD_XPPU_CFG_APERPERM_372_PERMISSION_MASK
27916 #define LPD_XPPU_CFG_APERPERM_372_PERMISSION_DEFVAL                                0x00000000
27917 #define LPD_XPPU_CFG_APERPERM_372_PERMISSION_SHIFT                                 0
27918 #define LPD_XPPU_CFG_APERPERM_372_PERMISSION_MASK                                  0x000FFFFFU
27919
27920 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27921 #undef LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_DEFVAL
27922 #undef LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_SHIFT
27923 #undef LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_MASK
27924 #define LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_DEFVAL                                 0x00000000
27925 #define LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_SHIFT                                  27
27926 #define LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_MASK                                   0x08000000U
27927
27928 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27929                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27930 #undef LPD_XPPU_CFG_APERPERM_372_PARITY_DEFVAL
27931 #undef LPD_XPPU_CFG_APERPERM_372_PARITY_SHIFT
27932 #undef LPD_XPPU_CFG_APERPERM_372_PARITY_MASK
27933 #define LPD_XPPU_CFG_APERPERM_372_PARITY_DEFVAL                                    0x00000000
27934 #define LPD_XPPU_CFG_APERPERM_372_PARITY_SHIFT                                     28
27935 #define LPD_XPPU_CFG_APERPERM_372_PARITY_MASK                                      0xF0000000U
27936
27937 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27938                 h.*/
27939 #undef LPD_XPPU_CFG_APERPERM_373_PERMISSION_DEFVAL
27940 #undef LPD_XPPU_CFG_APERPERM_373_PERMISSION_SHIFT
27941 #undef LPD_XPPU_CFG_APERPERM_373_PERMISSION_MASK
27942 #define LPD_XPPU_CFG_APERPERM_373_PERMISSION_DEFVAL                                0x00000000
27943 #define LPD_XPPU_CFG_APERPERM_373_PERMISSION_SHIFT                                 0
27944 #define LPD_XPPU_CFG_APERPERM_373_PERMISSION_MASK                                  0x000FFFFFU
27945
27946 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27947 #undef LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_DEFVAL
27948 #undef LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_SHIFT
27949 #undef LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_MASK
27950 #define LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_DEFVAL                                 0x00000000
27951 #define LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_SHIFT                                  27
27952 #define LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_MASK                                   0x08000000U
27953
27954 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27955                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27956 #undef LPD_XPPU_CFG_APERPERM_373_PARITY_DEFVAL
27957 #undef LPD_XPPU_CFG_APERPERM_373_PARITY_SHIFT
27958 #undef LPD_XPPU_CFG_APERPERM_373_PARITY_MASK
27959 #define LPD_XPPU_CFG_APERPERM_373_PARITY_DEFVAL                                    0x00000000
27960 #define LPD_XPPU_CFG_APERPERM_373_PARITY_SHIFT                                     28
27961 #define LPD_XPPU_CFG_APERPERM_373_PARITY_MASK                                      0xF0000000U
27962
27963 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27964                 h.*/
27965 #undef LPD_XPPU_CFG_APERPERM_374_PERMISSION_DEFVAL
27966 #undef LPD_XPPU_CFG_APERPERM_374_PERMISSION_SHIFT
27967 #undef LPD_XPPU_CFG_APERPERM_374_PERMISSION_MASK
27968 #define LPD_XPPU_CFG_APERPERM_374_PERMISSION_DEFVAL                                0x00000000
27969 #define LPD_XPPU_CFG_APERPERM_374_PERMISSION_SHIFT                                 0
27970 #define LPD_XPPU_CFG_APERPERM_374_PERMISSION_MASK                                  0x000FFFFFU
27971
27972 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27973 #undef LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_DEFVAL
27974 #undef LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_SHIFT
27975 #undef LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_MASK
27976 #define LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_DEFVAL                                 0x00000000
27977 #define LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_SHIFT                                  27
27978 #define LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_MASK                                   0x08000000U
27979
27980 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
27981                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
27982 #undef LPD_XPPU_CFG_APERPERM_374_PARITY_DEFVAL
27983 #undef LPD_XPPU_CFG_APERPERM_374_PARITY_SHIFT
27984 #undef LPD_XPPU_CFG_APERPERM_374_PARITY_MASK
27985 #define LPD_XPPU_CFG_APERPERM_374_PARITY_DEFVAL                                    0x00000000
27986 #define LPD_XPPU_CFG_APERPERM_374_PARITY_SHIFT                                     28
27987 #define LPD_XPPU_CFG_APERPERM_374_PARITY_MASK                                      0xF0000000U
27988
27989 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
27990                 h.*/
27991 #undef LPD_XPPU_CFG_APERPERM_375_PERMISSION_DEFVAL
27992 #undef LPD_XPPU_CFG_APERPERM_375_PERMISSION_SHIFT
27993 #undef LPD_XPPU_CFG_APERPERM_375_PERMISSION_MASK
27994 #define LPD_XPPU_CFG_APERPERM_375_PERMISSION_DEFVAL                                0x00000000
27995 #define LPD_XPPU_CFG_APERPERM_375_PERMISSION_SHIFT                                 0
27996 #define LPD_XPPU_CFG_APERPERM_375_PERMISSION_MASK                                  0x000FFFFFU
27997
27998 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
27999 #undef LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_DEFVAL
28000 #undef LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_SHIFT
28001 #undef LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_MASK
28002 #define LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_DEFVAL                                 0x00000000
28003 #define LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_SHIFT                                  27
28004 #define LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_MASK                                   0x08000000U
28005
28006 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28007                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28008 #undef LPD_XPPU_CFG_APERPERM_375_PARITY_DEFVAL
28009 #undef LPD_XPPU_CFG_APERPERM_375_PARITY_SHIFT
28010 #undef LPD_XPPU_CFG_APERPERM_375_PARITY_MASK
28011 #define LPD_XPPU_CFG_APERPERM_375_PARITY_DEFVAL                                    0x00000000
28012 #define LPD_XPPU_CFG_APERPERM_375_PARITY_SHIFT                                     28
28013 #define LPD_XPPU_CFG_APERPERM_375_PARITY_MASK                                      0xF0000000U
28014
28015 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28016                 h.*/
28017 #undef LPD_XPPU_CFG_APERPERM_376_PERMISSION_DEFVAL
28018 #undef LPD_XPPU_CFG_APERPERM_376_PERMISSION_SHIFT
28019 #undef LPD_XPPU_CFG_APERPERM_376_PERMISSION_MASK
28020 #define LPD_XPPU_CFG_APERPERM_376_PERMISSION_DEFVAL                                0x00000000
28021 #define LPD_XPPU_CFG_APERPERM_376_PERMISSION_SHIFT                                 0
28022 #define LPD_XPPU_CFG_APERPERM_376_PERMISSION_MASK                                  0x000FFFFFU
28023
28024 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28025 #undef LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_DEFVAL
28026 #undef LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_SHIFT
28027 #undef LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_MASK
28028 #define LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_DEFVAL                                 0x00000000
28029 #define LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_SHIFT                                  27
28030 #define LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_MASK                                   0x08000000U
28031
28032 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28033                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28034 #undef LPD_XPPU_CFG_APERPERM_376_PARITY_DEFVAL
28035 #undef LPD_XPPU_CFG_APERPERM_376_PARITY_SHIFT
28036 #undef LPD_XPPU_CFG_APERPERM_376_PARITY_MASK
28037 #define LPD_XPPU_CFG_APERPERM_376_PARITY_DEFVAL                                    0x00000000
28038 #define LPD_XPPU_CFG_APERPERM_376_PARITY_SHIFT                                     28
28039 #define LPD_XPPU_CFG_APERPERM_376_PARITY_MASK                                      0xF0000000U
28040
28041 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28042                 h.*/
28043 #undef LPD_XPPU_CFG_APERPERM_377_PERMISSION_DEFVAL
28044 #undef LPD_XPPU_CFG_APERPERM_377_PERMISSION_SHIFT
28045 #undef LPD_XPPU_CFG_APERPERM_377_PERMISSION_MASK
28046 #define LPD_XPPU_CFG_APERPERM_377_PERMISSION_DEFVAL                                0x00000000
28047 #define LPD_XPPU_CFG_APERPERM_377_PERMISSION_SHIFT                                 0
28048 #define LPD_XPPU_CFG_APERPERM_377_PERMISSION_MASK                                  0x000FFFFFU
28049
28050 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28051 #undef LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_DEFVAL
28052 #undef LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_SHIFT
28053 #undef LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_MASK
28054 #define LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_DEFVAL                                 0x00000000
28055 #define LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_SHIFT                                  27
28056 #define LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_MASK                                   0x08000000U
28057
28058 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28059                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28060 #undef LPD_XPPU_CFG_APERPERM_377_PARITY_DEFVAL
28061 #undef LPD_XPPU_CFG_APERPERM_377_PARITY_SHIFT
28062 #undef LPD_XPPU_CFG_APERPERM_377_PARITY_MASK
28063 #define LPD_XPPU_CFG_APERPERM_377_PARITY_DEFVAL                                    0x00000000
28064 #define LPD_XPPU_CFG_APERPERM_377_PARITY_SHIFT                                     28
28065 #define LPD_XPPU_CFG_APERPERM_377_PARITY_MASK                                      0xF0000000U
28066
28067 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28068                 h.*/
28069 #undef LPD_XPPU_CFG_APERPERM_378_PERMISSION_DEFVAL
28070 #undef LPD_XPPU_CFG_APERPERM_378_PERMISSION_SHIFT
28071 #undef LPD_XPPU_CFG_APERPERM_378_PERMISSION_MASK
28072 #define LPD_XPPU_CFG_APERPERM_378_PERMISSION_DEFVAL                                0x00000000
28073 #define LPD_XPPU_CFG_APERPERM_378_PERMISSION_SHIFT                                 0
28074 #define LPD_XPPU_CFG_APERPERM_378_PERMISSION_MASK                                  0x000FFFFFU
28075
28076 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28077 #undef LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_DEFVAL
28078 #undef LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_SHIFT
28079 #undef LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_MASK
28080 #define LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_DEFVAL                                 0x00000000
28081 #define LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_SHIFT                                  27
28082 #define LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_MASK                                   0x08000000U
28083
28084 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28085                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28086 #undef LPD_XPPU_CFG_APERPERM_378_PARITY_DEFVAL
28087 #undef LPD_XPPU_CFG_APERPERM_378_PARITY_SHIFT
28088 #undef LPD_XPPU_CFG_APERPERM_378_PARITY_MASK
28089 #define LPD_XPPU_CFG_APERPERM_378_PARITY_DEFVAL                                    0x00000000
28090 #define LPD_XPPU_CFG_APERPERM_378_PARITY_SHIFT                                     28
28091 #define LPD_XPPU_CFG_APERPERM_378_PARITY_MASK                                      0xF0000000U
28092
28093 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28094                 h.*/
28095 #undef LPD_XPPU_CFG_APERPERM_379_PERMISSION_DEFVAL
28096 #undef LPD_XPPU_CFG_APERPERM_379_PERMISSION_SHIFT
28097 #undef LPD_XPPU_CFG_APERPERM_379_PERMISSION_MASK
28098 #define LPD_XPPU_CFG_APERPERM_379_PERMISSION_DEFVAL                                0x00000000
28099 #define LPD_XPPU_CFG_APERPERM_379_PERMISSION_SHIFT                                 0
28100 #define LPD_XPPU_CFG_APERPERM_379_PERMISSION_MASK                                  0x000FFFFFU
28101
28102 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28103 #undef LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_DEFVAL
28104 #undef LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_SHIFT
28105 #undef LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_MASK
28106 #define LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_DEFVAL                                 0x00000000
28107 #define LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_SHIFT                                  27
28108 #define LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_MASK                                   0x08000000U
28109
28110 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28111                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28112 #undef LPD_XPPU_CFG_APERPERM_379_PARITY_DEFVAL
28113 #undef LPD_XPPU_CFG_APERPERM_379_PARITY_SHIFT
28114 #undef LPD_XPPU_CFG_APERPERM_379_PARITY_MASK
28115 #define LPD_XPPU_CFG_APERPERM_379_PARITY_DEFVAL                                    0x00000000
28116 #define LPD_XPPU_CFG_APERPERM_379_PARITY_SHIFT                                     28
28117 #define LPD_XPPU_CFG_APERPERM_379_PARITY_MASK                                      0xF0000000U
28118
28119 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28120                 h.*/
28121 #undef LPD_XPPU_CFG_APERPERM_380_PERMISSION_DEFVAL
28122 #undef LPD_XPPU_CFG_APERPERM_380_PERMISSION_SHIFT
28123 #undef LPD_XPPU_CFG_APERPERM_380_PERMISSION_MASK
28124 #define LPD_XPPU_CFG_APERPERM_380_PERMISSION_DEFVAL                                0x00000000
28125 #define LPD_XPPU_CFG_APERPERM_380_PERMISSION_SHIFT                                 0
28126 #define LPD_XPPU_CFG_APERPERM_380_PERMISSION_MASK                                  0x000FFFFFU
28127
28128 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28129 #undef LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_DEFVAL
28130 #undef LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_SHIFT
28131 #undef LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_MASK
28132 #define LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_DEFVAL                                 0x00000000
28133 #define LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_SHIFT                                  27
28134 #define LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_MASK                                   0x08000000U
28135
28136 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28137                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28138 #undef LPD_XPPU_CFG_APERPERM_380_PARITY_DEFVAL
28139 #undef LPD_XPPU_CFG_APERPERM_380_PARITY_SHIFT
28140 #undef LPD_XPPU_CFG_APERPERM_380_PARITY_MASK
28141 #define LPD_XPPU_CFG_APERPERM_380_PARITY_DEFVAL                                    0x00000000
28142 #define LPD_XPPU_CFG_APERPERM_380_PARITY_SHIFT                                     28
28143 #define LPD_XPPU_CFG_APERPERM_380_PARITY_MASK                                      0xF0000000U
28144
28145 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28146                 h.*/
28147 #undef LPD_XPPU_CFG_APERPERM_381_PERMISSION_DEFVAL
28148 #undef LPD_XPPU_CFG_APERPERM_381_PERMISSION_SHIFT
28149 #undef LPD_XPPU_CFG_APERPERM_381_PERMISSION_MASK
28150 #define LPD_XPPU_CFG_APERPERM_381_PERMISSION_DEFVAL                                0x00000000
28151 #define LPD_XPPU_CFG_APERPERM_381_PERMISSION_SHIFT                                 0
28152 #define LPD_XPPU_CFG_APERPERM_381_PERMISSION_MASK                                  0x000FFFFFU
28153
28154 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28155 #undef LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_DEFVAL
28156 #undef LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_SHIFT
28157 #undef LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_MASK
28158 #define LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_DEFVAL                                 0x00000000
28159 #define LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_SHIFT                                  27
28160 #define LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_MASK                                   0x08000000U
28161
28162 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28163                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28164 #undef LPD_XPPU_CFG_APERPERM_381_PARITY_DEFVAL
28165 #undef LPD_XPPU_CFG_APERPERM_381_PARITY_SHIFT
28166 #undef LPD_XPPU_CFG_APERPERM_381_PARITY_MASK
28167 #define LPD_XPPU_CFG_APERPERM_381_PARITY_DEFVAL                                    0x00000000
28168 #define LPD_XPPU_CFG_APERPERM_381_PARITY_SHIFT                                     28
28169 #define LPD_XPPU_CFG_APERPERM_381_PARITY_MASK                                      0xF0000000U
28170
28171 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28172                 h.*/
28173 #undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_DEFVAL
28174 #undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT
28175 #undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK
28176 #define LPD_XPPU_CFG_APERPERM_382_PERMISSION_DEFVAL                                0x00000000
28177 #define LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT                                 0
28178 #define LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK                                  0x000FFFFFU
28179
28180 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28181 #undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_DEFVAL
28182 #undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT
28183 #undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK
28184 #define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_DEFVAL                                 0x00000000
28185 #define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT                                  27
28186 #define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK                                   0x08000000U
28187
28188 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28189                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28190 #undef LPD_XPPU_CFG_APERPERM_382_PARITY_DEFVAL
28191 #undef LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT
28192 #undef LPD_XPPU_CFG_APERPERM_382_PARITY_MASK
28193 #define LPD_XPPU_CFG_APERPERM_382_PARITY_DEFVAL                                    0x00000000
28194 #define LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT                                     28
28195 #define LPD_XPPU_CFG_APERPERM_382_PARITY_MASK                                      0xF0000000U
28196
28197 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28198                 h.*/
28199 #undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_DEFVAL
28200 #undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT
28201 #undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK
28202 #define LPD_XPPU_CFG_APERPERM_383_PERMISSION_DEFVAL                                0x00000000
28203 #define LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT                                 0
28204 #define LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK                                  0x000FFFFFU
28205
28206 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28207 #undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_DEFVAL
28208 #undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT
28209 #undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK
28210 #define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_DEFVAL                                 0x00000000
28211 #define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT                                  27
28212 #define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK                                   0x08000000U
28213
28214 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28215                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28216 #undef LPD_XPPU_CFG_APERPERM_383_PARITY_DEFVAL
28217 #undef LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT
28218 #undef LPD_XPPU_CFG_APERPERM_383_PARITY_MASK
28219 #define LPD_XPPU_CFG_APERPERM_383_PARITY_DEFVAL                                    0x00000000
28220 #define LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT                                     28
28221 #define LPD_XPPU_CFG_APERPERM_383_PARITY_MASK                                      0xF0000000U
28222
28223 /*Whether an APB access to the "hole" region and to an unimplemented register space causes PSLVERR*/
28224 #undef LPD_XPPU_SINK_ERR_CTRL_PSLVERR_DEFVAL
28225 #undef LPD_XPPU_SINK_ERR_CTRL_PSLVERR_SHIFT
28226 #undef LPD_XPPU_SINK_ERR_CTRL_PSLVERR_MASK
28227 #define LPD_XPPU_SINK_ERR_CTRL_PSLVERR_DEFVAL                                      0x00000000
28228 #define LPD_XPPU_SINK_ERR_CTRL_PSLVERR_SHIFT                                       0
28229 #define LPD_XPPU_SINK_ERR_CTRL_PSLVERR_MASK                                        0x00000001U
28230
28231 /*0=Bypass XPPU (transparent) 1=Enable XPPU permission checking*/
28232 #undef LPD_XPPU_CFG_CTRL_ENABLE_DEFVAL
28233 #undef LPD_XPPU_CFG_CTRL_ENABLE_SHIFT
28234 #undef LPD_XPPU_CFG_CTRL_ENABLE_MASK
28235 #define LPD_XPPU_CFG_CTRL_ENABLE_DEFVAL                                            0x00000000
28236 #define LPD_XPPU_CFG_CTRL_ENABLE_SHIFT                                             0
28237 #define LPD_XPPU_CFG_CTRL_ENABLE_MASK                                              0x00000001U
28238
28239 /*See Interuppt Status Register for details*/
28240 #undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL
28241 #undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
28242 #undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK
28243 #define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL                                        0x00000000
28244 #define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT                                         7
28245 #define LPD_XPPU_CFG_IEN_APER_PARITY_MASK                                          0x00000080U
28246
28247 /*See Interuppt Status Register for details*/
28248 #undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL
28249 #undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
28250 #undef LPD_XPPU_CFG_IEN_APER_TZ_MASK
28251 #define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL                                            0x00000000
28252 #define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT                                             6
28253 #define LPD_XPPU_CFG_IEN_APER_TZ_MASK                                              0x00000040U
28254
28255 /*See Interuppt Status Register for details*/
28256 #undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL
28257 #undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
28258 #undef LPD_XPPU_CFG_IEN_APER_PERM_MASK
28259 #define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL                                          0x00000000
28260 #define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT                                           5
28261 #define LPD_XPPU_CFG_IEN_APER_PERM_MASK                                            0x00000020U
28262
28263 /*See Interuppt Status Register for details*/
28264 #undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL
28265 #undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
28266 #undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK
28267 #define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL                                         0x00000000
28268 #define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT                                          3
28269 #define LPD_XPPU_CFG_IEN_MID_PARITY_MASK                                           0x00000008U
28270
28271 /*See Interuppt Status Register for details*/
28272 #undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL
28273 #undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT
28274 #undef LPD_XPPU_CFG_IEN_MID_RO_MASK
28275 #define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL                                             0x00000000
28276 #define LPD_XPPU_CFG_IEN_MID_RO_SHIFT                                              2
28277 #define LPD_XPPU_CFG_IEN_MID_RO_MASK                                               0x00000004U
28278
28279 /*See Interuppt Status Register for details*/
28280 #undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL
28281 #undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
28282 #undef LPD_XPPU_CFG_IEN_MID_MISS_MASK
28283 #define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL                                           0x00000000
28284 #define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT                                            1
28285 #define LPD_XPPU_CFG_IEN_MID_MISS_MASK                                             0x00000002U
28286
28287 /*See Interuppt Status Register for details*/
28288 #undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL
28289 #undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT
28290 #undef LPD_XPPU_CFG_IEN_INV_APB_MASK
28291 #define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL                                            0x00000000
28292 #define LPD_XPPU_CFG_IEN_INV_APB_SHIFT                                             0
28293 #define LPD_XPPU_CFG_IEN_INV_APB_MASK                                              0x00000001U
28294 #undef LPD_XPPU_CFG_APERPERM_152_OFFSET
28295 #define LPD_XPPU_CFG_APERPERM_152_OFFSET                                           0XFF981260
28296
28297 /*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
28298                 h.*/
28299 #undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_DEFVAL
28300 #undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT
28301 #undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK
28302 #define LPD_XPPU_CFG_APERPERM_152_PERMISSION_DEFVAL                                0x00000000
28303 #define LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT                                 0
28304 #define LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK                                  0x000FFFFFU
28305
28306 /*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
28307 #undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_DEFVAL
28308 #undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT
28309 #undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK
28310 #define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_DEFVAL                                 0x00000000
28311 #define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT                                  27
28312 #define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK                                   0x08000000U
28313
28314 /*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
28315                  bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
28316 #undef LPD_XPPU_CFG_APERPERM_152_PARITY_DEFVAL
28317 #undef LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT
28318 #undef LPD_XPPU_CFG_APERPERM_152_PARITY_MASK
28319 #define LPD_XPPU_CFG_APERPERM_152_PARITY_DEFVAL                                    0x00000000
28320 #define LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT                                     28
28321 #define LPD_XPPU_CFG_APERPERM_152_PARITY_MASK                                      0xF0000000U
28322 #undef SERDES_PLL_REF_SEL0_OFFSET
28323 #define SERDES_PLL_REF_SEL0_OFFSET                                                 0XFD410000
28324 #undef SERDES_PLL_REF_SEL1_OFFSET
28325 #define SERDES_PLL_REF_SEL1_OFFSET                                                 0XFD410004
28326 #undef SERDES_PLL_REF_SEL2_OFFSET
28327 #define SERDES_PLL_REF_SEL2_OFFSET                                                 0XFD410008
28328 #undef SERDES_PLL_REF_SEL3_OFFSET
28329 #define SERDES_PLL_REF_SEL3_OFFSET                                                 0XFD41000C
28330 #undef SERDES_L0_L0_REF_CLK_SEL_OFFSET
28331 #define SERDES_L0_L0_REF_CLK_SEL_OFFSET                                            0XFD402860
28332 #undef SERDES_L0_L1_REF_CLK_SEL_OFFSET
28333 #define SERDES_L0_L1_REF_CLK_SEL_OFFSET                                            0XFD402864
28334 #undef SERDES_L0_L2_REF_CLK_SEL_OFFSET
28335 #define SERDES_L0_L2_REF_CLK_SEL_OFFSET                                            0XFD402868
28336 #undef SERDES_L0_L3_REF_CLK_SEL_OFFSET
28337 #define SERDES_L0_L3_REF_CLK_SEL_OFFSET                                            0XFD40286C
28338 #undef SERDES_L2_TM_PLL_DIG_37_OFFSET
28339 #define SERDES_L2_TM_PLL_DIG_37_OFFSET                                             0XFD40A094
28340 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET
28341 #define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40A368
28342 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET
28343 #define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40A36C
28344 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET
28345 #define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40E368
28346 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET
28347 #define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40E36C
28348 #undef SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET
28349 #define SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD402368
28350 #undef SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET
28351 #define SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40236C
28352 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET
28353 #define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD406368
28354 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET
28355 #define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40636C
28356 #undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET
28357 #define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD402370
28358 #undef SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET
28359 #define SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD402374
28360 #undef SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET
28361 #define SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD402378
28362 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET
28363 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40237C
28364 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET
28365 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD406370
28366 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET
28367 #define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD406374
28368 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET
28369 #define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD406378
28370 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET
28371 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40637C
28372 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET
28373 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40A370
28374 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET
28375 #define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40A374
28376 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET
28377 #define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40A378
28378 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET
28379 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40A37C
28380 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET
28381 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40E370
28382 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET
28383 #define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40E374
28384 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET
28385 #define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40E378
28386 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET
28387 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40E37C
28388 #undef SERDES_L2_TM_DIG_6_OFFSET
28389 #define SERDES_L2_TM_DIG_6_OFFSET                                                  0XFD40906C
28390 #undef SERDES_L2_TX_DIG_TM_61_OFFSET
28391 #define SERDES_L2_TX_DIG_TM_61_OFFSET                                              0XFD4080F4
28392 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET
28393 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET                                      0XFD40E360
28394 #undef SERDES_L3_TM_DIG_6_OFFSET
28395 #define SERDES_L3_TM_DIG_6_OFFSET                                                  0XFD40D06C
28396 #undef SERDES_L3_TX_DIG_TM_61_OFFSET
28397 #define SERDES_L3_TX_DIG_TM_61_OFFSET                                              0XFD40C0F4
28398 #undef SERDES_L3_TXPMA_ST_0_OFFSET
28399 #define SERDES_L3_TXPMA_ST_0_OFFSET                                                0XFD40CB00
28400 #undef SERDES_L2_TM_AUX_0_OFFSET
28401 #define SERDES_L2_TM_AUX_0_OFFSET                                                  0XFD4090CC
28402 #undef SERDES_L0_TM_DIG_8_OFFSET
28403 #define SERDES_L0_TM_DIG_8_OFFSET                                                  0XFD401074
28404 #undef SERDES_L1_TM_DIG_8_OFFSET
28405 #define SERDES_L1_TM_DIG_8_OFFSET                                                  0XFD405074
28406 #undef SERDES_L2_TM_DIG_8_OFFSET
28407 #define SERDES_L2_TM_DIG_8_OFFSET                                                  0XFD409074
28408 #undef SERDES_L3_TM_DIG_8_OFFSET
28409 #define SERDES_L3_TM_DIG_8_OFFSET                                                  0XFD40D074
28410 #undef SERDES_L2_TM_MISC2_OFFSET
28411 #define SERDES_L2_TM_MISC2_OFFSET                                                  0XFD40989C
28412 #undef SERDES_L2_TM_IQ_ILL1_OFFSET
28413 #define SERDES_L2_TM_IQ_ILL1_OFFSET                                                0XFD4098F8
28414 #undef SERDES_L2_TM_IQ_ILL2_OFFSET
28415 #define SERDES_L2_TM_IQ_ILL2_OFFSET                                                0XFD4098FC
28416 #undef SERDES_L2_TM_ILL12_OFFSET
28417 #define SERDES_L2_TM_ILL12_OFFSET                                                  0XFD409990
28418 #undef SERDES_L2_TM_E_ILL1_OFFSET
28419 #define SERDES_L2_TM_E_ILL1_OFFSET                                                 0XFD409924
28420 #undef SERDES_L2_TM_E_ILL2_OFFSET
28421 #define SERDES_L2_TM_E_ILL2_OFFSET                                                 0XFD409928
28422 #undef SERDES_L2_TM_IQ_ILL3_OFFSET
28423 #define SERDES_L2_TM_IQ_ILL3_OFFSET                                                0XFD409900
28424 #undef SERDES_L2_TM_E_ILL3_OFFSET
28425 #define SERDES_L2_TM_E_ILL3_OFFSET                                                 0XFD40992C
28426 #undef SERDES_L2_TM_ILL8_OFFSET
28427 #define SERDES_L2_TM_ILL8_OFFSET                                                   0XFD409980
28428 #undef SERDES_L2_TM_IQ_ILL8_OFFSET
28429 #define SERDES_L2_TM_IQ_ILL8_OFFSET                                                0XFD409914
28430 #undef SERDES_L2_TM_IQ_ILL9_OFFSET
28431 #define SERDES_L2_TM_IQ_ILL9_OFFSET                                                0XFD409918
28432 #undef SERDES_L2_TM_E_ILL8_OFFSET
28433 #define SERDES_L2_TM_E_ILL8_OFFSET                                                 0XFD409940
28434 #undef SERDES_L2_TM_E_ILL9_OFFSET
28435 #define SERDES_L2_TM_E_ILL9_OFFSET                                                 0XFD409944
28436 #undef SERDES_L3_TM_MISC2_OFFSET
28437 #define SERDES_L3_TM_MISC2_OFFSET                                                  0XFD40D89C
28438 #undef SERDES_L3_TM_IQ_ILL1_OFFSET
28439 #define SERDES_L3_TM_IQ_ILL1_OFFSET                                                0XFD40D8F8
28440 #undef SERDES_L3_TM_IQ_ILL2_OFFSET
28441 #define SERDES_L3_TM_IQ_ILL2_OFFSET                                                0XFD40D8FC
28442 #undef SERDES_L3_TM_ILL12_OFFSET
28443 #define SERDES_L3_TM_ILL12_OFFSET                                                  0XFD40D990
28444 #undef SERDES_L3_TM_E_ILL1_OFFSET
28445 #define SERDES_L3_TM_E_ILL1_OFFSET                                                 0XFD40D924
28446 #undef SERDES_L3_TM_E_ILL2_OFFSET
28447 #define SERDES_L3_TM_E_ILL2_OFFSET                                                 0XFD40D928
28448 #undef SERDES_L3_TM_ILL11_OFFSET
28449 #define SERDES_L3_TM_ILL11_OFFSET                                                  0XFD40D98C
28450 #undef SERDES_L3_TM_IQ_ILL3_OFFSET
28451 #define SERDES_L3_TM_IQ_ILL3_OFFSET                                                0XFD40D900
28452 #undef SERDES_L3_TM_E_ILL3_OFFSET
28453 #define SERDES_L3_TM_E_ILL3_OFFSET                                                 0XFD40D92C
28454 #undef SERDES_L3_TM_ILL8_OFFSET
28455 #define SERDES_L3_TM_ILL8_OFFSET                                                   0XFD40D980
28456 #undef SERDES_L3_TM_IQ_ILL8_OFFSET
28457 #define SERDES_L3_TM_IQ_ILL8_OFFSET                                                0XFD40D914
28458 #undef SERDES_L3_TM_IQ_ILL9_OFFSET
28459 #define SERDES_L3_TM_IQ_ILL9_OFFSET                                                0XFD40D918
28460 #undef SERDES_L3_TM_E_ILL8_OFFSET
28461 #define SERDES_L3_TM_E_ILL8_OFFSET                                                 0XFD40D940
28462 #undef SERDES_L3_TM_E_ILL9_OFFSET
28463 #define SERDES_L3_TM_E_ILL9_OFFSET                                                 0XFD40D944
28464 #undef SERDES_L0_TM_RST_DLY_OFFSET
28465 #define SERDES_L0_TM_RST_DLY_OFFSET                                                0XFD4019A4
28466 #undef SERDES_L0_TM_ANA_BYP_15_OFFSET
28467 #define SERDES_L0_TM_ANA_BYP_15_OFFSET                                             0XFD401038
28468 #undef SERDES_L0_TM_ANA_BYP_12_OFFSET
28469 #define SERDES_L0_TM_ANA_BYP_12_OFFSET                                             0XFD40102C
28470 #undef SERDES_L1_TM_RST_DLY_OFFSET
28471 #define SERDES_L1_TM_RST_DLY_OFFSET                                                0XFD4059A4
28472 #undef SERDES_L1_TM_ANA_BYP_15_OFFSET
28473 #define SERDES_L1_TM_ANA_BYP_15_OFFSET                                             0XFD405038
28474 #undef SERDES_L1_TM_ANA_BYP_12_OFFSET
28475 #define SERDES_L1_TM_ANA_BYP_12_OFFSET                                             0XFD40502C
28476 #undef SERDES_L2_TM_RST_DLY_OFFSET
28477 #define SERDES_L2_TM_RST_DLY_OFFSET                                                0XFD4099A4
28478 #undef SERDES_L2_TM_ANA_BYP_15_OFFSET
28479 #define SERDES_L2_TM_ANA_BYP_15_OFFSET                                             0XFD409038
28480 #undef SERDES_L2_TM_ANA_BYP_12_OFFSET
28481 #define SERDES_L2_TM_ANA_BYP_12_OFFSET                                             0XFD40902C
28482 #undef SERDES_L3_TM_RST_DLY_OFFSET
28483 #define SERDES_L3_TM_RST_DLY_OFFSET                                                0XFD40D9A4
28484 #undef SERDES_L3_TM_ANA_BYP_15_OFFSET
28485 #define SERDES_L3_TM_ANA_BYP_15_OFFSET                                             0XFD40D038
28486 #undef SERDES_L3_TM_ANA_BYP_12_OFFSET
28487 #define SERDES_L3_TM_ANA_BYP_12_OFFSET                                             0XFD40D02C
28488 #undef SERDES_ICM_CFG0_OFFSET
28489 #define SERDES_ICM_CFG0_OFFSET                                                     0XFD410010
28490 #undef SERDES_ICM_CFG1_OFFSET
28491 #define SERDES_ICM_CFG1_OFFSET                                                     0XFD410014
28492 #undef SERDES_L0_TXPMD_TM_45_OFFSET
28493 #define SERDES_L0_TXPMD_TM_45_OFFSET                                               0XFD400CB4
28494 #undef SERDES_L1_TXPMD_TM_45_OFFSET
28495 #define SERDES_L1_TXPMD_TM_45_OFFSET                                               0XFD404CB4
28496 #undef SERDES_L0_TX_ANA_TM_118_OFFSET
28497 #define SERDES_L0_TX_ANA_TM_118_OFFSET                                             0XFD4001D8
28498 #undef SERDES_L1_TX_ANA_TM_118_OFFSET
28499 #define SERDES_L1_TX_ANA_TM_118_OFFSET                                             0XFD4041D8
28500 #undef SERDES_L3_TX_ANA_TM_118_OFFSET
28501 #define SERDES_L3_TX_ANA_TM_118_OFFSET                                             0XFD40C1D8
28502 #undef SERDES_L3_TM_CDR5_OFFSET
28503 #define SERDES_L3_TM_CDR5_OFFSET                                                   0XFD40DC14
28504 #undef SERDES_L3_TM_CDR16_OFFSET
28505 #define SERDES_L3_TM_CDR16_OFFSET                                                  0XFD40DC40
28506 #undef SERDES_L3_TM_EQ0_OFFSET
28507 #define SERDES_L3_TM_EQ0_OFFSET                                                    0XFD40D94C
28508 #undef SERDES_L3_TM_EQ1_OFFSET
28509 #define SERDES_L3_TM_EQ1_OFFSET                                                    0XFD40D950
28510 #undef SERDES_L1_TXPMD_TM_48_OFFSET
28511 #define SERDES_L1_TXPMD_TM_48_OFFSET                                               0XFD404CC0
28512 #undef SERDES_L0_TXPMD_TM_48_OFFSET
28513 #define SERDES_L0_TXPMD_TM_48_OFFSET                                               0XFD400CC0
28514 #undef SERDES_L1_TX_ANA_TM_18_OFFSET
28515 #define SERDES_L1_TX_ANA_TM_18_OFFSET                                              0XFD404048
28516 #undef SERDES_L0_TX_ANA_TM_18_OFFSET
28517 #define SERDES_L0_TX_ANA_TM_18_OFFSET                                              0XFD400048
28518 #undef SERDES_L3_TX_ANA_TM_18_OFFSET
28519 #define SERDES_L3_TX_ANA_TM_18_OFFSET                                              0XFD40C048
28520
28521 /*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
28522                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
28523                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
28524 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL
28525 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
28526 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK
28527 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL                                      0x0000000D
28528 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT                                       0
28529 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK                                        0x0000001FU
28530
28531 /*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
28532                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
28533                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
28534 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL
28535 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
28536 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK
28537 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL                                      0x00000008
28538 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT                                       0
28539 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK                                        0x0000001FU
28540
28541 /*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
28542                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
28543                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
28544 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL
28545 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
28546 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK
28547 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL                                      0x0000000F
28548 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT                                       0
28549 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK                                        0x0000001FU
28550
28551 /*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
28552                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
28553                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
28554 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL
28555 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
28556 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK
28557 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL                                      0x0000000E
28558 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT                                       0
28559 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK                                        0x0000001FU
28560
28561 /*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/
28562 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL
28563 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
28564 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK
28565 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
28566 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT                          7
28567 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK                           0x00000080U
28568
28569 /*Bit 3 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/
28570 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_DEFVAL
28571 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT
28572 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK
28573 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_DEFVAL                           0x00000080
28574 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT                            3
28575 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK                             0x00000008U
28576
28577 /*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/
28578 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL
28579 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
28580 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK
28581 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
28582 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT                          7
28583 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK                           0x00000080U
28584
28585 /*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/
28586 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL
28587 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
28588 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK
28589 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL                           0x00000080
28590 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT                            3
28591 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK                             0x00000008U
28592
28593 /*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/
28594 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL
28595 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
28596 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK
28597 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
28598 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT                          7
28599 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK                           0x00000080U
28600
28601 /*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/
28602 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL
28603 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
28604 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK
28605 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
28606 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT                          7
28607 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK                           0x00000080U
28608
28609 /*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/
28610 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL
28611 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
28612 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK
28613 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL                           0x00000080
28614 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT                            1
28615 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK                             0x00000002U
28616
28617 /*Enable/Disable coarse code satureation limiting logic*/
28618 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL
28619 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
28620 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK
28621 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL                 0x00000000
28622 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT                  4
28623 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK                   0x00000010U
28624
28625 /*Spread Spectrum No of Steps [7:0]*/
28626 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
28627 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
28628 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
28629 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
28630 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
28631 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
28632
28633 /*Spread Spectrum No of Steps [10:8]*/
28634 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
28635 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
28636 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
28637 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
28638 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
28639 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
28640
28641 /*Spread Spectrum No of Steps [7:0]*/
28642 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
28643 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
28644 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
28645 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
28646 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
28647 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
28648
28649 /*Spread Spectrum No of Steps [10:8]*/
28650 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
28651 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
28652 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
28653 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
28654 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
28655 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
28656
28657 /*Spread Spectrum No of Steps [7:0]*/
28658 #undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
28659 #undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
28660 #undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
28661 #define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
28662 #define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
28663 #define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
28664
28665 /*Spread Spectrum No of Steps [10:8]*/
28666 #undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
28667 #undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
28668 #undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
28669 #define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
28670 #define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
28671 #define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
28672
28673 /*Spread Spectrum No of Steps [7:0]*/
28674 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
28675 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
28676 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
28677 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
28678 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
28679 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
28680
28681 /*Spread Spectrum No of Steps [10:8]*/
28682 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
28683 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
28684 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
28685 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
28686 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
28687 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
28688
28689 /*Step Size for Spread Spectrum [7:0]*/
28690 #undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
28691 #undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
28692 #undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
28693 #define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
28694 #define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
28695 #define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
28696
28697 /*Step Size for Spread Spectrum [15:8]*/
28698 #undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
28699 #undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
28700 #undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
28701 #define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
28702 #define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
28703 #define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
28704
28705 /*Step Size for Spread Spectrum [23:16]*/
28706 #undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
28707 #undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
28708 #undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
28709 #define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
28710 #define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
28711 #define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
28712
28713 /*Step Size for Spread Spectrum [25:24]*/
28714 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
28715 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
28716 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
28717 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
28718 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
28719 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
28720
28721 /*Enable/Disable test mode force on SS step size*/
28722 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
28723 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
28724 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
28725 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
28726 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
28727 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
28728
28729 /*Enable/Disable test mode force on SS no of steps*/
28730 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
28731 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
28732 #undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
28733 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
28734 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
28735 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
28736
28737 /*Step Size for Spread Spectrum [7:0]*/
28738 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
28739 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
28740 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
28741 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
28742 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
28743 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
28744
28745 /*Step Size for Spread Spectrum [15:8]*/
28746 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
28747 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
28748 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
28749 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
28750 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
28751 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
28752
28753 /*Step Size for Spread Spectrum [23:16]*/
28754 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
28755 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
28756 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
28757 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
28758 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
28759 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
28760
28761 /*Step Size for Spread Spectrum [25:24]*/
28762 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
28763 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
28764 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
28765 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
28766 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
28767 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
28768
28769 /*Enable/Disable test mode force on SS step size*/
28770 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
28771 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
28772 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
28773 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
28774 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
28775 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
28776
28777 /*Enable/Disable test mode force on SS no of steps*/
28778 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
28779 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
28780 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
28781 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
28782 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
28783 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
28784
28785 /*Step Size for Spread Spectrum [7:0]*/
28786 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
28787 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
28788 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
28789 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
28790 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
28791 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
28792
28793 /*Step Size for Spread Spectrum [15:8]*/
28794 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
28795 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
28796 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
28797 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
28798 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
28799 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
28800
28801 /*Step Size for Spread Spectrum [23:16]*/
28802 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
28803 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
28804 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
28805 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
28806 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
28807 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
28808
28809 /*Step Size for Spread Spectrum [25:24]*/
28810 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
28811 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
28812 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
28813 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
28814 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
28815 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
28816
28817 /*Enable/Disable test mode force on SS step size*/
28818 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
28819 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
28820 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
28821 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
28822 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
28823 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
28824
28825 /*Enable/Disable test mode force on SS no of steps*/
28826 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
28827 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
28828 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
28829 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
28830 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
28831 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
28832
28833 /*Step Size for Spread Spectrum [7:0]*/
28834 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
28835 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
28836 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
28837 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
28838 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
28839 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
28840
28841 /*Step Size for Spread Spectrum [15:8]*/
28842 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
28843 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
28844 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
28845 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
28846 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
28847 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
28848
28849 /*Step Size for Spread Spectrum [23:16]*/
28850 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
28851 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
28852 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
28853 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
28854 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
28855 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
28856
28857 /*Step Size for Spread Spectrum [25:24]*/
28858 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
28859 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
28860 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
28861 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
28862 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
28863 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
28864
28865 /*Enable/Disable test mode force on SS step size*/
28866 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
28867 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
28868 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
28869 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
28870 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
28871 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
28872
28873 /*Enable/Disable test mode force on SS no of steps*/
28874 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
28875 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
28876 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
28877 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
28878 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
28879 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
28880
28881 /*Enable test mode forcing on enable Spread Spectrum*/
28882 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL
28883 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
28884 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK
28885 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL                     0x00000000
28886 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT                      7
28887 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK                       0x00000080U
28888
28889 /*Bypass Descrambler*/
28890 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
28891 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
28892 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK
28893 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL                                   0x00000000
28894 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT                                    1
28895 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK                                     0x00000002U
28896
28897 /*Enable Bypass for <1> TM_DIG_CTRL_6*/
28898 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
28899 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
28900 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
28901 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL                             0x00000000
28902 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT                              0
28903 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK                               0x00000001U
28904
28905 /*Bypass scrambler signal*/
28906 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
28907 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
28908 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK
28909 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL                                 0x00000000
28910 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT                                  1
28911 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK                                   0x00000002U
28912
28913 /*Enable/disable scrambler bypass signal*/
28914 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
28915 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
28916 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
28917 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL                           0x00000000
28918 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT                            0
28919 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK                             0x00000001U
28920
28921 /*Enable test mode force on fractional mode enable*/
28922 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL
28923 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
28924 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK
28925 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL                     0x00000000
28926 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT                      6
28927 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK                       0x00000040U
28928
28929 /*Bypass 8b10b decoder*/
28930 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL
28931 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
28932 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK
28933 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL                                   0x00000000
28934 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT                                    3
28935 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK                                     0x00000008U
28936
28937 /*Enable Bypass for <3> TM_DIG_CTRL_6*/
28938 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL
28939 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
28940 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK
28941 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL                                 0x00000000
28942 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT                                  2
28943 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK                                   0x00000004U
28944
28945 /*Bypass Descrambler*/
28946 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
28947 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
28948 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK
28949 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL                                   0x00000000
28950 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT                                    1
28951 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK                                     0x00000002U
28952
28953 /*Enable Bypass for <1> TM_DIG_CTRL_6*/
28954 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
28955 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
28956 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
28957 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL                             0x00000000
28958 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT                              0
28959 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK                               0x00000001U
28960
28961 /*Enable/disable encoder bypass signal*/
28962 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL
28963 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
28964 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK
28965 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL                                   0x00000000
28966 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT                                    3
28967 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK                                     0x00000008U
28968
28969 /*Bypass scrambler signal*/
28970 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
28971 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
28972 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK
28973 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL                                 0x00000000
28974 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT                                  1
28975 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK                                   0x00000002U
28976
28977 /*Enable/disable scrambler bypass signal*/
28978 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
28979 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
28980 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
28981 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL                           0x00000000
28982 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT                            0
28983 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK                             0x00000001U
28984
28985 /*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/
28986 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL
28987 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
28988 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK
28989 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL                                    0x00000001
28990 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT                                     4
28991 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK                                      0x000000F0U
28992
28993 /*Spare- not used*/
28994 #undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL
28995 #undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT
28996 #undef SERDES_L2_TM_AUX_0_BIT_2_MASK
28997 #define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL                                            0x00000000
28998 #define SERDES_L2_TM_AUX_0_BIT_2_SHIFT                                             5
28999 #define SERDES_L2_TM_AUX_0_BIT_2_MASK                                              0x00000020U
29000
29001 /*Enable Eye Surf*/
29002 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL
29003 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
29004 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK
29005 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL                                   0x00000000
29006 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT                                    4
29007 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK                                     0x00000010U
29008
29009 /*Enable Eye Surf*/
29010 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL
29011 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
29012 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK
29013 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL                                   0x00000000
29014 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT                                    4
29015 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK                                     0x00000010U
29016
29017 /*Enable Eye Surf*/
29018 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL
29019 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
29020 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK
29021 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL                                   0x00000000
29022 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT                                    4
29023 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK                                     0x00000010U
29024
29025 /*Enable Eye Surf*/
29026 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL
29027 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
29028 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK
29029 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL                                   0x00000000
29030 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT                                    4
29031 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK                                     0x00000010U
29032
29033 /*ILL calib counts BYPASSED with calcode bits*/
29034 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
29035 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
29036 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
29037 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL                            0x00000000
29038 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT                             7
29039 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK                              0x00000080U
29040
29041 /*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
29042 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
29043 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
29044 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
29045 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL                       0x00000000
29046 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT                        0
29047 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK                         0x000000FFU
29048
29049 /*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
29050 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
29051 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
29052 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
29053 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL                       0x00000000
29054 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT                        0
29055 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK                         0x000000FFU
29056
29057 /*G1A pll ctr bypass value*/
29058 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
29059 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
29060 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
29061 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL                              0x00000000
29062 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT                               0
29063 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK                                0x000000FFU
29064
29065 /*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
29066 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
29067 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
29068 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
29069 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL                         0x00000000
29070 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT                          0
29071 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK                           0x000000FFU
29072
29073 /*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
29074 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
29075 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
29076 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
29077 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL                         0x00000000
29078 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT                          0
29079 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK                           0x000000FFU
29080
29081 /*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
29082 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
29083 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
29084 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
29085 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL                       0x00000000
29086 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT                        0
29087 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK                         0x000000FFU
29088
29089 /*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
29090 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
29091 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
29092 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
29093 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL                         0x00000000
29094 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT                          0
29095 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK                           0x000000FFU
29096
29097 /*ILL calibration code change wait time*/
29098 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
29099 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
29100 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
29101 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL                                 0x00000002
29102 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT                                  0
29103 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK                                   0x000000FFU
29104
29105 /*IQ ILL polytrim bypass value*/
29106 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
29107 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
29108 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
29109 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL                     0x00000000
29110 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT                      0
29111 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK                       0x000000FFU
29112
29113 /*bypass IQ polytrim*/
29114 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
29115 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
29116 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
29117 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL                          0x00000000
29118 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT                           0
29119 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK                            0x00000001U
29120
29121 /*E ILL polytrim bypass value*/
29122 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
29123 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
29124 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
29125 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL                       0x00000000
29126 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT                        0
29127 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK                         0x000000FFU
29128
29129 /*bypass E polytrim*/
29130 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
29131 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
29132 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
29133 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL                            0x00000000
29134 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT                             0
29135 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK                              0x00000001U
29136
29137 /*ILL calib counts BYPASSED with calcode bits*/
29138 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
29139 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
29140 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
29141 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL                            0x00000000
29142 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT                             7
29143 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK                              0x00000080U
29144
29145 /*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
29146 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
29147 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
29148 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
29149 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL                       0x00000000
29150 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT                        0
29151 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK                         0x000000FFU
29152
29153 /*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
29154 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
29155 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
29156 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
29157 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL                       0x00000000
29158 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT                        0
29159 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK                         0x000000FFU
29160
29161 /*G1A pll ctr bypass value*/
29162 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
29163 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
29164 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
29165 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL                              0x00000000
29166 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT                               0
29167 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK                                0x000000FFU
29168
29169 /*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
29170 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
29171 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
29172 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
29173 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL                         0x00000000
29174 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT                          0
29175 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK                           0x000000FFU
29176
29177 /*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
29178 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
29179 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
29180 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
29181 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL                         0x00000000
29182 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT                          0
29183 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK                           0x000000FFU
29184
29185 /*G2A_PCIe1 PLL ctr bypass value*/
29186 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL
29187 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
29188 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK
29189 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL                  0x00000000
29190 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT                   4
29191 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK                    0x000000F0U
29192
29193 /*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
29194 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
29195 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
29196 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
29197 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL                       0x00000000
29198 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT                        0
29199 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK                         0x000000FFU
29200
29201 /*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
29202 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
29203 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
29204 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
29205 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL                         0x00000000
29206 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT                          0
29207 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK                           0x000000FFU
29208
29209 /*ILL calibration code change wait time*/
29210 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
29211 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
29212 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
29213 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL                                 0x00000002
29214 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT                                  0
29215 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK                                   0x000000FFU
29216
29217 /*IQ ILL polytrim bypass value*/
29218 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
29219 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
29220 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
29221 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL                     0x00000000
29222 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT                      0
29223 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK                       0x000000FFU
29224
29225 /*bypass IQ polytrim*/
29226 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
29227 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
29228 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
29229 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL                          0x00000000
29230 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT                           0
29231 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK                            0x00000001U
29232
29233 /*E ILL polytrim bypass value*/
29234 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
29235 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
29236 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
29237 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL                       0x00000000
29238 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT                        0
29239 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK                         0x000000FFU
29240
29241 /*bypass E polytrim*/
29242 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
29243 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
29244 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
29245 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL                            0x00000000
29246 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT                             0
29247 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK                              0x00000001U
29248
29249 /*Delay apb reset by specified amount*/
29250 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL
29251 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
29252 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK
29253 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL                                    0x00000000
29254 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT                                     0
29255 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK                                      0x000000FFU
29256
29257 /*Enable Bypass for <7> of TM_ANA_BYPS_15*/
29258 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
29259 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
29260 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
29261 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL               0x00000000
29262 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT                6
29263 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK                 0x00000040U
29264
29265 /*Enable Bypass for <7> of TM_ANA_BYPS_12*/
29266 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
29267 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
29268 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
29269 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL                      0x00000000
29270 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT                       6
29271 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK                        0x00000040U
29272
29273 /*Delay apb reset by specified amount*/
29274 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL
29275 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
29276 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK
29277 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL                                    0x00000000
29278 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT                                     0
29279 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK                                      0x000000FFU
29280
29281 /*Enable Bypass for <7> of TM_ANA_BYPS_15*/
29282 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
29283 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
29284 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
29285 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL               0x00000000
29286 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT                6
29287 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK                 0x00000040U
29288
29289 /*Enable Bypass for <7> of TM_ANA_BYPS_12*/
29290 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
29291 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
29292 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
29293 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL                      0x00000000
29294 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT                       6
29295 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK                        0x00000040U
29296
29297 /*Delay apb reset by specified amount*/
29298 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL
29299 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
29300 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK
29301 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL                                    0x00000000
29302 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT                                     0
29303 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK                                      0x000000FFU
29304
29305 /*Enable Bypass for <7> of TM_ANA_BYPS_15*/
29306 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
29307 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
29308 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
29309 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL               0x00000000
29310 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT                6
29311 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK                 0x00000040U
29312
29313 /*Enable Bypass for <7> of TM_ANA_BYPS_12*/
29314 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
29315 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
29316 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
29317 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL                      0x00000000
29318 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT                       6
29319 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK                        0x00000040U
29320
29321 /*Delay apb reset by specified amount*/
29322 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL
29323 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
29324 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK
29325 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL                                    0x00000000
29326 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT                                     0
29327 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK                                      0x000000FFU
29328
29329 /*Enable Bypass for <7> of TM_ANA_BYPS_15*/
29330 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
29331 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
29332 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
29333 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL               0x00000000
29334 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT                6
29335 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK                 0x00000040U
29336
29337 /*Enable Bypass for <7> of TM_ANA_BYPS_12*/
29338 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
29339 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
29340 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
29341 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL                      0x00000000
29342 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT                       6
29343 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK                        0x00000040U
29344
29345 /*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
29346                 , 7 - Unused*/
29347 #undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL
29348 #undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
29349 #undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK
29350 #define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL                                          0x00000000
29351 #define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT                                           0
29352 #define SERDES_ICM_CFG0_L0_ICM_CFG_MASK                                            0x00000007U
29353
29354 /*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
29355                  7 - Unused*/
29356 #undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL
29357 #undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
29358 #undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK
29359 #define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL                                          0x00000000
29360 #define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT                                           4
29361 #define SERDES_ICM_CFG0_L1_ICM_CFG_MASK                                            0x00000070U
29362
29363 /*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
29364                  7 - Unused*/
29365 #undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL
29366 #undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
29367 #undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK
29368 #define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL                                          0x00000000
29369 #define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT                                           0
29370 #define SERDES_ICM_CFG1_L2_ICM_CFG_MASK                                            0x00000007U
29371
29372 /*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
29373                  7 - Unused*/
29374 #undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL
29375 #undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
29376 #undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK
29377 #define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL                                          0x00000000
29378 #define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT                                           4
29379 #define SERDES_ICM_CFG1_L3_ICM_CFG_MASK                                            0x00000070U
29380
29381 /*Enable/disable DP post2 path*/
29382 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
29383 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
29384 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK
29385 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL                 0x00000000
29386 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT                  5
29387 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK                   0x00000020U
29388
29389 /*Override enable/disable of DP post2 path*/
29390 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL
29391 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
29392 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK
29393 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL            0x00000000
29394 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT             4
29395 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK              0x00000010U
29396
29397 /*Override enable/disable of DP post1 path*/
29398 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL
29399 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
29400 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK
29401 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL            0x00000000
29402 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT             2
29403 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK              0x00000004U
29404
29405 /*Enable/disable DP main path*/
29406 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL
29407 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
29408 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK
29409 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL                  0x00000000
29410 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT                   1
29411 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK                    0x00000002U
29412
29413 /*Override enable/disable of DP main path*/
29414 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL
29415 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
29416 #undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK
29417 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL             0x00000000
29418 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT              0
29419 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK               0x00000001U
29420
29421 /*Enable/disable DP post2 path*/
29422 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
29423 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
29424 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK
29425 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL                 0x00000000
29426 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT                  5
29427 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK                   0x00000020U
29428
29429 /*Override enable/disable of DP post2 path*/
29430 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL
29431 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
29432 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK
29433 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL            0x00000000
29434 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT             4
29435 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK              0x00000010U
29436
29437 /*Override enable/disable of DP post1 path*/
29438 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL
29439 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
29440 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK
29441 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL            0x00000000
29442 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT             2
29443 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK              0x00000004U
29444
29445 /*Enable/disable DP main path*/
29446 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL
29447 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
29448 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK
29449 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL                  0x00000000
29450 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT                   1
29451 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK                    0x00000002U
29452
29453 /*Override enable/disable of DP main path*/
29454 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL
29455 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
29456 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK
29457 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL             0x00000000
29458 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT              0
29459 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK               0x00000001U
29460
29461 /*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
29462 #undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
29463 #undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
29464 #undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
29465 #define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL                        0x00000000
29466 #define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT                         0
29467 #define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK                          0x00000001U
29468
29469 /*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
29470 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
29471 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
29472 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
29473 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL                        0x00000000
29474 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT                         0
29475 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK                          0x00000001U
29476
29477 /*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
29478 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
29479 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
29480 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
29481 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL                        0x00000000
29482 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT                         0
29483 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK                          0x00000001U
29484
29485 /*FPHL FSM accumulate cycles*/
29486 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL
29487 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
29488 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK
29489 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL                               0x00000000
29490 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT                                5
29491 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK                                 0x000000E0U
29492
29493 /*FFL Phase0 int gain aka 2ol SD update rate*/
29494 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL
29495 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
29496 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK
29497 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL                                  0x00000000
29498 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT                                   0
29499 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK                                    0x0000001FU
29500
29501 /*FFL Phase0 prop gain aka 1ol SD update rate*/
29502 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL
29503 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
29504 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK
29505 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL                                0x00000000
29506 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT                                 0
29507 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK                                  0x0000001FU
29508
29509 /*EQ stg 2 controls BYPASSED*/
29510 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL
29511 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
29512 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK
29513 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL                                   0x00000000
29514 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT                                    5
29515 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK                                     0x00000020U
29516
29517 /*EQ STG2 RL PROG*/
29518 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL
29519 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
29520 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK
29521 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL                                    0x00000000
29522 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT                                     0
29523 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK                                      0x00000003U
29524
29525 /*EQ stg 2 preamp mode val*/
29526 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL
29527 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
29528 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK
29529 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL                            0x00000000
29530 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT                             2
29531 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK                              0x00000004U
29532
29533 /*Margining factor value*/
29534 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
29535 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
29536 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK
29537 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL                 0x00000000
29538 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT                  0
29539 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK                   0x0000001FU
29540
29541 /*Margining factor value*/
29542 #undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
29543 #undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
29544 #undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK
29545 #define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL                 0x00000000
29546 #define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT                  0
29547 #define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK                   0x0000001FU
29548
29549 /*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
29550 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
29551 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
29552 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
29553 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL                           0x00000002
29554 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT                            0
29555 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK                             0x000000FFU
29556
29557 /*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
29558 #undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
29559 #undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
29560 #undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
29561 #define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL                           0x00000002
29562 #define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT                            0
29563 #define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK                             0x000000FFU
29564
29565 /*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
29566 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
29567 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
29568 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
29569 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL                           0x00000002
29570 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT                            0
29571 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK                             0x000000FFU
29572 #undef CRL_APB_RST_LPD_TOP_OFFSET
29573 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
29574 #undef USB3_0_FPD_POWER_PRSNT_OFFSET
29575 #define USB3_0_FPD_POWER_PRSNT_OFFSET                                              0XFF9D0080
29576 #undef USB3_0_FPD_PIPE_CLK_OFFSET
29577 #define USB3_0_FPD_PIPE_CLK_OFFSET                                                 0XFF9D007C
29578 #undef CRL_APB_RST_LPD_TOP_OFFSET
29579 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
29580 #undef CRL_APB_RST_LPD_IOU0_OFFSET
29581 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
29582 #undef SIOU_SATA_MISC_CTRL_OFFSET
29583 #define SIOU_SATA_MISC_CTRL_OFFSET                                                 0XFD3D0100
29584 #undef CRF_APB_RST_FPD_TOP_OFFSET
29585 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
29586 #undef CRF_APB_RST_FPD_TOP_OFFSET
29587 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
29588 #undef DP_DP_PHY_RESET_OFFSET
29589 #define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
29590 #undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
29591 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
29592 #undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET
29593 #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET                                             0XFE20C200
29594 #undef USB3_0_XHCI_GFLADJ_OFFSET
29595 #define USB3_0_XHCI_GFLADJ_OFFSET                                                  0XFE20C630
29596 #undef PCIE_ATTRIB_ATTR_25_OFFSET
29597 #define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
29598 #undef SATA_AHCI_VENDOR_PP2C_OFFSET
29599 #define SATA_AHCI_VENDOR_PP2C_OFFSET                                               0XFD0C00AC
29600 #undef SATA_AHCI_VENDOR_PP3C_OFFSET
29601 #define SATA_AHCI_VENDOR_PP3C_OFFSET                                               0XFD0C00B0
29602 #undef SATA_AHCI_VENDOR_PP4C_OFFSET
29603 #define SATA_AHCI_VENDOR_PP4C_OFFSET                                               0XFD0C00B4
29604 #undef SATA_AHCI_VENDOR_PP5C_OFFSET
29605 #define SATA_AHCI_VENDOR_PP5C_OFFSET                                               0XFD0C00B8
29606
29607 /*USB 0 reset for control registers*/
29608 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
29609 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
29610 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
29611 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
29612 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
29613 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
29614
29615 /*This bit is used to choose between PIPE power present and 1'b1*/
29616 #undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
29617 #undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
29618 #undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK
29619 #define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
29620 #define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT                                        0
29621 #define USB3_0_FPD_POWER_PRSNT_OPTION_MASK                                         0x00000001U
29622
29623 /*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/
29624 #undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
29625 #undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
29626 #undef USB3_0_FPD_PIPE_CLK_OPTION_MASK
29627 #define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
29628 #define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT                                           0
29629 #define USB3_0_FPD_PIPE_CLK_OPTION_MASK                                            0x00000001U
29630
29631 /*USB 0 sleep circuit reset*/
29632 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
29633 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
29634 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
29635 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
29636 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
29637 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
29638
29639 /*USB 0 reset*/
29640 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
29641 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
29642 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
29643 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
29644 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
29645 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
29646
29647 /*GEM 3 reset*/
29648 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
29649 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
29650 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
29651 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
29652 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
29653 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
29654
29655 /*Sata PM clock control select*/
29656 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
29657 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
29658 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK
29659 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
29660 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT                                  0
29661 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK                                   0x00000003U
29662
29663 /*Sata block level reset*/
29664 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
29665 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
29666 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
29667 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
29668 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
29669 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
29670
29671 /*Display Port block level reset (includes DPDMA)*/
29672 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
29673 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
29674 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
29675 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
29676 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
29677 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
29678
29679 /*Set to '1' to hold the GT in reset. Clear to release.*/
29680 #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
29681 #undef DP_DP_PHY_RESET_GT_RESET_SHIFT
29682 #undef DP_DP_PHY_RESET_GT_RESET_MASK
29683 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL                                            0x00010003
29684 #define DP_DP_PHY_RESET_GT_RESET_SHIFT                                             1
29685 #define DP_DP_PHY_RESET_GT_RESET_MASK                                              0x00000002U
29686
29687 /*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
29688                 ane0 Bits [3:2] - lane 1*/
29689 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
29690 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
29691 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
29692 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL                                   0x00000000
29693 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                                    0
29694 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                                     0x0000000FU
29695
29696 /*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
29697                 he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
29698                 C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
29699                 . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
29700                 UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
29701                 alue. Note: This field is valid only in device mode.*/
29702 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL
29703 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
29704 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK
29705 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL                                   0x00000000
29706 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT                                    10
29707 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK                                     0x00003C00U
29708
29709 /*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
29710                  of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
29711                 time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
29712                 ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
29713                 off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
29714                 ng hibernation. - This bit is valid only in device mode.*/
29715 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL
29716 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
29717 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK
29718 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL                                     0x00000000
29719 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT                                      9
29720 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK                                       0x00000200U
29721
29722 /*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
29723                 _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
29724                  to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
29725                 ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
29726                 n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
29727                 d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
29728                 d.*/
29729 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL
29730 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
29731 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK
29732 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL                                    0x00000000
29733 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT                                     8
29734 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK                                      0x00000100U
29735
29736 /*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
29737                 Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
29738                 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
29739                  in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
29740                  active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/
29741 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL
29742 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
29743 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK
29744 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL                                      0x00000000
29745 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT                                       7
29746 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK                                        0x00000080U
29747
29748 /*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
29749                 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
29750                 ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
29751                 B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/
29752 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL
29753 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
29754 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK
29755 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL                                      0x00000000
29756 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT                                       5
29757 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK                                        0x00000020U
29758
29759 /*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
29760                 e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
29761                 ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
29762                 lected through DWC_USB3_HSPHY_INTERFACE.*/
29763 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL
29764 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
29765 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK
29766 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL                               0x00000000
29767 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT                                4
29768 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK                                 0x00000010U
29769
29770 /*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
29771                  8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
29772                 lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
29773                  ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
29774                  any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/
29775 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL
29776 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
29777 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK
29778 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL                                       0x00000000
29779 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT                                        3
29780 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK                                         0x00000008U
29781
29782 /*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
29783                 a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
29784                 dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
29785                 e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
29786                 The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
29787                 ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
29788                  clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
29789                 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/
29790 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL
29791 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
29792 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK
29793 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL                                     0x00000000
29794 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT                                      0
29795 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK                                       0x00000007U
29796
29797 /*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
29798                 alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
29799                 _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
29800                 TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
29801                 riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
29802                 cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
29803                 uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
29804                 ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
29805                 RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/
29806 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL
29807 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
29808 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK
29809 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL                              0x00000000
29810 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT                               8
29811 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK                                0x003FFF00U
29812
29813 /*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
29814                 ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
29815 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
29816 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
29817 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK
29818 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL              0x00000905
29819 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT               9
29820 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK                0x00000200U
29821
29822 /*Status Read value of PLL Lock*/
29823 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
29824 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
29825 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
29826 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
29827 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
29828 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
29829 #define SERDES_L1_PLL_STATUS_READ_1_OFFSET                                         0XFD4063E4
29830
29831 /*Status Read value of PLL Lock*/
29832 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
29833 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
29834 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
29835 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
29836 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
29837 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
29838 #define SERDES_L2_PLL_STATUS_READ_1_OFFSET                                         0XFD40A3E4
29839
29840 /*Status Read value of PLL Lock*/
29841 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
29842 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
29843 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
29844 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
29845 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
29846 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
29847 #define SERDES_L3_PLL_STATUS_READ_1_OFFSET                                         0XFD40E3E4
29848
29849 /*CIBGMN: COMINIT Burst Gap Minimum.*/
29850 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL
29851 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
29852 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK
29853 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL                                        0x28184D1B
29854 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT                                         0
29855 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK                                          0x000000FFU
29856
29857 /*CIBGMX: COMINIT Burst Gap Maximum.*/
29858 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL
29859 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
29860 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK
29861 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL                                        0x28184D1B
29862 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT                                         8
29863 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK                                          0x0000FF00U
29864
29865 /*CIBGN: COMINIT Burst Gap Nominal.*/
29866 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL
29867 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
29868 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK
29869 #define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL                                         0x28184D1B
29870 #define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT                                          16
29871 #define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK                                           0x00FF0000U
29872
29873 /*CINMP: COMINIT Negate Minimum Period.*/
29874 #undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL
29875 #undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
29876 #undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK
29877 #define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL                                         0x28184D1B
29878 #define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT                                          24
29879 #define SATA_AHCI_VENDOR_PP2C_CINMP_MASK                                           0xFF000000U
29880
29881 /*CWBGMN: COMWAKE Burst Gap Minimum.*/
29882 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL
29883 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
29884 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK
29885 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL                                        0x0E081906
29886 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT                                         0
29887 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK                                          0x000000FFU
29888
29889 /*CWBGMX: COMWAKE Burst Gap Maximum.*/
29890 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL
29891 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
29892 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK
29893 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL                                        0x0E081906
29894 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT                                         8
29895 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK                                          0x0000FF00U
29896
29897 /*CWBGN: COMWAKE Burst Gap Nominal.*/
29898 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL
29899 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
29900 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK
29901 #define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL                                         0x0E081906
29902 #define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT                                          16
29903 #define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK                                           0x00FF0000U
29904
29905 /*CWNMP: COMWAKE Negate Minimum Period.*/
29906 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL
29907 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
29908 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK
29909 #define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL                                         0x0E081906
29910 #define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT                                          24
29911 #define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK                                           0xFF000000U
29912
29913 /*BMX: COM Burst Maximum.*/
29914 #undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL
29915 #undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
29916 #undef SATA_AHCI_VENDOR_PP4C_BMX_MASK
29917 #define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL                                           0x064A0813
29918 #define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT                                            0
29919 #define SATA_AHCI_VENDOR_PP4C_BMX_MASK                                             0x000000FFU
29920
29921 /*BNM: COM Burst Nominal.*/
29922 #undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL
29923 #undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
29924 #undef SATA_AHCI_VENDOR_PP4C_BNM_MASK
29925 #define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL                                           0x064A0813
29926 #define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT                                            8
29927 #define SATA_AHCI_VENDOR_PP4C_BNM_MASK                                             0x0000FF00U
29928
29929 /*SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
29930                 rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
29931                  Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
29932                 500ns based on a 150MHz PMCLK.*/
29933 #undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL
29934 #undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
29935 #undef SATA_AHCI_VENDOR_PP4C_SFD_MASK
29936 #define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL                                           0x064A0813
29937 #define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT                                            16
29938 #define SATA_AHCI_VENDOR_PP4C_SFD_MASK                                             0x00FF0000U
29939
29940 /*PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
29941                  value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128*/
29942 #undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL
29943 #undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
29944 #undef SATA_AHCI_VENDOR_PP4C_PTST_MASK
29945 #define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL                                          0x064A0813
29946 #define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT                                           24
29947 #define SATA_AHCI_VENDOR_PP4C_PTST_MASK                                            0xFF000000U
29948
29949 /*RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.*/
29950 #undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL
29951 #undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
29952 #undef SATA_AHCI_VENDOR_PP5C_RIT_MASK
29953 #define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL                                           0x3FFC96A4
29954 #define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT                                            0
29955 #define SATA_AHCI_VENDOR_PP5C_RIT_MASK                                             0x000FFFFFU
29956
29957 /*RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
29958                  completed, for a fast SERDES it is suggested that this value be 54.2us / 4*/
29959 #undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL
29960 #undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
29961 #undef SATA_AHCI_VENDOR_PP5C_RCT_MASK
29962 #define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL                                           0x3FFC96A4
29963 #define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT                                            20
29964 #define SATA_AHCI_VENDOR_PP5C_RCT_MASK                                             0xFFF00000U
29965 #undef CRL_APB_RST_LPD_TOP_OFFSET
29966 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
29967 #undef CRL_APB_RST_LPD_IOU0_OFFSET
29968 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
29969 #undef CRF_APB_RST_FPD_TOP_OFFSET
29970 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
29971 #undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
29972 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
29973 #undef DP_DP_PHY_RESET_OFFSET
29974 #define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
29975 #undef CRF_APB_RST_FPD_TOP_OFFSET
29976 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
29977
29978 /*USB 0 reset for control registers*/
29979 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
29980 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
29981 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
29982 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
29983 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
29984 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
29985
29986 /*USB 0 sleep circuit reset*/
29987 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
29988 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
29989 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
29990 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
29991 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
29992 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
29993
29994 /*USB 0 reset*/
29995 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
29996 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
29997 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
29998 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
29999 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
30000 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
30001
30002 /*GEM 3 reset*/
30003 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
30004 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
30005 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
30006 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
30007 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
30008 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
30009
30010 /*Sata block level reset*/
30011 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
30012 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
30013 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
30014 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
30015 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
30016 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
30017
30018 /*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
30019                 ane0 Bits [3:2] - lane 1*/
30020 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
30021 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
30022 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
30023 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL                                   0x00000000
30024 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                                    0
30025 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                                     0x0000000FU
30026
30027 /*Set to '1' to hold the GT in reset. Clear to release.*/
30028 #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
30029 #undef DP_DP_PHY_RESET_GT_RESET_SHIFT
30030 #undef DP_DP_PHY_RESET_GT_RESET_MASK
30031 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL                                            0x00010003
30032 #define DP_DP_PHY_RESET_GT_RESET_SHIFT                                             1
30033 #define DP_DP_PHY_RESET_GT_RESET_MASK                                              0x00000002U
30034
30035 /*Display Port block level reset (includes DPDMA)*/
30036 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
30037 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
30038 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
30039 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
30040 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
30041 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
30042 #undef CRF_APB_RST_FPD_TOP_OFFSET
30043 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
30044 #undef CRL_APB_RST_LPD_TOP_OFFSET
30045 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
30046 #undef FPD_SLCR_AFI_FS_OFFSET
30047 #define FPD_SLCR_AFI_FS_OFFSET                                                     0XFD615000
30048 #undef LPD_SLCR_AFI_FS_OFFSET
30049 #define LPD_SLCR_AFI_FS_OFFSET                                                     0XFF419000
30050 #undef AFIFM0_AFIFM_RDCTRL_OFFSET
30051 #define AFIFM0_AFIFM_RDCTRL_OFFSET                                                 0XFD360000
30052 #undef AFIFM1_AFIFM_RDCTRL_OFFSET
30053 #define AFIFM1_AFIFM_RDCTRL_OFFSET                                                 0XFD370000
30054 #undef AFIFM2_AFIFM_RDCTRL_OFFSET
30055 #define AFIFM2_AFIFM_RDCTRL_OFFSET                                                 0XFD380000
30056 #undef AFIFM3_AFIFM_RDCTRL_OFFSET
30057 #define AFIFM3_AFIFM_RDCTRL_OFFSET                                                 0XFD390000
30058 #undef AFIFM4_AFIFM_RDCTRL_OFFSET
30059 #define AFIFM4_AFIFM_RDCTRL_OFFSET                                                 0XFD3A0000
30060 #undef AFIFM5_AFIFM_RDCTRL_OFFSET
30061 #define AFIFM5_AFIFM_RDCTRL_OFFSET                                                 0XFD3B0000
30062 #undef AFIFM6_AFIFM_RDCTRL_OFFSET
30063 #define AFIFM6_AFIFM_RDCTRL_OFFSET                                                 0XFF9B0000
30064 #undef AFIFM0_AFIFM_WRCTRL_OFFSET
30065 #define AFIFM0_AFIFM_WRCTRL_OFFSET                                                 0XFD360014
30066 #undef AFIFM1_AFIFM_WRCTRL_OFFSET
30067 #define AFIFM1_AFIFM_WRCTRL_OFFSET                                                 0XFD370014
30068 #undef AFIFM2_AFIFM_WRCTRL_OFFSET
30069 #define AFIFM2_AFIFM_WRCTRL_OFFSET                                                 0XFD380014
30070 #undef AFIFM3_AFIFM_WRCTRL_OFFSET
30071 #define AFIFM3_AFIFM_WRCTRL_OFFSET                                                 0XFD390014
30072 #undef AFIFM4_AFIFM_WRCTRL_OFFSET
30073 #define AFIFM4_AFIFM_WRCTRL_OFFSET                                                 0XFD3A0014
30074 #undef AFIFM5_AFIFM_WRCTRL_OFFSET
30075 #define AFIFM5_AFIFM_WRCTRL_OFFSET                                                 0XFD3B0014
30076 #undef AFIFM6_AFIFM_WRCTRL_OFFSET
30077 #define AFIFM6_AFIFM_WRCTRL_OFFSET                                                 0XFF9B0014
30078 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET
30079 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET                                         0XFFD80118
30080 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET
30081 #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET                                           0XFFD80120
30082
30083 /*AF_FM0 block level reset*/
30084 #undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL
30085 #undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT
30086 #undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK
30087 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL                                   0x000F9FFE
30088 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT                                    7
30089 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK                                     0x00000080U
30090
30091 /*AF_FM1 block level reset*/
30092 #undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL
30093 #undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT
30094 #undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK
30095 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL                                   0x000F9FFE
30096 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT                                    8
30097 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK                                     0x00000100U
30098
30099 /*AF_FM2 block level reset*/
30100 #undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL
30101 #undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT
30102 #undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK
30103 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL                                   0x000F9FFE
30104 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT                                    9
30105 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK                                     0x00000200U
30106
30107 /*AF_FM3 block level reset*/
30108 #undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL
30109 #undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT
30110 #undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK
30111 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL                                   0x000F9FFE
30112 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT                                    10
30113 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK                                     0x00000400U
30114
30115 /*AF_FM4 block level reset*/
30116 #undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL
30117 #undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT
30118 #undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK
30119 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL                                   0x000F9FFE
30120 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT                                    11
30121 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK                                     0x00000800U
30122
30123 /*AF_FM5 block level reset*/
30124 #undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL
30125 #undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT
30126 #undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK
30127 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL                                   0x000F9FFE
30128 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT                                    12
30129 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK                                     0x00001000U
30130
30131 /*AFI FM 6*/
30132 #undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL
30133 #undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT
30134 #undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK
30135 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL                                   0x00188FDF
30136 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT                                    19
30137 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK                                     0x00080000U
30138
30139 /*Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
30140                 : 128-bit AXI data width 11: reserved*/
30141 #undef FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL
30142 #undef FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT
30143 #undef FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK
30144 #define FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL                                          0x00000A00
30145 #define FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT                                           8
30146 #define FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK                                            0x00000300U
30147
30148 /*Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
30149                 : 128-bit AXI data width 11: reserved*/
30150 #undef FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL
30151 #undef FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT
30152 #undef FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK
30153 #define FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL                                          0x00000A00
30154 #define FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT                                           10
30155 #define FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK                                            0x00000C00U
30156
30157 /*Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
30158                 : 128-bit AXI data width 11: reserved*/
30159 #undef LPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL
30160 #undef LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT
30161 #undef LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK
30162 #define LPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL                                          0x00000200
30163 #define LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT                                           8
30164 #define LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK                                            0x00000300U
30165
30166 /*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
30167                 bit enabled*/
30168 #undef AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
30169 #undef AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
30170 #undef AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
30171 #define AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30172 #define AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT                                     0
30173 #define AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30174
30175 /*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
30176                 bit enabled*/
30177 #undef AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
30178 #undef AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
30179 #undef AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
30180 #define AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30181 #define AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT                                     0
30182 #define AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30183
30184 /*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
30185                 bit enabled*/
30186 #undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
30187 #undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
30188 #undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
30189 #define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30190 #define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT                                     0
30191 #define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30192
30193 /*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
30194                 bit enabled*/
30195 #undef AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
30196 #undef AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
30197 #undef AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
30198 #define AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30199 #define AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT                                     0
30200 #define AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30201
30202 /*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
30203                 bit enabled*/
30204 #undef AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
30205 #undef AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
30206 #undef AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
30207 #define AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30208 #define AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT                                     0
30209 #define AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30210
30211 /*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
30212                 bit enabled*/
30213 #undef AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
30214 #undef AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
30215 #undef AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
30216 #define AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30217 #define AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT                                     0
30218 #define AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30219
30220 /*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
30221                 bit enabled*/
30222 #undef AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
30223 #undef AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
30224 #undef AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
30225 #define AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30226 #define AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT                                     0
30227 #define AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30228
30229 /*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
30230                 -bit enabled*/
30231 #undef AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
30232 #undef AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
30233 #undef AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
30234 #define AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30235 #define AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT                                     0
30236 #define AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30237
30238 /*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
30239                 -bit enabled*/
30240 #undef AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
30241 #undef AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
30242 #undef AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
30243 #define AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30244 #define AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT                                     0
30245 #define AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30246
30247 /*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
30248                 -bit enabled*/
30249 #undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
30250 #undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
30251 #undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
30252 #define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30253 #define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT                                     0
30254 #define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30255
30256 /*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
30257                 -bit enabled*/
30258 #undef AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
30259 #undef AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
30260 #undef AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
30261 #define AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30262 #define AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT                                     0
30263 #define AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30264
30265 /*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
30266                 -bit enabled*/
30267 #undef AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
30268 #undef AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
30269 #undef AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
30270 #define AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30271 #define AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT                                     0
30272 #define AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30273
30274 /*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
30275                 -bit enabled*/
30276 #undef AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
30277 #undef AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
30278 #undef AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
30279 #define AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30280 #define AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT                                     0
30281 #define AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30282
30283 /*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
30284                 -bit enabled*/
30285 #undef AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
30286 #undef AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
30287 #undef AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
30288 #define AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL                                    0x000003B0
30289 #define AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT                                     0
30290 #define AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_MASK                                      0x00000003U
30291
30292 /*Power-up Request Interrupt Enable for PL*/
30293 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL
30294 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
30295 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK
30296 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL                                      0x00000000
30297 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT                                       23
30298 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK                                        0x00800000U
30299
30300 /*Power-up Request Trigger for PL*/
30301 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL
30302 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
30303 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK
30304 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL                                        0x00000000
30305 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT                                         23
30306 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK                                          0x00800000U
30307
30308 /*Power-up Request Status for PL*/
30309 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL
30310 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT
30311 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK
30312 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL                                      0x00000000
30313 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT                                       23
30314 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK                                        0x00800000U
30315 #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET                                         0XFFD80110
30316 #undef GPIO_MASK_DATA_5_MSW_OFFSET
30317 #define GPIO_MASK_DATA_5_MSW_OFFSET                                                0XFF0A002C
30318 #undef GPIO_DIRM_5_OFFSET
30319 #define GPIO_DIRM_5_OFFSET                                                         0XFF0A0344
30320 #undef GPIO_OEN_5_OFFSET
30321 #define GPIO_OEN_5_OFFSET                                                          0XFF0A0348
30322 #undef GPIO_DATA_5_OFFSET
30323 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
30324 #undef GPIO_DATA_5_OFFSET
30325 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
30326 #undef GPIO_DATA_5_OFFSET
30327 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
30328
30329 /*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/
30330 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL
30331 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
30332 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK
30333 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL                                     0x00000000
30334 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT                                      16
30335 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK                                       0xFFFF0000U
30336
30337 /*Operation is the same as DIRM_0[DIRECTION_0]*/
30338 #undef GPIO_DIRM_5_DIRECTION_5_DEFVAL
30339 #undef GPIO_DIRM_5_DIRECTION_5_SHIFT
30340 #undef GPIO_DIRM_5_DIRECTION_5_MASK
30341 #define GPIO_DIRM_5_DIRECTION_5_DEFVAL
30342 #define GPIO_DIRM_5_DIRECTION_5_SHIFT                                              0
30343 #define GPIO_DIRM_5_DIRECTION_5_MASK                                               0xFFFFFFFFU
30344
30345 /*Operation is the same as OEN_0[OP_ENABLE_0]*/
30346 #undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL
30347 #undef GPIO_OEN_5_OP_ENABLE_5_SHIFT
30348 #undef GPIO_OEN_5_OP_ENABLE_5_MASK
30349 #define GPIO_OEN_5_OP_ENABLE_5_DEFVAL
30350 #define GPIO_OEN_5_OP_ENABLE_5_SHIFT                                               0
30351 #define GPIO_OEN_5_OP_ENABLE_5_MASK                                                0xFFFFFFFFU
30352
30353 /*Output Data*/
30354 #undef GPIO_DATA_5_DATA_5_DEFVAL
30355 #undef GPIO_DATA_5_DATA_5_SHIFT
30356 #undef GPIO_DATA_5_DATA_5_MASK
30357 #define GPIO_DATA_5_DATA_5_DEFVAL
30358 #define GPIO_DATA_5_DATA_5_SHIFT                                                   0
30359 #define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
30360
30361 /*Output Data*/
30362 #undef GPIO_DATA_5_DATA_5_DEFVAL
30363 #undef GPIO_DATA_5_DATA_5_SHIFT
30364 #undef GPIO_DATA_5_DATA_5_MASK
30365 #define GPIO_DATA_5_DATA_5_DEFVAL
30366 #define GPIO_DATA_5_DATA_5_SHIFT                                                   0
30367 #define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
30368
30369 /*Output Data*/
30370 #undef GPIO_DATA_5_DATA_5_DEFVAL
30371 #undef GPIO_DATA_5_DATA_5_SHIFT
30372 #undef GPIO_DATA_5_DATA_5_MASK
30373 #define GPIO_DATA_5_DATA_5_DEFVAL
30374 #define GPIO_DATA_5_DATA_5_SHIFT                                                   0
30375 #define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
30376 #ifdef __cplusplus
30377 extern "C" {
30378 #endif
30379  int psu_init ();
30380  unsigned long psu_ps_pl_isolation_removal_data();
30381  unsigned long psu_ps_pl_reset_config_data();
30382  int psu_protection();
30383  int psu_fpd_protection();
30384  int psu_ocm_protection();
30385  int psu_ddr_protection();
30386  int psu_lpd_protection();
30387  int psu_protection_lock();
30388  unsigned long psu_apply_master_tz();
30389 #ifdef __cplusplus
30390 }
30391 #endif