git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <sata.h>
   9 #include <ahci.h>
  10 #include <scsi.h>
  11 #include <malloc.h>
  12 #include <wdt.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/psu_init_gpl.h>
  17 #include <asm/io.h>
  18 #include <dm/uclass.h>
  19 #include <usb.h>
  20 #include <dwc3-uboot.h>
  21 #include <zynqmppl.h>
  22 #include <i2c.h>
  23 #include <g_dnl.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  28 static struct udevice *watchdog_dev;
  29 #endif
  30
  31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  32     !defined(CONFIG_SPL_BUILD)
  33 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  34
  35 static const struct {
  36         u32 id;
  37         u32 ver;
  38         char *name;
  39         bool evexists;
  40 } zynqmp_devices[] = {
  41         {
  42                 .id = 0x10,
  43                 .name = "3eg",
  44         },
  45         {
  46                 .id = 0x10,
  47                 .ver = 0x2c,
  48                 .name = "3cg",
  49         },
  50         {
  51                 .id = 0x11,
  52                 .name = "2eg",
  53         },
  54         {
  55                 .id = 0x11,
  56                 .ver = 0x2c,
  57                 .name = "2cg",
  58         },
  59         {
  60                 .id = 0x20,
  61                 .name = "5ev",
  62                 .evexists = 1,
  63         },
  64         {
  65                 .id = 0x20,
  66                 .ver = 0x100,
  67                 .name = "5eg",
  68                 .evexists = 1,
  69         },
  70         {
  71                 .id = 0x20,
  72                 .ver = 0x12c,
  73                 .name = "5cg",
  74         },
  75         {
  76                 .id = 0x21,
  77                 .name = "4ev",
  78                 .evexists = 1,
  79         },
  80         {
  81                 .id = 0x21,
  82                 .ver = 0x100,
  83                 .name = "4eg",
  84                 .evexists = 1,
  85         },
  86         {
  87                 .id = 0x21,
  88                 .ver = 0x12c,
  89                 .name = "4cg",
  90         },
  91         {
  92                 .id = 0x30,
  93                 .name = "7ev",
  94                 .evexists = 1,
  95         },
  96         {
  97                 .id = 0x30,
  98                 .ver = 0x100,
  99                 .name = "7eg",
 100                 .evexists = 1,
 101         },
 102         {
 103                 .id = 0x30,
 104                 .ver = 0x12c,
 105                 .name = "7cg",
 106         },
 107         {
 108                 .id = 0x38,
 109                 .name = "9eg",
 110         },
 111         {
 112                 .id = 0x38,
 113                 .ver = 0x2c,
 114                 .name = "9cg",
 115         },
 116         {
 117                 .id = 0x39,
 118                 .name = "6eg",
 119         },
 120         {
 121                 .id = 0x39,
 122                 .ver = 0x2c,
 123                 .name = "6cg",
 124         },
 125         {
 126                 .id = 0x40,
 127                 .name = "11eg",
 128         },
 129         { /* For testing purpose only */
 130                 .id = 0x50,
 131                 .ver = 0x2c,
 132                 .name = "15cg",
 133         },
 134         {
 135                 .id = 0x50,
 136                 .name = "15eg",
 137         },
 138         {
 139                 .id = 0x58,
 140                 .name = "19eg",
 141         },
 142         {
 143                 .id = 0x59,
 144                 .name = "17eg",
 145         },
 146         {
 147                 .id = 0x61,
 148                 .name = "21dr",
 149         },
 150         {
 151                 .id = 0x63,
 152                 .name = "23dr",
 153         },
 154         {
 155                 .id = 0x65,
 156                 .name = "25dr",
 157         },
 158         {
 159                 .id = 0x64,
 160                 .name = "27dr",
 161         },
 162         {
 163                 .id = 0x60,
 164                 .name = "28dr",
 165         },
 166         {
 167                 .id = 0x62,
 168                 .name = "29dr",
 169         },
 170 };
 171 #endif
 172
 173 int chip_id(unsigned char id)
 174 {
 175         struct pt_regs regs;
 176         int val = -EINVAL;
 177
 178         if (current_el() != 3) {
 179                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 180                 regs.regs[1] = 0;
 181                 regs.regs[2] = 0;
 182                 regs.regs[3] = 0;
 183
 184                 smc_call(&regs);
 185
 186                 /*
 187                  * SMC returns:
 188                  * regs[0][31:0]  = status of the operation
 189                  * regs[0][63:32] = CSU.IDCODE register
 190                  * regs[1][31:0]  = CSU.version register
 191                  * regs[1][63:32] = CSU.IDCODE2 register
 192                  */
 193                 switch (id) {
 194                 case IDCODE:
 195                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 196                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 197                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 198                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 199                         val = regs.regs[0];
 200                         break;
 201                 case VERSION:
 202                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 203                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 204                         val = regs.regs[1];
 205                         break;
 206                 case IDCODE2:
 207                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 208                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 209                         val = regs.regs[1];
 210                         break;
 211                 default:
 212                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 213                 }
 214         } else {
 215                 switch (id) {
 216                 case IDCODE:
 217                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 218                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 219                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 220                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 221                         break;
 222                 case VERSION:
 223                         val = readl(ZYNQMP_CSU_VER_ADDR);
 224                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 225                         break;
 226                 default:
 227                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 228                 }
 229         }
 230
 231         return val;
 232 }
 233
 234 #define ZYNQMP_VERSION_SIZE             9
 235 #define ZYNQMP_PL_STATUS_BIT            9
 236 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 237 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 238
 239 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 240         !defined(CONFIG_SPL_BUILD)
 241 static char *zynqmp_get_silicon_idcode_name(void)
 242 {
 243         u32 i, id, ver;
 244         char *buf;
 245         static char name[ZYNQMP_VERSION_SIZE];
 246
 247         id = chip_id(IDCODE);
 248         ver = chip_id(IDCODE2);
 249
 250         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 251                 if ((zynqmp_devices[i].id == id) &&
 252                     (zynqmp_devices[i].ver == (ver &
 253                     ZYNQMP_CSU_VERSION_MASK))) {
 254                         strncat(name, "zu", 2);
 255                         strncat(name, zynqmp_devices[i].name,
 256                                 ZYNQMP_VERSION_SIZE - 3);
 257                         break;
 258                 }
 259         }
 260
 261         if (i >= ARRAY_SIZE(zynqmp_devices))
 262                 return "unknown";
 263
 264         if (!zynqmp_devices[i].evexists)
 265                 return name;
 266
 267         if (ver & ZYNQMP_PL_STATUS_MASK)
 268                 return name;
 269
 270         if (strstr(name, "eg") || strstr(name, "ev")) {
 271                 buf = strstr(name, "e");
 272                 *buf = '\0';
 273         }
 274
 275         return name;
 276 }
 277 #endif
 278
 279 int board_early_init_f(void)
 280 {
 281         int ret = 0;
 282 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 283         zynqmp_pmufw_version();
 284 #endif
 285
 286 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 287         ret = psu_init();
 288 #endif
 289
 290 #if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
 291         /* bss is not cleared at time when watchdog_reset() is called */
 292         watchdog_dev = NULL;
 293 #endif
 294
 295         return ret;
 296 }
 297
 298 int board_init(void)
 299 {
 300         printf("EL Level:\tEL%d\n", current_el());
 301
 302 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 303     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 304     defined(CONFIG_SPL_BUILD))
 305         if (current_el() != 3) {
 306                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 307                 printf("Chip ID:\t%s\n", zynqmppl.name);
 308                 fpga_init();
 309                 fpga_add(fpga_xilinx, &zynqmppl);
 310         }
 311 #endif
 312
 313 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
 314         if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 315                 puts("Watchdog: Not found!\n");
 316         } else {
 317                 wdt_start(watchdog_dev, 0, 0);
 318                 puts("Watchdog: Started\n");
 319         }
 320 #endif
 321
 322         return 0;
 323 }
 324
 325 #ifdef CONFIG_WATCHDOG
 326 /* Called by macro WATCHDOG_RESET */
 327 void watchdog_reset(void)
 328 {
 329 # if !defined(CONFIG_SPL_BUILD)
 330         static ulong next_reset;
 331         ulong now;
 332
 333         if (!watchdog_dev)
 334                 return;
 335
 336         now = timer_get_us();
 337
 338         /* Do not reset the watchdog too often */
 339         if (now > next_reset) {
 340                 wdt_reset(watchdog_dev);
 341                 next_reset = now + 1000;
 342         }
 343 # endif
 344 }
 345 #endif
 346
 347 int board_early_init_r(void)
 348 {
 349         u32 val;
 350
 351         if (current_el() != 3)
 352                 return 0;
 353
 354         val = readl(&crlapb_base->timestamp_ref_ctrl);
 355         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 356
 357         if (!val) {
 358                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 359                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 360                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 361
 362                 /* Program freq register in System counter */
 363                 writel(zynqmp_get_system_timer_freq(),
 364                        &iou_scntr_secure->base_frequency_id_register);
 365                 /* And enable system counter */
 366                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 367                        &iou_scntr_secure->counter_control_register);
 368         }
 369         return 0;
 370 }
 371
 372 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 373 {
 374 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 375     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 376     defined(CONFIG_ZYNQ_EEPROM_BUS)
 377         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 378
 379         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 380                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 381                         ethaddr, 6))
 382                 printf("I2C EEPROM MAC address read failed\n");
 383 #endif
 384
 385         return 0;
 386 }
 387
 388 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 389                          char * const argv[])
 390 {
 391         int ret = 0;
 392
 393         if (current_el() > 1) {
 394                 smp_kick_all_cpus();
 395                 dcache_disable();
 396                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 397                                     ES_TO_AARCH64);
 398         } else {
 399                 printf("FAIL: current EL is not above EL1\n");
 400                 ret = EINVAL;
 401         }
 402         return ret;
 403 }
 404
 405 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 406 int dram_init_banksize(void)
 407 {
 408         int ret;
 409
 410         ret = fdtdec_setup_memory_banksize();
 411         if (ret)
 412                 return ret;
 413
 414         mem_map_fill();
 415
 416         return 0;
 417 }
 418
 419 int dram_init(void)
 420 {
 421         if (fdtdec_setup_memory_size() != 0)
 422                 return -EINVAL;
 423
 424         return 0;
 425 }
 426 #else
 427 int dram_init_banksize(void)
 428 {
 429 #if defined(CONFIG_NR_DRAM_BANKS)
 430         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 431         gd->bd->bi_dram[0].size = get_effective_memsize();
 432 #endif
 433
 434         mem_map_fill();
 435
 436         return 0;
 437 }
 438
 439 int dram_init(void)
 440 {
 441         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 442                                     CONFIG_SYS_SDRAM_SIZE);
 443
 444         return 0;
 445 }
 446 #endif
 447
 448 void reset_cpu(ulong addr)
 449 {
 450 }
 451
 452 int board_late_init(void)
 453 {
 454         u32 reg = 0;
 455         u8 bootmode;
 456         const char *mode;
 457         char *new_targets;
 458         char *env_targets;
 459         int ret;
 460
 461         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 462                 debug("Saved variables - Skipping\n");
 463                 return 0;
 464         }
 465
 466         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 467         if (ret)
 468                 return -EINVAL;
 469
 470         if (reg >> BOOT_MODE_ALT_SHIFT)
 471                 reg >>= BOOT_MODE_ALT_SHIFT;
 472
 473         bootmode = reg & BOOT_MODES_MASK;
 474
 475         puts("Bootmode: ");
 476         switch (bootmode) {
 477         case USB_MODE:
 478                 puts("USB_MODE\n");
 479                 mode = "usb";
 480                 env_set("modeboot", "usb_dfu_spl");
 481                 break;
 482         case JTAG_MODE:
 483                 puts("JTAG_MODE\n");
 484                 mode = "pxe dhcp";
 485                 env_set("modeboot", "jtagboot");
 486                 break;
 487         case QSPI_MODE_24BIT:
 488         case QSPI_MODE_32BIT:
 489                 mode = "qspi0";
 490                 puts("QSPI_MODE\n");
 491                 env_set("modeboot", "qspiboot");
 492                 break;
 493         case EMMC_MODE:
 494                 puts("EMMC_MODE\n");
 495                 mode = "mmc0";
 496                 env_set("modeboot", "emmcboot");
 497                 break;
 498         case SD_MODE:
 499                 puts("SD_MODE\n");
 500                 mode = "mmc0";
 501                 env_set("modeboot", "sdboot");
 502                 break;
 503         case SD1_LSHFT_MODE:
 504                 puts("LVL_SHFT_");
 505                 /* fall through */
 506         case SD_MODE1:
 507                 puts("SD_MODE1\n");
 508 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 509                 mode = "mmc1";
 510                 env_set("sdbootdev", "1");
 511 #else
 512                 mode = "mmc0";
 513 #endif
 514                 env_set("modeboot", "sdboot");
 515                 break;
 516         case NAND_MODE:
 517                 puts("NAND_MODE\n");
 518                 mode = "nand0";
 519                 env_set("modeboot", "nandboot");
 520                 break;
 521         default:
 522                 mode = "";
 523                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 524                 break;
 525         }
 526
 527         /*
 528          * One terminating char + one byte for space between mode
 529          * and default boot_targets
 530          */
 531         env_targets = env_get("boot_targets");
 532         if (env_targets) {
 533                 new_targets = calloc(1, strlen(mode) +
 534                                      strlen(env_targets) + 2);
 535                 sprintf(new_targets, "%s %s", mode, env_targets);
 536         } else {
 537                 new_targets = calloc(1, strlen(mode) + 2);
 538                 sprintf(new_targets, "%s", mode);
 539         }
 540
 541         env_set("boot_targets", new_targets);
 542
 543         return 0;
 544 }
 545
 546 int checkboard(void)
 547 {
 548         puts("Board: Xilinx ZynqMP\n");
 549         return 0;
 550 }
 551
 552 #ifdef CONFIG_USB_DWC3
 553 static struct dwc3_device dwc3_device_data0 = {
 554         .maximum_speed = USB_SPEED_HIGH,
 555         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 556         .dr_mode = USB_DR_MODE_PERIPHERAL,
 557         .index = 0,
 558 };
 559
 560 static struct dwc3_device dwc3_device_data1 = {
 561         .maximum_speed = USB_SPEED_HIGH,
 562         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 563         .dr_mode = USB_DR_MODE_PERIPHERAL,
 564         .index = 1,
 565 };
 566
 567 int usb_gadget_handle_interrupts(int index)
 568 {
 569         dwc3_uboot_handle_interrupt(index);
 570         return 0;
 571 }
 572
 573 int board_usb_init(int index, enum usb_init_type init)
 574 {
 575         debug("%s: index %x\n", __func__, index);
 576
 577 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 578         g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 579 #endif
 580
 581         switch (index) {
 582         case 0:
 583                 return dwc3_uboot_init(&dwc3_device_data0);
 584         case 1:
 585                 return dwc3_uboot_init(&dwc3_device_data1);
 586         };
 587
 588         return -1;
 589 }
 590
 591 int board_usb_cleanup(int index, enum usb_init_type init)
 592 {
 593         dwc3_uboot_exit(index);
 594         return 0;
 595 }
 596 #endif