2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 #include <dwc3-uboot.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 !defined(CONFIG_SPL_BUILD)
27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
33 } zynqmp_devices[] = {
116 { /* For testing purpose only */
160 int chip_id(unsigned char id)
165 if (current_el() != 3) {
166 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
175 * regs[0][31:0] = status of the operation
176 * regs[0][63:32] = CSU.IDCODE register
177 * regs[1][31:0] = CSU.version register
178 * regs[1][63:32] = CSU.IDCODE2 register
182 regs.regs[0] = upper_32_bits(regs.regs[0]);
183 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
184 ZYNQMP_CSU_IDCODE_SVD_MASK;
185 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
189 regs.regs[1] = lower_32_bits(regs.regs[1]);
190 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
194 regs.regs[1] = lower_32_bits(regs.regs[1]);
195 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
199 printf("%s, Invalid Req:0x%x\n", __func__, id);
204 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
205 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
206 ZYNQMP_CSU_IDCODE_SVD_MASK;
207 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
210 val = readl(ZYNQMP_CSU_VER_ADDR);
211 val &= ZYNQMP_CSU_SILICON_VER_MASK;
214 printf("%s, Invalid Req:0x%x\n", __func__, id);
221 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
222 !defined(CONFIG_SPL_BUILD)
223 static char *zynqmp_get_silicon_idcode_name(void)
227 id = chip_id(IDCODE);
228 ver = chip_id(IDCODE2);
230 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
231 if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
232 return zynqmp_devices[i].name;
238 int board_early_init_f(void)
240 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
241 zynqmp_pmufw_version();
244 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
251 #define ZYNQMP_VERSION_SIZE 9
255 printf("EL Level:\tEL%d\n", current_el());
257 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
258 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
259 defined(CONFIG_SPL_BUILD))
260 if (current_el() != 3) {
261 static char version[ZYNQMP_VERSION_SIZE];
263 strncat(version, "zu", 2);
264 zynqmppl.name = strncat(version,
265 zynqmp_get_silicon_idcode_name(),
266 ZYNQMP_VERSION_SIZE - 3);
267 printf("Chip ID:\t%s\n", zynqmppl.name);
269 fpga_add(fpga_xilinx, &zynqmppl);
276 int board_early_init_r(void)
280 if (current_el() != 3)
283 val = readl(&crlapb_base->timestamp_ref_ctrl);
284 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
287 val = readl(&crlapb_base->timestamp_ref_ctrl);
288 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
289 writel(val, &crlapb_base->timestamp_ref_ctrl);
291 /* Program freq register in System counter */
292 writel(zynqmp_get_system_timer_freq(),
293 &iou_scntr_secure->base_frequency_id_register);
294 /* And enable system counter */
295 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
296 &iou_scntr_secure->counter_control_register);
301 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
303 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
304 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
305 defined(CONFIG_ZYNQ_EEPROM_BUS)
306 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
308 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
309 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
311 printf("I2C EEPROM MAC address read failed\n");
317 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
318 int dram_init_banksize(void)
320 return fdtdec_setup_memory_banksize();
325 if (fdtdec_setup_memory_size() != 0)
333 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
339 void reset_cpu(ulong addr)
343 int board_late_init(void)
351 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
352 debug("Saved variables - Skipping\n");
356 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
360 if (reg >> BOOT_MODE_ALT_SHIFT)
361 reg >>= BOOT_MODE_ALT_SHIFT;
363 bootmode = reg & BOOT_MODES_MASK;
370 env_set("modeboot", "usb_dfu_spl");
375 env_set("modeboot", "jtagboot");
377 case QSPI_MODE_24BIT:
378 case QSPI_MODE_32BIT:
381 env_set("modeboot", "qspiboot");
386 env_set("modeboot", "emmcboot");
391 env_set("modeboot", "sdboot");
398 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
400 env_set("sdbootdev", "1");
404 env_set("modeboot", "sdboot");
409 env_set("modeboot", "nandboot");
413 printf("Invalid Boot Mode:0x%x\n", bootmode);
418 * One terminating char + one byte for space between mode
419 * and default boot_targets
421 new_targets = calloc(1, strlen(mode) +
422 strlen(env_get("boot_targets")) + 2);
424 sprintf(new_targets, "%s %s", mode, env_get("boot_targets"));
425 env_set("boot_targets", new_targets);
432 puts("Board: Xilinx ZynqMP\n");
436 #ifdef CONFIG_USB_DWC3
437 static struct dwc3_device dwc3_device_data0 = {
438 .maximum_speed = USB_SPEED_HIGH,
439 .base = ZYNQMP_USB0_XHCI_BASEADDR,
440 .dr_mode = USB_DR_MODE_PERIPHERAL,
444 static struct dwc3_device dwc3_device_data1 = {
445 .maximum_speed = USB_SPEED_HIGH,
446 .base = ZYNQMP_USB1_XHCI_BASEADDR,
447 .dr_mode = USB_DR_MODE_PERIPHERAL,
451 int usb_gadget_handle_interrupts(int index)
453 dwc3_uboot_handle_interrupt(index);
457 int board_usb_init(int index, enum usb_init_type init)
459 debug("%s: index %x\n", __func__, index);
461 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
462 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
467 return dwc3_uboot_init(&dwc3_device_data0);
469 return dwc3_uboot_init(&dwc3_device_data1);
475 int board_usb_cleanup(int index, enum usb_init_type init)
477 dwc3_uboot_exit(index);