git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <netdev.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <asm/arch/clk.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/io.h>
  16 #include <usb.h>
  17 #include <dwc3-uboot.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 int board_init(void)
  22 {
  23         printf("EL Level:\tEL%d\n", current_el());
  24
  25         return 0;
  26 }
  27
  28 int board_early_init_r(void)
  29 {
  30         u32 val;
  31
  32         if (current_el() == 3) {
  33                 val = readl(&crlapb_base->timestamp_ref_ctrl);
  34                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  35                 writel(val, &crlapb_base->timestamp_ref_ctrl);
  36
  37                 /* Program freq register in System counter */
  38                 writel(zynqmp_get_system_timer_freq(),
  39                        &iou_scntr_secure->base_frequency_id_register);
  40                 /* And enable system counter */
  41                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
  42                        &iou_scntr_secure->counter_control_register);
  43         }
  44         /* Program freq register in System counter and enable system counter */
  45         writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
  46         writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
  47                ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
  48                &iou_scntr->counter_control_register);
  49
  50         return 0;
  51 }
  52
  53 int dram_init(void)
  54 {
  55         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  56
  57         return 0;
  58 }
  59
  60 int timer_init(void)
  61 {
  62         return 0;
  63 }
  64
  65 void reset_cpu(ulong addr)
  66 {
  67 }
  68
  69 #ifdef CONFIG_SCSI_AHCI_PLAT
  70 void scsi_init(void)
  71 {
  72         ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
  73         scsi_scan(1);
  74 }
  75 #endif
  76
  77 int board_late_init(void)
  78 {
  79         u32 reg = 0;
  80         u8 bootmode;
  81
  82         reg = readl(&crlapb_base->boot_mode);
  83         bootmode = reg & BOOT_MODES_MASK;
  84
  85         switch (bootmode) {
  86         case JTAG_MODE:
  87                 setenv("modeboot", "netboot");
  88                 break;
  89         case QSPI_MODE_24BIT:
  90         case QSPI_MODE_32BIT:
  91                 setenv("modeboot", "qspiboot");
  92                 break;
  93         case SD_MODE:
  94         case EMMC_MODE:
  95                 setenv("modeboot", "sdboot");
  96                 break;
  97         default:
  98                 printf("Invalid Boot Mode:0x%x\n", bootmode);
  99                 break;
 100         }
 101
 102         return 0;
 103 }
 104
 105 int checkboard(void)
 106 {
 107         puts("Board:\tXilinx ZynqMP\n");
 108         return 0;
 109 }
 110
 111 #ifdef CONFIG_USB_DWC3
 112 static struct dwc3_device dwc3_device_data = {
 113         .maximum_speed = USB_SPEED_HIGH,
 114         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 115         .dr_mode = USB_DR_MODE_PERIPHERAL,
 116         .index = 0,
 117 };
 118
 119 int usb_gadget_handle_interrupts(void)
 120 {
 121         dwc3_uboot_handle_interrupt(0);
 122         return 0;
 123 }
 124
 125 int board_usb_init(int index, enum usb_init_type init)
 126 {
 127         return dwc3_uboot_init(&dwc3_device_data);
 128 }
 129
 130 int board_usb_cleanup(int index, enum usb_init_type init)
 131 {
 132         dwc3_uboot_exit(index);
 133         return 0;
 134 }
 135 #endif