git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <usb.h>
  18 #include <dwc3-uboot.h>
  19 #include <zynqmppl.h>
  20 #include <i2c.h>
  21 #include <g_dnl.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  26     !defined(CONFIG_SPL_BUILD)
  27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  28
  29 static const struct {
  30         uint32_t id;
  31         char *name;
  32 } zynqmp_devices[] = {
  33         {
  34                 .id = 0x10,
  35                 .name = "3eg",
  36         },
  37         {
  38                 .id = 0x11,
  39                 .name = "2eg",
  40         },
  41         {
  42                 .id = 0x20,
  43                 .name = "5ev",
  44         },
  45         {
  46                 .id = 0x21,
  47                 .name = "4ev",
  48         },
  49         {
  50                 .id = 0x30,
  51                 .name = "7ev",
  52         },
  53         {
  54                 .id = 0x38,
  55                 .name = "9eg",
  56         },
  57         {
  58                 .id = 0x39,
  59                 .name = "6eg",
  60         },
  61         {
  62                 .id = 0x40,
  63                 .name = "11eg",
  64         },
  65         {
  66                 .id = 0x50,
  67                 .name = "15eg",
  68         },
  69         {
  70                 .id = 0x58,
  71                 .name = "19eg",
  72         },
  73         {
  74                 .id = 0x59,
  75                 .name = "17eg",
  76         },
  77 };
  78
  79 static int chip_id(void)
  80 {
  81         struct pt_regs regs;
  82         regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
  83         regs.regs[1] = 0;
  84         regs.regs[2] = 0;
  85         regs.regs[3] = 0;
  86
  87         smc_call(&regs);
  88
  89         return regs.regs[0];
  90 }
  91
  92 static char *zynqmp_get_silicon_idcode_name(void)
  93 {
  94         uint32_t i, id;
  95
  96         id = chip_id();
  97         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
  98                 if (zynqmp_devices[i].id == id)
  99                         return zynqmp_devices[i].name;
 100         }
 101         return "unknown";
 102 }
 103 #endif
 104
 105 #define ZYNQMP_VERSION_SIZE     9
 106
 107 int board_init(void)
 108 {
 109         printf("EL Level:\tEL%d\n", current_el());
 110
 111 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 112     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 113     defined(CONFIG_SPL_BUILD))
 114         if (current_el() != 3) {
 115                 static char version[ZYNQMP_VERSION_SIZE];
 116
 117                 strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
 118                 zynqmppl.name = strncat(version,
 119                                         zynqmp_get_silicon_idcode_name(),
 120                                         ZYNQMP_VERSION_SIZE);
 121                 printf("Chip ID:\t%s\n", zynqmppl.name);
 122                 fpga_init();
 123                 fpga_add(fpga_xilinx, &zynqmppl);
 124         }
 125 #endif
 126
 127         return 0;
 128 }
 129
 130 int board_early_init_r(void)
 131 {
 132         u32 val;
 133
 134         if (current_el() == 3) {
 135                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 136                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 137                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 138
 139                 /* Program freq register in System counter */
 140                 writel(zynqmp_get_system_timer_freq(),
 141                        &iou_scntr_secure->base_frequency_id_register);
 142                 /* And enable system counter */
 143                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 144                        &iou_scntr_secure->counter_control_register);
 145         }
 146         /* Program freq register in System counter and enable system counter */
 147         writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
 148         writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
 149                ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 150                &iou_scntr->counter_control_register);
 151
 152         return 0;
 153 }
 154
 155 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 156 {
 157 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 158     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 159     defined(CONFIG_ZYNQ_EEPROM_BUS)
 160         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 161
 162         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 163                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 164                         ethaddr, 6))
 165                 printf("I2C EEPROM MAC address read failed\n");
 166 #endif
 167
 168         return 0;
 169 }
 170
 171 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 172 /*
 173  * fdt_get_reg - Fill buffer by information from DT
 174  */
 175 static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
 176                                const u32 *cell, int n)
 177 {
 178         int i = 0, b, banks;
 179         int parent_offset = fdt_parent_offset(fdt, nodeoffset);
 180         int address_cells = fdt_address_cells(fdt, parent_offset);
 181         int size_cells = fdt_size_cells(fdt, parent_offset);
 182         char *p = buf;
 183         u64 val;
 184         u64 vals;
 185
 186         debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
 187               __func__, address_cells, size_cells, buf, cell);
 188
 189         /* Check memory bank setup */
 190         banks = n % (address_cells + size_cells);
 191         if (banks)
 192                 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
 193                       n, address_cells, size_cells);
 194
 195         banks = n / (address_cells + size_cells);
 196
 197         for (b = 0; b < banks; b++) {
 198                 debug("%s: Bank #%d:\n", __func__, b);
 199                 if (address_cells == 2) {
 200                         val = cell[i + 1];
 201                         val <<= 32;
 202                         val |= cell[i];
 203                         val = fdt64_to_cpu(val);
 204                         debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
 205                               __func__, val, p, &cell[i]);
 206                         *(phys_addr_t *)p = val;
 207                 } else {
 208                         debug("%s: addr32=%x, ptr=%p\n",
 209                               __func__, fdt32_to_cpu(cell[i]), p);
 210                         *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
 211                 }
 212                 p += sizeof(phys_addr_t);
 213                 i += address_cells;
 214
 215                 debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
 216                       sizeof(phys_addr_t));
 217
 218                 if (size_cells == 2) {
 219                         vals = cell[i + 1];
 220                         vals <<= 32;
 221                         vals |= cell[i];
 222                         vals = fdt64_to_cpu(vals);
 223
 224                         debug("%s: size64=%llx, ptr=%p, cell=%p\n",
 225                               __func__, vals, p, &cell[i]);
 226                         *(phys_size_t *)p = vals;
 227                 } else {
 228                         debug("%s: size32=%x, ptr=%p\n",
 229                               __func__, fdt32_to_cpu(cell[i]), p);
 230                         *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
 231                 }
 232                 p += sizeof(phys_size_t);
 233                 i += size_cells;
 234
 235                 debug("%s: ps=%p, i=%x, size=%zu\n",
 236                       __func__, p, i, sizeof(phys_size_t));
 237         }
 238
 239         /* Return the first address size */
 240         return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
 241 }
 242
 243 #define FDT_REG_SIZE  sizeof(u32)
 244 /* Temp location for sharing data for storing */
 245 /* Up to 64-bit address + 64-bit size */
 246 static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
 247
 248 void dram_init_banksize(void)
 249 {
 250         int bank;
 251
 252         memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
 253
 254         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 255                 debug("Bank #%d: start %llx\n", bank,
 256                       (unsigned long long)gd->bd->bi_dram[bank].start);
 257                 debug("Bank #%d: size %llx\n", bank,
 258                       (unsigned long long)gd->bd->bi_dram[bank].size);
 259         }
 260 }
 261
 262 int dram_init(void)
 263 {
 264         int node, len;
 265         const void *blob = gd->fdt_blob;
 266         const u32 *cell;
 267
 268         memset(&tmp, 0, sizeof(tmp));
 269
 270         /* find or create "/memory" node. */
 271         node = fdt_subnode_offset(blob, 0, "memory");
 272         if (node < 0) {
 273                 printf("%s: Can't get memory node\n", __func__);
 274                 return node;
 275         }
 276
 277         /* Get pointer to cells and lenght of it */
 278         cell = fdt_getprop(blob, node, "reg", &len);
 279         if (!cell) {
 280                 printf("%s: Can't get reg property\n", __func__);
 281                 return -1;
 282         }
 283
 284         gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
 285
 286         debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
 287
 288         return 0;
 289 }
 290 #else
 291 int dram_init(void)
 292 {
 293         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 294
 295         return 0;
 296 }
 297 #endif
 298
 299 void reset_cpu(ulong addr)
 300 {
 301 }
 302
 303 #ifdef CONFIG_SCSI_AHCI_PLAT
 304 void scsi_init(void)
 305 {
 306 #if defined(CONFIG_SATA_CEVA)
 307         init_sata(0);
 308 #endif
 309         ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
 310         scsi_scan(1);
 311 }
 312 #endif
 313
 314 int board_late_init(void)
 315 {
 316         u32 reg = 0;
 317         u8 bootmode;
 318         const char *mode;
 319         char *new_targets;
 320
 321         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 322                 debug("Saved variables - Skipping\n");
 323                 return 0;
 324         }
 325
 326         reg = readl(&crlapb_base->boot_mode);
 327         bootmode = reg & BOOT_MODES_MASK;
 328
 329         puts("Bootmode: ");
 330         switch (bootmode) {
 331         case USB_MODE:
 332                 puts("USB_MODE\n");
 333                 mode = "usb";
 334                 break;
 335         case JTAG_MODE:
 336                 puts("JTAG_MODE\n");
 337                 mode = "pxe dhcp";
 338                 break;
 339         case QSPI_MODE_24BIT:
 340         case QSPI_MODE_32BIT:
 341                 mode = "qspi0";
 342                 puts("QSPI_MODE\n");
 343                 break;
 344         case EMMC_MODE:
 345                 puts("EMMC_MODE\n");
 346                 mode = "mmc0";
 347                 break;
 348         case SD_MODE:
 349                 puts("SD_MODE\n");
 350                 mode = "mmc0";
 351                 break;
 352         case SD_MODE1:
 353                 puts("SD_MODE1\n");
 354 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 355                 mode = "mmc1";
 356 #else
 357                 mode = "mmc0";
 358 #endif
 359                 break;
 360         case NAND_MODE:
 361                 puts("NAND_MODE\n");
 362                 mode = "nand0";
 363                 break;
 364         default:
 365                 mode = "";
 366                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 367                 break;
 368         }
 369
 370         /*
 371          * One terminating char + one byte for space between mode
 372          * and default boot_targets
 373          */
 374         new_targets = calloc(1, strlen(mode) +
 375                                 strlen(getenv("boot_targets")) + 2);
 376
 377         sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
 378         setenv("boot_targets", new_targets);
 379
 380         return 0;
 381 }
 382
 383 int checkboard(void)
 384 {
 385         puts("Board: Xilinx ZynqMP\n");
 386         return 0;
 387 }
 388
 389 #ifdef CONFIG_USB_DWC3
 390 static struct dwc3_device dwc3_device_data0 = {
 391         .maximum_speed = USB_SPEED_HIGH,
 392         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 393         .dr_mode = USB_DR_MODE_PERIPHERAL,
 394         .index = 0,
 395 };
 396
 397 static struct dwc3_device dwc3_device_data1 = {
 398         .maximum_speed = USB_SPEED_HIGH,
 399         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 400         .dr_mode = USB_DR_MODE_PERIPHERAL,
 401         .index = 1,
 402 };
 403
 404 int usb_gadget_handle_interrupts(int index)
 405 {
 406         dwc3_uboot_handle_interrupt(index);
 407         return 0;
 408 }
 409
 410 int board_usb_init(int index, enum usb_init_type init)
 411 {
 412         debug("%s: index %x\n", __func__, index);
 413
 414         switch (index) {
 415         case 0:
 416                 return dwc3_uboot_init(&dwc3_device_data0);
 417         case 1:
 418                 return dwc3_uboot_init(&dwc3_device_data1);
 419         };
 420
 421         return -1;
 422 }
 423
 424 int board_usb_cleanup(int index, enum usb_init_type init)
 425 {
 426         dwc3_uboot_exit(index);
 427         return 0;
 428 }
 429 #endif