git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <usb.h>
  18 #include <dwc3-uboot.h>
  19 #include <zynqmppl.h>
  20 #include <i2c.h>
  21 #include <g_dnl.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  26     !defined(CONFIG_SPL_BUILD)
  27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  28
  29 static const struct {
  30         uint32_t id;
  31         char *name;
  32 } zynqmp_devices[] = {
  33         {
  34                 .id = 0x10,
  35                 .name = "3eg",
  36         },
  37         {
  38                 .id = 0x11,
  39                 .name = "2eg",
  40         },
  41         {
  42                 .id = 0x20,
  43                 .name = "5ev",
  44         },
  45         {
  46                 .id = 0x21,
  47                 .name = "4ev",
  48         },
  49         {
  50                 .id = 0x30,
  51                 .name = "7ev",
  52         },
  53         {
  54                 .id = 0x38,
  55                 .name = "9eg",
  56         },
  57         {
  58                 .id = 0x39,
  59                 .name = "6eg",
  60         },
  61         {
  62                 .id = 0x40,
  63                 .name = "11eg",
  64         },
  65         {
  66                 .id = 0x50,
  67                 .name = "15eg",
  68         },
  69         {
  70                 .id = 0x58,
  71                 .name = "19eg",
  72         },
  73         {
  74                 .id = 0x59,
  75                 .name = "17eg",
  76         },
  77 };
  78
  79 static int chip_id(void)
  80 {
  81         struct pt_regs regs;
  82         regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
  83         regs.regs[1] = 0;
  84         regs.regs[2] = 0;
  85         regs.regs[3] = 0;
  86
  87         smc_call(&regs);
  88
  89         /*
  90          * SMC returns:
  91          * regs[0][31:0]  = status of the operation
  92          * regs[0][63:32] = CSU.IDCODE register
  93          * regs[1][31:0]  = CSU.version register
  94          */
  95         regs.regs[0] = upper_32_bits(regs.regs[0]);
  96         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  97                         ZYNQMP_CSU_IDCODE_SVD_MASK;
  98         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  99
 100         return regs.regs[0];
 101 }
 102
 103 static char *zynqmp_get_silicon_idcode_name(void)
 104 {
 105         uint32_t i, id;
 106
 107         id = chip_id();
 108         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 109                 if (zynqmp_devices[i].id == id)
 110                         return zynqmp_devices[i].name;
 111         }
 112         return "unknown";
 113 }
 114 #endif
 115
 116 #define ZYNQMP_VERSION_SIZE     9
 117
 118 int board_init(void)
 119 {
 120         printf("EL Level:\tEL%d\n", current_el());
 121
 122 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 123     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 124     defined(CONFIG_SPL_BUILD))
 125         if (current_el() != 3) {
 126                 static char version[ZYNQMP_VERSION_SIZE];
 127
 128                 strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
 129                 zynqmppl.name = strncat(version,
 130                                         zynqmp_get_silicon_idcode_name(),
 131                                         ZYNQMP_VERSION_SIZE);
 132                 printf("Chip ID:\t%s\n", zynqmppl.name);
 133                 fpga_init();
 134                 fpga_add(fpga_xilinx, &zynqmppl);
 135         }
 136 #endif
 137
 138         return 0;
 139 }
 140
 141 int board_early_init_r(void)
 142 {
 143         u32 val;
 144
 145         if (current_el() == 3) {
 146                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 147                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 148                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 149
 150                 /* Program freq register in System counter */
 151                 writel(zynqmp_get_system_timer_freq(),
 152                        &iou_scntr_secure->base_frequency_id_register);
 153                 /* And enable system counter */
 154                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 155                        &iou_scntr_secure->counter_control_register);
 156         }
 157         /* Program freq register in System counter and enable system counter */
 158         writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
 159         writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
 160                ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 161                &iou_scntr->counter_control_register);
 162
 163         return 0;
 164 }
 165
 166 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 167 {
 168 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 169     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 170     defined(CONFIG_ZYNQ_EEPROM_BUS)
 171         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 172
 173         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 174                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 175                         ethaddr, 6))
 176                 printf("I2C EEPROM MAC address read failed\n");
 177 #endif
 178
 179         return 0;
 180 }
 181
 182 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 183 static const void *get_memory_reg_prop(const void *fdt, int *lenp)
 184 {
 185         int offset;
 186
 187         offset = fdt_path_offset(fdt, "/memory");
 188         if (offset < 0)
 189                 return NULL;
 190
 191         return fdt_getprop(fdt, offset, "reg", lenp);
 192 }
 193
 194 int dram_init(void)
 195 {
 196         const void *fdt = gd->fdt_blob;
 197         const fdt32_t *val;
 198         int ac, sc, len;
 199
 200         ac = fdt_address_cells(fdt, 0);
 201         sc = fdt_size_cells(fdt, 0);
 202         if (ac < 0 || sc < 1 || sc > 2) {
 203                 printf("invalid address/size cells\n");
 204                 return -EINVAL;
 205         }
 206
 207         val = get_memory_reg_prop(fdt, &len);
 208         if (len / sizeof(*val) < ac + sc)
 209                 return -EINVAL;
 210
 211         val += ac;
 212
 213         gd->ram_size = fdtdec_get_number(val, sc);
 214
 215         debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
 216
 217         return 0;
 218 }
 219
 220 void dram_init_banksize(void)
 221 {
 222         const void *fdt = gd->fdt_blob;
 223         const fdt32_t *val;
 224         int ac, sc, cells, len, i;
 225
 226         val = get_memory_reg_prop(fdt, &len);
 227         if (len < 0)
 228                 return;
 229
 230         ac = fdt_address_cells(fdt, 0);
 231         sc = fdt_size_cells(fdt, 0);
 232         if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
 233                 printf("invalid address/size cells\n");
 234                 return;
 235         }
 236
 237         cells = ac + sc;
 238
 239         len /= sizeof(*val);
 240
 241         for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
 242              i++, len -= cells) {
 243                 gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac);
 244                 val += ac;
 245                 gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc);
 246                 val += sc;
 247
 248                 debug("DRAM bank %d: start = %08lx, size = %08lx\n",
 249                       i, (unsigned long)gd->bd->bi_dram[i].start,
 250                       (unsigned long)gd->bd->bi_dram[i].size);
 251         }
 252 }
 253 #else
 254 int dram_init(void)
 255 {
 256         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 257
 258         return 0;
 259 }
 260 #endif
 261
 262 void reset_cpu(ulong addr)
 263 {
 264 }
 265
 266 int board_late_init(void)
 267 {
 268         u32 reg = 0;
 269         u8 bootmode;
 270         const char *mode;
 271         char *new_targets;
 272
 273         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 274                 debug("Saved variables - Skipping\n");
 275                 return 0;
 276         }
 277
 278         reg = readl(&crlapb_base->boot_mode);
 279         if (reg >> BOOT_MODE_ALT_SHIFT)
 280                 reg >>= BOOT_MODE_ALT_SHIFT;
 281
 282         bootmode = reg & BOOT_MODES_MASK;
 283
 284         puts("Bootmode: ");
 285         switch (bootmode) {
 286         case USB_MODE:
 287                 puts("USB_MODE\n");
 288                 mode = "usb";
 289                 break;
 290         case JTAG_MODE:
 291                 puts("JTAG_MODE\n");
 292                 mode = "pxe dhcp";
 293                 break;
 294         case QSPI_MODE_24BIT:
 295         case QSPI_MODE_32BIT:
 296                 mode = "qspi0";
 297                 puts("QSPI_MODE\n");
 298                 break;
 299         case EMMC_MODE:
 300                 puts("EMMC_MODE\n");
 301                 mode = "mmc0";
 302                 break;
 303         case SD_MODE:
 304                 puts("SD_MODE\n");
 305                 mode = "mmc0";
 306                 break;
 307         case SD1_LSHFT_MODE:
 308                 puts("LVL_SHFT_");
 309                 /* fall through */
 310         case SD_MODE1:
 311                 puts("SD_MODE1\n");
 312 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 313                 mode = "mmc1";
 314 #else
 315                 mode = "mmc0";
 316 #endif
 317                 break;
 318         case NAND_MODE:
 319                 puts("NAND_MODE\n");
 320                 mode = "nand0";
 321                 break;
 322         default:
 323                 mode = "";
 324                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 325                 break;
 326         }
 327
 328         /*
 329          * One terminating char + one byte for space between mode
 330          * and default boot_targets
 331          */
 332         new_targets = calloc(1, strlen(mode) +
 333                                 strlen(getenv("boot_targets")) + 2);
 334
 335         sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
 336         setenv("boot_targets", new_targets);
 337
 338         return 0;
 339 }
 340
 341 int checkboard(void)
 342 {
 343         puts("Board: Xilinx ZynqMP\n");
 344         return 0;
 345 }
 346
 347 #ifdef CONFIG_USB_DWC3
 348 static struct dwc3_device dwc3_device_data0 = {
 349         .maximum_speed = USB_SPEED_HIGH,
 350         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 351         .dr_mode = USB_DR_MODE_PERIPHERAL,
 352         .index = 0,
 353 };
 354
 355 static struct dwc3_device dwc3_device_data1 = {
 356         .maximum_speed = USB_SPEED_HIGH,
 357         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 358         .dr_mode = USB_DR_MODE_PERIPHERAL,
 359         .index = 1,
 360 };
 361
 362 int usb_gadget_handle_interrupts(int index)
 363 {
 364         dwc3_uboot_handle_interrupt(index);
 365         return 0;
 366 }
 367
 368 int board_usb_init(int index, enum usb_init_type init)
 369 {
 370         debug("%s: index %x\n", __func__, index);
 371
 372 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 373         g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 374 #endif
 375
 376         switch (index) {
 377         case 0:
 378                 return dwc3_uboot_init(&dwc3_device_data0);
 379         case 1:
 380                 return dwc3_uboot_init(&dwc3_device_data1);
 381         };
 382
 383         return -1;
 384 }
 385
 386 int board_usb_cleanup(int index, enum usb_init_type init)
 387 {
 388         dwc3_uboot_exit(index);
 389         return 0;
 390 }
 391 #endif