2 * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <spd_sdram.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 int board_early_init_f(void)
35 /* TBS: Setup the GPIO access for the user LEDs */
36 mfsdr(sdr_pfc0, sdrreg);
37 mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
38 out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
44 /*--------------------------------------------------------------------
45 * Setup the external bus controller/chip selects
46 *-------------------------------------------------------------------*/
47 mtebc (pb0ap, 0x04055200); /* 16MB Strata FLASH */
48 mtebc (pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
49 mtebc (pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */
50 mtebc (pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
52 /*--------------------------------------------------------------------
53 * Setup the interrupt controller polarities, triggers, etc.
54 *-------------------------------------------------------------------*/
56 * Because of the interrupt handling rework to handle 440GX interrupts
57 * with the common code, we needed to change names of the UIC registers.
58 * Here the new relationship:
60 * U-Boot name 440GX name
61 * -----------------------
67 mtdcr (uic1sr, 0xffffffff); /* clear all */
68 mtdcr (uic1er, 0x00000000); /* disable all */
69 mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
70 mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */
71 mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */
72 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
73 mtdcr (uic1sr, 0xffffffff); /* clear all */
75 mtdcr (uic2sr, 0xffffffff); /* clear all */
76 mtdcr (uic2er, 0x00000000); /* disable all */
77 mtdcr (uic2cr, 0x00000000); /* all non-critical */
78 mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */
79 mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */
80 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
81 mtdcr (uic2sr, 0xffffffff); /* clear all */
83 mtdcr (uic3sr, 0xffffffff); /* clear all */
84 mtdcr (uic3er, 0x00000000); /* disable all */
85 mtdcr (uic3cr, 0x00000000); /* all non-critical */
86 mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
87 mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
88 mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
89 mtdcr (uic3sr, 0xffffffff); /* clear all */
91 mtdcr (uic0sr, 0xfc000000); /* clear all */
92 mtdcr (uic0er, 0x00000000); /* disable all */
93 mtdcr (uic0cr, 0x00000000); /* all non-critical */
94 mtdcr (uic0pr, 0xfc000000); /* */
95 mtdcr (uic0tr, 0x00000000); /* */
96 mtdcr (uic0vr, 0x00000001); /* */
104 int checkboard (void)
106 printf ("Board: XES XPedite1000 440GX\n");
112 phys_size_t initdram (int board_type)
118 /*************************************************************************
121 * This routine is called just prior to registering the hose and gives
122 * the board the opportunity to check things. Returning a value of zero
123 * indicates that things are bad & PCI initialization should be aborted.
125 * Different boards may wish to customize the pci controller structure
126 * (add regions, override default access routines, etc) or perform
127 * certain pre-initialization actions.
129 ************************************************************************/
130 #if defined(CONFIG_PCI)
131 int pci_pre_init(struct pci_controller * hose )
134 /* See if we're supposed to setup the pci */
135 mfsdr(sdr_sdstp1, strap);
136 if ((strap & 0x00010000) == 0) {
140 #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
141 /* Setup System Device Register PCIX0_XCR */
142 mfsdr(sdr_xcr, strap);
144 mtsdr(sdr_xcr, strap);
148 #endif /* defined(CONFIG_PCI) */
150 /*************************************************************************
153 * The bootstrap configuration provides default settings for the pci
154 * inbound map (PIM). But the bootstrap config choices are limited and
155 * may not be sufficient for a given board.
157 ************************************************************************/
158 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
159 void pci_target_init(struct pci_controller * hose )
161 /*--------------------------------------------------------------------------+
163 *--------------------------------------------------------------------------*/
164 out32r( PCIX0_PIM0SA, 0 ); /* disable */
165 out32r( PCIX0_PIM1SA, 0 ); /* disable */
166 out32r( PCIX0_PIM2SA, 0 ); /* disable */
167 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
169 /*--------------------------------------------------------------------------+
170 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
171 * options to not support sizes such as 128/256 MB.
172 *--------------------------------------------------------------------------*/
173 out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
174 out32r( PCIX0_PIM0LAH, 0 );
175 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
177 out32r( PCIX0_BAR0, 0 );
179 /*--------------------------------------------------------------------------+
180 * Program the board's subsystem id/vendor id
181 *--------------------------------------------------------------------------*/
182 out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
183 out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
185 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
187 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
190 /*************************************************************************
193 * This routine is called to determine if a pci scan should be
194 * performed. With various hardware environments (especially cPCI and
195 * PPMC) it's insufficient to depend on the state of the arbiter enable
196 * bit in the strap register, or generic host/adapter assumptions.
198 * Rather than hard-code a bad assumption in the general 440 code, the
199 * 440 pci code requires the board to decide at runtime.
201 * Return 0 for adapter mode, non-zero for host (monarch) mode.
204 ************************************************************************/
205 #if defined(CONFIG_PCI)
206 int is_pci_host(struct pci_controller *hose)
208 return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
210 #endif /* defined(CONFIG_PCI) */
214 * Returns 1 if keys pressed to start the power-on long-running tests
215 * Called from board_init_f().
217 int post_hotkeys_pressed(void)
223 void post_word_store (ulong a)
225 volatile ulong *save_addr =
226 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
231 ulong post_word_load (void)
233 volatile ulong *save_addr =
234 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);