git.sur5r.net Git - u-boot/blob - cm_t43/board.c

   1 /*
   2  * Copyright (C) 2015 Compulab, Ltd.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <miiphy.h>
  10 #include <cpsw.h>
  11 #include <spl.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/mux.h>
  15 #include <asm/arch/ddr_defs.h>
  16 #include <asm/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/emif.h>
  19 #include <power/pmic.h>
  20 #include <power/tps65218.h>
  21 #include "board.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  26
  27 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  28
  29 const struct dpll_params dpll_mpu  = { 800,  24, 1,  -1, -1, -1, -1 };
  30 const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10,  8,  4 };
  31 const struct dpll_params dpll_per  = { 960,  24, 5,  -1, -1, -1, -1 };
  32 const struct dpll_params dpll_ddr  = { 400,  23, 1,  -1,  1, -1, -1 };
  33
  34 const struct ctrl_ioregs ioregs_ddr3 = {
  35         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
  36         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
  37         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
  38         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
  39         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
  40         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
  41         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
  42         .emif_sdram_config_ext  = 0x0143,
  43 };
  44
  45 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
  46 struct emif_regs ddr3_emif_regs = {
  47         .sdram_config                   = 0x638413B2,
  48         .ref_ctrl                       = 0x00000C30,
  49         .sdram_tim1                     = 0xEAAAD4DB,
  50         .sdram_tim2                     = 0x266B7FDA,
  51         .sdram_tim3                     = 0x107F8678,
  52         .read_idle_ctrl                 = 0x00050000,
  53         .zq_config                      = 0x50074BE4,
  54         .temp_alert_config              = 0x0,
  55         .emif_ddr_phy_ctlr_1            = 0x0E004008,
  56         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
  57         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
  58         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
  59         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
  60         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
  61         .emif_rd_wr_exec_thresh         = 0x80000405,
  62         .emif_prio_class_serv_map       = 0x80000001,
  63         .emif_connect_id_serv_1_map     = 0x80000094,
  64         .emif_connect_id_serv_2_map     = 0x00000000,
  65         .emif_cos_config                = 0x000FFFFF
  66 };
  67
  68 const u32 ext_phy_ctrl_const_base_ddr3[] = {
  69         0x00000000,
  70         0x00000044,
  71         0x00000044,
  72         0x00000046,
  73         0x00000046,
  74         0x00000000,
  75         0x00000059,
  76         0x00000077,
  77         0x00000093,
  78         0x000000A8,
  79         0x00000000,
  80         0x00000019,
  81         0x00000037,
  82         0x00000053,
  83         0x00000068,
  84         0x00000000,
  85         0x0,
  86         0x0,
  87         0x40000000,
  88         0x08102040
  89 };
  90
  91 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  92 {
  93         *regs = ext_phy_ctrl_const_base_ddr3;
  94         *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
  95 }
  96
  97 const struct dpll_params *get_dpll_ddr_params(void)
  98 {
  99         return &dpll_ddr;
 100 }
 101
 102 const struct dpll_params *get_dpll_mpu_params(void)
 103 {
 104         return &dpll_mpu;
 105 }
 106
 107 const struct dpll_params *get_dpll_core_params(void)
 108 {
 109         return &dpll_core;
 110 }
 111
 112 const struct dpll_params *get_dpll_per_params(void)
 113 {
 114         return &dpll_per;
 115 }
 116
 117 static void enable_vtt_regulator(void)
 118 {
 119         u32 temp;
 120
 121         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 122         writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 123         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 124         temp = temp & ~(GPIO_OE_ENABLE(7));
 125         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 126 }
 127
 128 void sdram_init(void)
 129 {
 130         unsigned long ram_size;
 131
 132         enable_vtt_regulator();
 133         config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
 134         ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 135         if (ram_size == 0x80000000 ||
 136             ram_size == 0x40000000 ||
 137             ram_size == 0x20000000)
 138                 return;
 139
 140         ddr3_emif_regs.sdram_config = 0x638453B2;
 141         config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
 142         ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 143         if (ram_size == 0x08000000)
 144                 return;
 145
 146         hang();
 147 }
 148 #endif
 149
 150 /* setup board specific PMIC */
 151 int power_init_board(void)
 152 {
 153         struct pmic *p;
 154
 155         power_tps65218_init(I2C_PMIC);
 156         p = pmic_get("TPS65218_PMIC");
 157         if (p && !pmic_probe(p))
 158                 puts("PMIC:  TPS65218\n");
 159
 160         return 0;
 161 }
 162
 163 int board_init(void)
 164 {
 165         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 166         gpmc_init();
 167         set_i2c_pin_mux();
 168         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 169         i2c_probe(TPS65218_CHIP_PM);
 170
 171         return 0;
 172 }
 173
 174 #ifdef CONFIG_DRIVER_TI_CPSW
 175
 176 static void cpsw_control(int enabled)
 177 {
 178         return;
 179 }
 180
 181 static struct cpsw_slave_data cpsw_slaves[] = {
 182         {
 183                 .slave_reg_ofs  = 0x208,
 184                 .sliver_reg_ofs = 0xd80,
 185                 .phy_addr       = 0,
 186                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 187         },
 188         {
 189                 .slave_reg_ofs  = 0x308,
 190                 .sliver_reg_ofs = 0xdc0,
 191                 .phy_addr       = 1,
 192                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 193         },
 194 };
 195
 196 static struct cpsw_platform_data cpsw_data = {
 197         .mdio_base              = CPSW_MDIO_BASE,
 198         .cpsw_base              = CPSW_BASE,
 199         .mdio_div               = 0xff,
 200         .channels               = 8,
 201         .cpdma_reg_ofs          = 0x800,
 202         .slaves                 = 2,
 203         .slave_data             = cpsw_slaves,
 204         .ale_reg_ofs            = 0xd00,
 205         .ale_entries            = 1024,
 206         .host_port_reg_ofs      = 0x108,
 207         .hw_stats_reg_ofs       = 0x900,
 208         .bd_ram_ofs             = 0x2000,
 209         .mac_control            = (1 << 5),
 210         .control                = cpsw_control,
 211         .host_port_num          = 0,
 212         .version                = CPSW_CTRL_VERSION_2,
 213 };
 214
 215 #define GPIO_PHY1_RST           170
 216 #define GPIO_PHY2_RST           168
 217
 218 int board_phy_config(struct phy_device *phydev)
 219 {
 220         unsigned short val;
 221
 222         /* introduce tx clock delay */
 223         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 224         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 225         val |= 0x0100;
 226         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 227
 228         if (phydev->drv->config)
 229                 return phydev->drv->config(phydev);
 230
 231         return 0;
 232 }
 233
 234 static void board_phy_init(void)
 235 {
 236         set_mdio_pin_mux();
 237         writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
 238         writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
 239         writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
 240
 241         /* For revision A */
 242         writel(0x2000009, 0x44df2e6c);
 243         writel(0x38a, 0x44df2e70);
 244
 245         mdelay(10);
 246
 247         gpio_request(GPIO_PHY1_RST, "phy1_rst");
 248         gpio_request(GPIO_PHY2_RST, "phy2_rst");
 249         gpio_direction_output(GPIO_PHY1_RST, 0);
 250         gpio_direction_output(GPIO_PHY2_RST, 0);
 251         mdelay(2);
 252
 253         gpio_set_value(GPIO_PHY1_RST, 1);
 254         gpio_set_value(GPIO_PHY2_RST, 1);
 255         mdelay(2);
 256 }
 257
 258 int board_eth_init(bd_t *bis)
 259 {
 260         int rv;
 261
 262         set_rgmii_pin_mux();
 263         writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
 264         board_phy_init();
 265
 266         rv = cpsw_register(&cpsw_data);
 267         if (rv < 0)
 268                 printf("Error %d registering CPSW switch\n", rv);
 269
 270         return rv;
 271 }
 272 #endif