3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <common.h> /* core U-Boot definitions */
29 #include <ACEX1K.h> /* ACEX device family */
31 #if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
33 /* Define FPGA_DEBUG to get debug printf's */
34 /* #define FPGA_DEBUG */
37 #define PRINTF(fmt,args...) printf (fmt ,##args)
39 #define PRINTF(fmt,args...)
42 #undef CFG_FPGA_CHECK_BUSY
43 #define CFG_FPGA_PROG_FEEDBACK
45 /* Note: The assumption is that we cannot possibly run fast enough to
46 * overrun the device (the Slave Parallel mode can free run at 50MHz).
47 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
48 * the board config file to slow things down.
50 #ifndef CONFIG_FPGA_DELAY
51 #define CONFIG_FPGA_DELAY()
55 #define CFG_FPGA_WAIT 100
58 static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
59 static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
60 /* static int ACEX1K_ps_info( Altera_desc *desc ); */
61 static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset );
63 /* ------------------------------------------------------------------------- */
64 /* ACEX1K Generic Implementation */
65 int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
67 int ret_val = FPGA_FAIL;
69 switch (desc->iface) {
71 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
72 ret_val = ACEX1K_ps_load (desc, buf, bsize);
75 /* Add new interface types here */
78 printf ("%s: Unsupported interface type, %d\n",
79 __FUNCTION__, desc->iface);
85 int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
87 int ret_val = FPGA_FAIL;
89 switch (desc->iface) {
91 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
92 ret_val = ACEX1K_ps_dump (desc, buf, bsize);
95 /* Add new interface types here */
98 printf ("%s: Unsupported interface type, %d\n",
99 __FUNCTION__, desc->iface);
105 int ACEX1K_info( Altera_desc *desc )
111 int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset)
113 int ret_val = FPGA_FAIL; /* assume a failure */
115 if (desc->family != Altera_ACEX1K) {
116 printf ("%s: Unsupported family type, %d\n",
117 __FUNCTION__, desc->family);
120 switch (desc->iface) {
122 ret_val = ACEX1K_ps_reloc (desc, reloc_offset);
125 /* Add new interface types here */
128 printf ("%s: Unsupported interface type, %d\n",
129 __FUNCTION__, desc->iface);
136 /* ------------------------------------------------------------------------- */
137 /* ACEX1K Passive Serial Generic Implementation */
139 static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
141 int ret_val = FPGA_FAIL; /* assume the worst */
142 Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
145 PRINTF ("%s: start with interface functions @ 0x%p\n",
149 size_t bytecount = 0;
150 unsigned char *data = (unsigned char *) buf;
151 int cookie = desc->cookie; /* make a local copy */
152 unsigned long ts; /* timestamp */
154 PRINTF ("%s: Function Table:\n"
162 __FUNCTION__, &fn, fn, fn->config, fn->status,
163 fn->clk, fn->data, fn->done);
164 #ifdef CFG_FPGA_PROG_FEEDBACK
165 printf ("Loading FPGA Device %d (@ %ld)...\n", cookie, ts);
169 * Run the pre configuration function if there is one.
175 /* Establish the initial state */
176 (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
178 udelay(2); /* T_cfg > 2us */
180 /* nSTATUS should be asserted now */
181 (*fn->done) (cookie);
182 if ( !(*fn->status) (cookie) ) {
183 puts ("** nSTATUS is not asserted.\n");
184 (*fn->abort) (cookie);
188 (*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */
189 udelay(2); /* T_cf2st1 < 4us */
191 /* Wait for nSTATUS to be released (i.e. deasserted) */
192 ts = get_timer (0); /* get current time */
194 CONFIG_FPGA_DELAY ();
195 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
196 puts ("** Timeout waiting for STATUS to go high.\n");
197 (*fn->abort) (cookie);
200 (*fn->done) (cookie);
201 } while ((*fn->status) (cookie));
203 /* Get ready for the burn */
204 CONFIG_FPGA_DELAY ();
207 while (bytecount < bsize) {
209 #ifdef CFG_FPGA_CHECK_CTRLC
211 (*fn->abort) (cookie);
215 /* Altera detects an error if INIT goes low (active)
216 while DONE is low (inactive) */
217 #if 0 /* not yet implemented */
218 if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
219 puts ("** CRC error during FPGA load.\n");
220 (*fn->abort) (cookie);
224 val = data [bytecount ++ ];
227 /* Deassert the clock */
228 (*fn->clk) (FALSE, TRUE, cookie);
229 CONFIG_FPGA_DELAY ();
231 (*fn->data) ( (val & 0x01), TRUE, cookie);
232 CONFIG_FPGA_DELAY ();
233 /* Assert the clock */
234 (*fn->clk) (TRUE, TRUE, cookie);
235 CONFIG_FPGA_DELAY ();
240 #ifdef CFG_FPGA_PROG_FEEDBACK
241 if (bytecount % (bsize / 40) == 0)
242 putc ('.'); /* let them know we are alive */
246 CONFIG_FPGA_DELAY ();
248 #ifdef CFG_FPGA_PROG_FEEDBACK
249 putc ('\n'); /* terminate the dotted line */
253 * Checking FPGA's CONF_DONE signal - correctly booted ?
256 if ( ! (*fn->done) (cookie) ) {
257 puts ("** Booting failed! CONF_DONE is still deasserted.\n");
258 (*fn->abort) (cookie);
263 * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
266 for (i = 0; i < 12; i++) {
267 CONFIG_FPGA_DELAY ();
268 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
269 CONFIG_FPGA_DELAY ();
270 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
273 ret_val = FPGA_SUCCESS;
275 #ifdef CFG_FPGA_PROG_FEEDBACK
276 if (ret_val == FPGA_SUCCESS) {
283 (*fn->post) (cookie);
286 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
292 static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
294 /* Readback is only available through the Slave Parallel and */
295 /* boundary-scan interfaces. */
296 printf ("%s: Passive Serial Dumping is unavailable\n",
301 static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
303 int ret_val = FPGA_FAIL; /* assume the worst */
304 Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn =
305 (Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns);
310 /* Get the relocated table address */
311 addr = (ulong) fn + reloc_offset;
312 fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr;
314 if (!fn_r->relocated) {
316 if (memcmp (fn_r, fn,
317 sizeof (Altera_ACEX1K_Passive_Serial_fns))
319 /* good copy of the table, fix the descriptor pointer */
320 desc->iface_fns = fn_r;
322 PRINTF ("%s: Invalid function table at 0x%p\n",
327 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
330 addr = (ulong) (fn->pre) + reloc_offset;
331 fn_r->pre = (Altera_pre_fn) addr;
333 addr = (ulong) (fn->config) + reloc_offset;
334 fn_r->config = (Altera_config_fn) addr;
336 addr = (ulong) (fn->status) + reloc_offset;
337 fn_r->status = (Altera_status_fn) addr;
339 addr = (ulong) (fn->done) + reloc_offset;
340 fn_r->done = (Altera_done_fn) addr;
342 addr = (ulong) (fn->clk) + reloc_offset;
343 fn_r->clk = (Altera_clk_fn) addr;
345 addr = (ulong) (fn->data) + reloc_offset;
346 fn_r->data = (Altera_data_fn) addr;
348 addr = (ulong) (fn->abort) + reloc_offset;
349 fn_r->abort = (Altera_abort_fn) addr;
351 addr = (ulong) (fn->post) + reloc_offset;
352 fn_r->post = (Altera_post_fn) addr;
354 fn_r->relocated = TRUE;
357 /* this table has already been moved */
358 /* XXX - should check to see if the descriptor is correct */
359 desc->iface_fns = fn_r;
362 ret_val = FPGA_SUCCESS;
364 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
371 #endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */