2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2002-2006
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <environment.h>
21 #include <init_helpers.h>
28 #include <status_led.h>
33 #ifdef CONFIG_MACH_TYPE
34 #include <asm/mach-types.h>
36 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
40 #include <asm/sections.h>
42 #include <linux/errno.h>
45 * Pointer to initial global data area
47 * Here we initialize it if needed.
49 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
50 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
51 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
52 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
54 DECLARE_GLOBAL_DATA_PTR;
58 * TODO(sjg@chromium.org): IMO this code should be
59 * refactored to a single function, something like:
61 * void led_set_state(enum led_colour_t colour, int on);
63 /************************************************************************
64 * Coloured LED functionality
65 ************************************************************************
66 * May be supplied by boards if desired
68 __weak void coloured_LED_init(void) {}
69 __weak void red_led_on(void) {}
70 __weak void red_led_off(void) {}
71 __weak void green_led_on(void) {}
72 __weak void green_led_off(void) {}
73 __weak void yellow_led_on(void) {}
74 __weak void yellow_led_off(void) {}
75 __weak void blue_led_on(void) {}
76 __weak void blue_led_off(void) {}
79 * Why is gd allocated a register? Prior to reloc it might be better to
80 * just pass it around to each function in this file?
82 * After reloc one could argue that it is hardly used and doesn't need
83 * to be in a register. Or if it is it should perhaps hold pointers to all
84 * global data for all modules, so that post-reloc we can avoid the massive
85 * literal pool we get on ARM. Or perhaps just encourage each module to use
89 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
90 static int init_func_watchdog_init(void)
92 # if defined(CONFIG_HW_WATCHDOG) && \
93 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
94 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
95 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
96 defined(CONFIG_IMX_WATCHDOG))
98 puts(" Watchdog enabled\n");
105 int init_func_watchdog_reset(void)
111 #endif /* CONFIG_WATCHDOG */
113 __weak void board_add_ram_info(int use_default)
115 /* please define platform specific board_add_ram_info() */
118 static int init_baud_rate(void)
120 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
124 static int display_text_info(void)
126 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
127 ulong bss_start, bss_end, text_base;
129 bss_start = (ulong)&__bss_start;
130 bss_end = (ulong)&__bss_end;
132 #ifdef CONFIG_SYS_TEXT_BASE
133 text_base = CONFIG_SYS_TEXT_BASE;
135 text_base = CONFIG_SYS_MONITOR_BASE;
138 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
139 text_base, bss_start, bss_end);
145 static int announce_dram_init(void)
151 static int show_dram_config(void)
153 unsigned long long size;
155 #ifdef CONFIG_NR_DRAM_BANKS
158 debug("\nRAM Configuration:\n");
159 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
160 size += gd->bd->bi_dram[i].size;
161 debug("Bank #%d: %llx ", i,
162 (unsigned long long)(gd->bd->bi_dram[i].start));
164 print_size(gd->bd->bi_dram[i].size, "\n");
172 print_size(size, "");
173 board_add_ram_info(0);
179 __weak int dram_init_banksize(void)
181 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
182 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
183 gd->bd->bi_dram[0].size = get_effective_memsize();
189 #if defined(CONFIG_SYS_I2C)
190 static int init_func_i2c(void)
193 #ifdef CONFIG_SYS_I2C
196 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
203 #if defined(CONFIG_VID)
204 __weak int init_func_vid(void)
210 #if defined(CONFIG_HARD_SPI)
211 static int init_func_spi(void)
220 static int setup_mon_len(void)
222 #if defined(__ARM__) || defined(__MICROBLAZE__)
223 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
224 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
225 gd->mon_len = (ulong)&_end - (ulong)_init;
226 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
227 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
228 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
229 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
230 #elif defined(CONFIG_SYS_MONITOR_BASE)
231 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
232 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
237 __weak int arch_cpu_init(void)
242 __weak int mach_cpu_init(void)
247 /* Get the top of usable RAM */
248 __weak ulong board_get_usable_ram_top(ulong total_size)
250 #ifdef CONFIG_SYS_SDRAM_BASE
252 * Detect whether we have so much RAM that it goes past the end of our
253 * 32-bit address space. If so, clip the usable RAM so it doesn't.
255 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
257 * Will wrap back to top of 32-bit space when reservations
265 static int setup_dest_addr(void)
267 debug("Monitor len: %08lX\n", gd->mon_len);
269 * Ram is setup, size stored in gd !!
271 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
272 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
274 * Subtract specified amount of memory to hide so that it won't
275 * get "touched" at all by U-Boot. By fixing up gd->ram_size
276 * the Linux kernel should now get passed the now "corrected"
277 * memory size and won't touch it either. This should work
278 * for arch/ppc and arch/powerpc. Only Linux board ports in
279 * arch/powerpc with bootwrapper support, that recalculate the
280 * memory size from the SDRAM controller setup will have to
283 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
285 #ifdef CONFIG_SYS_SDRAM_BASE
286 gd->ram_top = CONFIG_SYS_SDRAM_BASE;
288 gd->ram_top += get_effective_memsize();
289 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
290 gd->relocaddr = gd->ram_top;
291 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
292 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
294 * We need to make sure the location we intend to put secondary core
295 * boot code is reserved and not used by any part of u-boot
297 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
298 gd->relocaddr = determine_mp_bootpg(NULL);
299 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
306 /* reserve protected RAM */
307 static int reserve_pram(void)
311 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
312 gd->relocaddr -= (reg << 10); /* size is in kB */
313 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
317 #endif /* CONFIG_PRAM */
319 /* Round memory pointer down to next 4 kB limit */
320 static int reserve_round_4k(void)
322 gd->relocaddr &= ~(4096 - 1);
327 __weak int reserve_mmu(void)
329 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
330 /* reserve TLB table */
331 gd->arch.tlb_size = PGTABLE_SIZE;
332 gd->relocaddr -= gd->arch.tlb_size;
334 /* round down to next 64 kB limit */
335 gd->relocaddr &= ~(0x10000 - 1);
337 gd->arch.tlb_addr = gd->relocaddr;
338 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
339 gd->arch.tlb_addr + gd->arch.tlb_size);
341 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
343 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
344 * with location within secure ram.
346 gd->arch.tlb_allocated = gd->arch.tlb_addr;
354 static int reserve_video(void)
356 #ifdef CONFIG_DM_VIDEO
360 addr = gd->relocaddr;
361 ret = video_reserve(&addr);
364 gd->relocaddr = addr;
365 #elif defined(CONFIG_LCD)
366 # ifdef CONFIG_FB_ADDR
367 gd->fb_base = CONFIG_FB_ADDR;
369 /* reserve memory for LCD display (always full pages) */
370 gd->relocaddr = lcd_setmem(gd->relocaddr);
371 gd->fb_base = gd->relocaddr;
372 # endif /* CONFIG_FB_ADDR */
373 #elif defined(CONFIG_VIDEO) && \
374 (!defined(CONFIG_PPC)) && \
375 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
376 !defined(CONFIG_M68K)
377 /* reserve memory for video display (always full pages) */
378 gd->relocaddr = video_setmem(gd->relocaddr);
379 gd->fb_base = gd->relocaddr;
385 static int reserve_trace(void)
388 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
389 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
390 debug("Reserving %dk for trace data at: %08lx\n",
391 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
397 static int reserve_uboot(void)
400 * reserve memory for U-Boot code, data & bss
401 * round down to next 4 kB limit
403 gd->relocaddr -= gd->mon_len;
404 gd->relocaddr &= ~(4096 - 1);
405 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
406 /* round down to next 64 kB limit so that IVPR stays aligned */
407 gd->relocaddr &= ~(65536 - 1);
410 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
413 gd->start_addr_sp = gd->relocaddr;
418 /* reserve memory for malloc() area */
419 static int reserve_malloc(void)
421 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
422 debug("Reserving %dk for malloc() at: %08lx\n",
423 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
427 /* (permanently) allocate a Board Info struct */
428 static int reserve_board(void)
431 gd->start_addr_sp -= sizeof(bd_t);
432 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
433 memset(gd->bd, '\0', sizeof(bd_t));
434 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
435 sizeof(bd_t), gd->start_addr_sp);
440 static int setup_machine(void)
442 #ifdef CONFIG_MACH_TYPE
443 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
448 static int reserve_global_data(void)
450 gd->start_addr_sp -= sizeof(gd_t);
451 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
452 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
453 sizeof(gd_t), gd->start_addr_sp);
457 static int reserve_fdt(void)
459 #ifndef CONFIG_OF_EMBED
461 * If the device tree is sitting immediately above our image then we
462 * must relocate it. If it is embedded in the data section, then it
463 * will be relocated with other data.
466 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
468 gd->start_addr_sp -= gd->fdt_size;
469 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
470 debug("Reserving %lu Bytes for FDT at: %08lx\n",
471 gd->fdt_size, gd->start_addr_sp);
478 static int reserve_bootstage(void)
480 #ifdef CONFIG_BOOTSTAGE
481 int size = bootstage_get_size();
483 gd->start_addr_sp -= size;
484 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
485 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
492 int arch_reserve_stacks(void)
497 static int reserve_stacks(void)
499 /* make stack pointer 16-byte aligned */
500 gd->start_addr_sp -= 16;
501 gd->start_addr_sp &= ~0xf;
504 * let the architecture-specific code tailor gd->start_addr_sp and
507 return arch_reserve_stacks();
510 static int display_new_sp(void)
512 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
517 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
519 static int setup_board_part1(void)
524 * Save local variables to board info struct
526 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
527 bd->bi_memsize = gd->ram_size; /* size in bytes */
529 #ifdef CONFIG_SYS_SRAM_BASE
530 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
531 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
534 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
535 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
537 #if defined(CONFIG_M68K)
538 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
540 #if defined(CONFIG_MPC83xx)
541 bd->bi_immrbar = CONFIG_SYS_IMMR;
548 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
549 static int setup_board_part2(void)
553 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
554 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
555 #if defined(CONFIG_CPM2)
556 bd->bi_cpmfreq = gd->arch.cpm_clk;
557 bd->bi_brgfreq = gd->arch.brg_clk;
558 bd->bi_sccfreq = gd->arch.scc_clk;
559 bd->bi_vco = gd->arch.vco_out;
560 #endif /* CONFIG_CPM2 */
561 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
562 bd->bi_pcifreq = gd->pci_clk;
564 #if defined(CONFIG_EXTRA_CLOCK)
565 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
566 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
567 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
575 static int init_post(void)
577 post_bootmode_init();
578 post_run(NULL, POST_ROM | post_bootmode_get(0));
584 static int reloc_fdt(void)
586 #ifndef CONFIG_OF_EMBED
587 if (gd->flags & GD_FLG_SKIP_RELOC)
590 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
591 gd->fdt_blob = gd->new_fdt;
598 static int reloc_bootstage(void)
600 #ifdef CONFIG_BOOTSTAGE
601 if (gd->flags & GD_FLG_SKIP_RELOC)
603 if (gd->new_bootstage) {
604 int size = bootstage_get_size();
606 debug("Copying bootstage from %p to %p, size %x\n",
607 gd->bootstage, gd->new_bootstage, size);
608 memcpy(gd->new_bootstage, gd->bootstage, size);
609 gd->bootstage = gd->new_bootstage;
616 static int setup_reloc(void)
618 if (gd->flags & GD_FLG_SKIP_RELOC) {
619 debug("Skipping relocation due to flag\n");
623 #ifdef CONFIG_SYS_TEXT_BASE
625 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
626 #elif defined(CONFIG_M68K)
628 * On all ColdFire arch cpu, monitor code starts always
629 * just after the default vector table location, so at 0x400
631 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
633 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
636 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
638 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
639 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
640 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
646 #ifdef CONFIG_OF_BOARD_FIXUP
647 static int fix_fdt(void)
649 return board_fix_fdt((void *)gd->fdt_blob);
653 /* ARM calls relocate_code from its crt0.S */
654 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
655 !CONFIG_IS_ENABLED(X86_64)
657 static int jump_to_copy(void)
659 if (gd->flags & GD_FLG_SKIP_RELOC)
662 * x86 is special, but in a nice way. It uses a trampoline which
663 * enables the dcache if possible.
665 * For now, other archs use relocate_code(), which is implemented
666 * similarly for all archs. When we do generic relocation, hopefully
667 * we can make all archs enable the dcache prior to relocation.
669 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
671 * SDRAM and console are now initialised. The final stack can now
672 * be setup in SDRAM. Code execution will continue in Flash, but
673 * with the stack in SDRAM and Global Data in temporary memory
676 arch_setup_gd(gd->new_gd);
677 board_init_f_r_trampoline(gd->start_addr_sp);
679 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
686 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
687 static int initf_bootstage(void)
689 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
690 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
693 ret = bootstage_init(!from_spl);
697 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
698 CONFIG_BOOTSTAGE_STASH_SIZE);
700 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
701 if (ret && ret != -ENOENT) {
702 debug("Failed to unstash bootstage: err=%d\n", ret);
707 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
712 static int initf_console_record(void)
714 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
715 return console_record_init();
721 static int initf_dm(void)
723 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
726 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
727 ret = dm_init_and_scan(true);
728 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
732 #ifdef CONFIG_TIMER_EARLY
733 ret = dm_timer_init();
741 /* Architecture-specific memory reservation */
742 __weak int reserve_arch(void)
747 __weak int arch_cpu_init_dm(void)
752 static const init_fnc_t init_sequence_f[] = {
754 #ifdef CONFIG_OF_CONTROL
762 initf_bootstage, /* uses its own timer, so does not need DM */
763 initf_console_record,
764 #if defined(CONFIG_HAVE_FSP)
767 arch_cpu_init, /* basic arch cpu dependent setup */
768 mach_cpu_init, /* SoC/machine dependent CPU setup */
771 #if defined(CONFIG_BOARD_EARLY_INIT_F)
774 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
775 /* get CPU and bus clocks according to the environment variable */
776 get_clocks, /* get CPU and bus clocks (etc.) */
778 #if !defined(CONFIG_M68K)
779 timer_init, /* initialize timer */
781 #if defined(CONFIG_BOARD_POSTCLK_INIT)
784 env_init, /* initialize environment */
785 init_baud_rate, /* initialze baudrate settings */
786 serial_init, /* serial communications setup */
787 console_init_f, /* stage 1 init of console */
788 display_options, /* say that we are here */
789 display_text_info, /* show debugging info if required */
790 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
793 #if defined(CONFIG_DISPLAY_CPUINFO)
794 print_cpuinfo, /* display cpu info (and speed) */
796 #if defined(CONFIG_DTB_RESELECT)
799 #if defined(CONFIG_DISPLAY_BOARDINFO)
802 INIT_FUNC_WATCHDOG_INIT
803 #if defined(CONFIG_MISC_INIT_F)
806 INIT_FUNC_WATCHDOG_RESET
807 #if defined(CONFIG_SYS_I2C)
810 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
813 #if defined(CONFIG_HARD_SPI)
817 dram_init, /* configure available RAM banks */
821 INIT_FUNC_WATCHDOG_RESET
822 #if defined(CONFIG_SYS_DRAM_TEST)
824 #endif /* CONFIG_SYS_DRAM_TEST */
825 INIT_FUNC_WATCHDOG_RESET
830 INIT_FUNC_WATCHDOG_RESET
832 * Now that we have DRAM mapped and working, we can
833 * relocate the code and continue running from DRAM.
835 * Reserve memory at end of RAM for (top down in that order):
836 * - area that won't get touched by U-Boot and Linux (optional)
837 * - kernel log buffer
841 * - board info struct
864 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
868 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
869 INIT_FUNC_WATCHDOG_RESET
873 #ifdef CONFIG_OF_BOARD_FIXUP
876 INIT_FUNC_WATCHDOG_RESET
880 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
885 #if defined(CONFIG_XTENSA)
888 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
889 !CONFIG_IS_ENABLED(X86_64)
895 void board_init_f(ulong boot_flags)
897 gd->flags = boot_flags;
898 gd->have_console = 0;
900 if (initcall_run_list(init_sequence_f))
903 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
904 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64)
905 /* NOTREACHED - jump_to_copy() does not return */
910 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
912 * For now this code is only used on x86.
914 * init_sequence_f_r is the list of init functions which are run when
915 * U-Boot is executing from Flash with a semi-limited 'C' environment.
916 * The following limitations must be considered when implementing an
918 * - 'static' variables are read-only
919 * - Global Data (gd->xxx) is read/write
921 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
922 * supported). It _should_, if possible, copy global data to RAM and
923 * initialise the CPU caches (to speed up the relocation process)
925 * NOTE: At present only x86 uses this route, but it is intended that
926 * all archs will move to this when generic relocation is implemented.
928 static const init_fnc_t init_sequence_f_r[] = {
929 #if !CONFIG_IS_ENABLED(X86_64)
936 void board_init_f_r(void)
938 if (initcall_run_list(init_sequence_f_r))
942 * The pre-relocation drivers may be using memory that has now gone
943 * away. Mark serial as unavailable - this will fall back to the debug
946 * Do the same with log drivers since the memory may not be available.
948 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
954 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
955 * Transfer execution from Flash to RAM by calculating the address
956 * of the in-RAM copy of board_init_r() and calling it
958 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
960 /* NOTREACHED - board_init_r() does not return */
963 #endif /* CONFIG_X86 */