3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #if (CONFIG_COMMANDS & CFG_CMD_MII)
34 #ifdef CONFIG_TERSE_MII
36 * Display values from last command.
47 * mii read {addr} {reg}
48 * mii write {addr} {reg} {data}
51 int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
54 unsigned char addr, reg;
58 #if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
63 * We use the last specified parameters, unless new ones are
71 if ((flag & CMD_FLAG_REPEAT) == 0) {
74 addr = simple_strtoul (argv[2], NULL, 16);
76 reg = simple_strtoul (argv[3], NULL, 16);
78 data = simple_strtoul (argv[4], NULL, 16);
82 * check info/read/write.
85 unsigned char j, start, end;
91 * Look for any and all PHYs. Valid addresses are 0..31.
94 start = addr; end = addr + 1;
99 for (j = start; j < end; j++) {
100 if (miiphy_info (j, &oui, &model, &rev) == 0) {
101 printf ("PHY 0x%02X: "
108 miiphy_duplex (j) == FULL ? "FDX" : "HDX");
111 } else if (op == 'r') {
112 if (miiphy_read (addr, reg, &data) != 0) {
113 puts ("Error reading from the PHY\n");
116 printf ("%04X\n", data & 0x0000FFFF);
117 } else if (op == 'w') {
118 if (miiphy_write (addr, reg, data) != 0) {
119 puts ("Error writing to the PHY\n");
123 printf ("Usage:\n%s\n", cmdtp->usage);
128 * Save the parameters for repeats.
138 /***************************************************/
142 "mii - MII utility commands\n",
143 "info <addr> - display MII PHY info\n"
144 "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
145 "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
148 #else /* ! CONFIG_TERSE_MII ================================================= */
150 typedef struct _MII_reg_desc_t {
155 MII_reg_desc_t reg_0_5_desc_tbl[] = {
156 { 0, "PHY control register" },
157 { 1, "PHY status register" },
158 { 2, "PHY ID 1 register" },
159 { 3, "PHY ID 2 register" },
160 { 4, "Autonegotiation advertisement register" },
161 { 5, "Autonegotiation partner abilities register" },
164 typedef struct _MII_field_desc_t {
171 MII_field_desc_t reg_0_desc_tbl[] = {
172 { 15, 15, 0x01, "reset" },
173 { 14, 14, 0x01, "loopback" },
174 { 13, 6, 0x81, "speed selection" }, /* special */
175 { 12, 12, 0x01, "A/N enable" },
176 { 11, 11, 0x01, "power-down" },
177 { 10, 10, 0x01, "isolate" },
178 { 9, 9, 0x01, "restart A/N" },
179 { 8, 8, 0x01, "duplex" }, /* special */
180 { 7, 7, 0x01, "collision test enable" },
181 { 5, 0, 0x3f, "(reserved)" }
184 MII_field_desc_t reg_1_desc_tbl[] = {
185 { 15, 15, 0x01, "100BASE-T4 able" },
186 { 14, 14, 0x01, "100BASE-X full duplex able" },
187 { 13, 13, 0x01, "100BASE-X half duplex able" },
188 { 12, 12, 0x01, "10 Mbps full duplex able" },
189 { 11, 11, 0x01, "10 Mbps half duplex able" },
190 { 10, 10, 0x01, "100BASE-T2 full duplex able" },
191 { 9, 9, 0x01, "100BASE-T2 half duplex able" },
192 { 8, 8, 0x01, "extended status" },
193 { 7, 7, 0x01, "(reserved)" },
194 { 6, 6, 0x01, "MF preamble suppression" },
195 { 5, 5, 0x01, "A/N complete" },
196 { 4, 4, 0x01, "remote fault" },
197 { 3, 3, 0x01, "A/N able" },
198 { 2, 2, 0x01, "link status" },
199 { 1, 1, 0x01, "jabber detect" },
200 { 0, 0, 0x01, "extended capabilities" },
203 MII_field_desc_t reg_2_desc_tbl[] = {
204 { 15, 0, 0xffff, "OUI portion" },
207 MII_field_desc_t reg_3_desc_tbl[] = {
208 { 15, 10, 0x3f, "OUI portion" },
209 { 9, 4, 0x3f, "manufacturer part number" },
210 { 3, 0, 0x0f, "manufacturer rev. number" },
213 MII_field_desc_t reg_4_desc_tbl[] = {
214 { 15, 15, 0x01, "next page able" },
215 { 14, 14, 0x01, "reserved" },
216 { 13, 13, 0x01, "remote fault" },
217 { 12, 12, 0x01, "reserved" },
218 { 11, 11, 0x01, "asymmetric pause" },
219 { 10, 10, 0x01, "pause enable" },
220 { 9, 9, 0x01, "100BASE-T4 able" },
221 { 8, 8, 0x01, "100BASE-TX full duplex able" },
222 { 7, 7, 0x01, "100BASE-TX able" },
223 { 6, 6, 0x01, "10BASE-T full duplex able" },
224 { 5, 5, 0x01, "10BASE-T able" },
225 { 4, 0, 0x1f, "xxx to do" },
228 MII_field_desc_t reg_5_desc_tbl[] = {
229 { 15, 15, 0x01, "next page able" },
230 { 14, 14, 0x01, "acknowledge" },
231 { 13, 13, 0x01, "remote fault" },
232 { 12, 12, 0x01, "(reserved)" },
233 { 11, 11, 0x01, "asymmetric pause able" },
234 { 10, 10, 0x01, "pause able" },
235 { 9, 9, 0x01, "100BASE-T4 able" },
236 { 8, 8, 0x01, "100BASE-X full duplex able" },
237 { 7, 7, 0x01, "100BASE-TX able" },
238 { 6, 6, 0x01, "10BASE-T full duplex able" },
239 { 5, 5, 0x01, "10BASE-T able" },
240 { 4, 0, 0x1f, "xxx to do" },
243 #define DESC0LEN (sizeof(reg_0_desc_tbl)/sizeof(reg_0_desc_tbl[0]))
244 #define DESC1LEN (sizeof(reg_1_desc_tbl)/sizeof(reg_1_desc_tbl[0]))
245 #define DESC2LEN (sizeof(reg_2_desc_tbl)/sizeof(reg_2_desc_tbl[0]))
246 #define DESC3LEN (sizeof(reg_3_desc_tbl)/sizeof(reg_3_desc_tbl[0]))
247 #define DESC4LEN (sizeof(reg_4_desc_tbl)/sizeof(reg_4_desc_tbl[0]))
248 #define DESC5LEN (sizeof(reg_5_desc_tbl)/sizeof(reg_5_desc_tbl[0]))
250 typedef struct _MII_field_desc_and_len_t {
251 MII_field_desc_t * pdesc;
253 } MII_field_desc_and_len_t;
255 MII_field_desc_and_len_t desc_and_len_tbl[] = {
256 { reg_0_desc_tbl, DESC0LEN },
257 { reg_1_desc_tbl, DESC1LEN },
258 { reg_2_desc_tbl, DESC2LEN },
259 { reg_3_desc_tbl, DESC3LEN },
260 { reg_4_desc_tbl, DESC4LEN },
261 { reg_5_desc_tbl, DESC5LEN },
264 static void dump_reg(
266 MII_reg_desc_t * prd,
267 MII_field_desc_and_len_t * pdl);
269 static int special_field(
271 MII_field_desc_t * pdesc,
274 void MII_dump_0_to_5(
281 for (i = 0; i < 6; i++) {
282 if ((reglo <= i) && (i <= reghi))
283 dump_reg(regvals[i], ®_0_5_desc_tbl[i],
284 &desc_and_len_tbl[i]);
288 static void dump_reg(
290 MII_reg_desc_t * prd,
291 MII_field_desc_and_len_t * pdl)
294 ushort mask_in_place;
295 MII_field_desc_t * pdesc;
297 printf("%u. (%04hx) -- %s --\n",
298 prd->regno, regval, prd->name);
300 for (i = 0; i < pdl->len; i++) {
301 pdesc = &pdl->pdesc[i];
303 mask_in_place = pdesc->mask << pdesc->lo;
305 printf(" (%04hx:%04hx) %u.",
307 regval & mask_in_place,
310 if (special_field(prd->regno, pdesc, regval)) {
313 if (pdesc->hi == pdesc->lo)
314 printf("%2u ", pdesc->lo);
316 printf("%2u-%2u", pdesc->hi, pdesc->lo);
318 (regval & mask_in_place) >> pdesc->lo,
336 static int special_field(
338 MII_field_desc_t * pdesc,
341 if ((regno == 0) && (pdesc->lo == 6)) {
342 ushort speed_bits = regval & PHY_BMCR_SPEED_MASK;
343 printf("%2u,%2u = b%u%u speed selection = %s Mbps",
347 speed_bits == PHY_BMCR_1000_MBPS ? "1000" :
348 speed_bits == PHY_BMCR_100_MBPS ? "100" :
349 speed_bits == PHY_BMCR_10_MBPS ? "10" :
354 else if ((regno == 0) && (pdesc->lo == 8)) {
355 printf("%2u = %5u duplex = %s",
357 (regval >> pdesc->lo) & 1,
358 ((regval >> pdesc->lo) & 1) ? "full" : "half");
362 else if ((regno == 4) && (pdesc->lo == 0)) {
363 ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
364 printf("%2u-%2u = %5u selector = %s",
365 pdesc->hi, pdesc->lo, sel_bits,
366 sel_bits == PHY_ANLPAR_PSB_802_3 ?
368 sel_bits == PHY_ANLPAR_PSB_802_9 ?
369 "IEEE 802.9 ISLAN-16T" :
374 else if ((regno == 5) && (pdesc->lo == 0)) {
375 ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
376 printf("%2u-%2u = %u selector = %s",
377 pdesc->hi, pdesc->lo, sel_bits,
378 sel_bits == PHY_ANLPAR_PSB_802_3 ?
380 sel_bits == PHY_ANLPAR_PSB_802_9 ?
381 "IEEE 802.9 ISLAN-16T" :
396 static void extract_range(
402 *plo = simple_strtoul(input, &end, 16);
405 *phi = simple_strtoul(end, NULL, 16);
412 /* ---------------------------------------------------------------- */
413 int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
416 unsigned char addrlo, addrhi, reglo, reghi;
417 unsigned char addr, reg;
426 * We use the last specified parameters, unless new ones are
430 addrlo = last_addr_lo;
431 addrhi = last_addr_hi;
436 if ((flag & CMD_FLAG_REPEAT) == 0) {
439 extract_range(argv[2], &addrlo, &addrhi);
441 extract_range(argv[3], ®lo, ®hi);
443 data = simple_strtoul (argv[4], NULL, 16);
447 * check info/read/write.
450 unsigned char j, start, end;
456 * Look for any and all PHYs. Valid addresses are 0..31.
459 start = addrlo; end = addrhi;
464 for (j = start; j <= end; j++) {
465 if (miiphy_info (j, &oui, &model, &rev) == 0) {
466 printf("PHY 0x%02X: "
473 miiphy_duplex (j) == FULL ? "FDX" : "HDX");
476 } else if (op == 'r') {
477 for (addr = addrlo; addr <= addrhi; addr++) {
478 for (reg = reglo; reg <= reghi; reg++) {
480 if (miiphy_read (addr, reg, &data) != 0) {
482 "Error reading from the PHY addr=%02x reg=%02x\n",
486 if ((addrlo != addrhi) || (reglo != reghi))
487 printf("addr=%02x reg=%02x data=",
488 (uint)addr, (uint)reg);
489 printf("%04X\n", data & 0x0000FFFF);
492 if ((addrlo != addrhi) && (reglo != reghi))
495 } else if (op == 'w') {
496 for (addr = addrlo; addr <= addrhi; addr++) {
497 for (reg = reglo; reg <= reghi; reg++) {
498 if (miiphy_write (addr, reg, data) != 0) {
499 printf("Error writing to the PHY addr=%02x reg=%02x\n",
505 } else if (op == 'd') {
508 if ((reglo > 5) || (reghi > 5)) {
510 "The MII dump command only formats the "
511 "standard MII registers, 0-5.\n");
514 for (addr = addrlo; addr <= addrhi; addr++) {
515 for (reg = 0; reg < 6; reg++) {
516 if (miiphy_read(addr, reg, ®s[reg]) != 0) {
519 "Error reading from the PHY addr=%02x reg=%02x\n",
525 MII_dump_0_to_5(regs, reglo, reghi);
529 printf("Usage:\n%s\n", cmdtp->usage);
534 * Save the parameters for repeats.
537 last_addr_lo = addrlo;
538 last_addr_hi = addrhi;
546 /***************************************************/
550 "mii - MII utility commands\n",
551 "info <addr> - display MII PHY info\n"
552 "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
553 "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
554 "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
555 "Addr and/or reg may be ranges, e.g. 2-7.\n"
558 #endif /* CONFIG_TERSE_MII */
560 #endif /* CFG_CMD_MII */