3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 typedef struct _MII_reg_desc_t {
37 MII_reg_desc_t reg_0_5_desc_tbl[] = {
38 { 0, "PHY control register" },
39 { 1, "PHY status register" },
40 { 2, "PHY ID 1 register" },
41 { 3, "PHY ID 2 register" },
42 { 4, "Autonegotiation advertisement register" },
43 { 5, "Autonegotiation partner abilities register" },
46 typedef struct _MII_field_desc_t {
53 MII_field_desc_t reg_0_desc_tbl[] = {
54 { 15, 15, 0x01, "reset" },
55 { 14, 14, 0x01, "loopback" },
56 { 13, 6, 0x81, "speed selection" }, /* special */
57 { 12, 12, 0x01, "A/N enable" },
58 { 11, 11, 0x01, "power-down" },
59 { 10, 10, 0x01, "isolate" },
60 { 9, 9, 0x01, "restart A/N" },
61 { 8, 8, 0x01, "duplex" }, /* special */
62 { 7, 7, 0x01, "collision test enable" },
63 { 5, 0, 0x3f, "(reserved)" }
66 MII_field_desc_t reg_1_desc_tbl[] = {
67 { 15, 15, 0x01, "100BASE-T4 able" },
68 { 14, 14, 0x01, "100BASE-X full duplex able" },
69 { 13, 13, 0x01, "100BASE-X half duplex able" },
70 { 12, 12, 0x01, "10 Mbps full duplex able" },
71 { 11, 11, 0x01, "10 Mbps half duplex able" },
72 { 10, 10, 0x01, "100BASE-T2 full duplex able" },
73 { 9, 9, 0x01, "100BASE-T2 half duplex able" },
74 { 8, 8, 0x01, "extended status" },
75 { 7, 7, 0x01, "(reserved)" },
76 { 6, 6, 0x01, "MF preamble suppression" },
77 { 5, 5, 0x01, "A/N complete" },
78 { 4, 4, 0x01, "remote fault" },
79 { 3, 3, 0x01, "A/N able" },
80 { 2, 2, 0x01, "link status" },
81 { 1, 1, 0x01, "jabber detect" },
82 { 0, 0, 0x01, "extended capabilities" },
85 MII_field_desc_t reg_2_desc_tbl[] = {
86 { 15, 0, 0xffff, "OUI portion" },
89 MII_field_desc_t reg_3_desc_tbl[] = {
90 { 15, 10, 0x3f, "OUI portion" },
91 { 9, 4, 0x3f, "manufacturer part number" },
92 { 3, 0, 0x0f, "manufacturer rev. number" },
95 MII_field_desc_t reg_4_desc_tbl[] = {
96 { 15, 15, 0x01, "next page able" },
97 { 14, 14, 0x01, "reserved" },
98 { 13, 13, 0x01, "remote fault" },
99 { 12, 12, 0x01, "reserved" },
100 { 11, 11, 0x01, "asymmetric pause" },
101 { 10, 10, 0x01, "pause enable" },
102 { 9, 9, 0x01, "100BASE-T4 able" },
103 { 8, 8, 0x01, "100BASE-TX full duplex able" },
104 { 7, 7, 0x01, "100BASE-TX able" },
105 { 6, 6, 0x01, "10BASE-T full duplex able" },
106 { 5, 5, 0x01, "10BASE-T able" },
107 { 4, 0, 0x1f, "xxx to do" },
110 MII_field_desc_t reg_5_desc_tbl[] = {
111 { 15, 15, 0x01, "next page able" },
112 { 14, 14, 0x01, "acknowledge" },
113 { 13, 13, 0x01, "remote fault" },
114 { 12, 12, 0x01, "(reserved)" },
115 { 11, 11, 0x01, "asymmetric pause able" },
116 { 10, 10, 0x01, "pause able" },
117 { 9, 9, 0x01, "100BASE-T4 able" },
118 { 8, 8, 0x01, "100BASE-X full duplex able" },
119 { 7, 7, 0x01, "100BASE-TX able" },
120 { 6, 6, 0x01, "10BASE-T full duplex able" },
121 { 5, 5, 0x01, "10BASE-T able" },
122 { 4, 0, 0x1f, "xxx to do" },
125 #define DESC0LEN (sizeof(reg_0_desc_tbl)/sizeof(reg_0_desc_tbl[0]))
126 #define DESC1LEN (sizeof(reg_1_desc_tbl)/sizeof(reg_1_desc_tbl[0]))
127 #define DESC2LEN (sizeof(reg_2_desc_tbl)/sizeof(reg_2_desc_tbl[0]))
128 #define DESC3LEN (sizeof(reg_3_desc_tbl)/sizeof(reg_3_desc_tbl[0]))
129 #define DESC4LEN (sizeof(reg_4_desc_tbl)/sizeof(reg_4_desc_tbl[0]))
130 #define DESC5LEN (sizeof(reg_5_desc_tbl)/sizeof(reg_5_desc_tbl[0]))
132 typedef struct _MII_field_desc_and_len_t {
133 MII_field_desc_t * pdesc;
135 } MII_field_desc_and_len_t;
137 MII_field_desc_and_len_t desc_and_len_tbl[] = {
138 { reg_0_desc_tbl, DESC0LEN },
139 { reg_1_desc_tbl, DESC1LEN },
140 { reg_2_desc_tbl, DESC2LEN },
141 { reg_3_desc_tbl, DESC3LEN },
142 { reg_4_desc_tbl, DESC4LEN },
143 { reg_5_desc_tbl, DESC5LEN },
146 static void dump_reg(
148 MII_reg_desc_t * prd,
149 MII_field_desc_and_len_t * pdl);
151 static int special_field(
153 MII_field_desc_t * pdesc,
156 void MII_dump_0_to_5(
163 for (i = 0; i < 6; i++) {
164 if ((reglo <= i) && (i <= reghi))
165 dump_reg(regvals[i], ®_0_5_desc_tbl[i],
166 &desc_and_len_tbl[i]);
170 static void dump_reg(
172 MII_reg_desc_t * prd,
173 MII_field_desc_and_len_t * pdl)
176 ushort mask_in_place;
177 MII_field_desc_t * pdesc;
179 printf("%u. (%04hx) -- %s --\n",
180 prd->regno, regval, prd->name);
182 for (i = 0; i < pdl->len; i++) {
183 pdesc = &pdl->pdesc[i];
185 mask_in_place = pdesc->mask << pdesc->lo;
187 printf(" (%04hx:%04hx) %u.",
189 regval & mask_in_place,
192 if (special_field(prd->regno, pdesc, regval)) {
195 if (pdesc->hi == pdesc->lo)
196 printf("%2u ", pdesc->lo);
198 printf("%2u-%2u", pdesc->hi, pdesc->lo);
200 (regval & mask_in_place) >> pdesc->lo,
218 static int special_field(
220 MII_field_desc_t * pdesc,
223 if ((regno == 0) && (pdesc->lo == 6)) {
224 ushort speed_bits = regval & PHY_BMCR_SPEED_MASK;
225 printf("%2u,%2u = b%u%u speed selection = %s Mbps",
229 speed_bits == PHY_BMCR_1000_MBPS ? "1000" :
230 speed_bits == PHY_BMCR_100_MBPS ? "100" :
231 speed_bits == PHY_BMCR_10_MBPS ? "10" :
236 else if ((regno == 0) && (pdesc->lo == 8)) {
237 printf("%2u = %5u duplex = %s",
239 (regval >> pdesc->lo) & 1,
240 ((regval >> pdesc->lo) & 1) ? "full" : "half");
244 else if ((regno == 4) && (pdesc->lo == 0)) {
245 ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
246 printf("%2u-%2u = %5u selector = %s",
247 pdesc->hi, pdesc->lo, sel_bits,
248 sel_bits == PHY_ANLPAR_PSB_802_3 ?
250 sel_bits == PHY_ANLPAR_PSB_802_9 ?
251 "IEEE 802.9 ISLAN-16T" :
256 else if ((regno == 5) && (pdesc->lo == 0)) {
257 ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
258 printf("%2u-%2u = %u selector = %s",
259 pdesc->hi, pdesc->lo, sel_bits,
260 sel_bits == PHY_ANLPAR_PSB_802_3 ?
262 sel_bits == PHY_ANLPAR_PSB_802_9 ?
263 "IEEE 802.9 ISLAN-16T" :
278 static void extract_range(
284 *plo = simple_strtoul(input, &end, 16);
287 *phi = simple_strtoul(end, NULL, 16);
294 /* ---------------------------------------------------------------- */
295 int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
298 unsigned char addrlo, addrhi, reglo, reghi;
299 unsigned char addr, reg;
305 return cmd_usage(cmdtp);
307 #if defined(CONFIG_MII_INIT)
312 * We use the last specified parameters, unless new ones are
317 addrlo = last_addr_lo;
318 addrhi = last_addr_hi;
323 if ((flag & CMD_FLAG_REPEAT) == 0) {
325 if (strlen(argv[1]) > 1)
331 extract_range(argv[2], &addrlo, &addrhi);
333 extract_range(argv[3], ®lo, ®hi);
335 data = simple_strtoul (argv[4], NULL, 16);
338 /* use current device */
339 devname = miiphy_get_current_dev();
342 * check info/read/write.
345 unsigned char j, start, end;
351 * Look for any and all PHYs. Valid addresses are 0..31.
354 start = addrlo; end = addrhi;
359 for (j = start; j <= end; j++) {
360 if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
361 printf("PHY 0x%02X: "
367 miiphy_speed (devname, j),
368 miiphy_is_1000base_x (devname, j)
370 (miiphy_duplex (devname, j) == FULL)
374 } else if (op[0] == 'r') {
375 for (addr = addrlo; addr <= addrhi; addr++) {
376 for (reg = reglo; reg <= reghi; reg++) {
378 if (miiphy_read (devname, addr, reg, &data) != 0) {
380 "Error reading from the PHY addr=%02x reg=%02x\n",
384 if ((addrlo != addrhi) || (reglo != reghi))
385 printf("addr=%02x reg=%02x data=",
386 (uint)addr, (uint)reg);
387 printf("%04X\n", data & 0x0000FFFF);
390 if ((addrlo != addrhi) && (reglo != reghi))
393 } else if (op[0] == 'w') {
394 for (addr = addrlo; addr <= addrhi; addr++) {
395 for (reg = reglo; reg <= reghi; reg++) {
396 if (miiphy_write (devname, addr, reg, data) != 0) {
397 printf("Error writing to the PHY addr=%02x reg=%02x\n",
403 } else if (strncmp(op, "du", 2) == 0) {
406 if ((reglo > 5) || (reghi > 5)) {
408 "The MII dump command only formats the "
409 "standard MII registers, 0-5.\n");
412 for (addr = addrlo; addr <= addrhi; addr++) {
413 for (reg = reglo; reg < reghi + 1; reg++) {
414 if (miiphy_read(devname, addr, reg, ®s[reg]) != 0) {
417 "Error reading from the PHY addr=%02x reg=%02x\n",
423 MII_dump_0_to_5(regs, reglo, reghi);
426 } else if (strncmp(op, "de", 2) == 0) {
430 miiphy_set_current_dev (argv[2]);
432 return cmd_usage(cmdtp);
436 * Save the parameters for repeats.
440 last_addr_lo = addrlo;
441 last_addr_hi = addrhi;
449 /***************************************************/
453 "MII utility commands",
454 "device - list available devices\n"
455 "mii device <devname> - set current device\n"
456 "mii info <addr> - display MII PHY info\n"
457 "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
458 "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
459 "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
460 "Addr and/or reg may be ranges, e.g. 2-7."