2 * Driver for NAND support, Rick Bronson
3 * borrowed heavily from:
4 * (c) 1999 Machine Vision Holdings, Inc.
5 * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
14 #ifdef CONFIG_SHOW_BOOT_PROGRESS
15 # include <status_led.h>
16 # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
18 # define SHOW_BOOT_PROGRESS(arg)
21 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
23 #ifdef CONFIG_AT91RM9200DK
24 #include <asm/arch/hardware.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ids.h>
29 #include <jffs2/jffs2.h>
31 #ifdef CONFIG_OMAP1510
32 void archflashwp(void *archdata, int wp);
35 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
38 * Definition of the out of band configuration structure
40 struct nand_oob_config {
41 int ecc_pos[6]; /* position of ECC bytes inside oob */
42 int badblock_pos; /* position of bad block flag inside oob -1 = inactive */
43 int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */
44 } oob_config = { {0}, 0, 0};
49 /* ****************** WARNING *********************
50 * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
51 * erase (or at least attempt to erase) blocks that are marked
52 * bad. This can be very handy if you are _sure_ that the block
53 * is OK, say because you marked a good block bad to test bad
54 * block handling and you are done testing, or if you have
55 * accidentally marked blocks bad.
57 * Erasing factory marked bad blocks is a _bad_ idea. If the
58 * erase succeeds there is no reliable way to find them again,
59 * and attempting to program or erase bad blocks can affect
60 * the data in _other_ (good) blocks.
62 #define ALLOW_ERASE_BAD_DEBUG 0
64 #define CONFIG_MTD_NAND_ECC /* enable ECC */
65 #define CONFIG_MTD_NAND_ECC_JFFS2
67 /* bits for nand_rw() `cmd'; or together as needed */
68 #define NANDRW_READ 0x01
69 #define NANDRW_WRITE 0x00
70 #define NANDRW_JFFS2 0x02
71 #define NANDRW_JFFS2_SKIP 0x04
76 static void nand_print(struct nand_chip *nand);
77 int nand_rw (struct nand_chip* nand, int cmd,
78 size_t start, size_t len,
79 size_t * retlen, u_char * buf);
80 int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
81 static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
82 size_t * retlen, u_char *buf, u_char *ecc_code);
83 static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
84 size_t * retlen, const u_char * buf, u_char * ecc_code);
85 static void nand_print_bad(struct nand_chip *nand);
86 static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
87 size_t * retlen, u_char * buf);
88 static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
89 size_t * retlen, const u_char * buf);
90 static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
91 #ifdef CONFIG_MTD_NAND_ECC
92 static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
93 static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
96 struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
98 /* Current NAND Device */
99 static int curr_device = -1;
101 /* ------------------------------------------------------------------------- */
103 int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
110 printf ("Usage:\n%s\n", cmdtp->usage);
113 if (strcmp(argv[1],"info") == 0) {
118 for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
119 if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
120 continue; /* list only known devices */
121 printf ("Device %d: ", i);
122 nand_print(&nand_dev_desc[i]);
126 } else if (strcmp(argv[1],"device") == 0) {
127 if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
128 puts ("\nno devices available\n");
131 printf ("\nDevice %d: ", curr_device);
132 nand_print(&nand_dev_desc[curr_device]);
135 } else if (strcmp(argv[1],"bad") == 0) {
136 if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
137 puts ("\nno devices available\n");
140 printf ("\nDevice %d bad blocks:\n", curr_device);
141 nand_print_bad(&nand_dev_desc[curr_device]);
145 printf ("Usage:\n%s\n", cmdtp->usage);
148 if (strcmp(argv[1],"device") == 0) {
149 int dev = (int)simple_strtoul(argv[2], NULL, 10);
151 printf ("\nDevice %d: ", dev);
152 if (dev >= CFG_MAX_NAND_DEVICE) {
153 puts ("unknown device\n");
156 nand_print(&nand_dev_desc[dev]);
157 /*nand_print (dev);*/
159 if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
165 puts ("... is now current device\n");
169 else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
170 struct nand_chip* nand = &nand_dev_desc[curr_device];
172 ulong size = nand->totlen;
175 printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
176 curr_device, off, size);
178 ret = nand_erase (nand, off, size, 1);
180 printf("%s\n", ret ? "ERROR" : "OK");
185 printf ("Usage:\n%s\n", cmdtp->usage);
188 /* at least 4 args */
190 if (strncmp(argv[1], "read", 4) == 0 ||
191 strncmp(argv[1], "write", 5) == 0) {
192 ulong addr = simple_strtoul(argv[2], NULL, 16);
193 ulong off = simple_strtoul(argv[3], NULL, 16);
194 ulong size = simple_strtoul(argv[4], NULL, 16);
195 int cmd = (strncmp(argv[1], "read", 4) == 0) ?
196 NANDRW_READ : NANDRW_WRITE;
198 char* cmdtail = strchr(argv[1], '.');
200 if (cmdtail && !strncmp(cmdtail, ".oob", 2)) {
201 /* read out-of-band data */
202 if (cmd & NANDRW_READ) {
203 ret = nand_read_oob(nand_dev_desc + curr_device,
208 ret = nand_write_oob(nand_dev_desc + curr_device,
214 else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
215 cmd |= NANDRW_JFFS2; /* skip bad blocks */
216 else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
217 cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
218 if (cmd & NANDRW_READ)
219 cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
222 /* need ".e" same as ".j" for compatibility with older units */
223 else if (cmdtail && !strcmp(cmdtail, ".e"))
224 cmd |= NANDRW_JFFS2; /* skip bad blocks */
226 #ifdef CFG_NAND_SKIP_BAD_DOT_I
227 /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
228 /* ".i" for image -> read skips bad block (no 0xff) */
229 else if (cmdtail && !strcmp(cmdtail, ".i"))
230 cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
231 if (cmd & NANDRW_READ)
232 cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
233 #endif /* CFG_NAND_SKIP_BAD_DOT_I */
235 printf ("Usage:\n%s\n", cmdtp->usage);
239 printf ("\nNAND %s: device %d offset %ld, size %ld ... ",
240 (cmd & NANDRW_READ) ? "read" : "write",
241 curr_device, off, size);
243 ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
244 &total, (u_char*)addr);
246 printf (" %d bytes %s: %s\n", total,
247 (cmd & NANDRW_READ) ? "read" : "written",
248 ret ? "ERROR" : "OK");
251 } else if (strcmp(argv[1],"erase") == 0 &&
252 (argc == 4 || strcmp("clean", argv[2]) == 0)) {
253 int clean = argc == 5;
254 ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
255 ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
258 printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
259 curr_device, off, size);
261 ret = nand_erase (nand_dev_desc + curr_device, off, size, clean);
263 printf("%s\n", ret ? "ERROR" : "OK");
267 printf ("Usage:\n%s\n", cmdtp->usage);
277 "nand - NAND sub-system\n",
278 "info - show available NAND devices\n"
279 "nand device [dev] - show or set current device\n"
280 "nand read[.jffs2[s]] addr off size\n"
281 "nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
282 " at offset `off' to/from memory address `addr'\n"
283 "nand erase [clean] [off size] - erase `size' bytes from\n"
284 " offset `off' (entire device if not specified)\n"
285 "nand bad - show bad blocks\n"
286 "nand read.oob addr off size - read out-of-band data\n"
287 "nand write.oob addr off size - read out-of-band data\n"
290 int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
292 char *boot_device = NULL;
302 addr = CFG_LOAD_ADDR;
303 boot_device = getenv ("bootdevice");
306 addr = simple_strtoul(argv[1], NULL, 16);
307 boot_device = getenv ("bootdevice");
310 addr = simple_strtoul(argv[1], NULL, 16);
311 boot_device = argv[2];
314 addr = simple_strtoul(argv[1], NULL, 16);
315 boot_device = argv[2];
316 offset = simple_strtoul(argv[3], NULL, 16);
319 printf ("Usage:\n%s\n", cmdtp->usage);
320 SHOW_BOOT_PROGRESS (-1);
325 puts ("\n** No boot device **\n");
326 SHOW_BOOT_PROGRESS (-1);
330 dev = simple_strtoul(boot_device, &ep, 16);
332 if ((dev >= CFG_MAX_NAND_DEVICE) ||
333 (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
334 printf ("\n** Device %d not available\n", dev);
335 SHOW_BOOT_PROGRESS (-1);
339 printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
340 dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
343 if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset,
344 SECTORSIZE, NULL, (u_char *)addr)) {
345 printf ("** Read error on %d\n", dev);
346 SHOW_BOOT_PROGRESS (-1);
350 hdr = (image_header_t *)addr;
352 if (ntohl(hdr->ih_magic) == IH_MAGIC) {
354 print_image_hdr (hdr);
356 cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
359 printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
360 SHOW_BOOT_PROGRESS (-1);
364 if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt,
365 NULL, (u_char *)(addr+SECTORSIZE))) {
366 printf ("** Read error on %d\n", dev);
367 SHOW_BOOT_PROGRESS (-1);
371 /* Loading ok, update default load address */
375 /* Check if we should attempt an auto-start */
376 if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
378 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
380 local_args[0] = argv[0];
381 local_args[1] = NULL;
383 printf ("Automatic boot of image at addr 0x%08lx ...\n", addr);
385 do_bootm (cmdtp, 0, 1, local_args);
392 nboot, 4, 1, do_nandboot,
393 "nboot - boot from NAND device\n",
397 /* returns 0 if block containing pos is OK:
398 * valid erase block and
399 * not marked bad, or no bad mark position is specified
400 * returns 1 if marked bad or otherwise invalid
402 int check_block(struct nand_chip* nand, unsigned long pos)
406 int page0 = pos & (-nand->erasesize);
407 int page1 = page0 + nand->oobblock;
408 int badpos = oob_config.badblock_pos;
410 if (pos >= nand->totlen)
414 return 0; /* no way to check, assume OK */
416 /* Note - bad block marker can be on first or second page */
417 if (nand_read_oob(nand, page0 + badpos, 1, &retlen, &oob_data) ||
419 nand_read_oob(nand, page1 + badpos, 1, &retlen, &oob_data) ||
426 /* print bad blocks in NAND flash */
427 static void nand_print_bad(struct nand_chip* nand)
431 for (pos = 0; pos < nand->totlen; pos += nand->erasesize) {
432 if (check_block(nand, pos))
433 printf(" 0x%8.8lx\n", pos);
438 /* cmd: 0: NANDRW_WRITE write, fail on bad block
439 * 1: NANDRW_READ read, fail on bad block
440 * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks
441 * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks
442 * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks
444 int nand_rw (struct nand_chip* nand, int cmd,
445 size_t start, size_t len,
446 size_t * retlen, u_char * buf)
448 int ret = 0, n, total = 0;
450 /* eblk (once set) is the start of the erase block containing the
451 * data being processed.
453 unsigned long eblk = ~0; /* force mismatch on first pass */
454 unsigned long erasesize = nand->erasesize;
457 if ((start & (-erasesize)) != eblk) {
458 /* have crossed into new erase block, deal with
459 * it if it is sure marked bad.
461 eblk = start & (-erasesize); /* start of block */
462 if (check_block(nand, eblk)) {
463 if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {
465 start - eblk < erasesize) {
473 else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {
477 else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
488 /* The ECC will not be calculated correctly if
489 less than 512 is written or read */
490 /* Is request at least 512 bytes AND it starts on a proper boundry */
491 if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
492 printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
494 if (cmd & NANDRW_READ)
495 ret = nand_read_ecc(nand, start,
496 min(len, eblk + erasesize - start),
497 &n, (u_char*)buf, eccbuf);
499 ret = nand_write_ecc(nand, start,
500 min(len, eblk + erasesize - start),
501 &n, (u_char*)buf, eccbuf);
517 static void nand_print(struct nand_chip *nand)
519 if (nand->numchips > 1) {
520 printf("%s at 0x%lx,\n"
521 "\t %d chips %s, size %d MB, \n"
522 "\t total size %ld MB, sector size %ld kB\n",
523 nand->name, nand->IO_ADDR, nand->numchips,
524 nand->chips_name, 1 << (nand->chipshift - 20),
525 nand->totlen >> 20, nand->erasesize >> 10);
528 printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR);
529 print_size(nand->totlen, ", ");
530 print_size(nand->erasesize, " sector)\n");
534 /* ------------------------------------------------------------------------- */
536 static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
538 /* This is inline, to optimise the common case, where it's ready instantly */
541 #ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */
543 NAND_WAIT_READY(nand); /* do the worst case 25us wait */
546 #else /* has functional r/b signal */
547 NAND_WAIT_READY(nand);
552 /* NanD_Command: Send a flash command to the flash chip */
554 static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
556 unsigned long nandptr = nand->IO_ADDR;
558 /* Assert the CLE (Command Latch Enable) line to the flash chip */
559 NAND_CTL_SETCLE(nandptr);
561 /* Send the command */
562 WRITE_NAND_COMMAND(command, nandptr);
564 /* Lower the CLE line */
565 NAND_CTL_CLRCLE(nandptr);
568 if(command == NAND_CMD_RESET){
570 NanD_Command(nand, NAND_CMD_STATUS);
572 ret_val = READ_NAND(nandptr);/* wait till ready */
573 } while((ret_val & 0x40) != 0x40);
576 return NanD_WaitReady(nand, 0);
579 /* NanD_Address: Set the current address for the flash chip */
581 static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
583 unsigned long nandptr;
586 nandptr = nand->IO_ADDR;
588 /* Assert the ALE (Address Latch Enable) line to the flash chip */
589 NAND_CTL_SETALE(nandptr);
591 /* Send the address */
592 /* Devices with 256-byte page are addressed as:
593 * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
594 * there is no device on the market with page256
595 * and more than 24 bits.
596 * Devices with 512-byte page are addressed as:
597 * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
598 * 25-31 is sent only if the chip support it.
599 * bit 8 changes the read command to be sent
600 * (NAND_CMD_READ0 or NAND_CMD_READ1).
603 if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
604 WRITE_NAND_ADDRESS(ofs, nandptr);
606 ofs = ofs >> nand->page_shift;
608 if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE)
609 for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8)
610 WRITE_NAND_ADDRESS(ofs, nandptr);
612 /* Lower the ALE line */
613 NAND_CTL_CLRALE(nandptr);
615 /* Wait for the chip to respond */
616 return NanD_WaitReady(nand, 1);
619 /* NanD_SelectChip: Select a given flash chip within the current floor */
621 static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
623 /* Wait for it to be ready */
624 return NanD_WaitReady(nand, 0);
627 /* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
629 static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
633 NAND_ENABLE_CE(nand); /* set pin low */
635 if (NanD_Command(nand, NAND_CMD_RESET)) {
637 printf("NanD_Command (reset) for %d,%d returned true\n",
640 NAND_DISABLE_CE(nand); /* set pin high */
644 /* Read the NAND chip ID: 1. Send ReadID command */
645 if (NanD_Command(nand, NAND_CMD_READID)) {
647 printf("NanD_Command (ReadID) for %d,%d returned true\n",
650 NAND_DISABLE_CE(nand); /* set pin high */
654 /* Read the NAND chip ID: 2. Send address byte zero */
655 NanD_Address(nand, ADDR_COLUMN, 0);
657 /* Read the manufacturer and device id codes from the device */
659 mfr = READ_NAND(nand->IO_ADDR);
661 id = READ_NAND(nand->IO_ADDR);
663 NAND_DISABLE_CE(nand); /* set pin high */
664 /* No response - return failure */
665 if (mfr == 0xff || mfr == 0) {
667 printf("NanD_Command (ReadID) got %d %d\n", mfr, id);
672 /* Check it's the same as the first chip we identified.
673 * M-Systems say that any given nand_chip device should only
674 * contain _one_ type of flash part, although that's not a
675 * hardware restriction. */
677 if (nand->mfr == mfr && nand->id == id)
678 return 1; /* This is another the same the first */
680 printf("Flash chip at floor %d, chip %d is different:\n",
684 /* Print and store the manufacturer and ID codes. */
685 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
686 if (mfr == nand_flash_ids[i].manufacture_id &&
687 id == nand_flash_ids[i].model_id) {
689 printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
690 "Chip ID: 0x%2.2X (%s)\n", mfr, id,
691 nand_flash_ids[i].name);
697 nand_flash_ids[i].chipshift;
698 nand->page256 = nand_flash_ids[i].page256;
701 nand->oobblock = 256;
703 nand->page_shift = 8;
705 nand->oobblock = 512;
707 nand->page_shift = 9;
710 nand_flash_ids[i].pageadrlen;
712 nand_flash_ids[i].erasesize;
714 nand_flash_ids[i].name;
723 /* We haven't fully identified the chip. Print as much as we know. */
724 printf("Unknown flash chip found: %2.2X %2.2X\n",
731 /* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
733 static void NanD_ScanChips(struct nand_chip *nand)
736 int numchips[NAND_MAX_FLOORS];
737 int maxchips = NAND_MAX_CHIPS;
745 /* For each floor, find the number of valid chips it contains */
746 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
749 for (chip = 0; chip < maxchips && ret != 0; chip++) {
751 ret = NanD_IdentChip(nand, floor, chip);
759 /* If there are none at all that we recognise, bail */
760 if (!nand->numchips) {
762 puts ("No NAND flash chips recognised.\n");
767 /* Allocate an array to hold the information for each chip */
768 nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
770 puts ("No memory for allocating chip info structures\n");
776 /* Fill out the chip array with {floor, chipno} for each
777 * detected chip in the device. */
778 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
779 for (chip = 0; chip < numchips[floor]; chip++) {
780 nand->chips[ret].floor = floor;
781 nand->chips[ret].chip = chip;
782 nand->chips[ret].curadr = 0;
783 nand->chips[ret].curmode = 0x50;
788 /* Calculate and print the total size of the device */
789 nand->totlen = nand->numchips * (1 << nand->chipshift);
792 printf("%d flash chips found. Total nand_chip size: %ld MB\n",
793 nand->numchips, nand->totlen >> 20);
797 /* we need to be fast here, 1 us per read translates to 1 second per meg */
798 static void NanD_ReadBuf(struct nand_chip *nand, u_char *data_buf, int cntr)
800 unsigned long nandptr = nand->IO_ADDR;
803 *data_buf++ = READ_NAND(nandptr);
804 *data_buf++ = READ_NAND(nandptr);
805 *data_buf++ = READ_NAND(nandptr);
806 *data_buf++ = READ_NAND(nandptr);
807 *data_buf++ = READ_NAND(nandptr);
808 *data_buf++ = READ_NAND(nandptr);
809 *data_buf++ = READ_NAND(nandptr);
810 *data_buf++ = READ_NAND(nandptr);
811 *data_buf++ = READ_NAND(nandptr);
812 *data_buf++ = READ_NAND(nandptr);
813 *data_buf++ = READ_NAND(nandptr);
814 *data_buf++ = READ_NAND(nandptr);
815 *data_buf++ = READ_NAND(nandptr);
816 *data_buf++ = READ_NAND(nandptr);
817 *data_buf++ = READ_NAND(nandptr);
818 *data_buf++ = READ_NAND(nandptr);
823 *data_buf++ = READ_NAND(nandptr);
831 static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
832 size_t * retlen, u_char *buf, u_char *ecc_code)
836 #ifdef CONFIG_MTD_NAND_ECC
843 /* Do not allow reads past end of device */
844 if ((start + len) > nand->totlen) {
845 printf ("%s: Attempt read beyond end of device %x %x %x\n", __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
850 /* First we calculate the starting page */
851 /*page = shr(start, nand->page_shift);*/
852 page = start >> nand->page_shift;
854 /* Get raw starting column */
855 col = start & (nand->oobblock - 1);
857 /* Initialize return value */
860 /* Select the NAND device */
861 NAND_ENABLE_CE(nand); /* set pin low */
863 /* Loop until all data read */
864 while (*retlen < len) {
867 #ifdef CONFIG_MTD_NAND_ECC
869 /* Do we have this page in cache ? */
870 if (nand->cache_page == page)
872 /* Send the read command */
873 NanD_Command(nand, NAND_CMD_READ0);
874 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
875 /* Read in a page + oob data */
876 NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize);
878 /* copy data into cache, for read out of cache and if ecc fails */
879 if (nand->data_cache)
880 memcpy (nand->data_cache, nand->data_buf, nand->oobblock + nand->oobsize);
882 /* Pick the ECC bytes out of the oob data */
883 for (j = 0; j < 6; j++)
884 ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
886 /* Calculate the ECC and verify it */
887 /* If block was not written with ECC, skip ECC */
888 if (oob_config.eccvalid_pos != -1 &&
889 (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
891 nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
892 switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
894 printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
898 case 2: /* transfer ECC corrected data to cache */
899 if (nand->data_cache)
900 memcpy (nand->data_cache, nand->data_buf, 256);
905 if (oob_config.eccvalid_pos != -1 &&
906 nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
908 nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
909 switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
911 printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
915 case 2: /* transfer ECC corrected data to cache */
916 if (nand->data_cache)
917 memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
922 /* Read the data from ECC data buffer into return buffer */
923 data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
925 if ((*retlen + (nand->oobblock - col)) >= len) {
926 memcpy (buf + *retlen, data_poi, len - *retlen);
929 memcpy (buf + *retlen, data_poi, nand->oobblock - col);
930 *retlen += nand->oobblock - col;
932 /* Set cache page address, invalidate, if ecc_failed */
933 nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
935 ecc_status += ecc_failed;
939 /* Send the read command */
940 NanD_Command(nand, NAND_CMD_READ0);
941 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
942 /* Read the data directly into the return buffer */
943 if ((*retlen + (nand->oobblock - col)) >= len) {
944 NanD_ReadBuf(nand, buf + *retlen, len - *retlen);
949 NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col);
950 *retlen += nand->oobblock - col;
953 /* For subsequent reads align to page boundary. */
955 /* Increment page address */
959 /* De-select the NAND device */
960 NAND_DISABLE_CE(nand); /* set pin high */
963 * Return success, if no ECC failures, else -EIO
964 * fs driver will take care of that, because
965 * retlen == desired len and result == -EIO
967 return ecc_status ? -1 : 0;
971 * Nand_page_program function is used for write and writev !
973 static int nand_write_page (struct nand_chip *nand,
974 int page, int col, int last, u_char * ecc_code)
978 unsigned long nandptr = nand->IO_ADDR;
979 #ifdef CONFIG_MTD_NAND_ECC
980 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
981 int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
985 for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
986 nand->data_buf[i] = 0xff;
988 #ifdef CONFIG_MTD_NAND_ECC
989 /* Zero out the ECC array */
990 for (i = 0; i < 6; i++)
993 /* Read back previous written data, if col > 0 */
995 NanD_Command(nand, NAND_CMD_READ0);
996 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
997 for (i = 0; i < col; i++)
998 nand->data_buf[i] = READ_NAND (nandptr);
1001 /* Calculate and write the ECC if we have enough data */
1002 if ((col < nand->eccsize) && (last >= nand->eccsize)) {
1003 nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
1004 for (i = 0; i < 3; i++)
1005 nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i];
1006 if (oob_config.eccvalid_pos != -1)
1007 nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] = 0xf0;
1010 /* Calculate and write the second ECC if we have enough data */
1011 if ((nand->oobblock == 512) && (last == nand->oobblock)) {
1012 nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
1013 for (i = 3; i < 6; i++)
1014 nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i];
1015 if (oob_config.eccvalid_pos != -1)
1016 nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] &= 0x0f;
1019 /* Prepad for partial page programming !!! */
1020 for (i = 0; i < col; i++)
1021 nand->data_buf[i] = 0xff;
1023 /* Postpad for partial page programming !!! oob is already padded */
1024 for (i = last; i < nand->oobblock; i++)
1025 nand->data_buf[i] = 0xff;
1027 /* Send command to begin auto page programming */
1028 NanD_Command(nand, NAND_CMD_READ0);
1029 NanD_Command(nand, NAND_CMD_SEQIN);
1030 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
1032 /* Write out complete page of data */
1033 for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
1034 WRITE_NAND(nand->data_buf[i], nand->IO_ADDR);
1036 /* Send command to actually program the data */
1037 NanD_Command(nand, NAND_CMD_PAGEPROG);
1038 NanD_Command(nand, NAND_CMD_STATUS);
1043 ret_val = READ_NAND(nandptr); /* wait till ready */
1044 } while((ret_val & 0x40) != 0x40);
1047 /* See if device thinks it succeeded */
1048 if (READ_NAND(nand->IO_ADDR) & 0x01) {
1049 printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, page);
1053 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1055 * The NAND device assumes that it is always writing to
1056 * a cleanly erased page. Hence, it performs its internal
1057 * write verification only on bits that transitioned from
1058 * 1 to 0. The device does NOT verify the whole page on a
1059 * byte by byte basis. It is possible that the page was
1060 * not completely erased or the page is becoming unusable
1061 * due to wear. The read with ECC would catch the error
1062 * later when the ECC page check fails, but we would rather
1063 * catch it early in the page write stage. Better to write
1064 * no data than invalid data.
1067 /* Send command to read back the page */
1068 if (col < nand->eccsize)
1069 NanD_Command(nand, NAND_CMD_READ0);
1071 NanD_Command(nand, NAND_CMD_READ1);
1072 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
1074 /* Loop through and verify the data */
1075 for (i = col; i < last; i++) {
1076 if (nand->data_buf[i] != readb (nand->IO_ADDR)) {
1077 printf ("%s: Failed write verify, page 0x%08x ", __FUNCTION__, page);
1082 #ifdef CONFIG_MTD_NAND_ECC
1084 * We also want to check that the ECC bytes wrote
1085 * correctly for the same reasons stated above.
1087 NanD_Command(nand, NAND_CMD_READOOB);
1088 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
1089 for (i = 0; i < nand->oobsize; i++)
1090 nand->data_buf[i] = readb (nand->IO_ADDR);
1091 for (i = 0; i < ecc_bytes; i++) {
1092 if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
1093 printf ("%s: Failed ECC write "
1094 "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
1103 static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
1104 size_t * retlen, const u_char * buf, u_char * ecc_code)
1106 int i, page, col, cnt, ret = 0;
1108 /* Do not allow write past end of device */
1109 if ((to + len) > nand->totlen) {
1110 printf ("%s: Attempt to write past end of page\n", __FUNCTION__);
1114 /* Shift to get page */
1115 page = ((int) to) >> nand->page_shift;
1117 /* Get the starting column */
1118 col = to & (nand->oobblock - 1);
1120 /* Initialize return length value */
1123 /* Select the NAND device */
1124 #ifdef CONFIG_OMAP1510
1127 NAND_ENABLE_CE(nand); /* set pin low */
1129 /* Check the WP bit */
1130 NanD_Command(nand, NAND_CMD_STATUS);
1131 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1132 printf ("%s: Device is write protected!!!\n", __FUNCTION__);
1137 /* Loop until all data is written */
1138 while (*retlen < len) {
1139 /* Invalidate cache, if we write to this page */
1140 if (nand->cache_page == page)
1141 nand->cache_page = -1;
1143 /* Write data into buffer */
1144 if ((col + len) >= nand->oobblock)
1145 for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++)
1146 nand->data_buf[i] = buf[(*retlen + cnt)];
1148 for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++)
1149 nand->data_buf[i] = buf[(*retlen + cnt)];
1150 /* We use the same function for write and writev !) */
1151 ret = nand_write_page (nand, page, col, i, ecc_code);
1155 /* Next data start at page boundary */
1158 /* Update written bytes count */
1161 /* Increment page address */
1169 /* De-select the NAND device */
1170 NAND_DISABLE_CE(nand); /* set pin high */
1171 #ifdef CONFIG_OMAP1510
1177 /* read from the 16 bytes of oob data that correspond to a 512 byte
1178 * page or 2 256-byte pages.
1180 static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
1181 size_t * retlen, u_char * buf)
1184 struct Nand *mychip;
1187 mychip = &nand->chips[ofs >> nand->chipshift];
1189 /* update address for 2M x 8bit devices. OOB starts on the second */
1190 /* page to maintain compatibility with nand_read_ecc. */
1191 if (nand->page256) {
1198 NAND_ENABLE_CE(nand); /* set pin low */
1199 NanD_Command(nand, NAND_CMD_READOOB);
1200 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1202 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1203 /* Note: datasheet says it should automaticaly wrap to the */
1204 /* next OOB block, but it didn't work here. mf. */
1205 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1206 len256 = (ofs | 0x7) + 1 - ofs;
1207 NanD_ReadBuf(nand, buf, len256);
1209 NanD_Command(nand, NAND_CMD_READOOB);
1210 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1213 NanD_ReadBuf(nand, &buf[len256], len - len256);
1216 /* Reading the full OOB data drops us off of the end of the page,
1217 * causing the flash device to go into busy mode, so we need
1218 * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
1220 ret = NanD_WaitReady(nand, 1);
1221 NAND_DISABLE_CE(nand); /* set pin high */
1227 /* write to the 16 bytes of oob data that correspond to a 512 byte
1228 * page or 2 256-byte pages.
1230 static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
1231 size_t * retlen, const u_char * buf)
1235 unsigned long nandptr = nand->IO_ADDR;
1238 printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
1239 (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
1240 buf[8], buf[9], buf[14],buf[15]);
1243 NAND_ENABLE_CE(nand); /* set pin low to enable chip */
1245 /* Reset the chip */
1246 NanD_Command(nand, NAND_CMD_RESET);
1248 /* issue the Read2 command to set the pointer to the Spare Data Area. */
1249 NanD_Command(nand, NAND_CMD_READOOB);
1250 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1252 /* update address for 2M x 8bit devices. OOB starts on the second */
1253 /* page to maintain compatibility with nand_read_ecc. */
1254 if (nand->page256) {
1261 /* issue the Serial Data In command to initial the Page Program process */
1262 NanD_Command(nand, NAND_CMD_SEQIN);
1263 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1265 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1266 /* Note: datasheet says it should automaticaly wrap to the */
1267 /* next OOB block, but it didn't work here. mf. */
1268 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1269 len256 = (ofs | 0x7) + 1 - ofs;
1270 for (i = 0; i < len256; i++)
1271 WRITE_NAND(buf[i], nandptr);
1273 NanD_Command(nand, NAND_CMD_PAGEPROG);
1274 NanD_Command(nand, NAND_CMD_STATUS);
1278 ret_val = READ_NAND(nandptr); /* wait till ready */
1279 }while((ret_val & 0x40) != 0x40);
1282 if (READ_NAND(nandptr) & 1) {
1283 puts ("Error programming oob data\n");
1284 /* There was an error */
1285 NAND_DISABLE_CE(nand); /* set pin high */
1289 NanD_Command(nand, NAND_CMD_SEQIN);
1290 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1293 for (i = len256; i < len; i++)
1294 WRITE_NAND(buf[i], nandptr);
1296 NanD_Command(nand, NAND_CMD_PAGEPROG);
1297 NanD_Command(nand, NAND_CMD_STATUS);
1301 ret_val = READ_NAND(nandptr); /* wait till ready */
1302 } while((ret_val & 0x40) != 0x40);
1305 if (READ_NAND(nandptr) & 1) {
1306 puts ("Error programming oob data\n");
1307 /* There was an error */
1308 NAND_DISABLE_CE(nand); /* set pin high */
1313 NAND_DISABLE_CE(nand); /* set pin high */
1319 int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
1321 /* This is defined as a structure so it will work on any system
1322 * using native endian jffs2 (the default).
1324 static struct jffs2_unknown_node clean_marker = {
1325 JFFS2_MAGIC_BITMASK,
1326 JFFS2_NODETYPE_CLEANMARKER,
1327 8 /* 8 bytes in this node */
1329 unsigned long nandptr;
1330 struct Nand *mychip;
1333 if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
1334 printf ("Offset and size must be sector aligned, erasesize = %d\n",
1335 (int) nand->erasesize);
1339 nandptr = nand->IO_ADDR;
1341 /* Select the NAND device */
1342 #ifdef CONFIG_OMAP1510
1345 NAND_ENABLE_CE(nand); /* set pin low */
1347 /* Check the WP bit */
1348 NanD_Command(nand, NAND_CMD_STATUS);
1349 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1350 printf ("nand_write_ecc: Device is write protected!!!\n");
1355 /* Check the WP bit */
1356 NanD_Command(nand, NAND_CMD_STATUS);
1357 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1358 printf ("%s: Device is write protected!!!\n", __FUNCTION__);
1363 /* FIXME: Do nand in the background. Use timers or schedule_task() */
1365 /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/
1366 mychip = &nand->chips[ofs >> nand->chipshift];
1368 /* always check for bad block first, genuine bad blocks
1369 * should _never_ be erased.
1371 if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) {
1372 /* Select the NAND device */
1373 NAND_ENABLE_CE(nand); /* set pin low */
1375 NanD_Command(nand, NAND_CMD_ERASE1);
1376 NanD_Address(nand, ADDR_PAGE, ofs);
1377 NanD_Command(nand, NAND_CMD_ERASE2);
1379 NanD_Command(nand, NAND_CMD_STATUS);
1384 ret_val = READ_NAND(nandptr); /* wait till ready */
1385 } while((ret_val & 0x40) != 0x40);
1388 if (READ_NAND(nandptr) & 1) {
1389 printf ("%s: Error erasing at 0x%lx\n",
1390 __FUNCTION__, (long)ofs);
1391 /* There was an error */
1396 int n; /* return value not used */
1399 /* clean marker position and size depend
1400 * on the page size, since 256 byte pages
1401 * only have 8 bytes of oob data
1403 if (nand->page256) {
1404 p = NAND_JFFS2_OOB8_FSDAPOS;
1405 l = NAND_JFFS2_OOB8_FSDALEN;
1408 p = NAND_JFFS2_OOB16_FSDAPOS;
1409 l = NAND_JFFS2_OOB16_FSDALEN;
1412 ret = nand_write_oob(nand, ofs + p, l, &n,
1413 (u_char *)&clean_marker);
1414 /* quit here if write failed */
1419 ofs += nand->erasesize;
1420 len -= nand->erasesize;
1424 /* De-select the NAND device */
1425 NAND_DISABLE_CE(nand); /* set pin high */
1426 #ifdef CONFIG_OMAP1510
1432 static inline int nandcheck(unsigned long potential, unsigned long physadr)
1437 unsigned long nand_probe(unsigned long physadr)
1439 struct nand_chip *nand = NULL;
1440 int i = 0, ChipID = 1;
1442 #ifdef CONFIG_MTD_NAND_ECC_JFFS2
1443 oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
1444 oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
1445 oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
1446 oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
1447 oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
1448 oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
1449 oob_config.eccvalid_pos = 4;
1451 oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
1452 oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
1453 oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
1454 oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
1455 oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
1456 oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
1457 oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
1459 oob_config.badblock_pos = 5;
1461 for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
1462 if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
1463 nand = &nand_dev_desc[i];
1470 memset((char *)nand, 0, sizeof(struct nand_chip));
1472 nand->IO_ADDR = physadr;
1473 nand->cache_page = -1; /* init the cache page */
1474 NanD_ScanChips(nand);
1476 if (nand->totlen == 0) {
1477 /* no chips found, clean up and quit */
1478 memset((char *)nand, 0, sizeof(struct nand_chip));
1479 nand->ChipID = NAND_ChipID_UNKNOWN;
1483 nand->ChipID = ChipID;
1484 if (curr_device == -1)
1487 nand->data_buf = malloc (nand->oobblock + nand->oobsize);
1488 if (!nand->data_buf) {
1489 puts ("Cannot allocate memory for data structures.\n");
1493 return (nand->totlen);
1496 #ifdef CONFIG_MTD_NAND_ECC
1498 * Pre-calculated 256-way 1 byte column parity
1500 static const u_char nand_ecc_precalc_table[] = {
1501 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
1502 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1503 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1504 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1505 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1506 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1507 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1508 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1509 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1510 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1511 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1512 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1513 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1514 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1515 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1516 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
1521 * Creates non-inverted ECC code from line parity
1523 static void nand_trans_result(u_char reg2, u_char reg3,
1526 u_char a, b, i, tmp1, tmp2;
1528 /* Initialize variables */
1532 /* Calculate first ECC byte */
1533 for (i = 0; i < 4; i++) {
1534 if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
1537 if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
1543 /* Calculate second ECC byte */
1545 for (i = 0; i < 4; i++) {
1546 if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
1549 if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
1555 /* Store two of the ECC bytes */
1561 * Calculate 3 byte ECC code for 256 byte block
1563 static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
1565 u_char idx, reg1, reg3;
1568 /* Initialize variables */
1570 ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
1572 /* Build up column parity */
1573 for(j = 0; j < 256; j++) {
1575 /* Get CP0 - CP5 from table */
1576 idx = nand_ecc_precalc_table[dat[j]];
1579 /* All bit XOR = 1 ? */
1585 /* Create non-inverted ECC code from line parity */
1586 nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code);
1588 /* Calculate final ECC code */
1589 ecc_code[0] = ~ecc_code[0];
1590 ecc_code[1] = ~ecc_code[1];
1591 ecc_code[2] = ((~reg1) << 2) | 0x03;
1595 * Detect and correct a 1 bit error for 256 byte block
1597 static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
1599 u_char a, b, c, d1, d2, d3, add, bit, i;
1601 /* Do error detection */
1602 d1 = calc_ecc[0] ^ read_ecc[0];
1603 d2 = calc_ecc[1] ^ read_ecc[1];
1604 d3 = calc_ecc[2] ^ read_ecc[2];
1606 if ((d1 | d2 | d3) == 0) {
1611 a = (d1 ^ (d1 >> 1)) & 0x55;
1612 b = (d2 ^ (d2 >> 1)) & 0x55;
1613 c = (d3 ^ (d3 >> 1)) & 0x54;
1615 /* Found and will correct single bit error in the data */
1616 if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
1620 for (i=0; i<4; i++) {
1627 for (i=0; i<4; i++) {
1636 for (i=0; i<3; i++) {
1666 /* ECC Code Error Correction */
1667 read_ecc[0] = calc_ecc[0];
1668 read_ecc[1] = calc_ecc[1];
1669 read_ecc[2] = calc_ecc[2];
1673 /* Uncorrectable Error */
1679 /* Should never happen */
1685 #ifdef CONFIG_JFFS2_NAND
1687 int read_jffs2_nand(size_t start, size_t len,
1688 size_t * retlen, u_char * buf, int nanddev)
1690 return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2,
1691 start, len, retlen, buf);
1694 #endif /* CONFIG_JFFS2_NAND */
1697 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */