2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <bootretry.h>
21 #include <asm/processor.h>
26 * Follows routines for the output of infos about devices on PCI bus.
29 void pci_header_show(pci_dev_t dev);
30 void pci_header_show_brief(pci_dev_t dev);
35 * Description: Show information about devices on PCI bus.
36 * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
37 * the output will be more or less exhaustive.
39 * Inputs: bus_no the number of the bus to be scanned.
44 void pciinfo(int BusNum, int ShortPCIListing)
46 struct pci_controller *hose = pci_bus_to_hose(BusNum);
49 unsigned char HeaderType;
50 unsigned short VendorID;
57 printf("Scanning PCI devices on bus %d\n", BusNum);
59 if (ShortPCIListing) {
60 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
61 printf("_____________________________________________________________\n");
64 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
67 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
69 * If this is not a multi-function device, we skip the rest.
71 if (Function && !(HeaderType & 0x80))
74 dev = PCI_BDF(BusNum, Device, Function);
76 if (pci_skip_dev(hose, dev))
79 ret = pci_read_config_word(dev, PCI_VENDOR_ID,
83 if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
86 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
90 printf("%02x.%02x.%02x ", BusNum, Device, Function);
91 pci_header_show_brief(dev);
95 printf("\nFound PCI device %02x.%02x.%02x:\n",
96 BusNum, Device, Function);
104 printf("Cannot read bus configuration: %d\n", ret);
109 * Subroutine: pci_header_show_brief
111 * Description: Reads and prints the header of the
112 * specified PCI device in short form.
114 * Inputs: dev Bus+Device+Function number
119 void pci_header_show_brief(pci_dev_t dev)
124 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
125 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
126 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
127 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
129 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
131 pci_class_str(class), subclass);
134 struct pci_reg_info {
136 enum pci_size_t size;
140 static int pci_field_width(enum pci_size_t size)
153 static unsigned long pci_read_config(pci_dev_t dev, int offset,
154 enum pci_size_t size)
162 pci_read_config_byte(dev, offset, &val8);
165 pci_read_config_word(dev, offset, &val16);
169 pci_read_config_dword(dev, offset, &val32);
174 static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
176 for (; regs->name; regs++) {
177 printf(" %s =%*s%#.*lx\n", regs->name,
178 (int)(28 - strlen(regs->name)), "",
179 pci_field_width(regs->size),
180 pci_read_config(dev, regs->offset, regs->size));
184 static struct pci_reg_info regs_start[] = {
185 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
186 { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
187 { "command register ID", PCI_SIZE_16, PCI_COMMAND },
188 { "status register", PCI_SIZE_16, PCI_STATUS },
189 { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
193 static struct pci_reg_info regs_rest[] = {
194 { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
195 { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
196 { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
197 { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
198 { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
199 { "BIST", PCI_SIZE_8, PCI_BIST },
200 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
204 static struct pci_reg_info regs_normal[] = {
205 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
206 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
207 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
208 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
209 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
210 { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
211 { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
212 { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
213 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
214 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
215 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
216 { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
217 { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
221 static struct pci_reg_info regs_bridge[] = {
222 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
223 { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
224 { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
225 { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
226 { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
227 { "IO base", PCI_SIZE_8, PCI_IO_BASE },
228 { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
229 { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
230 { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
231 { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
232 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
233 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
234 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
235 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
236 { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
237 { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
238 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
239 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
240 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
241 { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
245 static struct pci_reg_info regs_cardbus[] = {
246 { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
247 { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
248 { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
249 { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
250 { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
251 { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
252 { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
253 { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
254 { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
255 { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
256 { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
257 { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
258 { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
259 { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
260 { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
261 { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
262 { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
263 { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
264 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
265 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
266 { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
267 { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
268 { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
269 { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
274 * Subroutine: PCI_Header_Show
276 * Description: Reads the header of the specified PCI device.
278 * Inputs: BusDevFunc Bus+Device+Function number
283 void pci_header_show(pci_dev_t dev)
285 u8 class, header_type;
287 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
288 pci_show_regs(dev, regs_start);
290 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
291 printf(" class code = 0x%.2x (%s)\n", class,
292 pci_class_str(class));
293 pci_show_regs(dev, regs_rest);
295 switch (header_type & 0x03) {
296 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
297 pci_show_regs(dev, regs_normal);
299 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
300 pci_show_regs(dev, regs_bridge);
302 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
303 pci_show_regs(dev, regs_cardbus);
307 printf("unknown header\n");
312 /* Convert the "bus.device.function" identifier into a number.
314 static pci_dev_t get_pci_dev(char* name)
318 int bdfs[3] = {0,0,0};
323 for (i = 0, iold = 0, n = 0; i < len; i++) {
324 if (name[i] == '.') {
325 memcpy(cnum, &name[iold], i - iold);
326 cnum[i - iold] = '\0';
327 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
331 strcpy(cnum, &name[iold]);
334 bdfs[n] = simple_strtoul(cnum, NULL, 16);
335 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
338 static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
340 #define DISP_LINE_LEN 16
341 ulong i, nbytes, linebytes;
345 length = 0x40 / size; /* Standard PCI configuration space */
348 * once, and all accesses are with the specified bus width.
350 nbytes = length * size;
356 printf("%08lx:", addr);
357 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
358 for (i=0; i<linebytes; i+= size) {
360 pci_read_config_dword(bdf, addr, &val4);
361 printf(" %08x", val4);
362 } else if (size == 2) {
363 pci_read_config_word(bdf, addr, &val2);
364 printf(" %04x", val2);
366 pci_read_config_byte(bdf, addr, &val1);
367 printf(" %02x", val1);
377 } while (nbytes > 0);
382 static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
385 pci_write_config_dword(bdf, addr, value);
387 else if (size == 2) {
388 ushort val = value & 0xffff;
389 pci_write_config_word(bdf, addr, val);
392 u_char val = value & 0xff;
393 pci_write_config_byte(bdf, addr, val);
399 pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
407 /* Print the address, followed by value. Then accept input for
408 * the next value. A non-converted value exits.
411 printf("%08lx:", addr);
413 pci_read_config_dword(bdf, addr, &val4);
414 printf(" %08x", val4);
416 else if (size == 2) {
417 pci_read_config_word(bdf, addr, &val2);
418 printf(" %04x", val2);
421 pci_read_config_byte(bdf, addr, &val1);
422 printf(" %02x", val1);
425 nbytes = cli_readline(" ? ");
426 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
427 /* <CR> pressed as only input, don't modify current
428 * location and move to next. "-" pressed will go back.
431 addr += nbytes ? -size : size;
433 /* good enough to not time out */
434 bootretry_reset_cmd_timeout();
436 #ifdef CONFIG_BOOT_RETRY_TIME
437 else if (nbytes == -2) {
438 break; /* timed out, exit the command */
443 i = simple_strtoul(console_buffer, &endp, 16);
444 nbytes = endp - console_buffer;
446 /* good enough to not time out
448 bootretry_reset_cmd_timeout();
449 pci_cfg_write (bdf, addr, size, i);
459 /* PCI Configuration Space access commands
462 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
463 * pci next[.b, .w, .l] bus.device.function [addr]
464 * pci modify[.b, .w, .l] bus.device.function [addr]
465 * pci write[.b, .w, .l] bus.device.function addr value
467 static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
469 ulong addr = 0, value = 0, size = 0;
479 case 'd': /* display */
481 case 'm': /* modify */
482 case 'w': /* write */
483 /* Check for a size specification. */
484 size = cmd_get_data_size(argv[1], 4);
486 addr = simple_strtoul(argv[3], NULL, 16);
488 value = simple_strtoul(argv[4], NULL, 16);
489 case 'h': /* header */
492 if ((bdf = get_pci_dev(argv[2])) == -1)
495 #ifdef CONFIG_CMD_PCI_ENUM
499 default: /* scan bus */
500 value = 1; /* short listing */
502 if (argv[argc-1][0] == 'l') {
507 busnum = simple_strtoul(argv[1], NULL, 16);
509 pciinfo(busnum, value);
513 switch (argv[1][0]) {
514 case 'h': /* header */
515 pci_header_show(bdf);
517 case 'd': /* display */
518 return pci_cfg_display(bdf, addr, size, value);
519 #ifdef CONFIG_CMD_PCI_ENUM
521 # ifdef CONFIG_DM_PCI
522 printf("This command is not yet supported with driver model\n");
531 ret = pci_cfg_modify(bdf, addr, size, value, 0);
533 case 'm': /* modify */
536 ret = pci_cfg_modify(bdf, addr, size, value, 1);
538 case 'w': /* write */
541 ret = pci_cfg_write(bdf, addr, size, value);
550 return CMD_RET_USAGE;
553 /***************************************************/
555 #ifdef CONFIG_SYS_LONGHELP
556 static char pci_help_text[] =
558 " - short or long list of PCI devices on bus 'bus'\n"
559 #ifdef CONFIG_CMD_PCI_ENUM
561 " - re-enumerate PCI buses\n"
564 " - show header of PCI device 'bus.device.function'\n"
565 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
566 " - display PCI configuration space (CFG)\n"
567 "pci next[.b, .w, .l] b.d.f address\n"
568 " - modify, read and keep CFG address\n"
569 "pci modify[.b, .w, .l] b.d.f address\n"
570 " - modify, auto increment CFG address\n"
571 "pci write[.b, .w, .l] b.d.f address value\n"
572 " - write to CFG address";
577 "list and access PCI Configuration Space", pci_help_text