2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <bootretry.h>
21 #include <asm/processor.h>
31 static int pci_byte_size(enum pci_size_t size)
44 static int pci_field_width(enum pci_size_t size)
46 return pci_byte_size(size) * 2;
49 static unsigned long pci_read_config(pci_dev_t dev, int offset,
58 pci_read_config_byte(dev, offset, &val8);
61 pci_read_config_word(dev, offset, &val16);
65 pci_read_config_dword(dev, offset, &val32);
70 static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
72 for (; regs->name; regs++) {
73 printf(" %s =%*s%#.*lx\n", regs->name,
74 (int)(28 - strlen(regs->name)), "",
75 pci_field_width(regs->size),
76 pci_read_config(dev, regs->offset, regs->size));
80 static struct pci_reg_info regs_start[] = {
81 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
82 { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
83 { "command register ID", PCI_SIZE_16, PCI_COMMAND },
84 { "status register", PCI_SIZE_16, PCI_STATUS },
85 { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
89 static struct pci_reg_info regs_rest[] = {
90 { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
91 { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
92 { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
93 { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
94 { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
95 { "BIST", PCI_SIZE_8, PCI_BIST },
96 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
100 static struct pci_reg_info regs_normal[] = {
101 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
102 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
103 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
104 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
105 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
106 { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
107 { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
108 { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
109 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
110 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
111 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
112 { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
113 { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
117 static struct pci_reg_info regs_bridge[] = {
118 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
119 { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
120 { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
121 { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
122 { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
123 { "IO base", PCI_SIZE_8, PCI_IO_BASE },
124 { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
125 { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
126 { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
127 { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
128 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
129 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
130 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
131 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
132 { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
133 { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
134 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
135 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
136 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
137 { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
141 static struct pci_reg_info regs_cardbus[] = {
142 { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
143 { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
144 { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
145 { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
146 { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
147 { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
148 { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
149 { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
150 { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
151 { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
152 { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
153 { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
154 { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
155 { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
156 { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
157 { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
158 { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
159 { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
160 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
161 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
162 { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
163 { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
164 { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
165 { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
170 * pci_header_show() - Show the header of the specified PCI device.
172 * @dev: Bus+Device+Function number
174 void pci_header_show(pci_dev_t dev)
176 u8 class, header_type;
178 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
179 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
180 pci_show_regs(dev, regs_start);
182 printf(" class code = 0x%.2x (%s)\n", class,
183 pci_class_str(class));
184 pci_show_regs(dev, regs_rest);
186 switch (header_type & 0x03) {
187 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
188 pci_show_regs(dev, regs_normal);
190 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
191 pci_show_regs(dev, regs_bridge);
193 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
194 pci_show_regs(dev, regs_cardbus);
198 printf("unknown header\n");
204 * pci_header_show_brief() - Show the short-form PCI device header
206 * Reads and prints the header of the specified PCI device in short form.
208 * @dev: Bus+Device+Function number
210 void pci_header_show_brief(pci_dev_t dev)
215 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
216 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
217 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
218 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
220 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
222 pci_class_str(class), subclass);
226 * pciinfo() - Show a list of devices on the PCI bus
228 * Show information about devices on PCI bus. Depending on @short_pci_listing
229 * the output will be more or less exhaustive.
231 * @bus_num: The number of the bus to be scanned
232 * @short_pci_listing: true to use short form, showing only a brief header
235 void pciinfo(int bus_num, int short_pci_listing)
237 struct pci_controller *hose = pci_bus_to_hose(bus_num);
240 unsigned char header_type;
241 unsigned short vendor_id;
248 printf("Scanning PCI devices on bus %d\n", bus_num);
250 if (short_pci_listing) {
251 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
252 printf("_____________________________________________________________\n");
255 for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
258 for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
261 * If this is not a multi-function device, we skip
264 if (function && !(header_type & 0x80))
267 dev = PCI_BDF(bus_num, device, function);
269 if (pci_skip_dev(hose, dev))
272 ret = pci_read_config_word(dev, PCI_VENDOR_ID,
276 if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
280 pci_read_config_byte(dev, PCI_HEADER_TYPE,
284 if (short_pci_listing) {
285 printf("%02x.%02x.%02x ", bus_num, device,
287 pci_header_show_brief(dev);
289 printf("\nFound PCI device %02x.%02x.%02x:\n",
290 bus_num, device, function);
291 pci_header_show(dev);
298 printf("Cannot read bus configuration: %d\n", ret);
303 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
305 * @name: Device string in the form "bus.device.function" where each is in hex
306 * @return encoded pci_dev_t or -1 if the string was invalid
308 static pci_dev_t get_pci_dev(char *name)
312 int bdfs[3] = {0,0,0};
317 for (i = 0, iold = 0, n = 0; i < len; i++) {
318 if (name[i] == '.') {
319 memcpy(cnum, &name[iold], i - iold);
320 cnum[i - iold] = '\0';
321 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
325 strcpy(cnum, &name[iold]);
328 bdfs[n] = simple_strtoul(cnum, NULL, 16);
330 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
333 static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
336 #define DISP_LINE_LEN 16
337 ulong i, nbytes, linebytes;
341 byte_size = pci_byte_size(size);
343 length = 0x40 / byte_size; /* Standard PCI config space */
346 * once, and all accesses are with the specified bus width.
348 nbytes = length * byte_size;
350 printf("%08lx:", addr);
351 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
352 for (i = 0; i < linebytes; i += byte_size) {
355 val = pci_read_config(bdf, addr, size);
356 printf(" %0*lx", pci_field_width(size), val);
365 } while (nbytes > 0);
370 static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
373 pci_write_config_dword(bdf, addr, value);
375 else if (size == 2) {
376 ushort val = value & 0xffff;
377 pci_write_config_word(bdf, addr, val);
380 u_char val = value & 0xff;
381 pci_write_config_byte(bdf, addr, val);
386 static int pci_cfg_modify(pci_dev_t bdf, ulong addr, enum pci_size_t size,
387 ulong value, int incrflag)
393 /* Print the address, followed by value. Then accept input for
394 * the next value. A non-converted value exits.
397 printf("%08lx:", addr);
398 val = pci_read_config(bdf, addr, size);
399 printf(" %0*lx", pci_field_width(size), val);
401 nbytes = cli_readline(" ? ");
402 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
403 /* <CR> pressed as only input, don't modify current
404 * location and move to next. "-" pressed will go back.
407 addr += nbytes ? -size : size;
409 /* good enough to not time out */
410 bootretry_reset_cmd_timeout();
412 #ifdef CONFIG_BOOT_RETRY_TIME
413 else if (nbytes == -2) {
414 break; /* timed out, exit the command */
419 i = simple_strtoul(console_buffer, &endp, 16);
420 nbytes = endp - console_buffer;
422 /* good enough to not time out
424 bootretry_reset_cmd_timeout();
425 pci_cfg_write (bdf, addr, size, i);
435 /* PCI Configuration Space access commands
438 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
439 * pci next[.b, .w, .l] bus.device.function [addr]
440 * pci modify[.b, .w, .l] bus.device.function [addr]
441 * pci write[.b, .w, .l] bus.device.function addr value
443 static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
445 ulong addr = 0, value = 0, cmd_size = 0;
446 enum pci_size_t size = PCI_SIZE_32;
457 case 'd': /* display */
459 case 'm': /* modify */
460 case 'w': /* write */
461 /* Check for a size specification. */
462 cmd_size = cmd_get_data_size(argv[1], 4);
463 size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
465 addr = simple_strtoul(argv[3], NULL, 16);
467 value = simple_strtoul(argv[4], NULL, 16);
468 case 'h': /* header */
471 if ((bdf = get_pci_dev(argv[2])) == -1)
474 #ifdef CONFIG_CMD_PCI_ENUM
478 default: /* scan bus */
479 value = 1; /* short listing */
481 if (argv[argc-1][0] == 'l') {
486 busnum = simple_strtoul(argv[1], NULL, 16);
488 pciinfo(busnum, value);
494 switch (argv[1][0]) {
495 case 'h': /* header */
496 pci_header_show(dev);
498 case 'd': /* display */
499 return pci_cfg_display(dev, addr, size, value);
500 #ifdef CONFIG_CMD_PCI_ENUM
502 # ifdef CONFIG_DM_PCI
503 printf("This command is not yet supported with driver model\n");
512 ret = pci_cfg_modify(dev, addr, size, value, 0);
514 case 'm': /* modify */
517 ret = pci_cfg_modify(dev, addr, size, value, 1);
519 case 'w': /* write */
522 ret = pci_cfg_write(dev, addr, size, value);
531 return CMD_RET_USAGE;
534 /***************************************************/
536 #ifdef CONFIG_SYS_LONGHELP
537 static char pci_help_text[] =
539 " - short or long list of PCI devices on bus 'bus'\n"
540 #ifdef CONFIG_CMD_PCI_ENUM
542 " - re-enumerate PCI buses\n"
545 " - show header of PCI device 'bus.device.function'\n"
546 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
547 " - display PCI configuration space (CFG)\n"
548 "pci next[.b, .w, .l] b.d.f address\n"
549 " - modify, read and keep CFG address\n"
550 "pci modify[.b, .w, .l] b.d.f address\n"
551 " - modify, auto increment CFG address\n"
552 "pci write[.b, .w, .l] b.d.f address value\n"
553 " - write to CFG address";
558 "list and access PCI Configuration Space", pci_help_text