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bfin: make env offset sector aligned for bct-brettl2 and ibf-dsp561 boards
[u-boot] / common / cmd_reginfo.c
1 /*
2  * (C) Copyright 2000
3  * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <command.h>
10 #if defined(CONFIG_8xx)
11 #include <mpc8xx.h>
12 #elif defined (CONFIG_4xx)
13 extern void ppc4xx_reginfo(void);
14 #elif defined (CONFIG_5xx)
15 #include <mpc5xx.h>
16 #elif defined (CONFIG_MPC5200)
17 #include <mpc5xxx.h>
18 #elif defined (CONFIG_MPC86xx)
19 extern void mpc86xx_reginfo(void);
20 #elif defined(CONFIG_MPC85xx)
21 extern void mpc85xx_reginfo(void);
22 #endif
23
24 static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
25                        char * const argv[])
26 {
27 #if defined(CONFIG_8xx)
28         volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
29         volatile memctl8xx_t *memctl = &immap->im_memctl;
30         volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
31         volatile sit8xx_t *timers = &immap->im_sit;
32
33         /* Hopefully more PowerPC  knowledgable people will add code to display
34          * other useful registers
35          */
36
37         printf ("\nSystem Configuration registers\n"
38
39                 "\tIMMR\t0x%08X\n", get_immr(0));
40
41         printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
42         printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
43
44         printf("\tSWT\t0x%08X",    sysconf->sc_swt);
45         printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
46
47         printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
48                 sysconf->sc_sipend, sysconf->sc_simask);
49         printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
50                 sysconf->sc_siel, sysconf->sc_sivec);
51         printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
52                 sysconf->sc_tesr, sysconf->sc_sdcr);
53
54         printf ("Memory Controller Registers\n"
55
56                 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
57         printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
58         printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
59         printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
60         printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
61         printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
62         printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
63         printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
64         printf ("\n"
65                 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
66                 memctl->memc_mamr, memctl->memc_mbmr );
67         printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
68                 memctl->memc_mstat, memctl->memc_mptpr );
69         printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
70
71         printf ("\nSystem Integration Timers\n"
72                 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
73                 timers->sit_tbscr, timers->sit_rtcsc);
74         printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
75
76         /*
77          * May be some CPM info here?
78          */
79
80 #elif defined (CONFIG_4xx)
81         ppc4xx_reginfo();
82 #elif defined(CONFIG_5xx)
83
84         volatile immap_t        *immap  = (immap_t *)CONFIG_SYS_IMMR;
85         volatile memctl5xx_t    *memctl = &immap->im_memctl;
86         volatile sysconf5xx_t   *sysconf = &immap->im_siu_conf;
87         volatile sit5xx_t       *timers = &immap->im_sit;
88         volatile car5xx_t       *car = &immap->im_clkrst;
89         volatile uimb5xx_t      *uimb = &immap->im_uimb;
90
91         puts ("\nSystem Configuration registers\n");
92         printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
93         printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
94         printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
95         printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
96         printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
97
98         puts ("\nMemory Controller Registers\n");
99         printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
100         printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
101         printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
102         printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
103         printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
104         printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
105
106         puts ("\nSystem Integration Timers\n");
107         printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
108         printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
109
110         puts ("\nClocks and Reset\n");
111         printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
112
113         puts ("\nU-Bus to IMB3 Bus Interface\n");
114         printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
115         puts ("\n\n");
116
117 #elif defined(CONFIG_MPC5200)
118         puts ("\nMPC5200 registers\n");
119         printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
120         puts ("Memory map registers\n");
121         printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
122                 *(volatile ulong*)MPC5XXX_CS0_START,
123                 *(volatile ulong*)MPC5XXX_CS0_STOP,
124                 *(volatile ulong*)MPC5XXX_CS0_CFG,
125                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
126         printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
127                 *(volatile ulong*)MPC5XXX_CS1_START,
128                 *(volatile ulong*)MPC5XXX_CS1_STOP,
129                 *(volatile ulong*)MPC5XXX_CS1_CFG,
130                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
131         printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
132                 *(volatile ulong*)MPC5XXX_CS2_START,
133                 *(volatile ulong*)MPC5XXX_CS2_STOP,
134                 *(volatile ulong*)MPC5XXX_CS2_CFG,
135                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
136         printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
137                 *(volatile ulong*)MPC5XXX_CS3_START,
138                 *(volatile ulong*)MPC5XXX_CS3_STOP,
139                 *(volatile ulong*)MPC5XXX_CS3_CFG,
140                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
141         printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
142                 *(volatile ulong*)MPC5XXX_CS4_START,
143                 *(volatile ulong*)MPC5XXX_CS4_STOP,
144                 *(volatile ulong*)MPC5XXX_CS4_CFG,
145                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
146         printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
147                 *(volatile ulong*)MPC5XXX_CS5_START,
148                 *(volatile ulong*)MPC5XXX_CS5_STOP,
149                 *(volatile ulong*)MPC5XXX_CS5_CFG,
150                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
151         printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
152                 *(volatile ulong*)MPC5XXX_CS6_START,
153                 *(volatile ulong*)MPC5XXX_CS6_STOP,
154                 *(volatile ulong*)MPC5XXX_CS6_CFG,
155                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
156         printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
157                 *(volatile ulong*)MPC5XXX_CS7_START,
158                 *(volatile ulong*)MPC5XXX_CS7_STOP,
159                 *(volatile ulong*)MPC5XXX_CS7_CFG,
160                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
161         printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
162                 *(volatile ulong*)MPC5XXX_BOOTCS_START,
163                 *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
164                 *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
165                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
166         printf ("\tSDRAMCS0: %08lX\n",
167                 *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
168         printf ("\tSDRAMCS1: %08lX\n",
169                 *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
170 #elif defined(CONFIG_MPC86xx)
171         mpc86xx_reginfo();
172
173 #elif defined(CONFIG_MPC85xx)
174         mpc85xx_reginfo();
175
176 #elif defined(CONFIG_BLACKFIN)
177         puts("\nSystem Configuration registers\n");
178 #ifndef __ADSPBF60x__
179         puts("\nPLL Registers\n");
180         printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
181                 bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
182         printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
183                 bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
184         printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());
185
186         puts("\nEBIU AMC Registers\n");
187         printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
188         printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
189                 bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
190 # ifdef EBIU_MODE
191         printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
192                 bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
193         printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
194                 bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
195 # endif
196
197 # ifdef EBIU_RSTCTL
198         puts("\nEBIU DDR Registers\n");
199         printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
200                 bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
201         printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
202                 bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
203         printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
204                 bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
205         printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
206                 bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
207 # else
208         puts("\nEBIU SDC Registers\n");
209         printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
210                 bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
211         printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
212                 bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
213 # endif
214 #else
215         puts("\nCGU Registers\n");
216         printf("\tCGU_DIV:   0x%08x   CGU_CTL:      0x%08x\n",
217                 bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
218         printf("\tCGU_STAT:  0x%08x   CGU_LOCKCNT:  0x%08x\n",
219                 bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());
220
221         puts("\nSMC DDR Registers\n");
222         printf("\tDDR_CFG:   0x%08x   DDR_TR0:      0x%08x\n",
223                 bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
224         printf("\tDDR_TR1:   0x%08x   DDR_TR2:      0x%08x\n",
225                 bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
226         printf("\tDDR_MR:    0x%08x   DDR_EMR1:     0x%08x\n",
227                 bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
228         printf("\tDDR_CTL:   0x%08x   DDR_STAT:     0x%08x\n",
229                 bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
230         printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
231 #endif
232 #endif /* CONFIG_BLACKFIN */
233
234         return 0;
235 }
236
237  /**************************************************/
238
239 #if defined(CONFIG_CMD_REGINFO)
240 U_BOOT_CMD(
241         reginfo,        2,      1,      do_reginfo,
242         "print register information",
243         ""
244 );
245 #endif