git.sur5r.net Git - u-boot/blob - common/cmd_reginfo.c

   1 /*
   2  * (C) Copyright 2000
   3  * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #if defined(CONFIG_8xx)
  27 #include <mpc8xx.h>
  28 #elif defined (CONFIG_4xx)
  29 extern void ppc4xx_reginfo(void);
  30 #elif defined (CONFIG_5xx)
  31 #include <mpc5xx.h>
  32 #elif defined (CONFIG_MPC5200)
  33 #include <mpc5xxx.h>
  34 #elif defined (CONFIG_MPC86xx)
  35 extern void mpc86xx_reginfo(void);
  36 #elif defined(CONFIG_MPC85xx)
  37 extern void mpc85xx_reginfo(void);
  38 #endif
  39
  40 static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
  41                        char * const argv[])
  42 {
  43 #if defined(CONFIG_8xx)
  44         volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
  45         volatile memctl8xx_t *memctl = &immap->im_memctl;
  46         volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
  47         volatile sit8xx_t *timers = &immap->im_sit;
  48
  49         /* Hopefully more PowerPC  knowledgable people will add code to display
  50          * other useful registers
  51          */
  52
  53         printf ("\nSystem Configuration registers\n"
  54
  55                 "\tIMMR\t0x%08X\n", get_immr(0));
  56
  57         printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
  58         printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
  59
  60         printf("\tSWT\t0x%08X",    sysconf->sc_swt);
  61         printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
  62
  63         printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
  64                 sysconf->sc_sipend, sysconf->sc_simask);
  65         printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
  66                 sysconf->sc_siel, sysconf->sc_sivec);
  67         printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
  68                 sysconf->sc_tesr, sysconf->sc_sdcr);
  69
  70         printf ("Memory Controller Registers\n"
  71
  72                 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
  73         printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
  74         printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
  75         printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
  76         printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
  77         printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
  78         printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
  79         printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
  80         printf ("\n"
  81                 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
  82                 memctl->memc_mamr, memctl->memc_mbmr );
  83         printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
  84                 memctl->memc_mstat, memctl->memc_mptpr );
  85         printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
  86
  87         printf ("\nSystem Integration Timers\n"
  88                 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
  89                 timers->sit_tbscr, timers->sit_rtcsc);
  90         printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
  91
  92         /*
  93          * May be some CPM info here?
  94          */
  95
  96 #elif defined (CONFIG_4xx)
  97         ppc4xx_reginfo();
  98 #elif defined(CONFIG_5xx)
  99
 100         volatile immap_t        *immap  = (immap_t *)CONFIG_SYS_IMMR;
 101         volatile memctl5xx_t    *memctl = &immap->im_memctl;
 102         volatile sysconf5xx_t   *sysconf = &immap->im_siu_conf;
 103         volatile sit5xx_t       *timers = &immap->im_sit;
 104         volatile car5xx_t       *car = &immap->im_clkrst;
 105         volatile uimb5xx_t      *uimb = &immap->im_uimb;
 106
 107         puts ("\nSystem Configuration registers\n");
 108         printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
 109         printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
 110         printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
 111         printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
 112         printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
 113
 114         puts ("\nMemory Controller Registers\n");
 115         printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
 116         printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
 117         printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
 118         printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
 119         printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
 120         printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
 121
 122         puts ("\nSystem Integration Timers\n");
 123         printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
 124         printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
 125
 126         puts ("\nClocks and Reset\n");
 127         printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
 128
 129         puts ("\nU-Bus to IMB3 Bus Interface\n");
 130         printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
 131         puts ("\n\n");
 132
 133 #elif defined(CONFIG_MPC5200)
 134         puts ("\nMPC5200 registers\n");
 135         printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
 136         puts ("Memory map registers\n");
 137         printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 138                 *(volatile ulong*)MPC5XXX_CS0_START,
 139                 *(volatile ulong*)MPC5XXX_CS0_STOP,
 140                 *(volatile ulong*)MPC5XXX_CS0_CFG,
 141                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
 142         printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 143                 *(volatile ulong*)MPC5XXX_CS1_START,
 144                 *(volatile ulong*)MPC5XXX_CS1_STOP,
 145                 *(volatile ulong*)MPC5XXX_CS1_CFG,
 146                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
 147         printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 148                 *(volatile ulong*)MPC5XXX_CS2_START,
 149                 *(volatile ulong*)MPC5XXX_CS2_STOP,
 150                 *(volatile ulong*)MPC5XXX_CS2_CFG,
 151                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
 152         printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 153                 *(volatile ulong*)MPC5XXX_CS3_START,
 154                 *(volatile ulong*)MPC5XXX_CS3_STOP,
 155                 *(volatile ulong*)MPC5XXX_CS3_CFG,
 156                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
 157         printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 158                 *(volatile ulong*)MPC5XXX_CS4_START,
 159                 *(volatile ulong*)MPC5XXX_CS4_STOP,
 160                 *(volatile ulong*)MPC5XXX_CS4_CFG,
 161                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
 162         printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 163                 *(volatile ulong*)MPC5XXX_CS5_START,
 164                 *(volatile ulong*)MPC5XXX_CS5_STOP,
 165                 *(volatile ulong*)MPC5XXX_CS5_CFG,
 166                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
 167         printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 168                 *(volatile ulong*)MPC5XXX_CS6_START,
 169                 *(volatile ulong*)MPC5XXX_CS6_STOP,
 170                 *(volatile ulong*)MPC5XXX_CS6_CFG,
 171                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
 172         printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 173                 *(volatile ulong*)MPC5XXX_CS7_START,
 174                 *(volatile ulong*)MPC5XXX_CS7_STOP,
 175                 *(volatile ulong*)MPC5XXX_CS7_CFG,
 176                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
 177         printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
 178                 *(volatile ulong*)MPC5XXX_BOOTCS_START,
 179                 *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
 180                 *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
 181                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
 182         printf ("\tSDRAMCS0: %08lX\n",
 183                 *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
 184         printf ("\tSDRAMCS1: %08lX\n",
 185                 *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
 186 #elif defined(CONFIG_MPC86xx)
 187         mpc86xx_reginfo();
 188
 189 #elif defined(CONFIG_MPC85xx)
 190         mpc85xx_reginfo();
 191
 192 #elif defined(CONFIG_BLACKFIN)
 193         puts("\nSystem Configuration registers\n");
 194 #ifndef __ADSPBF60x__
 195         puts("\nPLL Registers\n");
 196         printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
 197                 bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
 198         printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
 199                 bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
 200         printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());
 201
 202         puts("\nEBIU AMC Registers\n");
 203         printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
 204         printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
 205                 bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
 206 # ifdef EBIU_MODE
 207         printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
 208                 bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
 209         printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
 210                 bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
 211 # endif
 212
 213 # ifdef EBIU_RSTCTL
 214         puts("\nEBIU DDR Registers\n");
 215         printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
 216                 bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
 217         printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
 218                 bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
 219         printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
 220                 bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
 221         printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
 222                 bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
 223 # else
 224         puts("\nEBIU SDC Registers\n");
 225         printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
 226                 bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
 227         printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
 228                 bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
 229 # endif
 230 #else
 231         puts("\nCGU Registers\n");
 232         printf("\tCGU_DIV:   0x%08x   CGU_CTL:      0x%08x\n",
 233                 bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
 234         printf("\tCGU_STAT:  0x%08x   CGU_LOCKCNT:  0x%08x\n",
 235                 bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());
 236
 237         puts("\nSMC DDR Registers\n");
 238         printf("\tDDR_CFG:   0x%08x   DDR_TR0:      0x%08x\n",
 239                 bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
 240         printf("\tDDR_TR1:   0x%08x   DDR_TR2:      0x%08x\n",
 241                 bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
 242         printf("\tDDR_MR:    0x%08x   DDR_EMR1:     0x%08x\n",
 243                 bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
 244         printf("\tDDR_CTL:   0x%08x   DDR_STAT:     0x%08x\n",
 245                 bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
 246         printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
 247 #endif
 248 #endif /* CONFIG_BLACKFIN */
 249
 250         return 0;
 251 }
 252
 253  /**************************************************/
 254
 255 #if defined(CONFIG_CMD_REGINFO)
 256 U_BOOT_CMD(
 257         reginfo,        2,      1,      do_reginfo,
 258         "print register information",
 259         ""
 260 );
 261 #endif