git.sur5r.net Git - u-boot/blob - common/cmd_tsi148.c

   1 /*
   2  * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
   3  *
   4  * base on universe.h by
   5  *
   6  * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <command.h>
  29 #include <malloc.h>
  30 #include <asm/io.h>
  31 #include <pci.h>
  32
  33 #include <tsi148.h>
  34
  35 #define PCI_VENDOR PCI_VENDOR_ID_TUNDRA
  36 #define PCI_DEVICE PCI_DEVICE_ID_TUNDRA_TSI148
  37
  38 typedef struct _TSI148_DEV TSI148_DEV;
  39
  40 struct _TSI148_DEV {
  41         int           bus;
  42         pci_dev_t     busdevfn;
  43         TSI148       *uregs;
  44         unsigned int  pci_bs;
  45 };
  46
  47 static TSI148_DEV *dev;
  48
  49 /*
  50  * Most of the TSI148 register are BIGENDIAN
  51  * This is the reason for the __raw_writel(htonl(x), x) usage!
  52  */
  53
  54 int tsi148_init(void)
  55 {
  56         int j, result;
  57         pci_dev_t busdevfn;
  58         unsigned int val;
  59
  60         busdevfn = pci_find_device(PCI_VENDOR, PCI_DEVICE, 0);
  61         if (busdevfn == -1) {
  62                 puts("Tsi148: No Tundra Tsi148 found!\n");
  63                 return -1;
  64         }
  65
  66         /* Lets turn Latency off */
  67         pci_write_config_dword(busdevfn, 0x0c, 0);
  68
  69         dev = malloc(sizeof(*dev));
  70         if (NULL == dev) {
  71                 puts("Tsi148: No memory!\n");
  72                 return -1;
  73         }
  74
  75         memset(dev, 0, sizeof(*dev));
  76         dev->busdevfn = busdevfn;
  77
  78         pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val);
  79         val &= ~0xf;
  80         dev->uregs = (TSI148 *)val;
  81
  82         debug("Tsi148: Base    : %p\n", dev->uregs);
  83
  84         /* check mapping */
  85         debug("Tsi148: Read via mapping, PCI_ID = %08X\n",
  86               readl(&dev->uregs->pci_id));
  87         if (((PCI_DEVICE << 16) | PCI_VENDOR) != readl(&dev->uregs->pci_id)) {
  88                 printf("Tsi148: Cannot read PCI-ID via Mapping: %08x\n",
  89                        readl(&dev->uregs->pci_id));
  90                 result = -1;
  91                 goto break_30;
  92         }
  93
  94         debug("Tsi148: PCI_BS = %08X\n", readl(&dev->uregs->pci_mbarl));
  95
  96         dev->pci_bs = readl(&dev->uregs->pci_mbarl);
  97
  98         /* turn off windows */
  99         for (j = 0; j < 8; j++) {
 100                 __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat);
 101                 __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat);
 102         }
 103
 104         /* Tsi148 VME timeout etc */
 105         __raw_writel(htonl(0x00000084), &dev->uregs->vctrl);
 106
 107 #ifdef DEBUG
 108         if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0)
 109                 printf("Tsi148: System Controller!\n");
 110         else
 111                 printf("Tsi148: Not System Controller!\n");
 112 #endif
 113
 114         /*
 115          * Lets turn off interrupts
 116          */
 117         /* Disable interrupts in Tsi148 first */
 118         __raw_writel(htonl(0x00000000), &dev->uregs->inten);
 119         /* Disable interrupt out */
 120         __raw_writel(htonl(0x00000000), &dev->uregs->inteo);
 121         eieio();
 122         /* Reset all IRQ's */
 123         __raw_writel(htonl(0x03ff3f00), &dev->uregs->intc);
 124         /* Map all ints to 0 */
 125         __raw_writel(htonl(0x00000000), &dev->uregs->intm1);
 126         __raw_writel(htonl(0x00000000), &dev->uregs->intm2);
 127         eieio();
 128
 129         val = __raw_readl(&dev->uregs->vstat);
 130         val &= ~(0x00004000);
 131         __raw_writel(val, &dev->uregs->vstat);
 132         eieio();
 133
 134         debug("Tsi148: register struct size %08x\n", sizeof(TSI148));
 135
 136         return 0;
 137
 138  break_30:
 139         free(dev);
 140         dev = NULL;
 141
 142         return result;
 143 }
 144
 145 /*
 146  * Create pci slave window (access: pci -> vme)
 147  */
 148 int tsi148_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr,
 149                             int size, int vam, int vdw)
 150 {
 151         int result, i;
 152         unsigned int ctl = 0;
 153
 154         if (NULL == dev) {
 155                 result = -1;
 156                 goto exit_10;
 157         }
 158
 159         for (i = 0; i < 8; i++) {
 160                 if (0x00000000 == readl(&dev->uregs->outbound[i].otat))
 161                         break;
 162         }
 163
 164         if (i > 7) {
 165                 printf("Tsi148: No Image available\n");
 166                 result = -1;
 167                 goto exit_10;
 168         }
 169
 170         debug("Tsi148: Using image %d\n", i);
 171
 172         printf("Tsi148: Pci addr %08x\n", pciAddr);
 173
 174         __raw_writel(htonl(pciAddr), &dev->uregs->outbound[i].otsal);
 175         __raw_writel(0x00000000, &dev->uregs->outbound[i].otsau);
 176         __raw_writel(htonl(pciAddr + size), &dev->uregs->outbound[i].oteal);
 177         __raw_writel(0x00000000, &dev->uregs->outbound[i].oteau);
 178         __raw_writel(htonl(vmeAddr - pciAddr), &dev->uregs->outbound[i].otofl);
 179         __raw_writel(0x00000000, &dev->uregs->outbound[i].otofu);
 180
 181         switch (vam & VME_AM_Axx) {
 182         case VME_AM_A16:
 183                 ctl = 0x00000000;
 184                 break;
 185         case VME_AM_A24:
 186                 ctl = 0x00000001;
 187                 break;
 188         case VME_AM_A32:
 189                 ctl = 0x00000002;
 190                 break;
 191         }
 192
 193         switch (vam & VME_AM_Mxx) {
 194         case VME_AM_DATA:
 195                 ctl |= 0x00000000;
 196                 break;
 197         case VME_AM_PROG:
 198                 ctl |= 0x00000010;
 199                 break;
 200         }
 201
 202         if (vam & VME_AM_SUP)
 203                 ctl |= 0x00000020;
 204
 205         switch (vdw & VME_FLAG_Dxx) {
 206         case VME_FLAG_D16:
 207                 ctl |= 0x00000000;
 208                 break;
 209         case VME_FLAG_D32:
 210                 ctl |= 0x00000040;
 211                 break;
 212         }
 213
 214         ctl |= 0x80040000;      /* enable, no prefetch */
 215
 216         __raw_writel(htonl(ctl), &dev->uregs->outbound[i].otat);
 217
 218         debug("Tsi148: window-addr                =%p\n",
 219               &dev->uregs->outbound[i].otsau);
 220         debug("Tsi148: pci slave window[%d] attr  =%08x\n",
 221               i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat)));
 222         debug("Tsi148: pci slave window[%d] start =%08x\n",
 223               i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal)));
 224         debug("Tsi148: pci slave window[%d] end   =%08x\n",
 225               i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal)));
 226         debug("Tsi148: pci slave window[%d] offset=%08x\n",
 227               i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl)));
 228
 229         return 0;
 230
 231  exit_10:
 232         return -result;
 233 }
 234
 235 unsigned int tsi148_eval_vam(int vam)
 236 {
 237         unsigned int ctl = 0;
 238
 239         switch (vam & VME_AM_Axx) {
 240         case VME_AM_A16:
 241                 ctl = 0x00000000;
 242                 break;
 243         case VME_AM_A24:
 244                 ctl = 0x00000010;
 245                 break;
 246         case VME_AM_A32:
 247                 ctl = 0x00000020;
 248                 break;
 249         }
 250         switch (vam & VME_AM_Mxx) {
 251         case VME_AM_DATA:
 252                 ctl |= 0x00000001;
 253                 break;
 254         case VME_AM_PROG:
 255                 ctl |= 0x00000002;
 256                 break;
 257         case (VME_AM_PROG | VME_AM_DATA):
 258                 ctl |= 0x00000003;
 259                 break;
 260         }
 261
 262         if (vam & VME_AM_SUP)
 263                 ctl |= 0x00000008;
 264         if (vam & VME_AM_USR)
 265                 ctl |= 0x00000004;
 266
 267         return ctl;
 268 }
 269
 270 /*
 271  * Create vme slave window (access: vme -> pci)
 272  */
 273 int tsi148_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr,
 274                             int size, int vam)
 275 {
 276         int result, i;
 277         unsigned int ctl = 0;
 278
 279         if (NULL == dev) {
 280                 result = -1;
 281                 goto exit_10;
 282         }
 283
 284         for (i = 0; i < 8; i++) {
 285                 if (0x00000000 == readl(&dev->uregs->inbound[i].itat))
 286                         break;
 287         }
 288
 289         if (i > 7) {
 290                 printf("Tsi148: No Image available\n");
 291                 result = -1;
 292                 goto exit_10;
 293         }
 294
 295         debug("Tsi148: Using image %d\n", i);
 296
 297         __raw_writel(htonl(vmeAddr), &dev->uregs->inbound[i].itsal);
 298         __raw_writel(0x00000000, &dev->uregs->inbound[i].itsau);
 299         __raw_writel(htonl(vmeAddr + size), &dev->uregs->inbound[i].iteal);
 300         __raw_writel(0x00000000, &dev->uregs->inbound[i].iteau);
 301         __raw_writel(htonl(pciAddr - vmeAddr), &dev->uregs->inbound[i].itofl);
 302         if (vmeAddr > pciAddr)
 303                 __raw_writel(0xffffffff, &dev->uregs->inbound[i].itofu);
 304         else
 305                 __raw_writel(0x00000000, &dev->uregs->inbound[i].itofu);
 306
 307         ctl = tsi148_eval_vam(vam);
 308         ctl |= 0x80000000;      /* enable */
 309         __raw_writel(htonl(ctl), &dev->uregs->inbound[i].itat);
 310
 311         debug("Tsi148: window-addr                =%p\n",
 312               &dev->uregs->inbound[i].itsau);
 313         debug("Tsi148: vme slave window[%d] attr  =%08x\n",
 314               i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat)));
 315         debug("Tsi148: vme slave window[%d] start =%08x\n",
 316               i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal)));
 317         debug("Tsi148: vme slave window[%d] end   =%08x\n",
 318               i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal)));
 319         debug("Tsi148: vme slave window[%d] offset=%08x\n",
 320               i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl)));
 321
 322         return 0;
 323
 324  exit_10:
 325         return -result;
 326 }
 327
 328 /*
 329  * Create vme slave window (access: vme -> gcsr)
 330  */
 331 int tsi148_vme_gcsr_window(unsigned int vmeAddr, int vam)
 332 {
 333         int result;
 334         unsigned int ctl;
 335
 336         result = 0;
 337
 338         if (NULL == dev) {
 339                 result = 1;
 340         } else {
 341                 __raw_writel(htonl(vmeAddr), &dev->uregs->gbal);
 342                 __raw_writel(0x00000000, &dev->uregs->gbau);
 343
 344                 ctl = tsi148_eval_vam(vam);
 345                 ctl |= 0x00000080;      /* enable */
 346                 __raw_writel(htonl(ctl), &dev->uregs->gcsrat);
 347         }
 348
 349         return result;
 350 }
 351
 352 /*
 353  * Create vme slave window (access: vme -> crcsr)
 354  */
 355 int tsi148_vme_crcsr_window(unsigned int vmeAddr)
 356 {
 357         int result;
 358         unsigned int ctl;
 359
 360         result = 0;
 361
 362         if (NULL == dev) {
 363                 result = 1;
 364         } else {
 365                 __raw_writel(htonl(vmeAddr), &dev->uregs->crol);
 366                 __raw_writel(0x00000000, &dev->uregs->crou);
 367
 368                 ctl = 0x00000080;       /* enable */
 369                 __raw_writel(htonl(ctl), &dev->uregs->crat);
 370         }
 371
 372         return result;
 373 }
 374
 375 /*
 376  * Create vme slave window (access: vme -> crg)
 377  */
 378 int tsi148_vme_crg_window(unsigned int vmeAddr, int vam)
 379 {
 380         int result;
 381         unsigned int ctl;
 382
 383         result = 0;
 384
 385         if (NULL == dev) {
 386                 result = 1;
 387         } else {
 388                 __raw_writel(htonl(vmeAddr), &dev->uregs->cbal);
 389                 __raw_writel(0x00000000, &dev->uregs->cbau);
 390
 391                 ctl = tsi148_eval_vam(vam);
 392                 ctl |= 0x00000080;      /* enable */
 393                 __raw_writel(htonl(ctl), &dev->uregs->crgat);
 394         }
 395
 396         return result;
 397 }
 398
 399 /*
 400  * Tundra Tsi148 configuration
 401  */
 402 int do_tsi148(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 403 {
 404         ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, vdw = 0;
 405         char cmd = 'x';
 406
 407         /* get parameter */
 408         if (argc > 1)
 409                 cmd = argv[1][0];
 410         if (argc > 2)
 411                 addr1 = simple_strtoul(argv[2], NULL, 16);
 412         if (argc > 3)
 413                 addr2 = simple_strtoul(argv[3], NULL, 16);
 414         if (argc > 4)
 415                 size = simple_strtoul(argv[4], NULL, 16);
 416         if (argc > 5)
 417                 vam = simple_strtoul(argv[5], NULL, 16);
 418         if (argc > 6)
 419                 vdw = simple_strtoul(argv[6], NULL, 16);
 420
 421         switch (cmd) {
 422         case 'c':
 423                 if (strcmp(argv[1], "crg") == 0) {
 424                         vam = addr2;
 425                         printf("Tsi148: Configuring VME CRG Window "
 426                                "(VME->CRG):\n");
 427                         printf("  vme=%08lx vam=%02lx\n", addr1, vam);
 428                         tsi148_vme_crg_window(addr1, vam);
 429                 } else {
 430                         printf("Tsi148: Configuring VME CR/CSR Window "
 431                                "(VME->CR/CSR):\n");
 432                         printf("  pci=%08lx\n", addr1);
 433                         tsi148_vme_crcsr_window(addr1);
 434                 }
 435                 break;
 436         case 'i':               /* init */
 437                 tsi148_init();
 438                 break;
 439         case 'g':
 440                 vam = addr2;
 441                 printf("Tsi148: Configuring VME GCSR Window (VME->GCSR):\n");
 442                 printf("  vme=%08lx vam=%02lx\n", addr1, vam);
 443                 tsi148_vme_gcsr_window(addr1, vam);
 444                 break;
 445         case 'v':               /* vme */
 446                 printf("Tsi148: Configuring VME Slave Window (VME->PCI):\n");
 447                 printf("  vme=%08lx pci=%08lx size=%08lx vam=%02lx\n",
 448                        addr1, addr2, size, vam);
 449                 tsi148_vme_slave_window(addr1, addr2, size, vam);
 450                 break;
 451         case 'p':               /* pci */
 452                 printf("Tsi148: Configuring PCI Slave Window (PCI->VME):\n");
 453                 printf("  pci=%08lx vme=%08lx size=%08lx vam=%02lx vdw=%02lx\n",
 454                        addr1, addr2, size, vam, vdw);
 455                 tsi148_pci_slave_window(addr1, addr2, size, vam, vdw);
 456                 break;
 457         default:
 458                 printf("Tsi148: Command %s not supported!\n", argv[1]);
 459         }
 460
 461         return 0;
 462 }
 463
 464 U_BOOT_CMD(
 465         tsi148, 7,      1,      do_tsi148,
 466         "initialize and configure Turndra Tsi148\n",
 467         "init\n"
 468         "    - initialize tsi148\n"
 469         "tsi148 vme   [vme_addr] [pci_addr] [size] [vam]\n"
 470         "    - create vme slave window (access: vme->pci)\n"
 471         "tsi148 pci   [pci_addr] [vme_addr] [size] [vam] [vdw]\n"
 472         "    - create pci slave window (access: pci->vme)\n"
 473         "tsi148 crg   [vme_addr] [vam]\n"
 474         "    - create vme slave window: (access vme->CRG\n"
 475         "tsi148 crcsr [pci_addr]\n"
 476         "    - create vme slave window: (access vme->CR/CSR\n"
 477         "tsi148 gcsr  [vme_addr] [vam]\n"
 478         "    - create vme slave window: (access vme->GCSR\n"
 479         "    [vam] = VMEbus Address-Modifier:  01 -> A16 Address Space\n"
 480         "                                      02 -> A24 Address Space\n"
 481         "                                      03 -> A32 Address Space\n"
 482         "                                      04 -> Usr        AM Code\n"
 483         "                                      08 -> Supervisor AM Code\n"
 484         "                                      10 -> Data AM Code\n"
 485         "                                      20 -> Program AM Code\n"
 486         "    [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n"
 487         "                                      03 -> D32 Data Width\n"
 488 );