]> git.sur5r.net Git - u-boot/blob - common/spl/spl_atf.c
dm: replace dm_dbg() with pr_debug()
[u-boot] / common / spl / spl_atf.c
1 /*
2  * Reference to the ARM TF Project,
3  * plat/arm/common/arm_bl2_setup.c
4  * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
5  * reserved.
6  * Copyright (C) 2016 Rockchip Electronic Co.,Ltd
7  * Written by Kever Yang <kever.yang@rock-chips.com>
8  *
9  * SPDX-License-Identifier:     BSD-3-Clause
10  */
11
12 #include <common.h>
13 #include <atf_common.h>
14 #include <errno.h>
15 #include <spl.h>
16
17 static struct bl2_to_bl31_params_mem bl31_params_mem;
18 static struct bl31_params *bl2_to_bl31_params;
19
20 /**
21  * bl2_plat_get_bl31_params() - prepare params for bl31.
22  *
23  * This function assigns a pointer to the memory that the platform has kept
24  * aside to pass platform specific and trusted firmware related information
25  * to BL31. This memory is allocated by allocating memory to
26  * bl2_to_bl31_params_mem structure which is a superset of all the
27  * structure whose information is passed to BL31
28  * NOTE: This function should be called only once and should be done
29  * before generating params to BL31
30  *
31  * @return bl31 params structure pointer
32  */
33 struct bl31_params *bl2_plat_get_bl31_params(void)
34 {
35         struct entry_point_info *bl33_ep_info;
36
37         /*
38          * Initialise the memory for all the arguments that needs to
39          * be passed to BL31
40          */
41         memset(&bl31_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem));
42
43         /* Assign memory for TF related information */
44         bl2_to_bl31_params = &bl31_params_mem.bl31_params;
45         SET_PARAM_HEAD(bl2_to_bl31_params, ATF_PARAM_BL31, ATF_VERSION_1, 0);
46
47         /* Fill BL31 related information */
48         SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info,
49                        ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
50
51         /* Fill BL32 related information if it exists */
52 #ifdef BL32_BASE
53         bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
54         SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, ATF_PARAM_EP,
55                        ATF_VERSION_1, 0);
56         bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
57         SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
58                        ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
59 #endif /* BL32_BASE */
60
61         /* Fill BL33 related information */
62         bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
63         bl33_ep_info = &bl31_params_mem.bl33_ep_info;
64         SET_PARAM_HEAD(bl33_ep_info, ATF_PARAM_EP, ATF_VERSION_1,
65                        ATF_EP_NON_SECURE);
66
67         /* BL33 expects to receive the primary CPU MPID (through x0) */
68         bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
69         bl33_ep_info->pc = CONFIG_SYS_TEXT_BASE;
70         bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
71                                      DISABLE_ALL_EXECPTIONS);
72
73         bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
74         SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info,
75                        ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
76
77         return bl2_to_bl31_params;
78 }
79
80 void raw_write_daif(unsigned int daif)
81 {
82         __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
83 }
84
85 void bl31_entry(void)
86 {
87         struct bl31_params *bl31_params;
88         void (*entry)(struct bl31_params *params, void *plat_params) = NULL;
89
90         bl31_params = bl2_plat_get_bl31_params();
91         entry = (void *)CONFIG_SPL_ATF_TEXT_BASE;
92
93         raw_write_daif(SPSR_EXCEPTION_MASK);
94         dcache_disable();
95
96         entry(bl31_params, NULL);
97 }