git.sur5r.net Git - u-boot/blob - configs/chromebook_link_defconfig

   1 CONFIG_X86=y
   2 CONFIG_SYS_MALLOC_F_LEN=0x1800
   3 CONFIG_DM_I2C=y
   4 CONFIG_VENDOR_GOOGLE=y
   5 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
   6 CONFIG_TARGET_CHROMEBOOK_LINK=y
   7 CONFIG_ENABLE_MRC_CACHE=y
   8 CONFIG_HAVE_MRC=y
   9 CONFIG_SMP=y
  10 CONFIG_HAVE_VGA_BIOS=y
  11 CONFIG_FIT=y
  12 CONFIG_BOOTSTAGE=y
  13 CONFIG_BOOTSTAGE_REPORT=y
  14 CONFIG_CMD_CPU=y
  15 # CONFIG_CMD_IMLS is not set
  16 # CONFIG_CMD_FLASH is not set
  17 CONFIG_CMD_GPIO=y
  18 # CONFIG_CMD_SETEXPR is not set
  19 # CONFIG_CMD_NFS is not set
  20 CONFIG_CMD_BOOTSTAGE=y
  21 CONFIG_CMD_TPM=y
  22 CONFIG_CMD_TPM_TEST=y
  23 CONFIG_OF_CONTROL=y
  24 CONFIG_REGMAP=y
  25 CONFIG_SYSCON=y
  26 CONFIG_CPU=y
  27 CONFIG_SYS_I2C_INTEL=y
  28 CONFIG_CMD_CROS_EC=y
  29 CONFIG_CROS_EC=y
  30 CONFIG_CROS_EC_LPC=y
  31 CONFIG_SPI_FLASH=y
  32 CONFIG_SPI_FLASH_GIGADEVICE=y
  33 CONFIG_SPI_FLASH_MACRONIX=y
  34 CONFIG_SPI_FLASH_WINBOND=y
  35 CONFIG_DM_PCI=y
  36 CONFIG_DM_RTC=y
  37 CONFIG_DEBUG_UART=y
  38 CONFIG_DEBUG_UART_BASE=0x3f8
  39 CONFIG_DEBUG_UART_CLOCK=1843200
  40 CONFIG_DEBUG_UART_BOARD_INIT=y
  41 CONFIG_SYS_NS16550=y
  42 CONFIG_ICH_SPI=y
  43 CONFIG_TIMER=y
  44 CONFIG_TPM_TIS_LPC=y
  45 CONFIG_USB=y
  46 CONFIG_DM_USB=y
  47 CONFIG_VIDEO_VESA=y
  48 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
  49 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
  50 CONFIG_USE_PRIVATE_LIBGCC=y
  51 CONFIG_TPM=y