]> git.sur5r.net Git - u-boot/blob - configs/minnowmax_defconfig
arm: socfpga: cyclone5: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS
[u-boot] / configs / minnowmax_defconfig
1 CONFIG_X86=y
2 CONFIG_VENDOR_INTEL=y
3 CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
4 CONFIG_TARGET_MINNOWMAX=y
5 CONFIG_HAVE_INTEL_ME=y
6 CONFIG_ENABLE_MRC_CACHE=y
7 CONFIG_SMP=y
8 CONFIG_HAVE_VGA_BIOS=y
9 CONFIG_GENERATE_PIRQ_TABLE=y
10 CONFIG_GENERATE_MP_TABLE=y
11 CONFIG_CMD_CPU=y
12 # CONFIG_CMD_IMLS is not set
13 # CONFIG_CMD_FLASH is not set
14 CONFIG_CMD_GPIO=y
15 # CONFIG_CMD_SETEXPR is not set
16 # CONFIG_CMD_NFS is not set
17 CONFIG_BOOTSTAGE=y
18 CONFIG_BOOTSTAGE_REPORT=y
19 CONFIG_CMD_BOOTSTAGE=y
20 CONFIG_OF_CONTROL=y
21 CONFIG_CPU=y
22 CONFIG_SPI_FLASH=y
23 CONFIG_SPI_FLASH_GIGADEVICE=y
24 CONFIG_SPI_FLASH_MACRONIX=y
25 CONFIG_SPI_FLASH_STMICRO=y
26 CONFIG_SPI_FLASH_WINBOND=y
27 CONFIG_DM_ETH=y
28 CONFIG_DM_PCI=y
29 CONFIG_DM_RTC=y
30 CONFIG_DEBUG_UART=y
31 CONFIG_DEBUG_UART_BASE=0x3f8
32 CONFIG_DEBUG_UART_CLOCK=1843200
33 CONFIG_SYS_NS16550=y
34 CONFIG_ICH_SPI=y
35 CONFIG_TIMER=y
36 CONFIG_USB=y
37 CONFIG_DM_USB=y
38 CONFIG_VIDEO_VESA=y
39 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
40 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
41 CONFIG_USE_PRIVATE_LIBGCC=y
42 CONFIG_SYS_VSNPRINTF=y