git.sur5r.net Git - u-boot/blob - configs/socfpga_sr1500_defconfig

   1 CONFIG_ARM=y
   2 CONFIG_ARCH_SOCFPGA=y
   3 CONFIG_SYS_MALLOC_F_LEN=0x2000
   4 CONFIG_TARGET_SOCFPGA_SR1500=y
   5 CONFIG_SPL_STACK_R_ADDR=0x00800000
   6 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
   7 CONFIG_FIT=y
   8 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
   9 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
  10 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
  11 CONFIG_SYS_CONSOLE_INFO_QUIET=y
  12 CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
  13 CONFIG_VERSION_VARIABLE=y
  14 # CONFIG_DISPLAY_BOARDINFO is not set
  15 CONFIG_BOARD_EARLY_INIT_F=y
  16 CONFIG_SPL=y
  17 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
  18 CONFIG_SPL_STACK_R=y
  19 CONFIG_HUSH_PARSER=y
  20 CONFIG_CMD_BOOTZ=y
  21 # CONFIG_CMD_IMLS is not set
  22 CONFIG_CMD_ASKENV=y
  23 CONFIG_CMD_GREPENV=y
  24 CONFIG_CMD_MEMTEST=y
  25 # CONFIG_CMD_FLASH is not set
  26 CONFIG_CMD_MMC=y
  27 CONFIG_CMD_SF=y
  28 CONFIG_CMD_SPI=y
  29 CONFIG_CMD_I2C=y
  30 CONFIG_CMD_GPIO=y
  31 CONFIG_CMD_DHCP=y
  32 CONFIG_CMD_MII=y
  33 CONFIG_CMD_PING=y
  34 CONFIG_CMD_CACHE=y
  35 CONFIG_CMD_TIME=y
  36 CONFIG_CMD_EXT4=y
  37 CONFIG_CMD_EXT4_WRITE=y
  38 CONFIG_CMD_FAT=y
  39 CONFIG_CMD_FS_GENERIC=y
  40 CONFIG_CMD_UBI=y
  41 CONFIG_SPL_DM=y
  42 CONFIG_SPL_DM_SEQ_ALIAS=y
  43 CONFIG_DM_GPIO=y
  44 CONFIG_DWAPB_GPIO=y
  45 CONFIG_SYS_I2C_DW=y
  46 CONFIG_DM_MMC=y
  47 CONFIG_MMC_DW=y
  48 CONFIG_SPI_FLASH=y
  49 CONFIG_SPI_FLASH_BAR=y
  50 CONFIG_SPI_FLASH_STMICRO=y
  51 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  52 CONFIG_DM_ETH=y
  53 CONFIG_ETH_DESIGNWARE=y
  54 CONFIG_SYS_NS16550=y
  55 CONFIG_CADENCE_QSPI=y
  56 CONFIG_USE_TINY_PRINTF=y