]> git.sur5r.net Git - u-boot/blob - configs/zynq_zed_defconfig
spl: fit: move fdt_record_loadable out of ARCH_FIXUP_FDT_MEMORY guard
[u-boot] / configs / zynq_zed_defconfig
1 CONFIG_ARM=y
2 CONFIG_ARCH_ZYNQ=y
3 CONFIG_SYS_TEXT_BASE=0x4000000
4 CONFIG_SPL_STACK_R_ADDR=0x200000
5 CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
6 CONFIG_DISTRO_DEFAULTS=y
7 CONFIG_FIT=y
8 CONFIG_FIT_SIGNATURE=y
9 CONFIG_FIT_VERBOSE=y
10 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
11 # CONFIG_DISPLAY_CPUINFO is not set
12 CONFIG_SPL=y
13 CONFIG_SPL_STACK_R=y
14 CONFIG_SPL_OS_BOOT=y
15 CONFIG_SYS_PROMPT="Zynq> "
16 CONFIG_CMD_THOR_DOWNLOAD=y
17 CONFIG_CMD_DFU=y
18 # CONFIG_CMD_FLASH is not set
19 CONFIG_CMD_FPGA_LOADBP=y
20 CONFIG_CMD_FPGA_LOADFS=y
21 CONFIG_CMD_FPGA_LOADMK=y
22 CONFIG_CMD_FPGA_LOADP=y
23 CONFIG_CMD_GPIO=y
24 CONFIG_CMD_MMC=y
25 CONFIG_CMD_SF=y
26 CONFIG_CMD_USB=y
27 # CONFIG_CMD_SETEXPR is not set
28 CONFIG_CMD_TFTPPUT=y
29 CONFIG_CMD_CACHE=y
30 CONFIG_CMD_EXT4_WRITE=y
31 CONFIG_ENV_IS_IN_SPI_FLASH=y
32 CONFIG_NET_RANDOM_ETHADDR=y
33 CONFIG_SPL_DM_SEQ_ALIAS=y
34 CONFIG_DFU_MMC=y
35 CONFIG_DFU_RAM=y
36 CONFIG_FPGA_XILINX=y
37 CONFIG_DM_GPIO=y
38 CONFIG_MMC_SDHCI=y
39 CONFIG_MMC_SDHCI_ZYNQ=y
40 CONFIG_SPI_FLASH=y
41 CONFIG_SPI_FLASH_BAR=y
42 CONFIG_SPI_FLASH_SPANSION=y
43 CONFIG_SPI_FLASH_STMICRO=y
44 CONFIG_SPI_FLASH_WINBOND=y
45 CONFIG_PHY_MARVELL=y
46 CONFIG_PHY_REALTEK=y
47 CONFIG_PHY_XILINX=y
48 CONFIG_ZYNQ_GEM=y
49 CONFIG_ZYNQ_SERIAL=y
50 CONFIG_ZYNQ_QSPI=y
51 CONFIG_USB=y
52 CONFIG_USB_EHCI_HCD=y
53 CONFIG_USB_ULPI_VIEWPORT=y
54 CONFIG_USB_ULPI=y
55 CONFIG_USB_STORAGE=y
56 CONFIG_USB_GADGET=y
57 CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
58 CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
59 CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
60 CONFIG_CI_UDC=y
61 CONFIG_USB_GADGET_DOWNLOAD=y
62 CONFIG_USB_FUNCTION_THOR=y