1 /******************************************************************************
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19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33 ******************************************************************************/
35 #ifndef OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H
36 #define OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H
45 #if defined(__MSP432E4X__)
46 #include "msp432e4x.h"
47 #elif defined(__MSP432P401X__)
48 #include "msp432p401x.h"
49 #elif defined(__MSP432P411X__)
50 #include "msp432p411x.h"
52 #error "Failed to match a device specific include file"
55 /* Structure type to access the System Control Block (SCB). */
57 volatile uint32_t CPUID; /* CPUID Base Register */
58 volatile uint32_t ICSR; /* Interrupt Control and State Register */
59 volatile uint32_t VTOR; /* Vector Table Offset Register */
60 volatile uint32_t AIRCR; /* Application Interrupt and Reset Control */
61 volatile uint32_t SCR; /* System Control Register */
62 volatile uint32_t CCR; /* Configuration Control Register */
63 volatile uint8_t SHP[12U]; /* System Handlers Priority Registers */
64 volatile uint32_t SHCSR; /* System Handler Control and State */
65 volatile uint32_t CFSR; /* Configurable Fault Status Register */
66 volatile uint32_t HFSR; /* HardFault Status Register */
67 volatile uint32_t DFSR; /* Debug Fault Status Register */
68 volatile uint32_t MMFAR; /* MemManage Fault Address Register */
69 volatile uint32_t BFAR; /* BusFault Address Register */
70 volatile uint32_t AFSR; /* Auxiliary Fault Status Register */
71 volatile uint32_t PFR[2U]; /* Processor Feature Register */
72 volatile uint32_t DFR; /* Debug Feature Register */
73 volatile uint32_t ADR; /* Auxiliary Feature Register */
74 volatile uint32_t MMFR[4U]; /* Memory Model Feature Register */
75 volatile uint32_t ISAR[5U]; /* Instruction Set Attributes Register */
76 uint32_t RESERVED0[5U];
77 volatile uint32_t CPACR; /* Coprocessor Access Control Register */
80 /* SCB:SCR register bits */
81 #define SCB_SCR_SLEEPDEEP_POS 2U
82 #define SCB_SCR_SLEEPDEEP_MSK (1UL << SCB_SCR_SLEEPDEEP_POS)
84 /* Memory mapping of Core Hardware */
85 #define SCS_BASE (0xE000E000UL) /* System Control Space Base Address */
86 #define SCB_BASE (SCS_BASE + 0x0D00UL) /* System Control Block Base Address */
87 #define SCB ((struct SCB_Type *)SCB_BASE) /* SCB configuration struct */
89 /* Definitions of standard bits */
90 #define BIT0 (uint16_t)(0x0001)
91 #define BIT1 (uint16_t)(0x0002)
92 #define BIT2 (uint16_t)(0x0004)
93 #define BIT3 (uint16_t)(0x0008)
94 #define BIT4 (uint16_t)(0x0010)
95 #define BIT5 (uint16_t)(0x0020)
96 #define BIT6 (uint16_t)(0x0040)
97 #define BIT7 (uint16_t)(0x0080)
98 #define BIT8 (uint16_t)(0x0100)
99 #define BIT9 (uint16_t)(0x0200)
100 #define BITA (uint16_t)(0x0400)
101 #define BITB (uint16_t)(0x0800)
102 #define BITC (uint16_t)(0x1000)
103 #define BITD (uint16_t)(0x2000)
104 #define BITE (uint16_t)(0x4000)
105 #define BITF (uint16_t)(0x8000)
106 #define BIT(x) ((uint16_t)1 << (x))
108 /* CPU Module prototypes */
109 extern uint32_t cpu_cpsid(void);
110 extern void cpu_wfi(void);
112 /* Clock Signal Module constants */
113 #define CS_DCO_FREQUENCY_3 CS_CTL0_DCORSEL_1
114 #define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4
116 /* Power Control Module constants */
117 #define PCM_KEY 0x695A0000
118 #define PCM_AM_LDO_VCORE0 0x00
119 #define PCM_AM_LDO_VCORE1 0x01
120 #define PCM_AM_DCDC_VCORE0 0x04
121 #define PCM_AM_DCDC_VCORE1 0x05
122 #define PCM_AM_LF_VCORE0 0x08
123 #define PCM_AM_LF_VCORE1 0x09
124 #define PCM_LPM0_LDO_VCORE0 0x10
125 #define PCM_LPM0_LDO_VCORE1 0x11
126 #define PCM_LPM0_DCDC_VCORE0 0x14
127 #define PCM_LPM0_DCDC_VCORE1 0x15
128 #define PCM_LPM0_LF_VCORE0 0x18
129 #define PCM_LPM0_LF_VCORE1 0x19
130 #define PCM_LPM3 0x20
131 #define PCM_LPM4 0x21
132 #define PCM_LPM35_VCORE0 0xC0
133 #define PCM_LPM45 0xA0
134 #define PCM_VCORE0 0x00
135 #define PCM_VCORE1 0x01
136 #define PCM_VCORELPM3 0x02
137 #define PCM_LDO_MODE 0x00
138 #define PCM_DCDC_MODE 0x01
139 #define PCM_LF_MODE 0x02
141 /* Power Control Module prototypes */
142 extern bool pcm_set_core_voltage_level(uint_fast8_t voltage_level);
143 extern uint8_t pcm_get_core_voltage_level(void);
144 extern bool pcm_set_power_mode(uint_fast8_t power_mode);
145 extern uint8_t pcm_get_power_mode(void);
146 extern bool pcm_set_power_state(uint_fast8_t power_state);
147 extern uint8_t pcm_get_power_state(void);
148 extern bool pcm_shutdown_device(uint32_t shutdown_mode);
149 extern bool pcm_goto_lpm0(void);
150 extern bool pcm_goto_lpm3(void);
151 extern bool pcm_goto_lpm4(void);
153 /* ROM API Function Pointers */
154 #define ROM_API_TABLE ((unsigned long *)0x02000800)
155 #define ROM_FLASH_CTL_TABLE ((unsigned long *)(ROM_API_TABLE[7]))
156 #define ROM_PCM_TABLE ((unsigned long *)(ROM_API_TABLE[13]))
157 #define ROM_WDT_TABLE ((unsigned long *)(ROM_API_TABLE[25]))
158 #define ROM_SYS_CTL_A_TABLE ((unsigned long *)(ROM_API_TABLE[26]))
159 #define ROM_FLASH_CTL_A_TABLE ((unsigned long *)(ROM_API_TABLE[27]))
161 #if defined(__MSP432P401X__)
162 #define ROM_FLASH_CTL_UNPROTECT_SECTOR \
163 ((bool (*)(uint_fast8_t memory_space, \
164 uint32_t sector_mask))ROM_FLASH_CTL_TABLE[4])
166 #if defined(__MSP432P401X__)
167 #define ROM_FLASH_CTL_PROTECT_SECTOR \
168 ((bool (*)(uint_fast8_t memory_space, \
169 uint32_t sector_mask))ROM_FLASH_CTL_TABLE[5])
171 #if defined(__MSP432P401X__)
172 #define ROM_FLASH_CTL_PERFORM_MASS_ERASE \
173 ((bool (*)(void))ROM_FLASH_CTL_TABLE[8])
175 #if defined(__MSP432P401X__)
176 #define ROM_FLASH_CTL_ERASE_SECTOR \
177 ((bool (*)(uint32_t addr))ROM_FLASH_CTL_TABLE[9])
179 #if defined(__MSP432P401X__)
180 #define ROM_FLASH_CTL_PROGRAM_MEMORY \
181 ((bool (*)(void *src, void *dest, uint32_t length))ROM_FLASH_CTL_TABLE[10])
183 #if defined(__MSP432P401X__)
184 #define ROM_FLASH_CTL_SET_WAIT_STATE \
185 ((void (*)(uint32_t bank, uint32_t wait_state))ROM_FLASH_CTL_TABLE[21])
187 #if defined(__MSP432P401X__)
188 #define ROM_FLASH_CTL_GET_WAIT_STATE \
189 ((uint32_t (*)(uint32_t bank))ROM_FLASH_CTL_TABLE[22])
191 #if defined(__MSP432P401X__)
192 #define ROM_PCM_SET_CORE_VOLTAGE_LEVEL \
193 ((bool (*)(uint_fast8_t voltage_level))ROM_PCM_TABLE[0])
195 #if defined(__MSP432P401X__)
196 #define ROM_PCM_GET_CORE_VOLTAGE_LEVEL \
197 ((uint8_t (*)(void))ROM_PCM_TABLE[1])
199 #if defined(__MSP432P401X__)
200 #define ROM_PCM_SET_POWER_STATE \
201 ((bool (*)(uint_fast8_t power_state))ROM_PCM_TABLE[6])
203 #if defined(__MSP432P401X__)
204 #define ROM_PCM_GET_POWER_STATE \
205 ((uint8_t (*)(void))ROM_PCM_TABLE[8])
207 #if defined(__MSP432P401X__) || defined(__MSP432P411X__)
208 #define ROM_WDT_A_HOLD_TIMER \
209 ((void (*)(void))ROM_WDT_TABLE[0])
211 #if defined(__MSP432P411X__)
212 #define ROM_SYS_CTL_A_GET_FLASH_SIZE \
213 ((uint_least32_t (*)(void))ROM_SYS_CTL_A_TABLE[1])
215 #if defined(__MSP432P411X__)
216 #define ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE \
217 ((uint_least32_t (*)(void))ROM_SYS_CTL_A_TABLE[18])
219 #if defined(__MSP432P411X__)
220 #define ROM_FLASH_CTL_A_UNPROTECT_MEMORY \
221 ((bool (*)(uint32_t start_addr, uint32_t end_addr))ROM_FLASH_CTL_A_TABLE[4])
223 #if defined(__MSP432P411X__)
224 #define ROM_FLASH_CTL_A_PROTECT_MEMORY \
225 ((bool (*)(uint32_t start_addr, uint32_t end_addr))ROM_FLASH_CTL_A_TABLE[5])
227 #if defined(__MSP432P411X__)
228 #define ROM_FLASH_CTL_A_PERFORM_MASS_ERASE \
229 ((bool (*)(void))ROM_FLASH_CTL_A_TABLE[8])
231 #if defined(__MSP432P411X__)
232 #define ROM_FLASH_CTL_A_ERASE_SECTOR \
233 ((bool (*)(uint32_t addr))ROM_FLASH_CTL_A_TABLE[9])
235 #if defined(__MSP432P411X__)
236 #define ROM_FLASH_CTL_A_PROGRAM_MEMORY \
237 ((bool (*)(void *src, void *dest, uint32_t length)) \
238 ROM_FLASH_CTL_A_TABLE[10])
240 #if defined(__MSP432P411X__)
241 #define ROM_FLASH_CTL_A_SET_WAIT_STATE \
242 ((void (*)(uint32_t bank, uint32_t wait_state))ROM_FLASH_CTL_A_TABLE[21])
244 #if defined(__MSP432P411X__)
245 #define ROM_FLASH_CTL_A_GET_WAIT_STATE \
246 ((uint32_t (*)(uint32_t bank))ROM_FLASH_CTL_A_TABLE[22])
249 /* Map API functions to ROM or locally built functions */
250 #ifdef ROM_FLASH_CTL_UNPROTECT_SECTOR
251 #define MAP_FLASH_CTL_UNPROTECT_SECTOR ROM_FLASH_CTL_UNPROTECT_SECTOR
253 #define MAP_FLASH_CTL_UNPROTECT_SECTOR flash_ctl_unprotect_sector
255 #ifdef ROM_FLASH_CTL_PROTECT_SECTOR
256 #define MAP_FLASH_CTL_PROTECT_SECTOR ROM_FLASH_CTL_PROTECT_SECTOR
258 #define MAP_FLASH_CTL_PROTECT_SECTOR flash_ctl_protect_sector
260 #ifdef ROM_FLASH_CTL_PERFORM_MASS_ERASE
261 #define MAP_FLASH_CTL_PERFORM_MASS_ERASE ROM_FLASH_CTL_PERFORM_MASS_ERASE
263 #define MAP_FLASH_CTL_PERFORM_MASS_ERASE flash_ctl_perform_mass_erase
265 #ifdef ROM_FLASH_CTL_ERASE_SECTOR
266 #define MAP_FLASH_CTL_ERASE_SECTOR ROM_FLASH_CTL_ERASE_SECTOR
268 #define MAP_FLASH_CTL_ERASE_SECTOR flash_ctl_erase_sector
270 #ifdef ROM_FLASH_CTL_PROGRAM_MEMORY
271 #define MAP_FLASH_CTL_PROGRAM_MEMORY ROM_FLASH_CTL_PROGRAM_MEMORY
273 #define MAP_FLASH_CTL_PROGRAM_MEMORY flash_ctl_program_memory
275 #ifdef ROM_FLASH_CTL_SET_WAIT_STATE
276 #define MAP_FLASH_CTL_SET_WAIT_STATE ROM_FLASH_CTL_SET_WAIT_STATE
278 #define MAP_FLASH_CTL_SET_WAIT_STATE flash_ctl_set_wait_state
280 #ifdef ROM_FLASH_CTL_GET_WAIT_STATE
281 #define MAP_FLASH_CTL_GET_WAIT_STATE ROM_FLASH_CTL_GET_WAIT_STATE
283 #define MAP_FLASH_CTL_GET_WAIT_STATE flash_ctl_get_wait_state
285 #ifdef ROM_PCM_SET_CORE_VOLTAGE_LEVEL
286 #define MAP_PCM_SET_CORE_VOLTAGE_LEVEL ROM_PCM_SET_CORE_VOLTAGE_LEVEL
288 #define MAP_PCM_SET_CORE_VOLTAGE_LEVEL pcm_set_core_voltage_level
290 #ifdef ROM_PCM_GET_CORE_VOLTAGE_LEVEL
291 #define MAP_PCM_GET_CORE_VOLTAGE_LEVEL ROM_PCM_GET_CORE_VOLTAGE_LEVEL
293 #define MAP_PCM_GET_CORE_VOLTAGE_LEVEL pcm_get_core_voltage_level
295 #ifdef ROM_PCM_SET_POWER_STATE
296 #define MAP_PCM_SET_POWER_STATE ROM_PCM_SET_POWER_STATE
298 #define MAP_PCM_SET_POWER_STATE pcm_set_power_state
300 #ifdef ROM_PCM_GET_POWER_STATE
301 #define MAP_PCM_GET_POWER_STATE ROM_PCM_GET_POWER_STATE
303 #define MAP_PCM_GET_POWER_STATE pcm_get_power_state
305 #ifdef ROM_WDT_A_HOLD_TIMER
306 #define MAP_WDT_A_HOLD_TIMER ROM_WDT_A_HOLD_TIMER
308 #define MAP_WDT_A_HOLD_TIMER wdt_a_hold_timer
310 #ifdef ROM_SYS_CTL_A_GET_FLASH_SIZE
311 #define MAP_SYS_CTL_A_GET_FLASH_SIZE ROM_SYS_CTL_A_GET_FLASH_SIZE
313 #define MAP_SYS_CTL_A_GET_FLASH_SIZE sys_ctl_a_get_flash_size
315 #ifdef ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE
316 #define MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE
318 #define MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE sys_ctl_a_get_info_flash_size
320 #ifdef ROM_FLASH_CTL_A_UNPROTECT_MEMORY
321 #define MAP_FLASH_CTL_A_UNPROTECT_MEMORY ROM_FLASH_CTL_A_UNPROTECT_MEMORY
323 #define MAP_FLASH_CTL_A_UNPROTECT_MEMORY flash_ctl_a_unprotect_memory
325 #ifdef ROM_FLASH_CTL_A_PROTECT_MEMORY
326 #define MAP_FLASH_CTL_A_PROTECT_MEMORY ROM_FLASH_CTL_A_PROTECT_MEMORY
328 #define MAP_FLASH_CTL_A_PROTECT_MEMORY flash_ctl_a_protect_memory
330 #ifdef ROM_FLASH_CTL_A_PERFORM_MASS_ERASE
331 #define MAP_FLASH_CTL_A_PERFORM_MASS_ERASE ROM_FLASH_CTL_A_PERFORM_MASS_ERASE
333 #define MAP_FLASH_CTL_A_PERFORM_MASS_ERASE flash_ctl_a_perform_mass_erase
335 #ifdef ROM_FLASH_CTL_A_ERASE_SECTOR
336 #define MAP_FLASH_CTL_A_ERASE_SECTOR ROM_FLASH_CTL_A_ERASE_SECTOR
338 #define MAP_FLASH_CTL_A_ERASE_SECTOR flash_ctl_a_erase_sector
340 #ifdef ROM_FLASH_CTL_A_PROGRAM_MEMORY
341 #define MAP_FLASH_CTL_A_PROGRAM_MEMORY ROM_FLASH_CTL_A_PROGRAM_MEMORY
343 #define MAP_FLASH_CTL_A_PROGRAM_MEMORY flash_ctl_a_program_memory
345 #ifdef ROM_FLASH_CTL_A_SET_WAIT_STATE
346 #define MAP_FLASH_CTL_A_SET_WAIT_STATE ROM_FLASH_CTL_A_SET_WAIT_STATE
348 #define MAP_FLASH_CTL_A_SET_WAIT_STATE flash_ctl_a_set_wait_state
350 #ifdef ROM_FLASH_CTL_A_GET_WAIT_STATE
351 #define MAP_FLASH_CTL_A_GET_WAIT_STATE ROM_FLASH_CTL_A_GET_WAIT_STATE
353 #define MAP_FLASH_CTL_A_GET_WAIT_STATE flash_ctl_a_get_wait_state
356 /* Real Time Clock Module prototypes */
357 extern void rtc_c_hold_clock(void);
359 /* Watchdog Timer Module prototypes */
360 extern void wdt_a_hold_timer(void);
362 #if defined(__MCU_HAS_FLCTL_A__)
363 #define FLASH_A_BANK0 0x00
364 #define FLASH_A_BANK1 0x01
365 #define __INFO_FLASH_A_TECH_START__ 0x00200000
366 #define __INFO_FLASH_A_TECH_MIDDLE__ 0x00204000
369 #if defined(__MCU_HAS_FLCTL__)
370 #define FLASH_BANK0 0x00
371 #define FLASH_BANK1 0x01
372 #define FLASH_MAIN_MEMORY_SPACE_BANK0 0x01
373 #define FLASH_MAIN_MEMORY_SPACE_BANK1 0x02
374 #define FLASH_INFO_MEMORY_SPACE_BANK0 0x03
375 #define FLASH_INFO_MEMORY_SPACE_BANK1 0x04
376 #define FLASH_SECTOR0 FLCTL_BANK0_MAIN_WEPROT_PROT0
377 #define FLASH_SECTOR1 FLCTL_BANK0_MAIN_WEPROT_PROT1
384 #endif /* OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H */