1 /***************************************************************************
2 * Copyright (C) 2011 by Andreas Fritiofson *
3 * andreas.fritiofson@gmail.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
29 * r0 - flash base (in), status (out)
30 * r1 - count (halfword-16bit)
40 #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register from flash reg base */
41 #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
44 ldr r6, [r2, #0] /* read wp */
45 cmp r6, #0 /* abort if wp == 0 */
47 ldr r5, [r2, #4] /* read rp */
48 cmp r5, r6 /* wait until rp != wp */
50 movs r6, #1 /* set PG flag to enable flash programming */
51 str r6, [r0, #STM32_FLASH_CR_OFFSET]
52 ldrh r6, [r5] /* "*target_address++ = *rp++" */
57 ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */
61 movs r7, #0x14 /* check the error bits */
64 cmp r5, r3 /* wrap rp at end of buffer */
69 str r5, [r2, #4] /* store rp */
70 subs r1, r1, #1 /* decrement halfword count */
72 beq exit /* loop if not done */
76 str r0, [r2, #4] /* set rp = 0 on error */
78 mov r0, r6 /* return status in r0 */